JP2013031089A - Amplification device, amplification system and current-voltage conversion device - Google Patents

Abstract

An amplification device, an amplification system, and a current-voltage conversion device using the amplification device capable of appropriately canceling an offset voltage are provided.
According to an embodiment, an amplifying apparatus includes a main amplifier, a first sub-amplifier, and a second sub-amplifier. The main amplifier outputs a voltage obtained by amplifying the difference between the first input voltage and the second input voltage. The first sub-amplifier performs its own offset cancellation based on the output voltage when the input terminals are short-circuited, and based on the output voltage when the first input voltage and the second input voltage are input. To cancel the offset of the main amplifier. The second sub-amplifier performs its own offset cancellation based on the output voltage when the input terminals are short-circuited, and based on the output voltage when the first input voltage and the second input voltage are input. To cancel the offset of the main amplifier.
[Selection] Figure 2

Description

  Embodiments described herein relate generally to an amplification device, an amplification system, and a current-voltage conversion device.

  The operational amplifier is used, for example, in a current-voltage converter that converts current into voltage. In order to increase the conversion accuracy, the difference between the voltage input to the inverting input terminal of the operational amplifier and the voltage input to the non-inverting input terminal must be accurately amplified.

  However, in general, an operational amplifier has an offset voltage due to manufacturing variations. Therefore, even when the same voltage is input to the inverting input terminal and the non-inverting input terminal of the operational amplifier, there is a problem that an offset voltage of about ± 5 to 10 mV is output and conversion accuracy is lowered.

Japanese Patent Laid-Open No. 3-34683

  Provided are an amplifying device, an amplifying system, and a current-voltage converter using the amplifying device capable of appropriately canceling an offset voltage.

  According to the embodiment, the amplification device includes a main amplifier, a first sub-amplifier, and a second sub-amplifier. The main amplifier outputs a voltage obtained by amplifying the difference between the first input voltage and the second input voltage. The first sub-amplifier performs its own offset cancellation based on the output voltage when the input terminals are short-circuited, and based on the output voltage when the first input voltage and the second input voltage are input. To cancel the offset of the main amplifier. The second sub-amplifier performs its own offset cancellation based on the output voltage when the input terminals are short-circuited, and based on the output voltage when the first input voltage and the second input voltage are input. To cancel the offset of the main amplifier.

1 is a schematic block diagram of a current / voltage converter 1. FIG. 1 is a circuit diagram of an amplifying apparatus 100 according to an embodiment. FIG. 3 is a circuit diagram showing an example of a control circuit 150 that generates signals A and B and controls the amplifying apparatus 100. FIG. 4 is a voltage waveform diagram of each part of the control circuit 150 of FIG. 3. FIG. 3 is a circuit diagram of an amplifying apparatus 101 that is a first modification of FIG. 2. The circuit diagram of the amplifier 102 which is the 2nd modification of FIG. The circuit diagram of the amplifier 103 which is the 3rd modification of FIG. The amplifying apparatus 104 which is a modification of FIG.

  Hereinafter, embodiments will be specifically described with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic block diagram of the current-voltage converter 1. This current-voltage converter 1 converts an input current Iin into a digital voltage signal Vd. For example, the current-voltage converter 1 is mounted on the vehicle, and the digital voltage signal Vd is input to a microcomputer and used to monitor the current flowing through the relay.

  The current-voltage converter 1 includes a resistor R, an amplifier 100, a control circuit 150, and an A / D (Analog to Digital) converter 200.

  An input current Iin flows through the resistor R. One end of the resistor R is connected to the positive input terminal Vp of the amplification device 100, and the other end is grounded and connected to the negative input terminal Vn. The amplifying device 100 amplifies the difference between the voltage at the positive input terminal Vp and the voltage at the negative input terminal Vn, and outputs an analog voltage Va. The control circuit 150 controls the amplification device 100. The A / D converter 200 performs analog-digital conversion on the analog voltage Va output from the amplification device 100 to generate a digital voltage signal Vd.

  As a specific numerical example, the input current Iin is 0 to 3 A, and the resistance R is 100 mΩ. Therefore, the voltage difference between both input terminals of the amplifying apparatus 100 is 0 to 300 mV. On the other hand, the amplifying apparatus 100 amplifies the voltage difference by 12.5 times, for example. Therefore, the analog voltage Va output from the amplifying apparatus 100 is 0V to 3.75V. The A / D converter 200 converts this into a digital voltage signal Vd with 12-bit accuracy, for example.

  Assuming that the offset voltage of the amplifying apparatus 100 is 10 mV, the analog voltage Va that is multiplied by 12.5 by the amplifying apparatus 100 and has an output has a maximum error of 125 mV. This is an error of 3.3% or more with respect to 3.75 V of the analog voltage Va output from the amplifying apparatus 100.

  In order to convert the input current Iin into the digital voltage signal Vd with high accuracy, in this embodiment, the offset voltage is made as small as possible as follows.

  FIG. 2 is a circuit diagram of the amplifying apparatus 100 according to an embodiment. The amplifying apparatus 100 includes a main amplifier (MAIN) MA, sub-amplifiers (SUB) SA1 and SA2, switches SW1 to SW8, and capacitors C0 to C3. These are formed, for example, on the same semiconductor substrate.

  Each of the main amplifier MA and the sub-amplifiers SA1 and SA2 has a non-inverting input terminal (+), an inverting input terminal (−), an offset adjustment terminal (c), and an output terminal.

When the voltage difference input to the non-inverting input terminal and the inverting input terminal of the main amplifier MA is Vinm and the voltage input to the offset adjustment terminal is Vcm, the current flows from the offset adjustment terminal to the non-inverting input terminal side or the inverting input terminal side. By sinking or sinking the current, the main amplifier MA outputs a voltage Voutm represented by the following equation (1).
Voutm = Gm * (Vinm + Vofsm) + gm * Vcm (1)
Here, Gm and gm are constants indicating the gain of the main amplifier MA, and Vofsm is an offset voltage thereof.

Further, when the voltage difference input to the non-inverting input terminal and the inverting input terminal of the sub-amplifier SA1 is Vins and the voltages input to the offset adjustment terminal are Vins and Vcs, respectively, the offset adjustment terminal to the inverting input terminal side or the non-inverting input By sinking or sourcing current flowing to the terminal side, the sub-amplifier SA1 outputs a voltage Vouts expressed by the following equation (2).
Vouts = Gs * (Vins + Vofss) −gs * Vcs (2)
Here, Gs and gs are constants indicating the gain of the sub-amplifier SA1, and Vofss is an offset voltage thereof.

  By forming the sub-amplifier SA2 on the same semiconductor substrate as the sub-amplifier SA1, the characteristics of the sub-amplifier SA2 can be made substantially the same as those of the sub-amplifier SA1.

  A power supply voltage Vcc (for example, 5 V) and a reference voltage Vref (for example, Vcc / 2) are supplied to the main amplifier MA and the sub-amplifiers SA1 and SA2. Actually, a voltage higher than the reference voltage Vref by the equations (1) and (2) is output. However, in this specification, the description of the reference voltage Vref is omitted for the sake of simplicity. Further, when the output voltage of each amplifier is higher (lower) than the reference voltage Vref, the output voltage is said to be positive (negative).

  The circuit of FIG. 2 is configured as follows.

  The positive input terminal Vp (hereinafter, the input voltage (first input voltage) to the positive input terminal Vp is also expressed as Vp) of the amplifying apparatus 100 is connected to the non-inverting input terminal of the main amplifier MA. On the other hand, the negative input terminal Vn (hereinafter, the input voltage (second input voltage) to the negative input terminal Vn is also expressed as Vn) is connected to the inverting input terminals of the main amplifier MA and the sub-amplifiers SA1 and SA2. The switches SW1 and SW3 are connected between the positive input terminal Vp and the non-inverting input terminals of the sub-amplifiers SA1 and SA2. The switches SW2 and SW4 are connected between the non-inverting input terminal and the inverting input terminal of the sub-amplifiers SA1 and SA2, respectively.

  The output terminal of the sub-amplifier SA1 is connected to its own offset adjustment terminal via the switch SW5, and is connected to the offset adjustment terminal of the main amplifier MA via the switch SW6. The output terminal of the sub-amplifier SA2 is connected to its own offset adjustment terminal via the switch SW7, and is connected to the offset adjustment terminal of the main amplifier MA via the switch SW8. The output voltage of the main amplifier MA is an analog voltage Va that is an output of the amplifying apparatus 100.

  Capacitors C0 to C2 are respectively connected between the offset adjustment terminals of the main amplifier MA and the sub amplifiers SA1 and SA2 and the power supply terminal -Vcc. The voltage supplied to the power supply terminal -Vcc may be a constant voltage, for example, -5V.

  Of the switches, the switches SW1, SW4, SW6, and SW7 are turned on (short-circuited) when the signal A is high and turned off (opened) when the signal A is low. On the other hand, the switches SW2, SW3, SW5 and SW8 are turned on when the signal B is high and turned off when the signal B is low.

  FIG. 3 is a circuit diagram illustrating an example of the control circuit 150 that generates the signals A and B and controls the amplification device 100. The control circuit 150 includes inverter circuits I1 and I2, an inverting delay circuit D1, an AND circuit L1, and a NOR circuit L2. The inverting delay circuit D1 is configured using, for example, an inverter having hysteresis characteristics. FIG. 4 is a voltage waveform diagram of each part of the control circuit 150 of FIG.

  A clock signal CLK having a predetermined frequency (for example, 20 kHz) is input to the control circuit 150. The inverter circuit I1 supplies a signal P generated by inverting the clock signal CLK to the inverter circuit I2 and the delay circuit D1. The inverter circuit I2 supplies a signal Q generated by inverting the input signal P to the AND circuit L1 and the NOR circuit L2. The inverting delay circuit D1 supplies a signal R generated by inverting and delaying the input signal P to the AND circuit L1 and the NOR circuit L2. The AND circuit L1 outputs a logical product of the input signals Q and R as a signal A, and the NOR circuit L2 outputs an inversion of these logical sums as a signal B.

  Note that an inversion delay circuit D1 is provided as shown in FIG. 3, so that one of the signals A and B is reliably set to low and the other signal is set to high as shown in FIG. For example, the signal A is set high at time t2 after the signal B is reliably set low at time t1. The reason is that if one signal switches from high to low and the other signal switches from low to high at the same time, both signals A and B are instantaneously set to high, resulting in positive input terminal Vp. This is because the negative input terminal Vn may short-circuit and malfunction.

  Hereinafter, the operation of the amplifying apparatus 100 of FIG. 2 will be described in detail with reference to FIG. First, the operation of the sub-amplifier SA2 will be mainly described.

When the signal A is set high at time t2, the switches SW4 and SW7 are turned on. As a result, the non-inverting input terminal and the inverting input terminal of the sub-amplifier SA2 are short-circuited, the voltage difference becomes 0, and the output voltage is fed back to the offset adjustment terminal via the switch SW7. As a result, the output voltage Vouts2 of the sub-amplifier SA2 is expressed by the following equation (3) based on the equation (2).
Vouts2 = Gs * (0 + Vofss) −gs * Vouts2 (3)

The above formula (3) can be summarized as the following formula (4).
Vouts2 = Gs * Vofss / (1 + gs) (4)

  If the offset voltage Vofss of the sub-amplifier SA2 is 0, Vouts2 = 0. However, even if this is not the case, Gs caused by the offset voltage Vofss can be obtained by feedback control as can be seen from the above equation (4). * The influence of the Vofss term can be reduced. Thus, reducing the influence of the offset voltage is called offset cancellation.

  Thereafter, when the signal A is set low at time t3 and the switches SW4 and SW7 are turned off, the operation of the sub-amplifier SA2 canceling its own offset ends. At this time, a charge corresponding to the output voltage Vout2 of the above equation (4) is stored in the capacitor C2. This electric charge hardly discharges for at least about one cycle of the clock signal CLK for a while.

  As described above, during the period when the switches SW4 and SW7 are on, that is, the period when the signal A is high, the sub-amplifier SA2 cancels its own offset and charges the capacitor C2.

Next, when the signal B is set high at time t4, the switches SW3 and SW8 are turned on. Thus, the input voltage Vp is input to the non-inverting input terminal of the sub-amplifier SA2, and the input voltage Vn is input to the inverting input terminal. At this time, considering that the voltage represented by the above equation (4) is input to the offset adjustment terminal of the sub-amplifier SA2 by the capacitor C2, the output voltage Vouts2 of the sub-amplifier SA2 is represented by the following equation (5). .
Vouts2 = Gs * (Vp−Vn + Vofss) −gs * Gs * Vofss / (1 + gs) (5)

The output voltage Vouts2 is input to the offset adjustment terminal of the main amplifier MA via the switch SW8. Input voltages Vp and Vn are input to the non-inverting input terminal and the input terminal of the main amplifier MA, respectively. Therefore, the output voltage Va of the main amplifier MA is expressed by the following equation (6) based on the above equation (1).
Va = Gm * (Vp−Vn + Vofsm) + gm * Vouts2 (6)

Substituting the expression (5) into the expression (6) and arranging it as Vp−Vn = Vin, the output voltage Va is expressed by the following expression (7).
Va = (Gm + gm * Gs) * Vin
+ Gm * Vosfm + Gs * gm * Vofss / (1 + gs) (7)

Here, the gains gm and gs are designed to be sufficiently larger than the gains Gm and Gs. The main amplifier MA and the sub amplifiers SA1 and SA2 are formed so that the gains gm and gs are equal to each other. Therefore, the above equation (7) can be approximated by the following equation (8).
Va = gm * Gs * Vin + Gm * Vosfm + Gs * Vofss (8)

  That is, the voltage difference Vin input to the main amplifier MA is multiplied by gm * Gs, whereas the offset voltages Vofsm and Vofss are only multiplied by Gm and Gss, respectively. As a result, the influence of the offset voltages Vofsm and Vofss is reduced. it can.

  In this way, the sub-amplifier SA2 cancels the offset of the main amplifier MA while the switches SW3 and SW8 are on, that is, while the signal B is high.

  Thereafter, when the signal B is set low at time t5, the output voltage Vouts2 of the sub-amplifier SA2 is not directly used as the offset adjustment terminal of the main amplifier MA, but the charge corresponding to the output voltage Vouts2 of the above equation (5) is not generated. Since it is stored in the capacitor C0, the offset of the main amplifier MA can be canceled by the capacitor C0 even after the time t5.

  When the signal A is set low at time t3 and the switches SW4 and SW7 are turned off, the charge stored in the capacitor C2 gradually leaks. Therefore, the signal A is periodically set to high, the input terminals of the sub-amplifier SA2 are output, the offset cancellation is performed based on the output voltage, and the charge necessary for the offset cancellation is supplied to the capacitor C2. store.

  As described above, the sub-amplifier SA2 cancels its own offset while the input terminals are short-circuited during the period when the signal A is high. Further, the input voltages Vp and Vn are input during the period when the signal B is high, and the offset cancellation of the main amplifier MA is performed.

  On the other hand, during a period in which the signal B at time t4 to t5 is high, the switches SW2 and SW5 are turned on, and the subamplifier SA1 cancels its own offset similarly to the subamplifier SA2 at times t2 to t3. When the signal A is set high at time t6, the switches SW1 and SW6 are turned on, and the sub-amplifier SA1 cancels the offset of the main amplifier MA, similarly to the sub-amplifier SA2 at times t4 to t5.

  That is, the sub-amplifier SA1 cancels its own offset by short-circuiting the input terminals during the period when the signal B is high. Further, the input voltages Vp and Vn are input during the period when the signal A is high, and the offset cancellation of the main amplifier MA is performed.

  In summary, during the period when the signal A is high (time t2 to t3, t6 to t7, etc.), the sub-amplifier SA1 cancels the offset of the main amplifier MA, and the period when the signal B is high (time t4 to t5, t8). -T9 etc.), the sub-amplifier SA2 cancels the offset of the main amplifier MA. Further, during a period when both signals A and B are low (time t3 to t4, t5 to t6, etc.), the capacitor C0 in which charges corresponding to the offset canceling voltage are stored cancels the offset of the main amplifier MA. . Since the period when both signals A and B are low is very short, the leakage of the charge stored in the capacitor C0 can be almost ignored.

  In this way, the main amplifier MA can continuously output the offset canceled output voltage Va.

  If only the sub-amplifier SA1 is provided, the main amplifier MA is offset canceled by the sub-amplifier SA1 during the period when the signal A is high (for example, time t2 to t3) and by the capacitor C0 after the subsequent time t3. However, as time elapses, the charge stored in the capacitor C0 leaks and the voltage input to the offset adjustment terminal of the main amplifier MA gradually changes. Therefore, for example, near the time t5, the main amplifier MA is not appropriately offset canceled. Therefore, when only the sub-amplifier SA1 is provided, the period during which an appropriate output voltage Va is obtained from the main amplifier MA is limited to about times t2 to t4.

  On the other hand, in the present embodiment, two sub-amplifiers SA1 and SA2 are provided and the offset cancellation of the main amplifier MA is performed alternately, so that an appropriate output voltage Va can be obtained continuously.

  As described above, in the first embodiment, the two sub-amplifiers SA1 and SA2 are provided, and their own offset cancellation and the offset cancellation of the main amplifier MA are alternately performed. Therefore, the offset canceled voltage is continuously output from the main amplifier MA, and the offset voltage can be canceled appropriately. As a result, the conversion accuracy of the current-voltage converter 1 can be improved.

  Hereinafter, some modifications will be described.

  FIG. 5 is a circuit diagram of an amplifying apparatus 101 which is a first modification of FIG. The amplifying device 101 in the figure includes buffers B0 to B2 that amplify and output an input voltage. Buffer B0 is connected between the connection node of switches SW6 and SW8 and the offset adjustment terminal of main amplifier MA. The buffer B1 is connected between the switch SW5 and the offset adjustment terminal of the sub amplifier SA1. The buffer B2 is connected between the switch SW8 and the offset adjustment terminal of the sub amplifier SA2.

  By designing the gains gm and gs to be sufficiently larger than the gains Gm and Gs, the offset of the main amplifier MA can be canceled as shown in the above equation (8), but when the gains gm and gs cannot be sufficiently increased. A buffer may be provided as shown in FIG.

  The voltages amplified by the buffers B0 to B2 are input to the offset adjustment terminals of the main amplifier MA and the sub amplifiers SA1 and SA2, respectively. Therefore, even if the gains gm and gs are not sufficiently larger than the gains Gm and Gs, if the product of the gains gm and gs and the gains of the buffers B0 to B2 is sufficiently larger than the gains Gm and Gs. It is possible to cancel the offset of the main amplifier MA.

  FIG. 6 is a circuit diagram of an amplifying apparatus 102 which is a second modification of FIG. The amplifying device 102 in the figure has a smoothing filter 10 including a resistor Rl and a capacitance Cl at the output terminal of the main amplifier MA, and the output of the smoothing filter 10 becomes an analog voltage Va. For example, the resistance Rl is 5.1 kΩ and the capacitance Cl is 0.1 μF. By providing the smoothing filter 10, the output voltage of the main amplifier MA is smoothed, and the accuracy of the analog voltage Va is further improved.

  FIG. 7 is a circuit diagram of an amplifying apparatus 103 which is a third modification of FIG. The amplifying device 103 in FIG. 1 includes a comparator (first comparator) 11 connected between the sub-amplifier SA1 and the switch SW5, and a comparator (second comparator) connected between the sub-amplifier SA2 and the switch SW7. Comparator) 12.

  The comparator 12 compares the output voltage of the sub-amplifier SA2 with a reference voltage Vref (for example, Vcc / 2) that is a threshold value, and outputs high when the output voltage of the sub-amplifier SA2 is large and low when the output voltage is small. The output voltage of the comparator 12 is binary, high or low, and corresponds to the sink current or source current for the sub-amplifier SA2, respectively.

  When the switch SW4 is on and the offset voltage of the sub-amplifier SA2 is positive (higher than the reference voltage Vref), the output of the comparator 12 is high and the output of the sub-amplifier SA2 is low. On the other hand, when the offset voltage of the sub-amplifier SA2 is negative (lower than the reference voltage Vref), the output of the comparator 12 is low and the output of the sub-amplifier SA2 is high. By such feedback control, the sub amplifier SA2 is offset canceled. At this time, the charge corresponding to the voltage Vout2 in the above equation (4) is also stored in the capacitor C2.

  Similarly, the comparator 11 cancels the offset of the sub-amplifier SA1. Thereafter, the offset voltage Va canceled by the same principle as that of the amplifying apparatus 100 of FIG. 2 is output from the main amplifier MA.

  In the amplifying apparatus 103, since the outputs of the comparators 11 and 12 are high or low, offset cancellation of the sub-amplifiers SA1 and SA2 and charging and discharging of the capacitors C1 and C2 can be performed more quickly. As a result, the accuracy of voltage amplification can be further improved.

  FIG. 8 is a circuit diagram of the amplifying apparatus 104 showing a modification of FIG. The amplifying device 104 in the figure includes resistors R10 to R13 and R20 to R23 in addition to the amplifying device 103 in FIG.

  The resistor R20 is connected between the switch SW3 and the non-inverting input terminal of the sub amplifier SA2. The resistor R21 is connected between the positive input terminal Vn and the inverting input terminal of the sub amplifier SA2. The resistor R22 is connected between the non-inverting input terminal of the sub-amplifier SA2 and the reference power supply terminal Vref. The resistor R23 is connected between the inverting input terminal and the output terminal of the sub amplifier SA2.

  For example, by setting the resistors R22 and R23 to be ten times that of the resistors R20 and R21, the voltage difference between the non-inverting input terminal and the inverting input terminal of the sub-amplifier SA2 is further multiplied by ten and input to the comparator 12. As a result, the voltage value input to the comparator 12 is not about the reference voltage Vref, which is the threshold value, but is surely a voltage value larger or smaller than this. Therefore, even when the input / output characteristics of the comparator 12 are not steep, or when the threshold value is slightly deviated from the reference voltage Vref, the comparator 12 can cancel the offset of the sub-amplifier SA2.

  The same applies to the resistors R10 to R13.

  Although some modifications have been described above, they may be combined as a matter of course.

  In the amplification device and the current-voltage conversion device according to each embodiment, the entire circuit may be formed on the same semiconductor substrate, or a part of the circuit may be formed on another semiconductor substrate. Moreover, you may mount on a printed circuit board etc. using discrete components.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Current voltage converter 10 Smoothing filter 11, 12 Comparator
100-104 Amplifier 150 Delay Inversion Circuit 200 A / D Converter

Claims (11)

A current-voltage converter for converting an input current into a corresponding digital voltage signal,
A resistance through which the input current flows;
An amplifier in which one end of the resistor is connected to a positive input terminal and the other end is connected to a negative input terminal;
A control circuit for controlling the amplification device;
An A / D converter for analog-to-digital conversion of the output voltage of the amplification device to generate the digital voltage signal;
The amplification device includes:
A main amplifier that outputs a voltage obtained by amplifying the difference between the voltage at one end of the resistor and the voltage at the other end of the resistor;
The offset of the main amplifier is based on the output signal when the voltage at one end of the resistor and the voltage at the other end of the resistor are input based on the output signal when the input terminals are short-circuited. A first sub-amplifier for canceling,
The offset of the main amplifier is based on the output signal when the voltage at one end of the resistor and the voltage at the other end of the resistor are input based on the output signal when the input terminals are short-circuited. A second sub-amplifier for canceling,
A smoothing filter for smoothing the output signal of the main amplifier;
A first switch for switching whether to input a voltage at one end of the resistor to the first sub-amplifier;
A second switch for switching whether or not the input terminals of the first sub-amplifier are short-circuited;
A third switch for switching whether to input the voltage at the other end of the resistor to the second sub-amplifier;
A fourth switch for switching whether or not the input terminals of the second sub-amplifier are short-circuited;
A fifth switch for switching whether or not to cancel the offset based on the output signal of the first sub-amplifier;
A sixth switch for switching whether to cancel the offset of the main amplifier based on the output signal of the first sub-amplifier;
A seventh switch for switching whether or not to cancel the offset of itself based on the output signal of the second sub-amplifier;
An eighth switch for switching whether to cancel the offset of the main amplifier based on the output signal of the second sub-amplifier;
A first buffer for amplifying an output signal of the first sub-amplifier when the input terminals of the first sub-amplifier are short-circuited;
A second buffer for amplifying an output signal of the second sub-amplifier when the input terminals of the second sub-amplifier are short-circuited;
The output signal of the first sub-amplifier when the voltage at one end of the resistor and the voltage at the other end of the resistor are input, or the voltage at one end of the resistor and the voltage at the other end of the resistor are input. A third buffer for amplifying the output signal of the second sub-amplifier;
A first comparator for comparing the output signal of the first sub-amplifier with a predetermined threshold;
A second comparator for comparing the output signal of the second sub-amplifier with a predetermined threshold;
The first sub-amplifier is offset canceled based on the output of the first comparator,
The second sub-amplifier is offset canceled based on the output of the second comparator,
The main amplifier is offset canceled based on the third buffer,
The control circuit includes:
The first, fourth, sixth, and seventh switches are turned on or off at the same timing,
A current-voltage converter characterized in that the second, third, fifth, and eighth switches are turned on at the same timing and when the first switch is turned off. A main amplifier that outputs a voltage obtained by amplifying the difference between the first input voltage and the second input voltage;
The offset cancellation of the main amplifier is performed based on the output signal when the first input voltage and the second input voltage are input, based on the output signal when the input terminals are short-circuited. A first sub-amplifier that performs
The offset cancellation of the main amplifier is performed based on the output signal when the first input voltage and the second input voltage are input, based on the output signal when the input terminals are short-circuited. And a second sub-amplifier for performing the above.   3. The amplifying apparatus according to claim 2, wherein when one of the first and second sub-amplifiers performs its own offset cancellation, the other performs offset cancellation of the main amplifier. A first switch for switching whether to input the first input voltage to the first sub-amplifier;
A second switch for switching whether or not the input terminals of the first sub-amplifier are short-circuited;
A third switch for switching whether to input the second input voltage to the second sub-amplifier;
A fourth switch for switching whether or not the input terminals of the second sub-amplifier are short-circuited;
A fifth switch for switching whether or not to cancel the offset based on the output signal of the first sub-amplifier;
A sixth switch for switching whether to cancel the offset of the main amplifier based on the output signal of the first sub-amplifier;
A seventh switch for switching whether or not to cancel the offset of itself based on the output signal of the second sub-amplifier;
An eighth switch for switching whether to cancel the offset of the main amplifier based on the output signal of the second sub-amplifier,
The first, fourth, sixth, and seventh switches are turned on or off at the same timing,
The amplifying apparatus according to claim 2 or 3, wherein the second, third, fifth, and eighth switches are turned on at the same timing and when the first switch is turned off. A first buffer for amplifying an output signal of the first sub-amplifier when the input terminals of the first sub-amplifier are short-circuited;
A second buffer for amplifying an output signal of the second sub-amplifier when the input terminals of the second sub-amplifier are short-circuited;
The output signal of the first sub-amplifier when the first input voltage and the second input voltage are input, or the second when the first input voltage and the second input voltage are input. A third buffer for amplifying the output signal of the sub-amplifier,
The first sub-amplifier is offset canceled based on the output of the first buffer,
The second sub-amplifier is offset canceled based on the output of the second buffer,
The amplifying apparatus according to claim 2, wherein the main amplifier is offset canceled based on the third buffer.   6. The amplifying apparatus according to claim 2, further comprising a smoothing filter that smoothes an output signal of the main amplifier. A first comparator for comparing the output signal of the first sub-amplifier with a predetermined threshold;
A second comparator for comparing the output signal of the second sub-amplifier with a predetermined threshold;
The first sub-amplifier is offset canceled based on the output of the first comparator,
The amplification apparatus according to claim 2, wherein the second sub-amplifier is offset canceled based on an output of the second comparator. The first input voltage is input to a first input terminal of the first sub-amplifier through a first resistor,
The second input voltage is input to a second input terminal of the first sub-amplifier through a second resistor,
A third resistor is connected between the first input terminal and a reference voltage terminal;
A fourth resistor is connected between the first input terminal and the output terminal of the first sub-amplifier;
The third resistor and the fourth resistor are larger than the first resistor and the second resistor,
The first input voltage is input to a third input terminal of the second sub-amplifier through a fifth resistor,
The second input voltage is input to a fourth input terminal of the second sub-amplifier through a sixth resistor,
A seventh resistor is connected between the third input terminal and a reference voltage terminal;
An eighth resistor is connected between the third input terminal and the output terminal of the second sub-amplifier;
The amplifying apparatus according to claim 2, wherein the seventh resistor and the eighth resistor are larger than the fifth resistor and the sixth resistor. A main amplifier that outputs a voltage obtained by amplifying the difference between the first input voltage and the second input voltage;
The offset cancellation of the main amplifier is performed based on the output signal when the first input voltage and the second input voltage are input, based on the output signal when the input terminals are short-circuited. A first sub-amplifier that performs
The offset cancellation of the main amplifier is performed based on the output signal when the first input voltage and the second input voltage are input, based on the output signal when the input terminals are short-circuited. A second sub-amplifier that performs
An amplification system comprising: a control circuit that controls so that when one of the first and second sub-amplifiers performs its own offset cancellation, the other performs offset cancellation of the main amplifier. A first switch for switching whether to input the first input voltage to the first sub-amplifier;
A second switch for switching whether or not the input terminals of the first sub-amplifier are short-circuited;
A third switch for switching whether to input the second input voltage to the second sub-amplifier;
A fourth switch for switching whether or not the input terminals of the second sub-amplifier are short-circuited;
A fifth switch for switching whether or not to cancel the offset based on the output signal of the first sub-amplifier;
A sixth switch for switching whether to cancel the offset of the main amplifier based on the output signal of the first sub-amplifier;
A seventh switch for switching whether or not to cancel the offset of itself based on the output signal of the second sub-amplifier;
An eighth switch for switching whether to cancel the offset of the main amplifier based on the output signal of the second sub-amplifier,
The control circuit includes:
The first, fourth, sixth, and seventh switches are turned on or off at the same timing,
The amplifying apparatus according to claim 9, wherein the second, third, fifth, and eighth switches are turned on at the same timing and when the first switch is turned off. A current-voltage converter for converting an input current into a corresponding digital voltage signal,
A resistance through which the input current flows;
An amplifier in which one end of the resistor is connected to a positive input terminal and the other end is connected to a negative input terminal;
An A / D converter for analog-to-digital conversion of the output voltage of the amplification device to generate the digital voltage signal;
The amplification device includes:
A main amplifier that outputs a voltage obtained by amplifying the difference between the voltage at one end of the resistor and the voltage at the other end of the resistor;
The offset of the main amplifier is based on the output signal when the voltage at one end of the resistor and the voltage at the other end of the resistor are input based on the output signal when the input terminals are short-circuited. A first sub-amplifier for canceling,
The offset of the main amplifier is based on the output signal when the voltage at one end of the resistor and the voltage at the other end of the resistor are input based on the output signal when the input terminals are short-circuited. And a second sub-amplifier that performs cancellation.

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