JP2013030604A - Field effect transistor - Google Patents

Abstract

A group III-V FET having an improved ability to supply electrons to a channel is provided.
A channel layer 4 of a narrow band gap material is formed on a substrate 2. A contact layer 6 made of a wide band gap material is formed in the source region on the channel layer 4. The source contact layer 6 is doped at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more. The FET 1 is configured such that carriers are directly injected into the undoped channel layer 4 by the source contact layer 6.
[Selection] Figure 1

Description

  The present invention relates to a compound semiconductor field effect transistor.

  According to the 2009 roadmap of ITRS (International Technology Roadmap for Semiconductors), in order to meet the characteristics required for future transistors, III-V group compound semiconductors in the N channel are used as high mobility channel materials. The need for germanium (Ge) has been pointed out in the P channel.

It has been predicted by simulations by a plurality of research institutions that a carrier concentration of about 10 ²⁰ cm ⁻³ in the source region is required to increase the current of the field effect transistor structure using a compound semiconductor. On the other hand, the channel region is desirably undoped or thinly doped oppositely from the source region from the viewpoint of suppressing ionized impurity scattering and threshold control.

  As a method for forming a high source carrier concentration region, an ion implantation method that is common in a Si (silicon) process or a modulation doping method to a wide gap material used in a buried channel of a III-V compound device is used.

M. Radosavljevic et. Al., IEDM. Technol. Digest 2009, pp.319-322 M. Radosavljevic et. Al., IEDM. Technol. Digest 2010, pp. 127-129 U. Singisetti et. Al., Electron Device Lett. Vol. 30 no.11, pp.1128-1130, Nov. 2009

However, the ion implantation method requires a high temperature for the activation treatment after implantation, so that it is difficult to dope a high concentration of 10 ¹⁹ cm ⁻³ or more to the III-V material. Regarding the modulation doping structure, in the buried channel, there is a restriction from the viewpoint of gate leakage current and threshold voltage regarding the dopant on the upper part of the channel, and a trade-off occurs between the carrier concentration and the series resistance.

As the source layer of the recess type surface channel, n ⁺ -InGaAs (indium gallium arsenide) is also used. In this case, InP (indium phosphide) or the like needs to be introduced as an etch stop layer for selective etching with the channel, but this etch stop layer may deteriorate the carrier injection capability.

  In recent years, metal source / drain structures have been studied. However, a high value is not obtained as an actual driving capability, and it is considered that there are still problems in the characteristics of the metal / semiconductor interface. Similarly, the regrowth type source / drain has a problem that a high-temperature and high-cost process is required.

  The present invention has been made in view of the above problems, and one of exemplary objects of an embodiment thereof is to provide a group III-V FET having an improved ability to supply electrons to a channel.

One embodiment of the present invention relates to a field effect transistor. This field effect transistor is a channel layer of a narrow band gap material and a contact layer of a wide band gap material formed in a source region on the channel layer, and is doped at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more. A source contact layer.

Another embodiment of the present invention is also a field effect transistor. This field effect transistor is a contact layer of a wide band gap material formed in a channel layer of a narrow band gap material and a source region on the channel layer, and a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ or more in the channel layer And a source contact layer doped at a high concentration so as to be supplied.

  According to these embodiments, a high concentration carrier can be injected into a channel intrinsic part from a source contact layer doped with a high concentration via a channel layer immediately below the source contact layer. In this case, the InP etch stop layer whose performance has been deteriorated is not necessary, and the resistance component resulting therefrom can be reduced. As a result, a high electron supply capability to the channel layer and a small series resistance can be realized.

  The wide band gap material forming the source contact layer may be InP.

InP of the source contact layer may have a (112) plane exposed by the etching anisotropy, and a channel length may be defined by a skirt of the inclined (112) plane.
By using InP, the channel intrinsic part can be formed by the anisotropic etch stop surface, and the process can be simplified and the cost can be reduced.

Yet another embodiment of the present invention is also a field effect transistor. This field effect transistor includes a channel layer and a source contact layer formed in a source region on the channel layer. The source contact layer has an inclined surface on the gate region side due to the etching anisotropy, and the channel length is defined by the bottom of the inclined surface.
According to this aspect, the process can be simplified and the cost can be reduced by forming the channel intrinsic portion using the anisotropic etch stop surface.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, the ability to supply electrons to the channel of a III-V compound semiconductor field effect transistor can be improved.

It is sectional drawing which shows the structure of N channel FET which concerns on embodiment. FIG. 2A is a diagram showing the structure (upper stage) and band structure (lower stage) of the junction of the source and channel of the conventional FET, and FIG. 2B is a diagram showing the source and channel of the FET in FIG. It is a figure which shows the structure (upper stage) and band structure (lower stage) of a junction part. 3A to 3F are views showing a method for manufacturing the FET of FIG. It is a figure which shows the source | sauce, drain layer structure, and gate stack of FET which were actually manufactured. And measured source-drain distance L _SD, a diagram showing the relationship between the measured channel length L _CH. 6A is a diagram showing drain voltage V _D -drain current _ID characteristics, and FIG. 6B is a diagram showing gate voltage V _G -drain current _ID characteristics.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 1 is a sectional view showing the structure of an N-channel FET (Field Effect Transistor) 1 according to the embodiment. The FET 1 includes a substrate 2, a buffer layer 3, a channel layer 4, a source contact layer 6, a drain contact layer 8, an upper source contact layer 10, an upper drain contact layer 12, a gate insulating film 14, a gate electrode 16, a source electrode 18, A drain electrode 20 is provided.

  The substrate 2 is, for example, a p-type InP substrate. A channel layer 4 of a narrow band gap material is formed on the upper surface of the substrate 2. As the narrow band gap material for forming the channel layer 4, for example, InGaAs or InAs which is an undoped III-V group compound semiconductor can be used. Between the substrate 2 and the channel layer 4, it is preferable to form a layer 3 (also simply referred to as a buffer layer) that also serves as a buffer layer and a channel under electron confinement layer. The buffer layer 3 is made of, for example, InAlAs or InP.

A source contact layer 6 made of a wide band gap material is formed in the source region in the upper layer of the channel layer 4. For example, InP is suitable as the wide band gap material. The source contact layer 6 is doped at a concentration that can supply a high carrier concentration of 1 × 10 ¹⁹ cm ⁻³ or more to the channel layer 4. Specifically, the source contact layer 6 is preferably doped at a high concentration of 1 × 10 ¹⁹ cm ⁻³ or more, preferably 2 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²⁰ cm ⁻³ .

  Similarly, a drain contact layer 8 made of a wide band gap material is formed in the upper drain region of the channel layer 4. The drain contact layer 8 is made of the same material InP as the source contact layer 6.

  InP has etching anisotropy on the (112) plane. Therefore, when the source contact layer 6 and the drain contact layer 8 are formed by etching, the (112) plane of the source contact layer 6 and the (112) plane of the drain contact layer 8 are exposed to be inclined to the gate region side. . The channel length can be controlled and miniaturized by the bottoms of the inclined surfaces of the source contact layer 6 and the drain contact layer 8. This point will be described later.

An upper source contact layer 10 is formed on the source contact layer 6. Similarly, an upper drain contact layer 12 is formed on the drain contact layer 8. The upper source contact layer 10 and the upper drain contact layer 12 are made of, for example, n ⁺ -InGaAs. As a result, the etching selectivity can be improved, and the contact characteristics between the metal electrodes 18 and 20 and the contact layers 6 and 8 can be improved.

An Al ₂ O ₃ gate insulating film 14 is formed so as to cover the source contact layer 6, the drain contact layer 8, the source electrode 18, and the drain electrode 20. Contact holes 22 and 24 are formed in regions of the gate insulating film 14 that overlap with the source electrode 18 and the drain electrode 20. Further, a Cr / Au gate electrode 16 is formed in the gate region of the gate insulating film 14.

  The above is the configuration of the FET 1 according to the embodiment.

  FIG. 2A is a diagram showing the structure (upper stage) and band structure (lower stage) of the junction of the source and channel of the conventional FET, and FIG. 2B is a diagram showing the source and channel of the FET in FIG. It is a figure which shows the structure (upper stage) and band structure (lower stage) of a junction part.

First, with reference to FIG. 2A, an ideal case FET with a regrowth type source / drain described in Non-Patent Document 3 will be described. As shown in the upper part of FIG. 2A, InGaAs, which is a narrow band gap material, is used as the source contact. In this case, even if there is a sufficient carrier concentration as a bulk, due to channel quantization, the height of the Fermi level (E _F ) seen from the bottom of the quantum level is lowered, and the electron concentration in the channel is lowered. End up.

Next, the FET 1 in FIG. 1 will be described. Figure 2 (b) as shown in the upper part, by forming a source contact layer with a wide band gap material doped with a high concentration, the height of the Fermi level E _F viewed from the quantum level of the channel, the band Even if the discontinuity increases and the energy of the quantum level is subtracted, a high electron concentration in the channel can be obtained.

  In consideration of device operation, the channel layer 4 below the source contact layer 6 can be regarded as a source region for the intrinsic channel portion. Therefore, the electron concentration in that region greatly affects the device operation at a high current. In the FET 1 according to the embodiment, the electron concentration in the region adjacent to the intrinsic channel portion of the InGaAs channel layer 4 is increased, so that depletion of electrons in the source can be suppressed and parasitic resistance can be reduced.

  As described above, according to the FET 1 of FIG. 1, high concentration carriers can be injected into the channel layer 4 from the source contact layer 6 doped with high concentration. In addition, since the InP etch stop layer, which has deteriorated performance in the conventional recessed field effect transistor, is not required, the resistance component caused by the etch stop layer can be reduced, and a small series resistance can be realized.

  The FET 1 according to the embodiment and the conventional HEMT have a similar configuration and have common points. However, the FET 1 according to the embodiment is a device having a completely different structure from the conventional HEMT, and the two should not be confused. Specifically, in the conventional HEMT, since the source and drain are modulation doping layers, a wide band gap layer in which doping is limited so that carriers do not exist in the channel is adjacent to the channel layer. On the other hand, the FET 1 according to the embodiment has a configuration in which carriers are directly injected from a strongly doped n + wide band gap layer, and the two are different in this respect.

Then, the manufacturing method of FET1 of FIG. 1 is demonstrated.
In addition, the manufacturing method demonstrated here is an example, and the manufacturing method of FET1 which concerns on this invention is not limited to it.

3A to 3F are diagrams showing a method for manufacturing the FET 1 of FIG.
As shown in FIG. 3A, the layer structure of the FET 1 is formed on the p-InP substrate 2 by MOVPE (Metal-Organic Vapor Phase Epitaxy) growth.

  Subsequently, a metal layer containing Ti / Pd / Au is formed on the upper contact layers 10 and 12. As shown in FIG. 3B, the source electrode 18 and the drain electrode 20 are formed by electron beam exposure, for example.

Subsequently, as shown in FIG. 3C, a recess structure is formed by wet etching. Specifically, using the source electrode 18 and the drain electrode 20 as a mask, the InGaAs layer as the upper contact layers 10 and 12 is etched with a solution of citric acid: hydrogen peroxide = 1: 1, and then the contact layer 6 8 are etched with a solution of HCl: H ₃ P0 ₄ = 1: 1. Due to the etching anisotropy of InP, the source contact layer 6 and the drain contact layer 8 are etched along the (112) plane. As a result, the source contact layer 6 and the drain contact layer 8 have a (112) plane that is inclined with respect to the (001) plane exposed on the gate region side. The inclination angle θ is approximately 38 °.

When a material having etching anisotropy is used as the source contact layer 6 and the drain contact layer 8, the channel length L _CH is defined by the interval between the bottoms of the inclined surfaces of the source contact layer 6 and the drain contact layer 8. That is, the channel length L _CH is approximately according to the following formula (1) according to the distance L _SD between the source electrode 18 and the drain electrode 20 functioning as an etching mask and the thickness H of the contact layers 6 and 8. Can be controlled.
L _CH = L _SD −2 × H / tan (θ) (1)
Conventionally, exposure / development conditions have to be highly controlled in order to reduce the channel length. On the other hand, in the embodiment, an FET having an extremely short channel length _LCH can be manufactured with a simple process and good reproducibility.

  After the etching of the source contact layer 6 and the drain contact layer 8, as shown in FIG. 3D, the gate insulating film 14 is formed so as to cover the source contact layer 6, the drain contact layer 8 and the exposed channel layer 4. It is formed.

  Subsequently, as shown in FIG. 3E, a gate electrode 16 is deposited in the gate region on the gate insulating film 14. Finally, as shown in FIG. 3F, contact holes 22 and 24 are formed in the source and drain regions of the gate insulating film 14.

  The present inventors manufactured FET1 by this manufacturing method, and evaluated the characteristic. FIG. 4 is a diagram showing the source, drain layer structure and gate stack of an actually manufactured FET.

The present inventors have prepared the source-drain distance _{L SD} differ FET1, to measure the respective channel length LCH. FIG. 5 is a diagram showing the relationship between the measured source-drain distance _LSD and the measured channel length _LCH . A solid line indicates a first-order approximate straight line of measured values. Although this straight line does not coincide with the equation (1), it can be seen that the channel length L _CH can be controlled according to the source-drain distance L _SD .

Subsequently, the dependence of the drain current I _{D on} the gate voltage V _G and the drain voltage V _D was measured for a device having a channel length (measured value) L _CH = 50 nm and a source-drain distance (design value) L _SD = 720 nm. . 6A is a diagram showing measured drain voltage V _D -drain current _ID characteristics, and FIG. 6B is a diagram showing measured gate voltage V _G -drain current _ID characteristics. is there.

As apparent from FIG. 6 (a), according to the FET1 according to the _embodiment, at _{V D = 0.5VV G = 3V,} 2.3A / mm very large drain current _{I D} can be obtained. This is much higher than the current reported current density (<1.5 A / mm) of InGaAs-based high mobility channels and far exceeds the typical drain current density in Si-based MOSFETs. Value.

  As described above, according to the FET 1 according to the embodiment, a very large drain current density can be obtained by using the highly doped wide band gap material as the recess type source contact layer 6.

In the FET 1 according to the embodiment, since the source region and the drain region are formed in the same manner, the drain contact layer 8 is also doped with a high concentration of 1 × 10 ¹⁹ cm ⁻³ or more. However, in the present invention, in order to realize a high carrier concentration in the channel region, the drain contact layer 8 is not necessarily doped with a high concentration like the source contact layer 6. However, since the drain contact layer having a high carrier concentration reduces resistance parasitic on the drain side, it contributes to improvement of device performance as a result. Therefore, the structure of the FET 1 according to the embodiment in which the carrier concentration is high not only in the source contact layer but also in the drain contact layer is advantageous from the viewpoints of both operation and manufacturing.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

  The materials and dimensions of the respective members described in the embodiments are examples, and those skilled in the art will understand that the respective materials and dimensions can be changed as appropriate.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 ... FET, 2 ... Substrate, 3 ... Buffer layer, 4 ... Channel layer, 6 ... Source contact layer, 8 ... Drain contact layer, 10 ... Upper source contact layer, 12 ... Upper drain contact layer, 14 ... Gate insulating film, 16 ... gate electrode, 18 ... source electrode, 20 ... drain electrode.

Claims (6)

A channel layer of narrow band gap material;
A contact layer of a wide bandgap material formed in a source region on the channel layer, doped at a concentration of 1 × 10 ¹⁹ cm ⁻³ or more;
A field effect transistor comprising: A channel layer of narrow band gap material;
A contact layer of a wide bandgap material formed in a source region on the channel layer, the source doped at a high concentration so as to supply a carrier concentration of 1 × 10 ¹⁹ cm ⁻³ or more to the channel layer A contact layer;
A field effect transistor comprising:   3. The field effect transistor according to claim 1, wherein the wide band gap material forming the source contact layer is InP.   4. The electric field according to claim 3, wherein the InP of the source contact layer has a (112) plane exposed by an etching anisotropy and a channel length defined by an inclined (112) plane skirt. 5. Effect transistor. A channel layer;
A source contact layer formed in a source region on the channel layer;
With
The field effect transistor according to claim 1, wherein the source contact layer has an inclined surface on the gate region side by etching anisotropy, and a channel length is defined by a skirt of the inclined surface.   The field effect transistor according to claim 5, wherein the source contact layer is InP.

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