JP2013021201A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device without a hump and a semiconductor device are provided.
A photosensitive positive resist material to be a lower resist film is applied on a film to be processed. By performing peripheral exposure processing and development processing on the lower resist material film, the portion of the lower resist material film located in the outer peripheral region is removed. By applying a photosensitive positive resist material to be the intermediate layer resist film and performing peripheral exposure processing and development processing, the portion of the intermediate layer resist material film located in the outer peripheral region is removed.
[Selection] Figure 21

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly to a semiconductor device manufacturing method to which a multilayer resist process is applied, and a semiconductor device manufactured by the manufacturing method.

  When manufacturing a semiconductor device including a semiconductor integrated circuit, as in an ion implantation process to a predetermined region in a semiconductor substrate or the like, an etching process to a film to be processed formed on the surface of the semiconductor substrate, etc. Selective processing (processing) is performed. In such a process, for the purpose of selectively protecting a film to be processed, a pattern of a composition sensitive to actinic rays such as ultraviolet rays, X-rays and electron beams, a so-called photosensitive photoresist film (photoresist film) is formed. Lithography is performed on the film to be processed. In this lithography, in particular, pattern formation by a photoresist film using ultraviolet rays is most widely used.

  As the integration and performance of semiconductor integrated circuits progress, miniaturization of circuit patterns and advanced dimensional control are required. In the exposure apparatus, the wavelength of the exposure light source is shortened from g-line (wavelength = 436 nm) of mercury lamp to i-line (wavelength = 365 nm), KrF excimer laser (wavelength = 248 nm), and ArF excimer laser (wavelength = 193 nm). Has been promoted. Recently, an immersion exposure technique has also appeared that can improve the resolution by filling water (pure water) between the reduction projection lens of the exposure apparatus and the photoresist film applied on the semiconductor substrate. The life of optical lithography has been extended.

  On the other hand, in the photoresist film, in order to ensure the resolution of the pattern, the film thickness of the photoresist film has been reduced, and recently, a photoresist film having a thickness of about 100 nm has been applied. . However, in lithography using an antireflection film such as an organic BARC (Bottom Anti Reflection Coating) film and a photoresist film by miniaturizing the pattern and reducing the thickness of the photoresist film, etching resistance to the film to be processed is ensured. Things are getting harder. Examples of the film to be processed include various film types such as a silicon oxide film or a polysilicon film.

  In order to ensure such etching resistance, a multilayer resist process has recently been introduced. A typical multi-layer resist process is a three-layer resist process. In the three-layer resist process, an upper layer resist film, an intermediate layer resist film, and a lower layer resist film are formed. The upper resist film is a resist film in which a pattern is formed by exposure and development, and is a photosensitive resist film. The lower resist film is a resist film that serves as a dry etching mask for the film to be processed. The intermediate layer resist film is a resist film having a role of transferring the pattern of the upper layer resist film to the lower layer resist film.

  In order to use the lower resist film as a mask for dry etching, a material having a high etching resistance and a function of flattening the step of the base or preventing reflection is used as the material of the lower resist film. In addition, in order to give the intermediate layer resist film etching selectivity with respect to the upper layer resist and the lower layer resist, a material containing high-concentration silicon (Si) atoms is used as the material of the intermediate layer resist film. By adopting such a multilayer resist process, high etching resistance (etching selection ratio) is ensured, and a fine pattern can be formed with high accuracy. Patent Document 1 is an example of a document that discloses a multilayer resist process.

Japanese Patent Publication No. 04-30740 JP 2010-93049 A

  However, the multilayer resist process has the following problems in the lower layer resist film or the intermediate layer resist film. In the step of forming the lower layer resist film or the intermediate layer resist film, first, a predetermined lower layer (intermediate layer) resist material is first applied on the surface of the wafer (semiconductor substrate). Next, a lower layer (intermediate layer) resist material film having a uniform thickness is formed on the wafer by rotating the wafer at a predetermined number of rotations. Next, while rotating the wafer, by spraying a predetermined organic solvent that dissolves the lower layer (intermediate layer) resist material onto the portion of the lower layer (intermediate layer) resist material film located at the edge of the wafer, the edge rinse is performed. Done. Thereafter, baking is performed at a predetermined temperature to crosslink the lower layer (intermediate layer) resist material, thereby forming a lower layer (intermediate layer) resist film.

  Among the steps of forming the series of lower layer (intermediate layer) resist films, in the step of performing edge rinse, the lower layer (intermediate layer) resist material located on the outer peripheral portion of the wafer is dissolved. The dissolved lower layer (intermediate layer) resist material is blown outward from the rotating wafer. On the other hand, the dissolved lower layer (intermediate layer) resist material remaining on the wafer without being blown may swell and rise when the lower layer (intermediate layer) resist material is dried. For this reason, the film thickness of the lower layer (intermediate layer) resist material film located on the outermost periphery is thicker than the film thickness of the lower layer (intermediate layer) resist material film located on the inner side. The portion where the lower layer (intermediate layer) resist material film swells and rises is called “hump”.

  If processing such as etching is performed on the film to be processed in a state where humps are generated in the lower layer (intermediate layer) resist film, a resist residue of the lower layer resist film or the intermediate layer resist film may be generated. In addition, a residue of the processed film (processed film residue) may be generated. These residues cause generation of foreign matters. Note that Patent Document 2 is an example of a document that discloses a phenomenon in which a hump occurs and a problem that occurs with the occurrence of a hump.

  The present invention has been made to solve the above problems, and one object is to provide a method for manufacturing a semiconductor device without humps, and another object is a method for manufacturing such a semiconductor device. It is to provide a semiconductor device without humps manufactured by

  A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps. A film to be processed is formed on the main surface of the semiconductor substrate. A first resist material is applied so as to cover the film to be processed. A first film is formed by a first resist material applied on the film to be processed. Of the first film covering the film to be processed, a first peripheral exposure process is performed on a portion of the first film located in the first outer peripheral region extending along the outer edge of the semiconductor substrate. By performing the development process with a predetermined developer, the first peripheral exposure process was performed while leaving a portion of the first film located inside the first outer peripheral area where the first peripheral exposure process was not performed. A portion of the first film located in the first outer peripheral region is removed. By applying at least a second resist material so as to cover the first film, a second film made of the second resist material is formed on the first film. A predetermined pattern is formed by subjecting the second film to a predetermined photolithography process. By removing the portion of the first film that is exposed without being covered by the predetermined pattern of the second film, the pattern of the first film corresponding to the predetermined pattern is formed on the first film. The portion of the film to be processed that is exposed without being covered by the pattern of the first film is removed.

  A semiconductor device according to another embodiment of the present invention is a semiconductor device manufactured by the semiconductor device manufacturing method.

  According to the method of manufacturing a semiconductor device according to the embodiment of the present invention, no hump is generated in the first film, thereby reducing a resist residue or a processed film residue. As a result, it is possible to suppress a decrease in yield of the semiconductor device due to the generation of foreign matter. In addition, deterioration of the reliability of the semiconductor device due to film peeling can be suppressed.

  According to the semiconductor device according to another embodiment of the present invention, a decrease in yield or a deterioration in reliability is suppressed.

It is a figure which shows the structure of an example of the resist material used as the lower layer resist film applied to the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment. FIG. 3 is a cross-sectional view showing a step performed after the step shown in FIG. 2 in the same embodiment. In the same embodiment, it is a figure which shows reaction of the part to which the peripheral exposure process was performed in the resist material. FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment. FIG. 6 is a cross-sectional view showing a step performed after the step shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view showing a step performed after the step shown in FIG. 6 in the same embodiment. FIG. 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the same embodiment. In the same embodiment, it is a figure which shows the crosslinking reaction by the high temperature baking process of the resist material used as a lower layer resist film. In the same embodiment, it is a figure which shows the structure of an example of the resist material used as an intermediate | middle layer resist film. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the same embodiment. FIG. 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the same embodiment. In the same embodiment, it is a figure which shows the image of the crosslinking reaction of a base polymer in the resist material used as an intermediate | middle layer resist film. FIG. 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the same embodiment. FIG. 16 is a cross-sectional view showing a step performed after the step shown in FIG. 15 in the same embodiment. FIG. 17 is a cross-sectional view showing a step performed after the step shown in FIG. 16 in the same embodiment. FIG. 18 is a cross-sectional view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view showing a step performed after the step shown in FIG. 18 in the same embodiment. FIG. 20 is a cross-sectional view showing a step performed after the step shown in FIG. 19 in the same embodiment. FIG. 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the same embodiment. FIG. 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in the same embodiment. FIG. 23 is a cross-sectional view showing a step performed after the step shown in FIG. 22 in the same embodiment. FIG. 24 is a cross-sectional view showing a step performed after the step shown in FIG. 23 in the same embodiment. FIG. 25 is a cross-sectional view showing a step performed after the step shown in FIG. 24 in the same embodiment. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on a comparative example. FIG. 27 is a cross-sectional view showing a step performed after the step shown in FIG. 26. FIG. 28 is a cross-sectional view showing a step performed after the step shown in FIG. 27. FIG. 29 is a cross-sectional view showing a step performed after the step shown in FIG. 28. FIG. 30 is a cross-sectional view showing a step performed after the step shown in FIG. 29. FIG. 31 is a cross-sectional view showing a step performed after the step shown in FIG. 30. FIG. 32 is a cross-sectional view showing a step performed after the step shown in FIG. 31. FIG. 33 is a cross-sectional view showing a step performed after the step shown in FIG. 32. FIG. 34 is a cross-sectional view showing a step performed after the step shown in FIG. 33. FIG. 35 is a cross-sectional view showing a step performed after the step shown in FIG. 34. In the same embodiment, it is a figure which shows the structure of the other example of the resist material used as a lower layer resist film. FIG. 37 is a diagram showing a reaction of a portion subjected to peripheral exposure processing when the resist material shown in FIG. 36 is applied in the embodiment. In the same embodiment, it is a figure which shows the structure of the other example of the resist material used as an intermediate | middle layer resist film. It is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 40 is a cross-sectional view showing a step performed after the step shown in FIG. 39 in the same embodiment. FIG. 41 is a cross-sectional view showing a process performed after the process shown in FIG. 40 in the same embodiment. FIG. 42 is a cross-sectional view showing a process performed after the process shown in FIG. 41 in the same Example. FIG. 43 is a cross-sectional view showing a step performed after the step shown in FIG. 42 in the same embodiment. FIG. 44 is a cross-sectional view showing a step performed after the step shown in FIG. 43 in the same embodiment. FIG. 45 is a cross-sectional view showing a step performed after the step shown in FIG. 44 in the same embodiment. FIG. 46 is a cross-sectional view showing a step performed after the step shown in FIG. 45 in the same embodiment. FIG. 47 is a cross-sectional view showing a step performed after the step shown in FIG. 46 in the same embodiment. FIG. 48 is a cross-sectional view showing a step performed after the step shown in FIG. 47 in the same embodiment.

Embodiment 1
Here, the main part of the manufacturing method of the semiconductor device to which the multilayer resist process is applied will be described. As a multilayer resist process, a three-layer resist process of a lower layer resist film, an intermediate layer resist film, and an upper layer resist film is taken as an example. First, a film to be processed to be subjected to predetermined processing is formed on the surface of a semiconductor substrate. Next, a lower resist film is formed in contact with the film to be processed.

  A photosensitive positive resist material is used as a resist material for the lower resist film. With this resist material, a desired pattern is formed by exposure with g-line and development with an aqueous alkaline solution. As an example of such a resist material, here, as shown in FIG. 1, a positive resist material in which a naphthoquinonediazide-based photosensitizer is contained in a novolak-based base polymer is exemplified.

  A predetermined amount of a positive resist material is dropped onto a film to be processed by a resist coating apparatus. Thereafter, the semiconductor substrate is rotated at a predetermined number of revolutions and pre-baked at a predetermined temperature, whereby a uniform film thickness is formed on the surface of the semiconductor substrate 1 (surface of the film 2 to be processed) as shown in FIG. The lower resist material film 3 is formed. Next, as shown in FIG. 3, peripheral exposure processing is performed by irradiating the portion of the lower resist material film 3 located in a predetermined outer peripheral region of the semiconductor substrate 1 with exposure light 54.

  At this time, as shown in FIG. 4, in the portion of the lower resist material film 3 irradiated with the exposure light (lower resist material film 3a), the naphthoquinonediazide group, which is a photosensitizer, is photodecomposed into indenecarboxylic acid. The lower resist material film 3a becomes soluble in an alkali developer. In the peripheral exposure process, light having a wavelength of 250 to 600 nm is usually irradiated using a mercury lamp, but 436 nm (g line), 405 nm (h line) or 365 nm (i line) is used using a wavelength selection filter. You may select and irradiate the light of the wavelength.

  Next, as shown in FIG. 5, a post-exposure bake (PEB) process is performed at a predetermined temperature to form a lower resist film 3b. Next, as shown in FIG. 6, development processing is performed with an alkaline developer (arrow 62). By performing the development process, the lower resist film 3a which is located in the outer peripheral region of the semiconductor substrate and is soluble in the alkaline developer is removed, and as shown in FIG. 3b is formed.

  Next, as shown in FIG. 8, for example, high temperature baking (heat 61) is performed on the lower resist film 3b at a temperature of about 180 ° C. or higher. By performing the high temperature baking treatment, as shown in FIG. 9, a thermal crosslinking reaction occurs in the resist (lower resist film 3b) containing the naphthoquinone diazide photosensitizer, a crosslinked polymer is generated, and the lower resist film 3b is formed. Harden. By curing the lower layer resist film 3b, in the next step, the lower layer resist which becomes insoluble in the solvent of the resist material to be the intermediate layer resist film and does not cause intermixing with the intermediate layer resist material film (intermediate layer resist film) Can be a membrane.

  Next, an intermediate layer resist film is formed in contact with the lower layer resist film. As the resist material to be the intermediate layer resist film, a photosensitive positive resist material is used in the same manner as the resist material to be the lower layer resist film. This resist material is composed of a polymer containing silicon (Si) atoms and a photoacid generator.

  As a polymer containing a silicon (Si) atom, here, for example, as shown in FIG. 10, the side chain has acid decomposability or alkali solubility, and optical properties, adhesion, glass transition temperature, etc. are adjusted. There is a silicon main chain type siloxane polymer which has been chemically modified. Examples of the photoacid generator include a sulfonium salt and an iodonium salt.

  A predetermined amount of resist material to be the intermediate layer resist film is dropped onto the lower layer resist film by a resist coating apparatus. Thereafter, the semiconductor substrate is rotated at a predetermined number of revolutions, and a pre-baking process is performed at a predetermined temperature, thereby forming the intermediate layer resist material layer 4 so as to cover the lower layer resist film 3b as shown in FIG. The

  Next, as shown in FIG. 12, the peripheral exposure process is performed by irradiating the exposure light 54 to the portion of the intermediate layer resist material film 4 located in a predetermined outer peripheral region of the semiconductor substrate 1. In the portion of the intermediate layer resist film 4 irradiated with the exposure light (interlayer layer resist material film 4a), the photoacid generator is photolyzed to generate an acid.

  Next, as shown in FIG. 13, the intermediate layer resist film 4b is formed by performing PEB processing (heat 61) at a predetermined temperature. In the exposed portion, the acid acts as a catalyst to decompose the acid-decomposable group of the base polymer, and the exposed portion becomes the intermediate layer resist material film 4a having a property soluble in an alkali developer.

  Next, as shown in FIG. 15, development processing is performed with an alkaline developer (arrow 62). By performing the development process, the portion of the intermediate layer resist film 4a that is soluble in the alkaline developer located in the outer peripheral region of the semiconductor substrate is removed, and the outer peripheral edge is cut as shown in FIG. Intermediate layer resist film 4b is formed.

  Next, as shown in FIG. 17, for example, high-temperature baking (heat 61) is performed on the intermediate layer resist film 4b at a temperature of about 180 ° C. or higher. By performing the high temperature baking treatment, as shown in FIG. 14, the cross-linking reaction by the acid generated in the intermediate layer resist material film 4 is promoted, the base polymer 41 is cross-linked to form a cross-linked polymer 43, and the intermediate layer resist is formed. The film is cured. When the intermediate layer resist film 4b is cured, in the next step, the intermediate layer resist film becomes insoluble in the solvent of the resist material to be the upper layer resist film and does not cause intermixing with the upper layer resist material film (upper layer resist film). Can be.

  Next, an upper resist film is formed in contact with the intermediate resist film. As a resist material to be an upper resist film, a positive resist material is taken as an example. A predetermined amount of the resist material to be the upper resist film is dropped onto the intermediate resist film by a resist coating apparatus. Thereafter, by rotating the semiconductor substrate at a predetermined number of revolutions and performing a pre-baking process at a predetermined temperature, as shown in FIG. 18, the upper layer resist material film 5 is formed so as to cover the intermediate layer resist film 4b. The

  Next, a predetermined pattern (not shown) is exposed to a portion of the upper resist material film located in the region where the chip is formed by performing a predetermined photolithography process on the upper resist material film 5. Next, as shown in FIG. 19, peripheral exposure processing is performed by irradiating the portion of the upper resist material film 5 located in a predetermined outer peripheral region of the semiconductor substrate 1 with exposure light 54. Next, the upper resist film 5b (see FIG. 20) is formed by subjecting the upper resist material film 5 subjected to the photoengraving process to PEB treatment at a predetermined temperature.

  Next, by performing development processing with a predetermined developer (arrow 62), a predetermined pattern is formed on the upper resist film 5b in the chip formation region CR as shown in FIG. On the other hand, in the outer peripheral portion PR of the semiconductor substrate 1, the upper resist film 5b is removed, and the surface of the lower resist film 3b and the surface of the intermediate resist film 4b without humps are exposed. Thus, as shown in FIG. 21, a lower resist film 3b, an intermediate resist film 4b, and an upper resist film 5b for patterning the film to be processed 2 are formed.

Next, the processed film 2 is patterned by the lower resist film 3b, the intermediate resist film 4b, and the upper resist film 5b. First, as shown in FIG. 22, by etching the intermediate layer resist film 4b using the upper layer resist film 5b as a mask, the pattern of the upper layer resist film 5b is transferred to the intermediate layer resist film 4b. In this case, a resist material containing silicon (Si) atoms is applied as a resist material to be an intermediate layer resist film, and etching is performed using, for example, a fluorine-based gas such as CF ₄ , so that the upper resist film 5b On the other hand, a high etching selectivity can be obtained.

Next, as shown in FIG. 23, by etching the lower resist film 3b using the intermediate resist film 4b as a mask, the pattern of the upper resist film 5b becomes the lower resist film 3b via the intermediate resist film 4b. Transcribed. In this case, for example, etching is performed using a gas such as oxygen (O ₂ ) or nitrogen (N ₂ ) / hydrogen (H ₂ ) to obtain a high etching selectivity with respect to the intermediate layer resist film 4 b. Can do.

  Next, as shown in FIG. 24, the processed film 2 is patterned by etching the processed film 2 using the lower resist film 3b as a mask. Thereafter, as shown in FIG. 25, oxygen plasma ashing is performed to remove the lower resist film 3b and the like remaining on the semiconductor substrate 1, and the patterning of the film 2 to be processed is completed.

  In the semiconductor device manufacturing method described above, the portion of the lower resist material film 3 and the portion of the intermediate layer resist material film 4 that are respectively located in predetermined outer peripheral regions of the semiconductor substrate are removed, and the outer peripheral portion PR of the semiconductor substrate 1 is removed. No hump is formed on the lower resist material film 3 or the intermediate resist material film 4. Thereby, resist residues or processed film residues can be reduced. This will be described with a comparative example.

  In the method of manufacturing a semiconductor device according to the comparative example, first, a lower layer resist material is applied onto a film to be processed formed on the surface of the semiconductor substrate by a resist coating apparatus, and the semiconductor substrate is rotated at a predetermined rotational speed. As a result, as shown in FIG. 26, a lower resist material film 103 having a uniform film thickness is formed on the surface of the semiconductor substrate 101.

  Next, as shown in FIG. 27, edge rinsing is performed by discharging the solvent 165 from the solvent discharge nozzle 154 and spraying it onto the lower resist material film 103. Next, the lower resist material film 103 is dried. At this time, as shown in FIG. 28, the components of the lower resist material film dissolved and left on the semiconductor substrate 101 may swell and rise to generate a hump 103a. Next, as shown in FIG. 29, the lower resist material film 103 is cross-linked by performing a baking process 166 on the semiconductor substrate 101 at a predetermined temperature. As shown in FIG. It is formed.

  Next, an intermediate layer resist film 104b is formed through a process similar to the process of applying an intermediate layer resist material to the surface of the semiconductor substrate 101 and forming the lower layer resist film. In the intermediate layer resist film 104b, a hump 104a may be generated when the intermediate layer resist material layer is dried (see FIG. 31). Next, an upper resist material is applied to the surface of the semiconductor substrate 101, and the upper resist film 105b is formed through a process similar to the process of forming the upper resist film in the above-described embodiment. Thus, as shown in FIG. 31, a lower resist film 103b, an intermediate resist film 104b, and an upper resist film 105b for patterning the film to be processed 102 are formed. Humps 103a and 104a are observed in the lower resist film 103b or the intermediate resist film 104b exposed on the outer periphery of the semiconductor substrate 101.

  Next, the processing target film 102 is patterned by the lower resist film 103b, the intermediate resist film 104b, and the upper resist film 105b. First, as shown in FIG. 32, the upper resist film 105b is used as a mask to etch the intermediate resist film 104b, whereby the pattern of the upper resist film 105b is transferred to the intermediate resist film 104b. At this time, the portion of the intermediate layer resist film 104b where the hump 104a is generated often becomes a resist residue 104c. Further, the hump 103a of the lower resist film 103b often remains without being etched.

  Next, as shown in FIG. 33, by etching the lower resist film 103b using the intermediate resist film 104b as a mask, the pattern of the upper resist film 105b is changed to the lower resist film 103b via the intermediate resist film 104b. Transcribed. At this time, the portion of the lower resist film 103b where the hump 103a is generated often becomes the resist residue 103c in the outer peripheral portion of the semiconductor substrate 101 to be removed up to the lower resist film 103b. . Further, at the position where the resist residue 104c is located, the resist residue 104c may serve as a mask, and the portion of the lower resist film 103b located immediately below the resist residue 104c may become the resist residue 103d.

  As described above, in the method for manufacturing a semiconductor device according to the comparative example, at the time when a resist mask (such as the lower layer resist film 103b) for patterning the film to be processed 102 is formed, the resist residue is formed on the outer periphery of the semiconductor substrate 101. In many cases, 103c, 103d, and 104c exist.

  Next, as shown in FIG. 34, the processed film 102 is patterned by etching the processed film 102 using the lower resist film 103b and the like as a mask. At this time, where the resist residues 104c and 103d are located, the resist residue serves as a mask, and the portion of the processed film 102 becomes the processed film residue 102b. Further, even in the place where the resist residue 103c is located, the portion of the film to be processed 102 becomes the film residue 102a to be processed.

  Thereafter, as shown in FIG. 35, the lower resist film 103b and the like are removed by performing an oxygen plasma ashing process. At this time, the resist residue 103d may not be completely removed. Further, the processed film residues 102a and 102b are not removed and are left on the outer peripheral portion of the semiconductor substrate 101.

  In the manufacturing method of the semiconductor device according to the comparative example, when the manufacturing process proceeds in a state where the processed film residues 102a and 102b and the like exist on the outer peripheral portion of the semiconductor substrate, the processed film residues 102a and 102b and the like become foreign matters. There is a risk of decreasing the yield of the semiconductor device. In addition, the reliability of the semiconductor device may be lowered due to film peeling.

  In addition, after patterning the upper resist film, if it is necessary to perform a regeneration process (rework process) due to defects such as dimensions and overlay accuracy, the intermediate resist film is etched back using a fluorine-based gas, The lower resist film is ashed using oxygen gas. For this reason, the portion of the intermediate layer resist film or the lower layer resist film cannot often be completely removed at the place where the hump is generated, which becomes a cause of generation of foreign matters.

  On the other hand, there is a method of removing the processed film residues 102a, 102b and the like remaining on the outer peripheral portion of the semiconductor substrate 101, and bevel etching or bevel CMP (Chemical Mechanical Polishing) is generally known. By performing this bevel etching after performing a predetermined etching process and regeneration process, the processed film residues 102a, 102b, etc. are removed. However, when these processes are performed, the underlying semiconductor substrate 101 is damaged, which may affect the yield and reliability of the semiconductor device, and limit the number of times the regeneration process is performed. There is also a need.

  On the other hand, in the method for manufacturing a semiconductor device described above, positive resist materials having photosensitivity are applied as the lower layer resist film and the intermediate layer resist film, respectively, and lower layers positioned in predetermined outer peripheral regions of the semiconductor substrate, respectively. The resist (material) film portion and the intermediate layer resist (material) film portion are removed. As a result, unlike the conventional three-layer resist process, hump does not occur in the outer peripheral portion of the semiconductor substrate, and the decrease in the yield of the semiconductor device due to the generation of foreign matters can be suppressed. In addition, deterioration of the reliability of the semiconductor device due to film peeling can be suppressed.

  In addition, after patterning the upper resist film, all resists can be used without damaging the underlying layer (film, semiconductor substrate, etc.) even if it is necessary to perform a regeneration process due to defects such as dimensions or overlay accuracy. The film can be completely removed, and then a resist pattern can be formed again. Further, since there is no damage to the underlying semiconductor substrate due to the regeneration process, there is no need to limit the number of times the regeneration process is performed.

(Registration materials)
In the semiconductor device manufacturing method described above, a positive resist material in which a naphthoquinonediazide-based photosensitizer is contained in a novolak-based base polymer is taken as an example of a resist material to be a lower resist film. In addition, as a resist material for forming the intermediate layer resist film, a polymer containing a silicon (Si) atom and having a siloxane polymer as a skeleton is given as an example. Here, a resist material applied as a lower layer resist film or an intermediate layer resist film in the above-described semiconductor device manufacturing method will be described.

  First, a resist material applied as a conventional general lower layer resist film or intermediate layer resist film in a three-layer resist process is composed of a base polymer, a crosslinking agent, a thermal acid generator, and a solvent. In this resist material, the thermal acid generator is decomposed by baking after spin coating, and an acid is generated in the resist material film. The generated acid causes a crosslinking reaction between the base polymer and the crosslinking agent.

  On the other hand, the resist material applied as the lower layer resist film or the intermediate layer resist film used in the above-described semiconductor device manufacturing method has photosensitivity and solubility in an alkali developer, and the exposed portion is dissolved and removed. Positive development characteristics. Further, this resist material has a property of being cured by high-temperature baking or curing.

(About lower layer resist material)
Since the lower resist film is required to have high etching resistance, flattening of the underlying step and antireflection effect, a base polymer generally containing a high concentration of aromatic rings such as phenolic resin is applied. Is done. Further, in the lower resist film, it is necessary to crosslink the base polymer and insolubilize it in the resist material solvent so as not to cause intermixing with the resist material to be the intermediate resist film applied thereon.

  In the method for manufacturing a semiconductor device described above, a positive resist material in which a naphthoquinone diazide photosensitizer is contained in a novolak base polymer is taken as an example. In addition to this, as a resist material for the lower resist film, a chemically amplified positive photoresist material composed of a photoacid generator (PAG) and a polyvinylphenol polymer may be applied. it can. FIG. 36 shows an example of the structure of such a chemically amplified positive photoresist material. In this positive photoresist material, polyvinyl acetalized ethylphenol is applied as a base polymer, and triphenylsulfonium trifluoromethanesulfonate is applied as a photoacid generator.

  FIG. 37 shows the reaction of the portion irradiated with the exposure light when such a chemically amplified positive photoresist material is used. As shown in FIG. 37, in the portion of the positive photoresist material irradiated with the exposure light, the photoacid generator is photolyzed to generate an acid (proton). The generated acid acts as a catalyst to remove the acetal group of the base polymer and becomes soluble in an alkali developer.

  The base polymer of the resist material used as the lower resist film is a polymer containing a naphthalene skeleton, an anthracene skeleton, a fluorene skeleton, a pyrene skeleton, etc. in addition to a polymer containing a benzene skeleton such as the above-mentioned novolak polymer or polyvinylphenol polymer. These resist materials are advantageous for imparting higher etching resistance as a lower resist film.

  As the photoacid generator, a sulfonium salt or an iodonium salt is more effective, but in addition to these, an imide sulfonate, a diazomethane, an organic halide, or the like may be used.

  The resist material used as the lower resist film has photosensitivity and solubility in an alkali developer, and is cured by high-temperature baking, DUV curing, electron beam curing, or curing by ion implantation such as argon. If it has a characteristic, it will not be restricted to the resist material mentioned above. The resist material may contain a cross-linking agent.

(Regarding the interlayer resist material)
A polymer containing a high concentration of silicon (Si) atoms is used for the intermediate layer resist film in order to have an etching selectivity with respect to the upper layer resist film and the lower layer resist film. In addition, the intermediate layer resist film does not dissolve in the solvent of the resist material that crosslinks the polymer and becomes the upper layer resist film so that the intermediate layer resist film and the upper layer resist (material) film applied thereon are not intermixed. It is necessary to do so. The resist material further needs to have photosensitivity and positive development characteristics.

  In the semiconductor device manufacturing method described above, a photosensitive positive resist material including a polymer having a siloxane polymer as a skeleton as a polymer containing silicon (Si) atoms and a photoacid generator is taken as an example. In addition to this, as shown in FIG. 38, the polymer of the intermediate layer resist includes a group containing a silicon (Si) atom in the skeleton of an acrylic polymer and the like, and is acid-decomposable or alkali-soluble, optical characteristics, adhesion It is also possible to apply a silicon side chain polymer into which a side chain for adjusting the properties, glass transition temperature, etc. is introduced.

  As the photoacid generator, sulfonium salts and iodonium salts are most effective, but in addition to these, imide sulfonates, diazomethanes, organic halides, and the like may be applied. When the exposure light is irradiated, the photoacid generator is photolyzed to generate an acid. The generated acid becomes a catalyst, decomposes the acid-decomposable group of the base polymer, and becomes soluble in an alkali developer.

  The resist material for the intermediate layer resist film has photosensitivity and solubility in an alkali developer, and is cured by high-temperature baking, DUV curing, electron beam curing, curing by ion implantation such as argon, and the like. If it has, it will not be restricted to the resist material mentioned above. The resist material may contain a cross-linking agent.

(About upper layer resist material)
In the semiconductor device manufacturing method described above, the case where the peripheral exposure process is performed is described by taking a positive resist material as an example of the resist material to be the upper resist film. The resist material to be the upper resist film is not limited to a positive resist material, and a negative resist material may be applied. In this case, the upper resist (material) film located in the outer peripheral region of the semiconductor substrate is not irradiated with the exposure light, and the upper resist (material) film located in the outer peripheral region is removed by development processing. That's fine.

Embodiment 2
Here, an example of a more specific method for manufacturing a semiconductor device to which a multilayer resist process is applied will be described. First, as shown in FIG. 39, the insulating film 19 is formed by subjecting the surface of the semiconductor substrate 1 to thermal oxidation. On the insulating film 19, for example, a conductive film 20 including a polysilicon film and a metal silicide film thereof is formed.

  Next, a three-layer resist process is applied as a photolithography process for patterning the gate electrode. That is, a process similar to the series of three-layer resist processes shown in FIGS. 1 to 21 is applied to form a lower resist film 21, an intermediate resist film 22, and an upper resist film 23 as shown in FIG. . In the chip formation region CR in the semiconductor substrate 1, a resist pattern 23a of the upper resist film 23 for patterning the gate electrode is formed. On the other hand, in the outer peripheral portion PR of the semiconductor substrate 1, the intermediate layer resist film 22 and the lower layer resist film 21 without hump are exposed.

  Next, by etching the intermediate layer resist film 22 using the resist pattern 23a of the upper layer resist film 23 as a mask, the resist pattern 23a is transferred to the intermediate layer resist film 22 as a resist pattern 22a. Further, the intermediate layer resist film By etching the lower resist film 21 using the resist pattern 22a of 22 as a mask, the resist pattern 23a is transferred to the lower resist film 21 as the resist pattern 21a.

  Thus, as shown in FIG. 41, resist patterns 23a, 22a, and 21a are formed by the lower layer resist film, the intermediate layer resist film, and the upper layer resist film for patterning the gate electrode. FIG. 41 shows a state where the resist pattern 23a of the upper resist film 23 is left, but at least the resist pattern 21a of the lower resist film 21 may be left.

  Next, the conductive film 20 is etched using the resist patterns 23a, 22a, and 21a as a mask, thereby forming the gate electrode 20a as shown in FIG. Next, using the gate electrode 20a as a mask, an n-type impurity region 24a is formed by, for example, implanting an n-type impurity with a low dose into the semiconductor substrate 1 (see FIG. 43). Next, an insulating film (not shown) is formed so as to cover the gate electrode 20a. By performing anisotropic etching on the insulating film, a sidewall insulating film 25 is formed on the side wall of the gate electrode 20a (see FIG. 43).

  Next, n-type high-concentration impurity regions 24b are formed by implanting n-type impurities with a high dose using the gate electrode 20a and the sidewall insulating film 25 as a mask. Thus, as shown in FIG. 43, a MOS (including a gate electrode 20a, an n-type low-concentration impurity region 24a, and an n-type high-concentration impurity region 24b formed on the surface of the semiconductor substrate 1 with the gate insulating film 19a interposed therebetween. Metal Oxide Semiconductor) transistors are formed. Next, an interlayer insulating film 26 such as a silicon oxide film is formed on the semiconductor substrate 1 so as to cover the gate electrode 20a and the like (see FIG. 44).

  Next, a three-layer resist process is applied as a photoengraving process for forming contact holes in the interlayer insulating film 26. That is, a process similar to the series of three-layer resist processes shown in FIGS. 1 to 21 is applied to form a lower resist film 27, an intermediate resist film 28, and an upper resist film 29 as shown in FIG. . In the chip formation region CR in the semiconductor substrate 1, a resist pattern 29a of the upper resist film 29 for forming a contact hole is formed. On the other hand, in the outer peripheral portion PR of the semiconductor substrate 1, the intermediate layer resist film 28 and the lower layer resist film 27 without hump are exposed.

  Next, the resist pattern 29a of the upper resist film 29 is transferred to the intermediate resist film 28 and the lower resist film 27 to form a resist pattern (not shown) for forming contact holes. By performing anisotropic etching on interlayer insulating film 26 using the resist pattern as a mask, contact hole 30 exposing the surface of n-type high concentration impurity region 24b is formed as shown in FIG. Thereafter, the resist pattern is removed. Next, as shown in FIG. 46, a predetermined conductive film 31 including a barrier metal or the like is formed on the interlayer insulating film 26 so as to fill the contact hole.

  Next, a three-layer resist process is applied as a photolithography process for patterning the conductive film 31. That is, a process similar to the series of three-layer resist processes shown in FIGS. 1 to 21 is applied to form a lower resist film 32, an intermediate resist film 33, and an upper resist film 34 as shown in FIG. . In the chip formation region CR in the semiconductor substrate 1, a resist pattern 34a of the upper resist film 34 for patterning the conductive film 31 is formed. On the other hand, the intermediate layer resist film 33 and the lower layer resist film 32 without hump are exposed at the outer peripheral portion PR in the semiconductor substrate 1.

  The resist pattern 34a of the upper resist film 34 is transferred to the intermediate resist film 33 and the lower resist film 32, and a resist pattern (not shown) for patterning the conductive film is formed. By performing anisotropic etching on the conductive film 31 using the resist pattern as a mask, a wiring 31a electrically connected to the n-type high concentration impurity region 24b is formed as shown in FIG. Thereafter, the lower resist film 32 and the like are removed. Thus, a main part of the semiconductor device including the transistor is formed.

  In the above-described semiconductor device manufacturing method to which the three-layer resist process is applied as the photoengraving process, by performing the peripheral exposure process, the lower resist (material) film portion located in the predetermined outer peripheral region of the semiconductor substrate and the middle A layer resist (material) film part is made soluble in a developer, and the part is dissolved in the developer and removed to form a lower resist film and an intermediate resist film without humps. it can. Thereby, the resist residue or the processed film residue is reduced in the outer peripheral portion of the semiconductor substrate 1 after patterning the processed film such as the conductive film 20, the interlayer insulating film 26, and the conductive film 31. As a result, it is possible to suppress a decrease in yield of the semiconductor device due to the generation of foreign matter, and it is possible to suppress deterioration in reliability of the semiconductor device due to film peeling.

  Note that the above-described three-layer resist process is not limited to the steps described in the first embodiment or the second embodiment, and can be widely applied to steps in which photolithography is performed. The photolithography process is not limited to the three-layer resist process, and the resist pattern transferred to the photosensitive resist has an etching resistance in relation to the etching of the film to be processed, and the photosensitive resist film. As long as it is a process for transferring to a two-layer resist process, it can be applied to a two-layer resist process or a four-layer or more resist process.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is effectively used for a manufacturing method of a semiconductor device to which a multilayer resist process is applied.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Processed film, 3 Lower resist material film, 3b Lower resist film, 4 Intermediate resist material film, 4b Intermediate resist film, 5 Upper resist material film, 5b Upper resist film, 19 Insulating film, 19a Gate Insulating film, 20 conductive film, 20a gate electrode, 21 lower resist film, 21a resist pattern, 22 intermediate resist film, 22a resist pattern, 23 upper resist film, 23a resist pattern, 24a n-type low concentration impurity region, 24b n-type High concentration impurity region, 25 sidewall insulating film, 26 interlayer insulating film, 27 lower resist film, 28 intermediate resist film, 29 upper resist film, 29a resist pattern, 30 contact hole, 31 conductive film, 31a conductive film, 32 lower layer Resist film, 33 Intermediate layer resist film 34 upper resist film, 34a resist pattern, 41 a base polymer, 42 crosslinking agent, 43 crosslinked polymers, 54 exposure light, 61 heat, 62 developer.

Claims (5)

Forming a film to be processed on the main surface of the semiconductor substrate;
Applying a first resist material so as to cover the film to be processed;
Forming a first film with a first resist material applied on the film to be processed;
Performing a first peripheral exposure process on a portion of the first film located in a first outer peripheral region extending along an outer edge of the semiconductor substrate in the first film covering the processed film;
The first peripheral exposure process is performed by performing a development process with a predetermined developer so as to leave a portion of the first film positioned inside the first outer peripheral area where the first peripheral exposure process is not performed. Removing the portion of the first film located in the first outer peripheral region to which is applied;
Forming a second film of the second resist material on the first film by applying at least a second resist material so as to cover the first film;
Forming a predetermined pattern by subjecting the second film to a predetermined photolithography process;
By removing a portion of the first film that is exposed without being covered by the predetermined pattern of the second film, the first film has a first film corresponding to the predetermined pattern. Forming a pattern;
And a step of removing a portion of the film to be processed that is exposed without being covered by the pattern of the first film. Forming the predetermined pattern on the second film,
Performing a second peripheral exposure process on a portion of the second film located in a second outer peripheral region extending along an outer edge of the semiconductor substrate in the second film;
The method of manufacturing a semiconductor device according to claim 1, further comprising: removing the portion of the second film located in the second outer peripheral region by performing the development process. Forming the predetermined pattern on the second film,
The second film located inside the second outer peripheral area except for the second film part located in the second outer peripheral area extending along the outer edge of the semiconductor substrate in the second film. Irradiating the part of the film with exposure light;
The method for manufacturing a semiconductor device according to claim 1, further comprising: removing the portion of the second film located in the second outer peripheral region that is not irradiated with the exposure light by performing the development process. In the step of forming the second film, before applying the second resist material,
Applying a third resist material so as to cover the first film;
Performing a third peripheral exposure process on a portion of the third resist material located in a third outer peripheral region extending along an outer edge of the semiconductor substrate, of the third resist material covering the first film; ,
The third peripheral exposure process is performed by performing a development process with a predetermined developer so as to leave a portion of the third resist material located inside the third outer peripheral area where the third peripheral exposure process is not performed. Removing the portion of the third resist material located in the third outer peripheral region to which is applied,
Forming the predetermined pattern on the second film,
Forming the predetermined pattern on a resist film formed of the second resist material;
The other resist film corresponding to the predetermined pattern is removed by removing a portion of the other resist film formed by the third resist material that is exposed without being covered by the predetermined pattern formed on the resist film. Forming a resist film pattern,
The step of forming the pattern of the first film includes a step of removing at least a portion of the first film exposed without being covered by the pattern of the other resist film. The manufacturing method of the semiconductor device in any one.   A semiconductor device formed by the method for manufacturing a semiconductor device according to claim 1.

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