JP2013016730A - Variable capacitance device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable capacitance device in which circuitry can be downsized and power consumption can be reduced.SOLUTION: In a variable capacitance device, a capacitance detection circuit 31 outputs a detection signal Sx corresponding to a capacitance value of a driving capacitor C1 in a variable capacitance device 2, and a reference signal Sy being a reference. A driving voltage control circuit 21 compares the detection signal Sx with the reference signal Sy, controls a driving voltage Vcont according to the comparison results, and increases or decreases capacitance of the driving capacitor C1. The driving voltage Vcont is applied to one end of the driving capacitor C1, and a detection current Icont from a current detection circuit 33 in a capacity detection circuit 31 is input periodically to the other end of the driving capacitor C1. Consequently, when the driving capacitor C1 is connected to the current detection circuit 33, a voltage on the other end of the driving capacitor C1 increases in accordance with the capacitance value of the driving capacitor C1 and amount of the detection current Icont, thereby the detection signal Sx corresponding to that voltage is output.

Description

  The present invention relates to a variable capacitance device including a variable capacitance element whose capacitance changes according to a driving voltage.

  In general, a variable capacitance element whose capacitance changes according to the drive voltage, a capacitance detection circuit that detects the capacitance of the variable capacitance element, and a capacitance detection value that is detected by the capacitance detection circuit approaches a desired value. There is known a variable capacitance device including a drive voltage control circuit for controlling a drive voltage (see, for example, Patent Document 1). Patent Document 1 discloses a configuration in which a ground is connected to one end of a variable capacitance element, and the other end is connected to a drive voltage supply source via a switch and a current source. In this case, the variable capacitance element is repeatedly charged and discharged by the switching operation of the switch, and the capacitance of the variable capacitance element is detected by the time average of the voltage applied to the variable capacitance element.

JP-A-11-274401

  By the way, in the variable capacitance device described in Patent Document 1, a voltage applied to the other end of the variable capacitance element is detected, and the drive voltage is controlled so that the detected voltage becomes a desired voltage value. At this time, the drive voltage becomes a high voltage of about several tens of volts. For this reason, when the drive voltage applied to the variable capacitance element is directly detected, it is necessary to make the capacitance detection circuit, the comparator for comparing the output, etc., a high breakdown voltage configuration, and the circuit becomes large. There is. In addition to this, charging and discharging of the variable capacitance element are repeated to detect the capacitance of the variable capacitance element, so that power corresponding to the product of the current from the current source and the drive voltage is consumed. Therefore, there is a problem that power consumption is large.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a variable capacitance device capable of downsizing a circuit and reducing power consumption.

  In order to solve the above-mentioned problem, the invention of claim 1 is a variable capacitance element whose capacitance changes according to a drive voltage, a capacitance detection circuit for detecting the capacitance of the variable capacitance device, and the capacitance detection. And a drive voltage control circuit that controls the drive voltage based on a detected value of capacitance by a circuit, wherein the drive voltage is supplied to one end side of the variable capacitance element, and the capacitance detection circuit Includes a detection current circuit that is driven by a power supply voltage lower than the drive voltage, and a detection switch that selectively connects the other end of the variable capacitance element to either the detection current circuit or the ground. And the capacitance detection circuit outputs the detection value according to a voltage applied to the other end of the variable capacitance element when the variable capacitance element and the detection current circuit are connected by the detection switch. It is characterized in that a configuration in which force.

  According to a second aspect of the present invention, a reference capacitor having one end connected to the drive voltage is provided, and the capacitor detection circuit includes a reference current circuit driven by the power supply voltage, and the other end of the reference capacitor for the reference. A reference switch selectively connected to either the current circuit or the ground, and the capacitance detection circuit connects the reference capacitor and the reference current circuit with the reference switch. The reference value is output in accordance with the voltage applied to the other end side.

  According to a third aspect of the present invention, the detection current circuit and the reference current circuit are configured using a current mirror circuit that copies a current flowing through a single common current source.

  According to a fourth aspect of the present invention, the drive voltage control circuit includes a comparator that compares the detected value of the capacitance with a reference value, and boosts or lowers the drive voltage according to a comparison result of the comparator. It is configured.

  According to the first aspect of the present invention, when the variable capacitance element and the detection current circuit are connected by the detection switch, a current flows from the detection current circuit toward the variable capacitance element. At this time, the voltage on the other end side of the variable capacitance element is boosted according to the capacitance of the variable capacitance element. Therefore, the capacitance detection circuit can output a detection value according to the voltage applied to the other end side of the variable capacitance element when the variable capacitance element and the detection current circuit are connected by the detection switch. .

  In addition, a driving voltage is supplied to one end side of the variable capacitance element, and a detection current circuit is connected to the other end side of the variable capacitance element. For this reason, the voltage applied to the other end side of the variable capacitance element is the power supply voltage supplied to the detection current circuit at the maximum. Therefore, the voltage corresponding to the detection value output from the capacitance detection circuit can be made lower than the drive voltage, and the capacitance detection circuit and the like can be downsized.

  In addition, when the connection and disconnection of the variable capacitance element and the detection current circuit are repeated in order to detect the capacitance of the variable capacitance element, the product of the current from the detection current circuit and the power supply voltage is calculated. The corresponding power is consumed. For this reason, compared with the case where the electric power according to a drive voltage is consumed like a prior art, power consumption can be reduced.

  In the invention of claim 2, when the reference capacitor and the reference current circuit are connected by the reference switch, a current flows from the reference current circuit toward the reference capacitor. At this time, the voltage on the other end side of the reference capacitor is boosted according to the capacitance of the reference capacitor. For this reason, when the reference capacitance and the reference current circuit are connected by the reference switch, the capacitance detection circuit determines the capacitance reference of the variable capacitance element according to the voltage applied to the other end of the reference capacitance. Can be output.

  According to another aspect of the present invention, the detection current circuit and the reference current circuit are configured using a current mirror circuit that copies the current flowing through the common current source. For this reason, since a single common current source is used, it is possible to suppress variations in the detected capacitance value and the reference value, compared to the case where separate current sources and voltage sources are used.

  According to a fourth aspect of the present invention, the drive voltage control circuit includes a comparator that compares the detected capacitance value with a reference value. At this time, since the capacitance detection circuit outputs a voltage lower than the power supply voltage as the capacitance detection value, the input voltage of the comparator can be lower than the power supply voltage lower than the drive voltage, and the comparator has a low breakdown voltage. Circuit devices can be used.

1 is an overall configuration diagram showing a variable capacitance device according to a first embodiment of the present invention. It is a top view which shows the variable capacitance element in FIG. FIG. 3 is a cross-sectional view of the variable capacitor when viewed from the direction of arrows III-III in FIG. FIG. 2 is a block diagram illustrating a capacitance detection circuit in FIG. 1. It is a circuit diagram which shows the capacity | capacitance detection circuit in FIG. When the capacitance value of the drive capacitance is smaller than the target value, a characteristic line showing the time change of the first and second clock signals, the detection signal, the reference signal, the comparison result signal, the sampling signal, and the output signal of the level conversion circuit FIG. A characteristic line showing time changes of the first and second clock signals, the detection signal, the reference signal, the comparison result signal, the sampling signal, and the output signal of the level conversion circuit when the capacitance value of the drive capacitance is larger than the target value. FIG. It is a characteristic diagram which shows the time change of a drive voltage. It is a characteristic diagram which shows the relationship between the voltage between terminals of drive capacity, and the capacitance value of drive capacity and variable capacity. It is a circuit diagram which shows the capacity | capacitance detection circuit by 2nd Embodiment. It is a circuit diagram which shows the capacity | capacitance detection circuit by a modification.

  Hereinafter, a variable capacity device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 shows a variable capacitance device 1 according to an embodiment. The variable capacitance device 1 includes a variable capacitance element 2, a drive voltage control circuit 21, and a capacitance detection circuit 31.

  First, the variable capacitance element 2 will be described with reference to FIGS. 2 and 3.

  The variable capacitance element 2 is configured by MEMS (Micro Electro Mechanical Systems) driven by electrostatic force. The variable capacitance element 2 includes a substrate 3, lower drive electrodes 4A, 4B, and 5, a dielectric film 6, a beam portion 7, pad electrodes 8, 9A, 9B, 10A, and 10B, and resistance patterns 10C and 10D.

  The substrate 3 is made of, for example, a rectangular glass substrate. The beam portion 7 is formed in a rectangular flat plate shape in a plan view and an L shape in a side view. The beam portion 7 is a movable structure having a cantilever structure (spring structure) in which the right end portion in FIG. 2 is a support portion joined to the substrate 3 and the main portion is supported while being separated from the substrate 3. Part. The beam portion 7 is made of, for example, a low-resistance Si substrate (silicon substrate) having a resistivity of 0.01 Ωcm or less as a conductive substrate, and uses, for example, P (phosphorus), As (arsenic), B (boron), or the like as a dopant. ing.

  The lower drive electrodes 4A and 4B are each L-shaped and formed on the upper surface of the substrate 3, and have long line-shaped end portions along the axial direction of the beam portion 7 (left and right directions in FIG. 2). . The lower drive electrode 5 is formed in a U-shape on the upper surface of the substrate 3, and is arranged so that both sides of the lower drive electrodes 4A and 4B are sandwiched between both ends of a line shape that is long along the axial direction of the beam portion 7. To do. The dielectric film 6 is formed of, for example, a rectangular tantalum pentoxide having a thickness of about 200 nm, and is laminated on the substrate 3 so as to cover the end portions of the lower drive electrodes 4A and 4B and the both end portions of the lower drive electrode 5. The lower drive electrode 4A is connected to an input terminal (or output terminal) of an RF signal (high frequency signal) via a pad electrode 9A, and the lower drive electrode 4B is connected to an output terminal (or input terminal) of the RF signal. Connected through. The lower drive electrode 5 is connected to an input terminal of a DC voltage (DC voltage) that becomes the drive voltage Vcont via the pad electrode 10A and the resistance pattern 10C. The beam portion 7 is connected to the ground via the pad electrodes 8 and 10B and the resistance pattern 10D. The resistance patterns 10C and 10D are formed using, for example, a titanium oxide thin film having a thickness of about 5 nm and have a resistance of about 200 kΩ.

  Both end portions of the lower drive electrode 5 are arranged to face the beam portion 7 with the dielectric film 6 therebetween, and the lower drive electrode 5 and the beam portion 7 constitute a drive capacitor portion 11. When the drive voltage Vcont is applied from the drive voltage control circuit 21, the drive capacity unit 11 generates a drive capacity C 1 (electrostatic capacity) between both ends of the lower drive electrode 5 and the beam part 7. The drive capacitor C1 deforms the beam portion 7 by electrostatic attraction and brings the beam portion 7 into contact with the dielectric film 6 from the tip. The higher the drive voltage Vcont is, the larger the contact area between the beam portion 7 and the dielectric film 6 is.

  The lower drive electrodes 4A and 4B are arranged to face the beam portion 7 with the dielectric film 6 therebetween, and the lower drive electrodes 4A and 4B and the beam portion 7 constitute a variable capacitance unit 12. The variable capacitance unit 12 is used in a circuit that handles radio frequencies of, for example, several hundred MHz to several GHz, and varies according to the contact area between the beam portion 7 and the dielectric film 6 (capacitance). Produce. Since there is a possibility that a high-frequency signal leaks from the variable capacitance portion 12 to the drive voltage control circuit 21 or the ground via the beam portion 7, resistance patterns 10C and 10D are formed here for the purpose of blocking the leakage high-frequency signal. ing.

  2 has a structure in which a signal (voltage) is directly applied between an electrode pair including the lower drive electrode 5 and the beam portion 7 (hereinafter, this structure is referred to as an MIM structure). In addition, the structure of the variable capacitor 12 is such that two sets of electrode pairs consisting of the lower drive electrode 4A and the beam 7 and the lower drive electrode 4B and the beam 7 are connected in series, and a signal (voltage) is directly applied. This is a structure (hereinafter, this structure is referred to as a MIMIM structure). The MIMIM structure has an electrostatic attraction per area as small as about 1/4 compared with the MIM structure, and is advantageous in suppressing deformation of the beam portion 7 due to self-actuation. On the other hand, the MIM structure has a larger electrostatic attraction per area than the MIMIM structure, and is advantageous in reducing the electrode area. Therefore, it is preferable to employ the MIM structure for the drive capacitor unit 11 that requires a large electrostatic attraction and the MIMIM structure for the variable capacitor 12 that needs to suppress the electrostatic attraction.

  Note that the drive capacitor unit 11 and the variable capacitor unit 12 may adopt either the MIM structure or the MIMIM structure, respectively. Further, as shown in FIG. 9, the drive capacitor C1 of the drive capacitor unit 11 and the variable capacitor C2 of the variable capacitor unit 12 change together according to the voltage between the terminals of the drive capacitor C1 (voltage between both ends). The ratio is proportional to any factor. For this reason, the capacitance value of the drive capacitor C1 becomes a value corresponding to the capacitance value of the variable capacitor C2.

  Next, the drive voltage control circuit 21 will be described with reference to FIG.

  The drive voltage control circuit 21 includes a comparator 22, a sample hold circuit 23, and a drive voltage generation circuit 24.

  The comparator 22 receives a detection signal Sx indicating a detection value of the drive capacitor C1 and a reference signal Sy serving as a reference for the drive capacitor C1 from a capacitance detection circuit 31 described later. The comparator 22 compares the voltage level of the detection signal Sx with the voltage level of the reference signal Sy, and outputs a comparison result signal Se corresponding to these comparison results. For this reason, the comparison result signal Se is switched to the Low level or the High level according to the comparison result between the detection value of the drive capacitor C1 and the reference value. For example, when the detection signal Sx is at a voltage level smaller than the reference signal Sy, that is, when the drive capacity C1 is larger than the target value, the comparison result signal Se is at a high level. On the contrary, when the detection signal Sx has a voltage level larger than that of the reference signal Sy, that is, when the drive capacitance C1 is smaller than the target value, the comparison result signal Se becomes the Low level.

  The output terminal of the comparator 22 is input to the drive voltage generation circuit 24 via the sample hold circuit 23 that holds the comparison result signal Se for a predetermined time. The sample hold circuit 23 is connected to the oscillator 26, samples the comparison result signal Se based on the second clock signal CLK2 from the oscillator 26, and outputs a sampling signal Ssh. The oscillator 26 outputs first and second clock signals CLK1 and CLK2 of, for example, about several kHz to several tens of MHz. In order to reduce errors in the comparison result signal Se, the sample hold circuit 23 preferably samples the comparison result signal Se when the detection signal Sx and the reference signal Sy have sufficiently large values. Therefore, the second clock signal CLK2 is a pulse signal that rises as late as possible in the time during which the detection signal Sx and the reference signal Sy are boosted, that is, the time during which the first clock signal CLK1 is at the low level. .

  The drive voltage generation circuit 24 increases or decreases the drive voltage Vcont according to the sampling signal Ssh obtained by sampling the comparison result signal Se of the comparator 22. If the sampling signal Ssh is at a high level, the drive voltage Vcont is decreased to adjust the drive capacity C1 to decrease. Conversely, if the sampling signal Ssh is at a low level, the drive voltage Vcont is increased to adjust the drive capacitance C1.

  The drive voltage generation circuit 24 smoothes the output signal Vp output from the level conversion circuit 24A for adjusting the output signal Vp according to the comparison result of the comparator 22 and the level conversion circuit 24A, and drives the DC drive voltage Vcont. And a smoothing filter 24B that outputs. Here, the level conversion circuit 24A is connected to the high voltage generation circuit 25, and a high voltage Vh higher than the maximum value of the drive voltage Vcont is supplied from the high voltage generation circuit 25. Then, the level conversion circuit 24A sets the output signal Vp to the high voltage Vh or 0V according to the comparison result signal Se of the comparator 22. Specifically, if the comparison result signal Se of the comparator 22 is high level, the level conversion circuit 24A sets the output signal Vp to 0V, and if the comparison result signal Se of the comparator 22 is low level, The conversion circuit 24A sets the output signal Vp to the high voltage Vh. As a result, the time during which the output signal Vp is set to the high voltage Vh according to the comparison result signal Se is increased or decreased.

  Further, the smoothing filter 24B is constituted by a low-pass filter made of, for example, a resistor and a capacitor. The smoothing filter 24B smoothes the output signal Vp according to the time constant, and outputs a DC drive voltage Vcont according to the time when the output signal Vp is set to the high voltage Vh. For this reason, the drive voltage Vcont becomes higher when the time for which the output signal Vp is set to the high voltage Vh becomes longer, and becomes lower when the output signal Vp becomes shorter.

  On the other hand, the high voltage generation circuit 25 is constituted by a booster circuit that boosts the power supply voltage Vdd. Is output.

  The drive voltage generation circuit 24 is configured to adjust the drive voltage Vcont by increasing or decreasing the time for setting the output signal Vp to the high voltage Vh. However, the present invention is not limited to this, and a smoothing capacitor that outputs the drive voltage Vcont may be provided, and the drive voltage Vcont may be increased or decreased by flowing a source current or a sink current through the smoothing capacitor.

  Next, the capacitance detection circuit 31 will be described with reference to FIGS. 1, 4, and 5.

  The capacitance detection circuit 31 includes a detection signal output circuit 32 that is connected to the drive capacitor C1 of the variable capacitance element 2 and outputs a detection signal Sx, and a reference signal output circuit 35 that is connected to the reference capacitance Cref and outputs a reference signal Sy. ing. Here, the drive voltage Vcont is supplied to one end side of the drive capacitor C1 and the reference capacitor Cref.

  The detection signal output circuit 32 selectively connects the detection current circuit 33 having the detection current source 33A and the other end of the drive capacitor C1 of the variable capacitance element 2 to either the detection current circuit 33 or the ground. It is comprised with the switch 34 for a detection.

  The detection current circuit 33 includes a detection current source 33A driven by the power supply voltage Vdd and a current mirror circuit 33B including two MOS switches MP1 and MP2. The detection current source 33A is composed of, for example, a variable current source, and outputs a detection current Iton according to the ratio between the target value of the drive capacitor C1 and the reference capacitor Cref. At this time, the current value of the detection current Iton is set by the external input signals Sc1 to ScN for determining the target value of the drive capacitor C1.

  The MOS switches MP1 and MP2 of the current mirror circuit 33B are made of p-channel MOSFETs, and the sources are connected to each other and the gates are connected to each other. At this time, a power supply voltage Vdd lower than the high voltage Vh is applied to the sources of the MOS switches MP1 and MP2. The drain of the MOS switch MP1 is connected to the detection current source 33A and to the gates of the MOS switches MP1 and MP2. As a result, the detection current Itont output from the detection current source 33A is copied to the MOS switch MP2 through the MOS switch MP1.

  The detection switch 34 includes a MOS switch MP3 made of a p-channel MOSFET and a MOS switch MN1 made of an n-channel MOSFET. The source of the MOS switch MP3 is connected to the drain of the MOS switch MP2, and the source of the MOS switch MN1 is connected to the ground. The drains of the MOS switch MP3 and the MOS switch MN1 are connected to each other, and these drains are connected to the other end of the drive capacitor C1 and the input end of the comparator 22.

  The gates of the MOS switch MP3 and the MOS switch MN1 are connected to each other, and the first clock signal CLK1 is input from the oscillator 26. Thereby, the MOS switch MP3 and the MOS switch MN1 perform inverter operations with each other, and when one is turned on, the other is turned off. Specifically, when the first clock signal CLK1 becomes high level, the MOS switch MP3 is turned off and the MOS switch MN1 is turned on. As a result, the other end of the drive capacitor C1 is connected to the ground, and the detection signal Sx becomes 0V. On the other hand, when the first clock signal CLK1 becomes low level, the MOS switch MP3 is turned on and the MOS switch MN1 is turned off. Thus, the detection current Iton from the detection current source 33A is supplied to the other end side of the drive capacitor C1 through the current mirror circuit 33B, and the detection signal Sx gradually rises according to the detection current Itont and the drive capacitor C1. To do. At this time, the magnitude of the detection signal Sx is proportional to the detection current Itont and its supply time t and inversely proportional to the drive capacity C1, as shown in the equation (1).

  The reference signal output circuit 35 includes a reference current circuit 36 having a reference current source 36A, a reference switch 37 that selectively connects the other end of the reference capacitor Cref to either the detection current circuit 36 or the ground. It is constituted by.

  The reference current circuit 36 includes a reference current source 36A driven by the power supply voltage Vdd and a current mirror circuit 36B composed of two MOS switches MP4 and MP5. The reference current source 36A is configured by a current source that outputs a constant reference current Iref, for example.

  The current mirror circuit 36B is configured in substantially the same manner as the current mirror circuit 33B of the detection current circuit 33. For this reason, the MOS switches MP4 and MP5 of the current mirror circuit 36B are made of p-channel MOSFETs, the sources are connected to each other, the power supply voltage Vdd is applied, and the gates are connected to each other. The drain of the MOS switch MP4 is connected to the reference current source 36A and to the gates of the MOS switches MP4 and MP5. Thus, the reference current Iref output from the reference current source 36A is copied to the MOS switch MP5 through the MOS switch MP4.

  The reference switch 37 is configured in substantially the same manner as the detection switch 34 of the detection current circuit 33, and is switched ON and OFF in synchronization with the detection switch 34. For this reason, the reference switch 37 is constituted by a MOS switch MP6 made of a p-channel MOSFET and a MOS switch MN2 made of an n-channel MOSFET. The source of the MOS switch MP6 is connected to the drain of the MOS switch MP5, and the source of the MOS switch MN2 is connected to the ground. The drains of the MOS switch MP6 and the MOS switch MN2 are connected to each other, and these drains are connected to the other end side of the reference capacitor Cref and the input end of the comparator 22.

  The gates of the MOS switch MP6 and the MOS switch MN2 are connected to each other and the first clock signal CLK1 is input from the oscillator 26. Thereby, the MOS switch MP6 and the MOS switch MN2 perform an inverter operation with each other, and when one is turned on, the other is turned off. Specifically, when the first clock signal CLK1 becomes High level, the MOS switch MP6 is turned off and the MOS switch MN2 is turned on. As a result, the other end of the reference capacitor Cref is connected to the ground, and the reference signal Sy becomes 0V. On the other hand, when the first clock signal CLK1 becomes low level, the MOS switch MP6 is turned on and the MOS switch MN2 is turned off. Thus, the reference current Iref from the reference current source 36A is supplied to the other end side of the reference capacitor Cref through the current mirror circuit 36B, and the reference signal Sy gradually rises according to the reference current Iref and the reference capacitor Cref. To do. At this time, the magnitude of the reference signal Sy is proportional to the reference current Iref and its supply time t and inversely proportional to the reference capacitance Cref, as shown in the equation (2).

  Here, the drive voltage control circuit 21 controls the drive voltage Vcont so that the voltage levels of the detection signal Sx and the reference signal Sy match. At this time, since the detection signal Sx and the reference signal Sy increase together when the first clock signal CLK1 becomes the Low level, the supply time t becomes the same value in the equations (1) and (2). For this reason, when the voltage levels of the detection signal Sx and the reference signal Sy match, the ratio (Icont / C1) between the detection current Itont and the drive capacity C1 is the ratio between the reference current Iref and the reference capacity Cref (Iref / Cref). ) Will match. Therefore, when the detection current Iton is larger than the reference current Iref, the drive capacity C1 is also larger than the reference capacity Cref in accordance with the ratio of these currents (Icont / Iref).

  The variable capacitance device 1 according to the embodiment of the present invention has the above-described configuration. Next, the output operation of the detection signal Sx and the reference signal Sy by the capacitance detection circuit 31 will be described.

  6 and 7 exemplify time changes of the detection signal Sx and the reference signal Sy. The capacitance detection circuit 31 repeats the switching operation of the detection switch 34 and the reference switch 37 in synchronization with the first clock signal CLK1 input from the oscillator 26. At time t0 when the first clock signal CLK1 becomes high level, the detection switch 34 connects the drive capacitor C1 to the ground, and the reference switch 37 connects the reference capacitor Cref to the ground. At this time, the detection signal Sx and the reference signal Sy are both at the ground potential (0 V).

  At the time t1 when the first clock signal CLK1 is switched from the High level to the Low level, the detection switch 34 connects the drive capacitor C1 to the detection current circuit 33, and the reference switch 37 sets the reference capacitance Cref to the reference current circuit. Connect to 36. At this time, the detection current Iton is supplied to the drive capacitor C1, and the detection signal Sx rises. Similarly, the reference current Iref is supplied to the reference capacitor Cref, and the reference signal Sy also rises. The comparator 22 compares the detection signal Sx with the reference signal Sy and outputs a comparison result signal Se corresponding to the comparison results.

  At the time point t2 when the first clock signal CLK1 is switched from the Low level to the High level, the switches 34 and 37 are switched to the ground side, and the detection signal Sx and the reference signal Sy become the ground potential again. After time t3, the same operation as from time t0 to time t2 is repeated.

  Here, both the detection current circuit 33 and the reference current circuit 36 are driven by the power supply voltage Vdd. For this reason, the maximum voltage of the detection signal Sx and the reference signal Sy is the power supply voltage Vdd. Therefore, the capacitance detection circuit 31 and the comparator 22 can use a low breakdown voltage circuit device corresponding to the power supply voltage Vdd of about several volts.

  The first clock signal CLK1 is a periodic signal for repeatedly outputting the detection signal Sx and the like. Assuming that the duty ratio of the clock signal CLK1 is D1, the maximum value of the detection signal Sx is the power supply voltage Vdd. Therefore, the time average value Sx_ave of the maximum value of the detection signal Sx is expressed by the following equation (3): It is represented by the product of the power supply voltage Vdd and the duty ratio D1.

  Therefore, the terminal voltage applied to the drive capacitor C1 is the difference ΔV (ΔV = Vd−Sx_ave) between the drive voltage Vcont and the time average value Sx_ave. When the difference ΔV is larger than the power supply voltage Vdd, the variable capacitance element 2 is driven with a voltage (for example, several tens of volts) higher than the power supply voltage Vdd, and the other circuit blocks are driven with the low power supply voltage Vdd. Can do.

  Next, the capacity control operation of the drive capacity C1 by the capacity detection circuit 31 and the drive voltage control circuit 21 will be described.

  FIG. 6 shows a case where the capacitance value of the drive capacitor C1 is smaller than the target value and the detection signal Sx is larger than the reference signal Sy. For example, between the time t1 and the time t2, the detection switch 34 and the reference switch 37 are turned on, the drive capacitor C1 is connected to the detection current circuit 33, and the reference capacitor Cref is connected to the reference current circuit 36. When connected, the capacitance detection circuit 31 performs a capacitance detection operation. At this time, since the detection signal Sx is larger than the reference signal Sy (Sx> Sy), the comparison result signal Se of the comparator 22 is at a low level (for example, Se = 0V). For example, when the detection switch 34 and the reference switch 37 are turned off and the drive capacitor C1 and the reference capacitor Cref are both connected to the ground, for example, between the time t2 and the time t3, the detection signal Sx. The reference signal Sy becomes the ground potential, and the comparison result signal Se becomes the low level (for example, Se = 0V).

  Accordingly, the sample hold circuit 23 connected to the subsequent stage of the comparator 22 samples the comparison result signal Se based on the second clock signal CLK2 from the oscillator 26, and outputs a sampling signal Ssh that is stable at the low level. At this time, the level conversion circuit 24A is an inverting circuit that operates using the high voltage Vh input from the high voltage generation circuit 25 as a power supply, and the input threshold voltage is set to, for example, half the power supply voltage Vdd (Vdd / 2). For this reason, when the sampling signal Ssh is at the low level, the output signal Vp of the level conversion circuit 24A becomes the high voltage Vh. Since the smoothing filter 24B is connected to the subsequent stage of the level conversion circuit 24A, the potential of the drive voltage Vcont rises toward the high voltage Vh due to the time constant of the smoothing filter 24B. As a result, the inter-terminal voltage applied to the drive capacitor C1 of the variable capacitor 2 increases, the drive capacitor C1 increases, and the variable capacitor C2 increases.

  FIG. 7 shows a case where the capacitance value of the drive capacitor C1 is larger than the target value and the detection signal Sx is smaller than the reference signal Sy. For example, when the detection switch 34 and the reference switch 37 are ON, such as between the time point t1 and the time point t2, the capacitance detection circuit 31 performs a capacitance detection operation. At this time, since the detection signal Sx is smaller than the reference signal Sy (Sx <Sy), the comparison result signal Se of the comparator 22 is at a high level (for example, Se = Vdd). For example, when the detection switch 34 and the reference switch 37 are OFF, for example, between the time t2 and the time t3, the detection signal Sx and the reference signal Sy are at the ground potential, and the comparison result signal Se is Low. It becomes a level (for example, Se = 0V).

  The sample hold circuit 23 connected to the subsequent stage of the comparator 22 samples the comparison result signal Se based on the second clock signal CLK 2 from the oscillator 26. At this time, in the sample hold circuit 23, the section in which the capacitance detection circuit 31 performs the capacitance detection operation, that is, the drive capacitance C1 is connected to the detection current circuit 33, and the reference capacitance Cref is connected to the reference current circuit 36. A second clock signal CLK2 for performing sampling only in a certain section is input. Therefore, the sample hold circuit 23 outputs a sampling signal Ssh (Ssh = Vdd) which is stable at the power supply voltage Vdd as the High level. At this time, the level conversion circuit 24A is an inverting circuit that operates using the high voltage Vh input from the high voltage generation circuit 25 as a power supply. Therefore, when the sampling signal Ssh is at the high level, the output signal Vp of the level conversion circuit 24A is It becomes the ground potential (Vp = 0V). As a result, the potential of the drive voltage Vcont decreases toward the ground potential due to the time constant of the smoothing filter 24B. As a result, the inter-terminal voltage applied to the drive capacitor C1 of the variable capacitor 2 decreases, the drive capacitor C1 decreases, and the variable capacitor C2 decreases.

  The above-described capacity control feedback operation is repeated, and the drive voltage Vcont converges to the target voltage value as shown in FIG. As a result, the capacitance value of the drive capacitor C1 converges to the target value, and the variable capacitor C2 also converges to a value corresponding to the target value of the drive capacitor C1. Thus, in a state where the drive capacitor C1 has converged to the target value, current consumption between the drive capacitor C1 of the variable capacitor 2 and the drive voltage generation circuit 24 becomes extremely small. On the other hand, the time-average current Iton_ave required for detecting the capacity of the drive capacitor C1 is current consumption accompanying the detection signal Sx. Therefore, as shown in the following equation 4, the detection current Itont and the first clock signal It is represented by the product of the duty ratio D1 of CLK1. At this time, the power consumption W accompanying the capacity detection is represented by the product of the time average current Iton_ave and the power supply voltage Vdd as shown in the equation (5).

  As shown in the equation (5), it can be seen that the power consumption W accompanying the capacitance detection of the drive capacitor C1 is proportional to the power supply voltage Vdd connected to the detection current circuit 33. In this embodiment, since the low-voltage power supply voltage Vdd can be connected to the detection current circuit 33, the power consumption can be reduced.

  As described above, according to the variable capacitance device 1 according to the present embodiment, when the detection capacitor 34 connects the drive capacitance C1 of the variable capacitance element 2 to the detection current circuit 33, the detection current circuit 33 is driven. A detection current Iton flows toward the capacitor C1. At this time, the voltage at the other end connected to the detection current circuit 33 among the both ends of the drive capacitor C1 is boosted according to the capacitance value of the drive capacitor C1. Therefore, the capacitance detection circuit 31 outputs the detection signal Sx according to the voltage applied to the other end of the drive capacitance C1 when the drive capacitance C1 and the detection current circuit 33 are connected by the detection switch 34. can do.

  The drive voltage Vcont is supplied to one end side of the drive capacitor C1, and the detection current circuit 33 is connected to the other end side of the drive capacitor C1. For this reason, the voltage applied to the other end of the drive capacitor C1 is the power supply voltage Vdd supplied to the detection current circuit 33 at the maximum. Therefore, the voltage level of the detection signal Sx output from the capacitance detection circuit 31 can be made lower than the drive voltage Vcont, and the capacitance detection circuit 31 and the like can be downsized.

  Further, the drive voltage control circuit 21 includes a comparator 22 that compares the detection signal Sx of the drive capacitor C1 with the reference signal Sy. At this time, since the capacitance detection circuit 31 outputs a voltage lower than the power supply voltage Vdd as the detection signal Sx and the reference signal Sy, the input voltage of the comparator 22 can be lower than the power supply voltage Vdd lower than the drive voltage Vcont. A low breakdown voltage circuit device can be used for the comparator 22.

  In addition to this, when the connection and disconnection of the drive capacitor C1 and the detection current circuit 33 are repeated in order to detect the capacitance value of the drive capacitor C1, the detection current Itont and the power supply voltage from the detection current circuit 33 are detected. Electric power corresponding to the product of Vdd is consumed. For this reason, power consumption can be reduced compared with the case where the electric power according to the drive voltage Vcont is consumed like the prior art.

  Further, when the reference capacitor Cref and the reference current circuit 36 are connected by the reference switch 37, the reference current Iref flows from the reference current circuit 36 toward the reference capacitor Cref. At this time, the voltage at the other end connected to the reference current circuit 36 among both ends of the reference capacitor Cref is boosted according to the capacitance value of the reference capacitor Cref. For this reason, when the reference capacitance Cref and the reference current circuit 36 are connected by the reference switch 37, the capacitance detection circuit 31 has the drive capacitance C1 in accordance with the voltage applied to the other end side of the reference capacitance Cref. A reference signal Sy serving as a reference for the capacitance value can be output.

  Next, FIG. 10 shows a capacitance detection circuit according to the second embodiment. The feature of this embodiment is that the detection current circuit and the reference current circuit are currents flowing through a single common current source. Is configured using a current mirror circuit for copying. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  Similar to the capacitance detection circuit 31 according to the first embodiment, the capacitance detection circuit 41 according to the second embodiment is connected to the drive capacitor C1 of the variable capacitance element 2 and outputs a detection signal Sx to detect a current circuit 47 for detection. And a detection signal output circuit 32 comprising a detection switch 34 and a reference signal output circuit 35 comprising a reference current circuit 49 and a reference switch 37 for outputting a reference signal Sy connected to the reference capacitor Cref. However, the detection current circuit 47 and the reference current circuit 49 are configured using a current mirror circuit 43 that copies the current flowing through the single common current source 42.

  Here, the common current source 42 passes a predetermined constant current i0. The current mirror circuit 43 is configured by using, for example, four MOS switches MP7 to MP10, and copies the current i0 flowing through the common current source 42. These MOS switches MP7 to MP10 are made of p-channel MOSFETs, and the sources are connected to each other and the gates are connected to each other. The drain of the MOS switch MP7 is connected to the common current source 42 and to the gates of the MOS switches MP7 to MP10. Thus, when the current i0 of the common current source 42 flows through the MOS switch MP7, a current having the same magnitude as the current i0 of the common current source 42 flows also between the drains and sources of the MOS switches MP8 to MP10.

  The MOS switches MP8 and MP9 are connected to the current mirror circuit 46 via the MOS switches MN3 and MN4 of the current adjustment circuit 44. Specifically, the drains of the MOS switches MP8 and MP9 are connected to the drains of the MOS switches MN3 and MN4 made of n-channel MOSFETs, respectively, and the sources of the MOS switches MN3 and MN4 are connected to each other. The sources of the MOS switches MN 3 and MN 4 are connected to the source of the MOS switch MP 1 of the current mirror circuit 46, and a detection current Icont flows to the current mirror circuit 46.

  Further, a high level signal or a low level signal is input to the gates of the MOS switches MN3 and MN4 from the switch control circuit 45, and the MOS switches MN3 and MN4 are turned on and off according to the signal. Switches. At this time, the switch control circuit 45 switches ON / OFF of both or one of the MOS switches MN3 and MN4 according to the external input signals Sc1 and Sc2.

  Specifically, when the external input signal Sc1 is input, the switch control circuit 45 turns on the MOS switch MN3 and turns off the MOS switch MN4. At this time, the detection current Itont has the same magnitude as the current i0 of the common current source 42. On the other hand, when the external input signal Sc2 is input, the switch control circuit 45 turns on both the MOS switches MN3 and MN4. At this time, the detection current Iton is twice as large as the current i0 of the common current source. Thus, the switch control circuit 45 controls the magnitude of the detection current Itont according to the external input signals Sc1 and Sc2.

  Similar to the current mirror circuit 33B according to the first embodiment, the current mirror circuit 46 is configured using MOS switches MP1 and MP2. A power supply voltage Vdd is applied to the source of the MOS switch MP2 of the current mirror circuit 46. The drain of the MOS switch MP1 is connected to the ground and to the gates of the MOS switches MP1 and MP2. Therefore, the detection current Iton output from the current adjustment circuit 44 is copied to the MOS switch MP2 through the MOS switch MP1. The drain of the MOS switch MP2 is connected to the source of the MOS switch MP3 of the detection switch 34, and outputs a detection current Itonto the detection switch 34.

  Therefore, the common current source 42, the MOS switches MP7 to MP9 of the current mirror circuit 43, the current adjustment circuit 44, and the current mirror circuit 46 constitute a detection current circuit 47 that outputs a detection current Itonto the detection switch 34. doing.

  On the other hand, the MOS switch MP10 is connected to the current mirror circuit 48. At this time, a reference current Iref having the same magnitude as the current i0 of the common current source 42 flows between the drain and source of the MOS switch MP10. The drain of the MOS switch MP10 is connected to the source of the MOS switch MP4 of the current mirror circuit 48, and allows the reference current Iref to flow toward the current mirror circuit 48.

  Further, the current mirror circuit 48 is configured by using MOS switches MP4 and MP5, similarly to the current mirror circuit 36B according to the first embodiment. The power supply voltage Vdd is applied to the source of the MOS switch MP5 of the current mirror circuit 48. Further, the drain of the MOS switch MP4 is connected to the ground and also connected to the gates of the MOS switches MP4 and MP5. Therefore, the reference current Iref output from the MOS switch MP10 is copied to the MOS switch MP5 through the MOS switch MP4. The drain of the MOS switch MP5 is connected to the source of the MOS switch MP6 of the reference switch 37, and outputs a reference current Iref toward the reference switch 37.

  Accordingly, the common current source 42, the MOS switches MP7 and MP10 of the current mirror circuit 43, and the current mirror circuit 48 constitute a reference current circuit 49 that outputs a reference current Iref to the reference switch 37.

  Thus, the second embodiment can provide the same effects as those of the first embodiment. In the second embodiment, the detection current circuit 47 and the reference current circuit 49 are configured by using the current mirror circuit 43 that copies the current i0 flowing through the common current source. For this reason, since the single common current source 42 is used, variations in the detection signal Sx and the reference signal Sy of the drive capacitor C1 can be suppressed as compared with the case where separate current sources and voltage sources are used.

  This effect will be specifically described. Generally, when a reference power source is generated in an integrated circuit, variations in absolute values of current values occur by about 10 to 30%. In the prior art, since the capacitance detection current and the reference voltage are used, these absolute value variations tend to affect the capacitance detection accuracy, and the detection accuracy tends to decrease.

  In contrast, in the present embodiment, the relative variation of the detection current Itont and the reference current Iref is affected. In addition to this, since the current mirror circuit 43 is used, the variation in the copy current (current flowing in the MOS switches MP8 to MP10) copied from the current i0 flowing in the common current source 42 is the absolute value variation when separate power supplies are generated. Smaller than Since the capacitance detection accuracy of the drive capacitor C1 is affected by the detection current Itont and the reference current Iref based on the copy current, in this embodiment, it is easy to suppress variations in the detection current Itont and the reference current Iref. The accuracy of capacity detection can be increased.

  In the second embodiment, the two MOS switches MP7 and MP8 of the current mirror circuit 43 and the current adjustment circuit 44 are used to output two types of detection currents Icont. Arbitrary n MOS switches may be provided in the circuit to output n types of detection currents Icont.

  In the first and second embodiments, the target value of the drive capacitor C1 is changed by changing the detection current Itont. However, the reference current Iref and the reference capacitor Cref are changed. Thus, the target value of the drive capacity C1 may be changed.

  In the capacitance detection circuits 31 and 41 according to the first and second embodiments, in addition to the detection current circuits 33 and 47, a reference current circuit for outputting a reference signal Sy using a reference capacitance Cref. 36, 49. However, the present invention is not limited to this. For example, like the capacitance detection circuit 51 according to the modification shown in FIG. 11, the reference current circuit may be omitted and the detection current circuit 33 and the detection switch 34 may be used. . In this case, the reference signal Sy may be input to the comparator 22 using a reference voltage source 52 that outputs a predetermined reference voltage Vref. The reference voltage Vref may be variably set according to the target value of the drive capacitor C1.

  In the first and second embodiments, the capacitance detection circuits 31 and 41 are configured using MOSFETs, but may be configured using other switching elements such as bipolar transistor diodes.

  In the first and second embodiments, the drive capacitor C1 of the variable capacitor 2 is detected and the drive capacitor C1 is changed. However, the variable capacitor C2 is detected and the drive capacitor C1 is changed. It is good also as a structure. Furthermore, a single variable capacitor in which the drive capacitor C1 and the variable capacitor C2 are made common may be provided, and this variable capacitor may be detected and changed.

DESCRIPTION OF SYMBOLS 1 Variable capacity apparatus 2 Variable capacity element 21 Drive voltage control circuit 22 Comparator 31,41,51 Capacitance detection circuit 33,47 Detection current circuit 34 Detection switch 36,49 Reference current circuit 37 Reference switch 42 Common current source 43 Current mirror circuit

Claims (4)

A variable capacitance element whose capacitance changes according to the drive voltage, a capacitance detection circuit for detecting the capacitance of the variable capacitance element, and the drive voltage based on a capacitance detection value by the capacitance detection circuit. In a variable capacitance device including a drive voltage control circuit to control,
Supplying the drive voltage to one end of the variable capacitance element;
The capacitance detection circuit includes a detection current circuit that is driven by a power supply voltage lower than the drive voltage, and a detection that selectively connects the other end of the variable capacitance element to either the detection current circuit or the ground. Switch for
The capacitance detection circuit outputs the detection value according to a voltage applied to the other end of the variable capacitance element when the variable capacitance element and the detection current circuit are connected by the detection switch. A variable capacitance device characterized by having a configuration. A reference capacitor having one end connected to the drive voltage is provided,
The capacitance detection circuit includes a reference current circuit that is driven by the power supply voltage, and a reference switch that selectively connects the other end of the reference capacitor to either the reference current circuit or the ground.
The capacitance detection circuit is configured to output a reference value according to a voltage applied to the other end of the reference capacitor when the reference capacitor and the reference current circuit are connected by the reference switch. The variable capacitance device according to claim 1.   3. The variable capacitance device according to claim 2, wherein the detection current circuit and the reference current circuit are configured by using a current mirror circuit that copies a current flowing through a single common current source.   3. The drive voltage control circuit includes a comparator that compares a detected value of the capacitance with a reference value, and is configured to boost or lower the drive voltage according to a comparison result of the comparator. 3. The variable capacity device according to 3.

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