JP2013016722A - Cooling structure of semiconductor element - Google Patents
Cooling structure of semiconductor element Download PDFInfo
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- JP2013016722A JP2013016722A JP2011149822A JP2011149822A JP2013016722A JP 2013016722 A JP2013016722 A JP 2013016722A JP 2011149822 A JP2011149822 A JP 2011149822A JP 2011149822 A JP2011149822 A JP 2011149822A JP 2013016722 A JP2013016722 A JP 2013016722A
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Abstract
【課題】半導体素子を取付面にネジを用いずに取付ける場合、取付面に密着しないため十分な冷却性が得られないという課題があった。
【解決手段】取付面３に絶縁材２を配し、絶縁材２上に半導体素子１ａを取付けてなる半導体素子の冷却構造において、半導体素子１ａを取付面３に対して接触させるための狭圧手段４が、金属板の周りを絶縁体である樹脂７で被われた構成からなり、金属板を回路を構成する導体８の一部として用いることを特徴とする。
【選択図】図１When a semiconductor element is mounted on a mounting surface without using a screw, there is a problem that sufficient cooling cannot be obtained because the semiconductor element does not adhere to the mounting surface.
In a cooling structure of a semiconductor element in which an insulating material is disposed on a mounting surface and a semiconductor element is mounted on the insulating material, a narrow pressure for bringing the semiconductor element into contact with the mounting surface is provided. The means 4 has a configuration in which a metal plate is covered with a resin 7 as an insulator, and the metal plate is used as a part of a conductor 8 constituting a circuit.
[Selection] Figure 1
Description
本発明は、半導体素子の冷却構造に関するものである。 The present invention relates to a semiconductor element cooling structure.
従来技術の一実施例に係る半導体冷却構造につき、図７から図９を用いて説明する。図７は、従来技術の半導体冷却構造の平面図である。図８は、従来技術の半導体冷却構造の正面図である。図９は、従来技術の半導体冷却構造の断面図である。 A semiconductor cooling structure according to an embodiment of the prior art will be described with reference to FIGS. FIG. 7 is a plan view of a conventional semiconductor cooling structure. FIG. 8 is a front view of a conventional semiconductor cooling structure. FIG. 9 is a cross-sectional view of a conventional semiconductor cooling structure.
従来の半導体冷却構造１０１は、冷却媒体を内部に流通させる一対の冷却管１０３の間に、半導体素子１２１を内蔵した半導体モジュール１０２を複数個、互いの間に間隙部１１１を設けながら並列配置してなる。 In a conventional semiconductor cooling structure 101, a plurality of semiconductor modules 102 each including a semiconductor element 121 are arranged in parallel between a pair of cooling pipes 103 through which a cooling medium flows, while a gap 111 is provided therebetween. It becomes.
そして、図７に示すごとく、上記一対の冷却管１２１を半導体モジュール１０２に押圧するための挟圧手段１０４が、各半導体モジュール１０２ごとに個別に配設してある。なお、図８、図９においては、挟圧手段１０４の記載を省略してある。 As shown in FIG. 7, the clamping means 104 for pressing the pair of cooling pipes 121 against the semiconductor module 102 is individually provided for each semiconductor module 102. In FIGS. 8 and 9, the pinching means 104 is not shown.
一対の冷却管１０３のうちの少なくとも一方は、隣り合う半導体モジュール１０２の間の間隙部１１１に対向する部分に、挟圧手段１０４の加圧力によって変形可能な可変形部１３１を設けてなる。可変形部１３１は、塑性変形可能に構成されている。すなわち、冷却管１０３のうち少なくとも可変形部１３１は、塑性材料によって構成されている。 At least one of the pair of cooling pipes 103 is provided with a deformable portion 131 that can be deformed by the pressure of the clamping means 104 at a portion facing the gap 111 between the adjacent semiconductor modules 102. The deformable portion 131 is configured to be plastically deformable. That is, at least the deformable portion 131 of the cooling pipe 103 is made of a plastic material.
図７に示すごとく、挟圧手段１０４は、冷却管１０３における半導体モジュール１０２と反対側の面に配された一対の押圧板１４１と、一対の押圧板１４１をその端部において貫通する複数のスルーボルト１４２と、該スルーボルト１４２に螺合するナット１４３とからなる。そして、挟圧手段１０４は、スルーボルト１４２とナット１４３とによって、一対の押圧板１４１を互いに近づける方向に締め付けることによって、一対の冷却管１０３を半導体モジュール１０２に押圧させる。 As shown in FIG. 7, the clamping means 104 includes a pair of pressing plates 141 disposed on the surface of the cooling pipe 103 opposite to the semiconductor module 102, and a plurality of through holes that penetrate the pair of pressing plates 141 at their ends. It consists of a bolt 142 and a nut 143 screwed into the through bolt 142. The pinching means 104 presses the pair of cooling pipes 103 against the semiconductor module 102 by tightening the pair of pressing plates 141 in the direction in which the pair of pressing plates 141 are brought closer to each other with the through bolts 142 and the nuts 143.
このようにして、複数の半導体モジュール１０２に対してそれぞれ設けられた複数の挟圧手段１０４によって、それぞれの半導体モジュール１０２に冷却管１０３を押圧して密着させる。このとき、各半導体モジュール１０２への冷却管１０３の加圧力は、複数の半導体モジュール１０２において均等になるようにするものである。 In this way, the cooling pipes 103 are pressed and brought into close contact with the respective semiconductor modules 102 by the plurality of clamping means 104 respectively provided for the plurality of semiconductor modules 102. At this time, the pressure of the cooling pipe 103 to each semiconductor module 102 is made uniform in the plurality of semiconductor modules 102.
しかしながら，前記従来の構成では半導体素子を冷却管に密着させるために複雑な形状の狭圧手段を用いる必要があった。 However, in the conventional configuration, it is necessary to use a narrow pressure means having a complicated shape in order to bring the semiconductor element into close contact with the cooling pipe.
本発明は、前記従来の課題を解決するもので、単純な構造により半導体素子の取付面に対しての接触圧を確保することを目的とする。かつ、プリント基板の配線を低減可能とすることを目的とする。 The present invention solves the above-described conventional problems, and an object thereof is to secure a contact pressure with respect to a mounting surface of a semiconductor element with a simple structure. And it aims at enabling wiring of a printed circuit board to be reduced.
前記従来の課題を解決するために、本発明の半導体素子の冷却構造は、金属の導体を樹脂モールドした狭圧手段によって、半導体素子の取付け面への固定を行うものである。 In order to solve the above-described conventional problems, the semiconductor element cooling structure of the present invention fixes the semiconductor element to the mounting surface by a narrow pressure means in which a metal conductor is resin-molded.
本発明の半導体素子の冷却構造は、樹脂モールドした導体により、半導体素子を取付面に対して狭圧することと、その導体を回路の一部として使うことにより、回路基板の小型化を成すものである。 The semiconductor element cooling structure of the present invention reduces the size of the circuit board by constricting the semiconductor element against the mounting surface with a resin-molded conductor and using the conductor as part of the circuit. is there.
第１の発明は、取付面に絶縁材を配し、前記絶縁材上に半導体素子を取付けてなる半導体素子の冷却構造において、前記半導体素子を前記取付面に対して接触させるための狭圧手段が、金属板の周りを絶縁体である樹脂で被われた構成からなり、前記金属板は回路を構成する導体の一部として用いられるものである。これにより、半導体素子を取付面に対してより密着させることができ、また、制御基板の面積を減少させることができる。 A first aspect of the present invention is a semiconductor element cooling structure in which an insulating material is disposed on a mounting surface, and a semiconductor element is mounted on the insulating material. Narrow pressure means for bringing the semiconductor element into contact with the mounting surface However, the metal plate is covered with a resin which is an insulator, and the metal plate is used as a part of a conductor constituting a circuit. Thereby, the semiconductor element can be more closely attached to the mounting surface, and the area of the control board can be reduced.
第２の発明は、前記半導体素子を複数個配置し、前記複数の半導体素子間の間隙部にリブを設けた前記狭圧手段を持つものである。これにより、横方向の位置ずれが規制され、半導体素子の取付けが行いやすくなる。 According to a second aspect of the invention, there is provided the narrow pressure means in which a plurality of the semiconductor elements are arranged and a rib is provided in a gap portion between the plurality of semiconductor elements. Thereby, the positional deviation in the lateral direction is restricted, and the semiconductor element can be easily attached.
第３の発明は、前記複数個の半導体素子のネジ用穴部に挿入されるようにリブを設けた前記狭圧手段を持つものである。これにより、縦方向の位置ずれが規制され、半導体素子の取り付けが行いやすくなる。 According to a third aspect of the invention, there is provided the narrow pressure means provided with a rib so as to be inserted into a screw hole of the plurality of semiconductor elements. Thereby, the positional deviation in the vertical direction is restricted, and the semiconductor element can be easily attached.
第４の発明は、前記複数個の半導体素子と対向して、さらに複数個の半導体素子を設け、一つの狭圧手段で狭圧するものである。これにより、半導体素子の位置決めが容易になる。 According to a fourth aspect of the present invention, a plurality of semiconductor elements are further provided opposite to the plurality of semiconductor elements, and the pressure is narrowed by one narrowing means. This facilitates positioning of the semiconductor element.
以下、本発明の実施の形態について、図面を参照しながら説明する。なお、この実施の形態によってこの発明が限定されるものではない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiments.
（実施の形態１）
図１と図２を用いて本発明の実施の形態を説明する。図１は、実施の形態１に係る半導体素子の冷却構造の断面図を示し、図２は実施の形態１に係る半導体素子の冷却構造の平面透視図を示すものである。
(Embodiment 1)
An embodiment of the present invention will be described with reference to FIGS. 1 is a cross-sectional view of the semiconductor element cooling structure according to the first embodiment, and FIG. 2 is a plan perspective view of the semiconductor element cooling structure according to the first embodiment.
図１と図２に示すように、本実施の形態に係る半導体素子の冷却構造は、半導体素子１ａと、絶縁材２と、取付面３と、狭圧手段４とネジ５とによって構成されている。半導体素子１ａは、制御基板９にはんだ付けされている。狭圧手段４は、導体８を樹脂７で覆った構造となっている。 As shown in FIGS. 1 and 2, the semiconductor element cooling structure according to the present embodiment includes a semiconductor element 1 a, an insulating material 2, a mounting surface 3, a narrowing means 4, and a screw 5. Yes. The semiconductor element 1 a is soldered to the control board 9. The narrow pressure means 4 has a structure in which a conductor 8 is covered with a resin 7.
半導体素子１ａは取付面３との絶縁性と熱伝導性を考慮し熱伝導の良好な絶縁材２を介して取付面３に接触しており，狭圧手段４は半導体素子１ａを十分冷却できる一定の接触圧で狭圧手段４の両端部でネジ５によって取付面３に取り付けられている。 The semiconductor element 1a is in contact with the mounting surface 3 through an insulating material 2 having good heat conduction in consideration of insulation and thermal conductivity with the mounting surface 3, and the narrow pressure means 4 can sufficiently cool the semiconductor element 1a. It is attached to the attachment surface 3 with screws 5 at both ends of the narrow pressure means 4 with a constant contact pressure.
この狭圧手段４の内部に金属の導体８を配置することにより、樹脂のみの場合よりも、強固な構造となるため、取付面３に対してより密着させることができるものである。 By disposing the metal conductor 8 inside the narrow pressure means 4, a stronger structure is obtained than in the case of using only the resin, so that it can be more closely attached to the mounting surface 3.
また、導体８を回路の導電部として使用することによって制御基板９上のプリント配線を減らすことが出来るため、制御基板９の面積を減少させることが出来るものである。 Moreover, since the printed wiring on the control board 9 can be reduced by using the conductor 8 as a conductive part of the circuit, the area of the control board 9 can be reduced.
（実施の形態２）
図３と図４を用いて本発明の実施の形態を説明する。ただし、実施の形態１と同じ箇所は説明を省略する。図３は、実施の形態２に係る半導体素子の冷却構造の平面図であり、図４は本発明の実施の形態２における半導体素子の冷却構造の側面図である。
(Embodiment 2)
The embodiment of the present invention will be described with reference to FIGS. However, the description of the same parts as those in Embodiment 1 is omitted. FIG. 3 is a plan view of the semiconductor element cooling structure according to the second embodiment, and FIG. 4 is a side view of the semiconductor element cooling structure according to the second embodiment of the present invention.
図３と図４に示すように、図１の構成に加え、半導体素子１ａと並列に半導体素子１ｂと１ｃを配し、それぞれの間にリブ１０を設けることにより、横方向の位置ずれを規制することにより、実施の形態１の効果に加え、半導体素子１ａ〜１ｃの取付けが行いやすくしたものである。 As shown in FIGS. 3 and 4, in addition to the configuration of FIG. 1, semiconductor elements 1 b and 1 c are arranged in parallel with the semiconductor element 1 a, and ribs 10 are provided between them, thereby restricting lateral displacement. Thus, in addition to the effects of the first embodiment, the semiconductor elements 1a to 1c can be easily attached.
（実施の形態３）
図５を用いて本発明の実施の形態を説明する。ただし、実施の形態１又は２と同じ箇所は説明を省略する。図５は、本発明の実施の形態３における半導体素子の冷却構造の側面図である。
(Embodiment 3)
An embodiment of the present invention will be described with reference to FIG. However, the description of the same portions as those in Embodiment 1 or 2 is omitted. FIG. 5 is a side view of a semiconductor element cooling structure according to the third embodiment of the present invention.
図５に示すように、図４の構成に加え、ネジ穴１２に挿入されるようにリブ１１を設けることによって縦方向のずれを規制することにより、実施の形態１、２の効果に加え、半導体素子１ａ〜１ｃの取り付けが行いやすくなるものである。 As shown in FIG. 5, in addition to the configuration of FIG. 4, in addition to the effects of the first and second embodiments, the rib 11 is provided so as to be inserted into the screw hole 12, thereby restricting the shift in the vertical direction. The semiconductor elements 1a to 1c can be easily attached.
（実施の形態４）
図６を用いて本発明の実施の形態を説明する。ただし、実施の形態１ないし３と同じ箇所は説明を省略する。図６は、本発明の実施の形態４における半導体素子の冷却構造の平面図である。
(Embodiment 4)
An embodiment of the present invention will be described with reference to FIG. However, the description of the same parts as in the first to third embodiments is omitted. FIG. 6 is a plan view of a semiconductor element cooling structure according to the fourth embodiment of the present invention.
図６に示すように、半導体素子１ｄ〜１ｆを半導体素子１ａ〜１ｃと対向して設け、これを一体型の狭圧手段４で狭圧することで、実施の形態１の効果に加え、半導体素子１ａ〜１ｆを狭圧すると同時に、半導体素子１ａ〜１ｆの位置決めが容易になるものである。 As shown in FIG. 6, the semiconductor elements 1 d to 1 f are provided opposite to the semiconductor elements 1 a to 1 c, and the semiconductor elements 1 a to 1 f are narrowed by the integrated narrow pressure unit 4. At the same time as narrowing the pressures 1a to 1f, positioning of the semiconductor elements 1a to 1f is facilitated.
本発明は、電力変換装置に幅広く適用できるものである。 The present invention can be widely applied to power conversion devices.
１ 半導体素子
２ 絶縁材
３ 取付面
４ 狭圧手段
５ ネジ
７ 樹脂
８ 導体
９ 制御基板
１０、１１ リブ
１２ ネジ穴
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Insulating material 3 Mounting surface 4 Narrow pressure means 5 Screw 7 Resin 8 Conductor 9 Control board 10, 11 Rib 12 Screw hole
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| JP2011149822A JP2013016722A (en) | 2011-07-06 | 2011-07-06 | Cooling structure of semiconductor element |
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| JP2011149822A JP2013016722A (en) | 2011-07-06 | 2011-07-06 | Cooling structure of semiconductor element |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001217358A (en) * | 2000-01-31 | 2001-08-10 | Hitachi Ltd | Air cooling structure of multi-chip module |
| JP2005072249A (en) * | 2003-08-25 | 2005-03-17 | Toyota Industries Corp | Method for fixing semiconductor discrete part and discrete semiconductor device |
| JP2005252001A (en) * | 2004-03-04 | 2005-09-15 | Toshiba Corp | Module type semiconductor device |
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2011
- 2011-07-06 JP JP2011149822A patent/JP2013016722A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001217358A (en) * | 2000-01-31 | 2001-08-10 | Hitachi Ltd | Air cooling structure of multi-chip module |
| JP2005072249A (en) * | 2003-08-25 | 2005-03-17 | Toyota Industries Corp | Method for fixing semiconductor discrete part and discrete semiconductor device |
| JP2005252001A (en) * | 2004-03-04 | 2005-09-15 | Toshiba Corp | Module type semiconductor device |
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