JP2013016012A - Microcomputer - Google Patents

Abstract

An object of the present invention is to provide a microcomputer capable of reducing wasteful power consumption in resources.
In a microcomputer to which power is supplied from outside, each of the plurality of resources has a predetermined function and is not supplied with power when the power supplied from outside is activated, and a bus is connected to the plurality of resources. A control unit for supplying an access signal to the resource via the bus, and a plurality of resources provided to the corresponding resource from the power source supplied from the outside in response to a power activation signal. A plurality of in-resource power supply units for supplying in-resource power, and each of the plurality of resources, detecting whether an access signal supplied via the bus is addressed to a corresponding resource, and the access signal is A power control unit capable of outputting the power activation signal to a corresponding in-resource power supply unit when addressed to a corresponding resource; To.
[Selection] Figure 4

Description

  The present invention relates to a microcomputer.

  In recent years, semiconductor integrated circuits are required to reduce power consumption due to leakage current and the like. For example, general-purpose microcomputers (microcomputers) are equipped with a large number of resources and are configured to meet the needs of various users. However, many resources include resources that do not need to be operated depending on the user's purpose. If no measures for low power consumption are taken, when the microcomputer power is turned on, even resources that do not require operation are wasted.

  Usually, the microcomputer has a standby function for stopping the internal operation when an input waiting state or operation is not required. In the standby state, power is supplied only to limited resources such as RAM, and power to most other resources including the CPU is shut off. However, since power is supplied to all resources in the normal operation state, power is supplied to resources that do not require operation in the user's application, causing unnecessary power consumption.

  Therefore, as means for reducing the power consumption of resources that do not need to be operated, technologies for reducing the power consumption by stopping the clock supply to unnecessary resources (Patent Document 1, Patent Document 2), responding to received signals from the outside Then, technology to shut down or reduce the power to resources that do not require operation (Patent Document 3), register resources that do not require operation in the register in advance, and power off the power off signal from the CPU A technique (Patent Document 4) that outputs power to a control circuit and shuts off the power supply of resources that do not require operation has been proposed.

JP 04-127210 A Japanese Patent Laid-Open No. 05-324871 Japanese Patent Publication No. 57-028124 JP 63-12618 A

  However, since power is supplied to unnecessary resources until the power cut-off signal is output to the power cut-off control circuit after the microcomputer is turned on, unnecessary power consumption occurs. Further, in the invention described in Patent Document 4, it is necessary to determine unnecessary resources in advance, and it is not always possible to cut off the power supply of unnecessary resources according to the operation status.

  Accordingly, an object of the present invention is to provide a microcomputer that can reduce wasteful power consumption in resources as much as possible.

In order to achieve the above object, according to a first aspect of the present invention, in a microcomputer supplied with power from outside,
A plurality of resources each having a predetermined function, to which power is not supplied when the power supplied from outside is activated;
A control unit connected to the plurality of resources via a bus and supplying an access signal to the resources via the bus;
A plurality of in-resource power supply units that are respectively provided in the plurality of resources and that supply in-resource power to the corresponding resources from the power supplied from outside in response to a power activation signal;
Each of the plurality of resources is provided to detect whether an access signal supplied via the bus is addressed to a corresponding resource;
A power control unit capable of outputting the power activation signal to the corresponding in-resource power supply unit when the access signal is addressed to the corresponding resource.

  According to the first aspect, it is possible to reduce the power consumption of resources that do not require operation when the microcomputer is powered on.

It is a block diagram of the microcomputer in this Embodiment. FIG. 5 is a state diagram when a resource to which power is not supplied is accessed from the control unit after power-on of the microcomputer. It is a figure which shows the power consumption reduction effect in this Embodiment. FIG. 3 is a circuit diagram of a power control unit and an in-resource power supply unit in the first embodiment. It is a figure which shows the power status at the time of the power supply in a resource starting. It is a flowchart figure which shows operation | movement of the power supply control part in 1st Embodiment. It is a figure which shows the time chart in 1st Embodiment. FIG. 10 is a circuit diagram of a power control unit and an in-resource power supply unit according to the second embodiment. It is a flowchart figure which shows operation | movement of the power supply control part in 2nd Embodiment. It is a figure which shows the time chart in 2nd Embodiment. It is a flowchart figure which shows the power supply operation | movement of the car area network communication apparatus unit and waveform generator unit in 2nd Embodiment. FIG. 10 is a circuit diagram of a power control unit and an in-resource power supply unit according to the third embodiment. It is a flowchart figure which shows operation | movement of the power supply control part in 3rd Embodiment. It is a figure which shows the time chart in 3rd Embodiment. FIG. 10 is a circuit diagram of a power control unit and an in-resource power supply unit in a fourth embodiment. It is a flowchart figure which shows operation | movement of the power supply control part in 4th Embodiment. It is a figure which shows the time chart in 4th Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a configuration diagram of a microcomputer according to this embodiment. 1 includes a CPU 1, a debug support unit 2 that provides an on-chip debugging function 2, a nonvolatile semiconductor memory 3 for a program 3, a RAM 4, 6, a direct memory access (DMA) controller 5, and a nonvolatile semiconductor for data storage. Memory 7, car area network (CAN) communication device unit 8, clock generation circuit 9, multifunction serial 10 having multiple functions such as UART, external interrupt units 11, 22, output compare unit 12, free-run timer 13 , Input capture unit 14, watchdog timer unit 15, waveform generator unit 16 for generating an arbitrary waveform, LIN-UART 17, reload timer unit 18, up / down counter 19, A / D counter Converter 20, D / A converter 21, real-time clock unit 23, 32-bit wide high-speed internal bus 24, internal bus interface 25, 32-bit wide peripheral bus interface 26, 16-bit wide peripheral bus interface 27, buses b1, b2 , B3 and the like.

  That is, the microcomputer shown in FIG. 1 has a predetermined function such as the above unit in addition to the control unit such as the CPU 1 and the DMA controller 5 and the nonvolatile semiconductor memory 3 and RAM 4 for the program, and is accessed from the control unit. Has a number of resources that are controlled by The control unit and a large number of resources are connected via bus interfaces 24, 25, and 26 and buses b1, b2, and b3, and an access signal is transmitted from the control unit such as the CPU 1 or the DMA controller 5 to each resource via the bus. When supplied, the resource supplied with the access signal operates to realize a predetermined function. In order to start the microcomputer, power is supplied to the microcomputer from an external power source (not shown).

  In the microcomputer according to the present embodiment, when the power is activated, the power is not supplied to resources that do not need to operate when the power is activated. In FIG. 1, as an example, the debug support unit 2, FLASH 7, car area network communication device unit 8, multifunction serial 10, output compare unit 12, free-run timer 13, input capture unit 14, waveform generator unit 16 , LIN-UART 17, reload timer unit 18, up / down counter 19, etc. are not supplied with power as resources that do not need to be operated when the power is activated. Accordingly, when the microcomputer is powered on, power is supplied only to control units such as the CPU 1 and the DMA controller 5 and resources other than those described above.

  On the other hand, in the present embodiment, as shown in FIG. 1, the microcomputer controls the CPU 1 and the DMA controller 5 between the above-described resources that do not need to be operated when the power is turned on and the buses b1, b2, and b3. There are power control units 28 to 38 for detecting an access signal to the corresponding resource from the unit, and in-resource power supply units 39 to 49 for supplying power to the corresponding resource. In the present embodiment, the in-resource power supply units 39 to 49 are, for example, power switches that connect the power supply wiring in the microcomputer and the power supply wiring in the resource.

  FIG. 2 is a state diagram when a resource that is not supplied with power is accessed from the control unit after the microcomputer is powered on. In FIG. 2, when the power control units 30, 32, 33, 35, and 37 detect access signals to the corresponding resources, the power control units 30, 32, 33, 35, and 37 are power switches in the resource. A power activation signal is output to the supply units 41, 43, 44, 46, and 48. Then, the in-resource power supply units 41, 43, 44, 46, and 48 turn on the internal power switch in response to the power activation signal, and the car area network communication device unit 8, which is the corresponding resource, Power is supplied to the output compare unit 12, the free-run timer 13, the waveform generator unit 16, and the reload timer 18, respectively.

  For example, as shown by a broken line in FIG. 2, when an access signal is output from the CPU 1 to the communication device unit 8 for car area network, the power control unit 30 of the resource detects the access signal and A power activation signal is output to the power supply unit 41. Then, the in-resource power supply unit 41 supplies power to the car area network communication device unit 8 in response to the power activation signal. In FIG. 2, the resources 12, 13, 16, and 18 are similarly started to supply power in response to an access signal from the control unit. As described above, when the microcomputer is powered on, power is not necessarily supplied to all resources, and then power is supplied only to resources accessed from the control unit.

  FIG. 3 is a diagram showing the power consumption reduction effect in the present embodiment. The graph of FIG. 3 is a graph showing the transition of current consumption with respect to the operating state of the microcomputer, with the vertical axis representing current and the horizontal axis representing time. Moreover, in order to show the effect of this Embodiment, the two comparative examples are described collectively.

  The graph of Comparative Example 1 shows the transition of current consumption when power is supplied to all resources as the microcomputer is powered on. In Comparative Example 1, power W1 is consumed from time T0 when power is supplied to the microcomputer to time T10 when power is shut off.

  The graph of Comparative Example 2 shows the transition of current consumption when power is supplied to all resources when the microcomputer is powered on, and then the power of unnecessary resources is shut off. In Comparative Example 2, after the power supply to the microcomputer is started at time T0, the power of a plurality of unnecessary resources is sequentially cut off between time T1 and T2, and the microcomputer is turned off at time T10. Yes. As a result, the power W2 is consumed from time T0 to T10, and a power consumption reduction effect of ΔW21 = W1−W2 is obtained as compared with Comparative Example 1.

  On the other hand, in this embodiment, when power supply to the microcomputer is started at time T0, power is not supplied to a plurality of resources that do not require operation at the time of power activation, and time T1 during the normal operation state after power activation. From time T2 to time T2, power is supplied only to the resource to which the access signal is supplied from the control unit, and the microcomputer is turned off at time T10. For this reason, the power consumption at the time of starting the power source is less than that of the first and second comparative examples, and the power consumption state is low from the time T0 to the time T1 when the resource is first accessed. As a result, the power consumption W3 from time T0 to T10 is reduced by ΔW31 = W1−W3 from the first comparative example, and further by ΔW32 = W2−W3 from the second comparative example.

  In this way, for resources that do not require operation when the microcomputer power is turned on, power is not supplied when the power is turned on, and power is supplied to the resources when accessed from the control unit during operation after power is turned on. By doing so, the power consumption that can be reduced can be increased.

[First Embodiment]
As described above, in the first embodiment, when the microcomputer is powered on, only the control unit such as CPU 1 and the minimum necessary resources are activated, and after the activation, an access signal is supplied from the control unit such as CPU 1. The resources in the resource are supplied with power in response to the access signal. The control unit only needs to supply an access signal, and it is not necessary to confirm in advance which resource is supplied with power in the resource. For this purpose, each resource has an in-resource power supply unit that is a power switch and a power control unit.

  FIG. 4 is a circuit diagram of the power control unit and the in-resource power supply unit in the first embodiment. The resource 106 is provided in a power cutoff region where power can be individually supplied or shut off. The in-resource power supply unit includes power switches 104 and 105 that connect the power VDD in the microcomputer to the power in the resource 106, and a power management unit PMU 103 that controls on / off of the power switch. The power switches 104 and 105 are composed of, for example, P channel MOS transistors. The power control unit 102 includes an address decoding circuit 110, a start counter 111, a power status circuit 112, a bus control circuit 113, an instruction buffer 114, a buffer counter 115, and NAND gates 116 and 117.

  The address decoding circuit 110 detects an access signal supplied from the control unit such as the CPU 1 or the DMA controller 5 to the resource 106 via the bus 101, and in response to the detection of the access signal, the PMU 103, the activation counter 111, A power activation signal 126 is output to the power status circuit 112, and an address decode signal 125 is output to the instruction buffer 114.

  The PMU 103 controls on / off of the power switches 104 and 105 in response to the power activation signal 126. Two power switches 104 and 105 are provided. In response to the power activation signal 126, the PMU 103 supplies L level switch signals PSW1 and PSW2 to the power switches 104 and 105 at regular time intervals. 104 and 105 are sequentially turned on. As a result, the power supply in the resource rises in two stages from the potential 0 V to the reference potential. In order to prevent power supply noise from being applied to other circuits to which power is supplied as the power supply in the resource is started, the power supply is started in two stages as described above. Therefore, it takes a certain time for the in-resource power supply to boost to the reference potential. Even if there are not a plurality of power switches, it takes a certain time to activate the power in the resource.

  However, control units such as the CPU 1 and the DMA controller 5 send access signals such as an address signal, a write signal, and a data signal at the time of writing one after another regardless of whether or not the resource to be accessed is already powered on. Come to supply. On the other hand, after the resource detects the first access signal, it takes a certain time until the power in the resource is activated and the access signal from the control unit can be received. Therefore, in the present embodiment, the power status circuit 112 in the power control unit 102 manages the power status indicating the activation status of the in-resource power, and the power control unit 102 is supplied according to the power status signal 129. Temporary storage of the incoming access signal in the instruction buffer 114, transfer of the temporarily stored access signal after the in-resource power supply is activated, and the like are performed.

  The activation counter 111 starts counting in synchronization with a clock (not shown) in response to the power activation signal 126, and counts the time until the in-resource power supply is boosted to the reference potential, that is, the power activation waiting time. The count number n is determined in advance corresponding to the time required for power activation in the resource. When the activation counter 111 completes counting up to n, the power activation wait signal 127 is output to the power status 112.

  The instruction buffer 114 stores an access signal (address or data) from a control unit such as the CPU 1 in response to the address decode signal 125. The buffer counter 115 counts the number of data of the access signal stored in the instruction buffer 114 and outputs a count completion signal 135 to the power status circuit 112 when the count is zero.

  The power status circuit 112 generates a 2-bit power status signal 129 in response to the power activation signal 126, the power activation wait signal 127, and the count completion signal 135, and outputs it to the bus control circuit 113, the instruction buffer 114, and the NAND gate 116. To do.

  FIG. 5 is a diagram showing the power status when the in-resource power supply is activated. A power status signal 129 generated in response to the power activation signal 126, the power activation wait signal 127 and the count completion signal 135, and the corresponding power status status are shown. While the address decode circuit 110 has not yet detected an access signal from the control unit, the power activation signal 126 is “0” and the resource is in a power-off state (the power status signal 129 is “00”). Next, when the power activation signal 126 becomes “1”, the in-resource power supply starts to be activated, and while the power activation waiting signal 127 is “0”, it is in a wait state (the power status signal 129 is “01”). During this time, the access signal transmitted from the control unit is stored in the instruction buffer 114. Thereafter, when the power activation waiting signal 127 becomes “1”, it means that the activation of the in-resource power supply is completed, and the resource 106 can receive the access signal. Therefore, the access signal stored in the instruction buffer 114 is transferred to the resource 106 (the power status signal 129 is “10” for transfer). Finally, as described later, when all the access signals in the instruction buffer 114 are transferred to the resource 106, the count completion signal 135 becomes “1”, the power status is the power-on status (the power status signal 129 is “11”). )become.

  Returning to FIG. 4, the bus control circuit 113 is a selector that controls the bus path between the bus 101 and the resource 106 and the bus path between the instruction buffer 114 and the resource 106 in accordance with the power status signal 129. No bus path is connected while the power status signal 129 is “00” “01”. When the power status signal 129 becomes “10”, the bus control circuit 113 generates a bus path connecting the instruction buffer 114 and the resource 106, and the instruction buffer 114 transfers the stored access signal to the resource 106. Thereafter, when the power status signal becomes “11”, the bus control circuit 113 generates a bus path connecting the bus 101 and the resource 106, and the access signal supplied from the bus is directly input to the resource 106.

  The NAND gate 116 receives the first and second bits of the power status signal 129 as an input signal. When the power status signal 129 is “11”, the output is at the L level, and otherwise the output is at the H level.

  On the other hand, the NAND gate 117 receives the access signal from the control unit such as the CPU 1 and the output of the NAND gate 116 as an input signal, and if the power status signal 129 is not “11”, the access signal depends on the H level of the output of the NAND gate 116. If the power status signal 129 is “11”, the output is forcibly fixed to the H level and the access signal is cut off.

  FIG. 6 is a flowchart illustrating the operation of the power supply control unit in the first embodiment. In the figure, the power status is shown on the left side.

  First, in the power-off state (the power status signal 129 is “00”), when the microcomputer is powered on, the resource 106 that is power-controlled after power-on remains in the power-off state, and is not resource-controlled after power-on. Is activated (S101). The resources whose power is controlled are 7, 8, 10, 12, 13, 14, 16 to 19 in FIG.

  Next, when the address decoding circuit 110 detects that the access signal supplied from the control unit such as the CPU 1 via the bus 101 is addressed to the resource 106 (S102), the address decoding circuit 110 detects the PMU 103, the activation counter 111, and the like. A power activation signal 126 is output to the power status circuit 112. As a result, the power status becomes the wait status (the power status signal 129 is “01”).

  In the wait state, the PMU 103 sequentially outputs the switch signals PSW1 and PSW2 in response to the power activation signal 126, sequentially turns on the power switches 104 and 105, and starts activation of the in-resource power supply supplied to the resource 106. (S103). At the same time, the activation counter 111 starts counting the power supply waiting time in response to the power activation signal 126 (S104).

  If the power control unit 102 is supplied with an access signal from a control unit such as the CPU 1 while the in-resource power supply is boosted (“Yes” in S105), the bus control circuit 113 is supplied with the access signal from the control unit. The bus path connecting the bus 101 and the resource 106 is blocked (S106), the access signal is stored in the instruction buffer 114 (S107), and the buffer counter 115 counts the number of access signals stored in the instruction buffer 114 (S107). S108).

  When the in-resource power supply is boosted to the reference potential and the activation of the in-resource power supply is completed (YES in S109), the power supply status state shifts to the transfer state. In this transfer state, until the count value of the buffer counter 115 reaches 0 (NO in S110), the bus control circuit 113 generates a bus path connecting the instruction buffer 114 and the resource 106 (S111), and the instruction buffer 114 stores. The access signal thus transferred is transferred to the resource 106 (S112).

  When the counter number of the buffer counter 115 becomes 0 (YES in S110), that is, when the transfer of the access signal from the instruction buffer 114 to the resource 106 is completed (S113), the bus control circuit 113 transmits the resource from the bus 101 to the resource 106. (S114), the resource 106 starts a normal operation of receiving an access signal directly from the bus 101.

  FIG. 7 is a diagram illustrating a time chart according to the first embodiment. A signal waveform diagram is shown for the operation of the power supply control unit 102 shown in the flowchart of FIG. The power control unit 102 operates in synchronization with the clock 121. An address / data signal 122 and a write signal 124 are supplied as access signals from the control unit such as the CPU 1 to the resource 106 via the bus 101. Hereinafter, based on cycles T1 to T21 of the clock 121, the operation in the power supply control unit will be described.

  As address / data signal 122, address adrA-0 is supplied in cycle T2, and data data0 corresponding thereto is supplied in cycle T3. The control unit is supplied with the H level write signal 124 together with the data data0 in cycle T3 for one cycle. The address decode circuit 110 internally latches the address adrA-0 in the address / data signal 122 as the address signal 123 and detects whether the address is addressed to the resource 106. In the example of FIG. 7, the address decode circuit 110 detects that the address adrA-0 is an address addressed to the resource 106, and outputs an H-level address decode signal 125 at cycle T3.

  In response to this, the power supply start signal 126 becomes H level in cycle T4, the start counter 111 starts counting down from n, and the power supply start wait time 128 as the counter value of the start counter is synchronized with the clock 121 from n. It has been decremented. Also, from cycle T4, addresses and data as access signals are sequentially stored in the respective buffers 131 in the instruction buffer 114. In cycles T4 and T5, the next address and data are supplied, and then in cycles T9 and T10, the address and data are sequentially input in two clock cycles until the eighth address adrA-7 and data data7 are supplied. Are supplied and stored in the instruction buffer 114.

  The write counter 132 in the buffer counter 115 is incremented every time an access signal is stored and indicates the next write address. When the eighth address and data are stored, the count value of the write counter 132 becomes “8”. ing. Further, the read counter 133 is incremented every time the stored access signal is read and indicates the next read address, and remains “0” until the cycle T13. The buffer count number 134 indicates the number of access signals stored in the instruction buffer 114, and is a value obtained by subtracting the count value of the read counter 133 from the write counter 132.

  The cycles from T4 to T12 are in the wait state. When the decrement value by the activation counter 111 reaches “0” in cycle T13, the activation counter 111 sets the power activation waiting signal 127 to the H level. As a result, the power supply status state becomes the transfer state. In response to the transfer state “10” of the power status signal 129, the instruction buffer 114 starts to transfer the stored access signal to the resource 106 in order from the read address of the read counter 133. At this time, the bus control circuit 113 generates a bus path from the instruction buffer 114 to the resource 106 according to the transfer state “10” of the power status signal 129.

  When the eighth access signals adrA-7 and data7 are transferred to the resource 106 in cycle T20, the buffer count number 134 in the buffer counter 115 becomes “0”, and the power status circuit 112 receives the power status signal 129. Is set to “11” in the power-on state. In response to this, the bus control circuit 113 generates a bus path from the bus 101 to the resource 106, and the resource 106 inputs an access signal directly from the bus 101.

  As described above, according to the first embodiment, when the power supply control unit 102 detects an access signal addressed to itself from a control unit such as a CPU in a resource that has been turned off when the microcomputer is powered on. , The power switch of the corresponding in-resource power supply unit is turned on to start the power in the resource. As a result, power is supplied only to resources that are accessed from the control unit and need to be operated, and the power consumption of the resources can be reduced.

  Further, the power supply control unit 102 stores the access signal (address and data) continuously supplied from the control unit during boosting of the in-resource power supply in the instruction buffer 114, and after completing the boosting of the in-resource power supply, The access signal (address and data) in 114 is transferred to the corresponding resource. Further, the power supply control unit 102 restores the bus path between the bus 101 and the resource 106 after completing the transfer of all stored access signals, and then the resource 106 inputs the access signal directly from the bus 101. As described above, the power supply control unit 102 activates the in-resource power supply in response to the access signal from the control unit. However, even if access signals are successively supplied from the control unit as in the normal operation, they are transferred to the instruction buffer 114. Therefore, the control unit such as the CPU 1 can operate normally even if some of the resources are not activated when the power is activated. An access signal can be transmitted to the resource.

[Second Embodiment]
In the second embodiment, when the microcomputer is activated, only the control unit and the minimum necessary resources are activated, and after the activation, two resources supplied with an access signal from the control unit are connected to the access signal. In response to each, the in-resource power is supplied.

  FIG. 8 is a circuit diagram of the power control unit and the in-resource power supply unit in the second embodiment. The resources 206 and 210 provided in the power shut-off area where the power can be individually supplied or shut off are resources that do not need to be operated when the microcomputer is powered on, and the power is shut off. The in-resource power supply unit of the resource 206 includes switches 204 and 205 that supply the power VDD in the microcomputer to the resource 206, and a power management unit PMU 203 that controls on / off of the power switch. The in-resource power supply unit of the resource 210 includes switches 208 and 209 that supply the power VDD in the microcomputer to the resource 210, and a power management unit PMU 203 that controls on / off of the power switch. The in-resource power supply unit of the resources 206 and 210 boosts the in-resource power supply in two stages as in the first embodiment. On the other hand, the power control unit 202 of the resource 206 includes an address decoding circuit 220, a start counter 221, a power status circuit 222, a bus control circuit 223, an instruction buffer 224, a buffer counter 225, and NAND gates 226 and 227. The power supply control unit 207 of the resource 210 includes an address decoding circuit 230, a start counter 231, a power supply status circuit 232, a bus control circuit 233, an instruction buffer 234, a buffer counter 235, and NAND gates 236 and 237. That is, the power control unit 202 and the in-resource power control units 203 to 205 of the resource 206, and the power control unit 207 and the in-resource power control units 203, 208, and 209 of the resource 210 are described in the first embodiment. Correspond to the power control unit 102 and the in-resource power control units 103 to 105 of the resource 106, respectively.

  After the microcomputer power is turned on, when the access signals are supplied to the resources 206 and 210 from the control unit such as the CPU 1 or the DMA controller 5 via the bus 101, the address decoding circuit 220 receives the resource 206 via the bus 201. The addressed access signal is detected, and in response to the access signal, the power activation signal 246 is output to the PMU 203, the activation counter 221 and the power status circuit 222, and the address decode signal 245 is output to the instruction buffer 224. The address decoding circuit 230 detects an access signal addressed to the resource 210 via the bus 201, and in response to the access signal, sends a power activation signal 265 to the PMU 203, the activation counter 231 and the power status circuit 232 to the instruction buffer. An address decode signal 264 is output to 234.

  In response to the power activation signal 246, the PMU 203 supplies the L level switch signals PSW1 and PSW2 to the power switches 204 and 205 at regular intervals, and sequentially turns on the power switches 204 and 205. In response to the power activation signal 265, the PMU 203 supplies the L level switch signals PSW3 and PSW4 to the power switches 208 and 209 at regular time intervals, and sequentially turns on the power switches 208 and 209.

  The activation counters 221 and 231 respond to the power activation signals 246 and 265, respectively, start counting in synchronization with a clock (not shown), and count the time until the in-resource power supply is boosted to the reference potential, that is, the power activation waiting time. To do. When the activation counter completes counting to a predetermined count number n, it outputs power activation waiting signals 247 and 267 to the power status circuits 222 and 232, respectively.

  The power status circuits 222 and 232 generate 2-bit power status signals 249 and 268 in response to the power activation signals 246 and 265, the power activation wait signals 247 and 266, and the count completion signals 256 and 275, respectively. 223 and 233, instruction buffers 224 and 234, and NAND gates 226 and 236, respectively.

  The bus control circuit 223 is a selector that controls the bus path between the bus 201 and the resource 206 and the bus path between the instruction buffer 224 and the resource 206 in accordance with the power status signal 249. The bus control circuit 233 is a selector that controls the bus path between the bus 201 and the resource 210 and the bus path between the instruction buffer 234 and the resource 210 according to the power status signal 268. No bus path is connected while the power status signals 249 and 268 are “00” and “01”. When the power status signals 249 and 268 become “10”, the bus control circuits 223 and 233 generate bus paths that connect the instruction buffers 224 and 234 and the resources 206 and 210, respectively, and the instruction buffers 224 and 234 store them. Are transferred to the resources 206 and 210, respectively. Thereafter, when the power status signal becomes “11”, the bus control circuits 223 and 233 respectively generate a bus path that connects the bus 201 and the resource 206 and a bus path that connects the bus 201 and the resource 210. The supplied access signal is directly input to the resources 206 and 210.

  The NAND gates 226 and 236 receive the first and second bits of the power status signals 249 and 268 as input signals. When the power status signals 249 and 268 are “11”, the output is L level, otherwise the H level. It becomes.

  The NAND gates 227 and 237 receive the access signal from the control unit and the outputs of the NAND gates 226 and 236 as input signals. If the power status signals 249 and 268 are not “11”, the output of the NAND gates 226 and 236 is H When the power status signals 249 and 268 are “11”, the access signals are forcibly fixed to the H level and the access signals are cut off, respectively.

  As described above, when the power control unit 202 of the resource 206 and the power control unit 207 of the resource 210 detect the access signal addressed to themselves, they respectively perform the power supply operation within the resource in the same manner as in the first embodiment. .

  FIG. 9 is a flowchart showing the operation of the power supply control unit in the second embodiment.

  First, the resources such as the resources 206 and 210 that do not need to be operated when the power is turned on are left in the power-off state, and the microcomputer is turned on. Thereafter, the resources 206 and 210 are supplied with an access signal from the control unit such as the CPU 1 via the bus 201.

  First, when the address decode circuit 220 of the resource 206 detects that the access signal is addressed to the resource 206 (S201), the address decode circuit 220 outputs a power activation signal 246 to the PMU 203, activation counter 221, and power status circuit 222. . In response to the power activation signal 246, the PMU 203 sequentially outputs switch signals PSW1 and PSW2, turns on the switches 204 and 205 in order, and starts activation of the in-resource power supplied to the resource 206 (S202). If the resource 206 is supplied with an access signal from the control unit via the bus while boosting the power supply in the resource, the bus control circuit 223 causes the bus 201 and the resource 206 to which the access signal from the control unit is supplied. And the access signal is stored in the instruction buffer 224 (S203), and the buffer counter 225 counts the number of access signals stored in the instruction buffer 224. When the in-resource power supply is boosted to the reference potential and the activation of the in-resource power supply is completed (S204), the bus control circuit 223 generates a bus path that connects the instruction buffer 224 and the resource 206, and the counter value of the buffer counter 225 is Until it becomes 0, the instruction buffer 224 transfers the stored access signal to the resource 206 (S205). When the counter value of the buffer counter 225 reaches 0, that is, when the transfer of the access signal from the instruction buffer 224 to the resource 206 is completed, the bus control circuit 223 generates a bus path from the bus 201 to the resource 206. (S206), the resource 206 starts a normal operation of receiving an access signal directly from the bus 201 (S207).

  On the other hand, when the access to the resource 210 occurs following the access to the resource 206, the address decoding circuit 230 of the resource 210 detects that the access signal is addressed to the resource 210 (S211), and the address decoding circuit 230 detects the PMU 203. The power supply activation signal 265 is output to the activation counter 231 and the power supply status circuit 232. In response to the power activation signal 265, the PMU 203 outputs switch signals PSW3 and PSW4, turns on the switches 208 and 209 in order, and starts activation of the in-resource power supplied to the resource 210 (S212). If the resource 210 is supplied with an access signal from the control unit via the bus while the in-resource power supply is boosted, the bus control circuit 233 receives the bus 201 and the resource 210 to which the access signal from the control unit is supplied. And the access signal is stored in the instruction buffer 234 (S213), and the buffer counter 235 counts the number of access signals stored in the instruction buffer 234. When the in-resource power supply is boosted to the reference potential and the activation of the in-resource power supply is completed (S214), the bus control circuit 233 generates a bus path connecting the instruction buffer 234 and the resource 210, and the counter value of the buffer counter 235 is Until it becomes 0, the instruction buffer 234 transfers the stored access signal to the resource 210 (S215). When the counter value of the buffer counter 235 reaches 0, that is, when the transfer of the access signal from the instruction buffer 234 to the resource 210 is completed, the bus control circuit 233 generates a bus path from the bus 201 to the resource 210. (S216), the resource 210 starts a normal operation of receiving an access signal directly from the bus 201 (S217).

  As described above, when the power control unit 202 of the resource 206 and the power control unit 207 of the resource 210 detect the access signal addressed to the resource 206, they respectively perform the in-resource power supply operation as in the first embodiment.

  FIG. 10 is a diagram illustrating a time chart in the second embodiment. A signal waveform diagram is shown for the operation of the power control units 202 and 207 shown in the flowchart of FIG. The power control units 202 and 207 operate in synchronization with the clock 241. An address / data signal 242 and a write signal 244 are supplied to the resources 206 and 210 via the bus 201 from a control unit such as the CPU 1. Hereinafter, the operation in the power supply control unit will be described based on the cycles T1 to T34 of the clock 241.

  As address / data signal 242, address adrA-0 is supplied in cycle T2, and data dataA-0 corresponding thereto is supplied in cycle T3. The address decode circuits 220 and 230 internally latch the address adrA-0 as the address signals 243 and 262 out of the address / data signal 242, and detect whether or not each address is addressed to itself. In the example of FIG. 10, the address decode circuit 220 detects that the address adrA-0 is addressed to the resource 206, and outputs an H-level address decode signal 245 at cycle T3.

  In response to this, the power source activation signal 246 becomes H level in cycle T4, the activation counter 221 starts counting down from n, and the power source activation waiting time 248 as the counter value of the activation counter 221 is synchronized with the clock 241 from n. Have been decremented. Also, from cycle T4, addresses and data as access signals are sequentially stored in the respective buffers 252 in the instruction buffer 224. In cycles T4 and T5, the next address and data are supplied, and then in cycles T11 and T12, the address and data are transferred in two clock cycles until the eighth address adrA-7 and data dataA-7 are supplied. They are supplied in order and stored in the instruction buffer 224.

  The write counter 253 in the buffer counter 225 is incremented every time an access signal is stored and indicates the next write address. When the eighth address and data are stored, the count value of the write counter 253 becomes “8”. ing. Further, the read counter 254 is incremented every time the stored access signal is read and indicates the next read address, and remains “0” until the cycle T15. The buffer count number 255 indicates the number of access signals stored in the instruction buffer 224, and is a value obtained by subtracting the count value of the read counter 254 from the write counter 253.

  From cycle T4 to T14 is a wait state. When the decrement value by the activation counter 221 reaches “0” in cycle T15, the activation counter 221 sets the power activation waiting signal 247 to the H level. As a result, the power supply status state becomes the transfer state. In response to the transfer state “10” of the power status signal 249, the instruction buffer 224 starts to transfer the stored access signal to the resource 206 in order from the read address of the read counter 254. At this time, the bus control circuit 223 generates a bus path from the instruction buffer 224 to the resource 206 according to the transfer state “10” of the power status signal 249.

  When the eighth access signals adrA-7 and dataA-7 are transferred to the resource 206 in cycle T23, the buffer count number 255 in the buffer counter 225 becomes “0”, and the power status circuit 222 The signal 249 is set to “11” in the power-on state. In response to this, the bus control circuit 223 generates a bus path from the bus 201 to the resource 206. As a result, when the ninth access signals adrA-8 and dataA-8 are transferred to the resource 206 in cycle T25, the resource 206 inputs the access signal directly from the bus 201.

  On the other hand, the address decoding circuit 230 corresponding to the resource 210 detects that the address adrB-0 of the access signal supplied in cycle T9 is addressed to itself, and outputs an H-level address decoding signal 264 in cycle T10. ing.

  In response to this, the power activation signal 265 becomes H level at cycle T11, the activation counter 231 starts counting down from n, and the power activation waiting time 266 which is the counter value of the activation counter 231 is synchronized with the clock 241 from n. It has been decremented. In addition, from the cycle T11, addresses and data as access signals are sequentially stored in the respective buffers 271 in the instruction buffer 234. In cycles T13 and T14, the next address and data are supplied. After that, until the third address adrB-2 and data dataB-2 are supplied in cycles T15 and T16, the address and data are transferred in two clock cycles. They are supplied in order and stored in the instruction buffer 234.

  The write counter 272 in the buffer counter 235 is incremented every time an access signal is stored and indicates the next write address. When the third address and data are stored, the count value of the write counter 272 becomes “3”. ing. Further, the read counter 273 is incremented every time the stored access signal is read to indicate the next read address, and remains “0” until the cycle T23. The buffer count number 274 indicates the number of access signals stored in the instruction buffer 234, and is a value obtained by subtracting the count value of the read counter 273 from the write counter 272.

  From cycle T11 to T22 is a wait state. When the decrement value by the activation counter 231 reaches “0” in cycle T23, the activation counter 231 sets the power activation waiting signal 266 to the H level. As a result, the power status becomes the transfer state. In response to the transfer state “10” of the power status signal 268, the instruction buffer 234 starts to transfer the stored access signal to the resource 210 in order from the read address of the read counter 273. At this time, the bus control circuit 233 generates a bus path from the instruction buffer 234 to the resource 210 according to the transfer state “10” of the power status signal 268.

  When the third access signals adrB-2 and dataB-2 are transferred to the resource 210 in cycle T29, the buffer count number 274 in the buffer counter 235 becomes “0”, and the power status circuit 232 The signal 268 is set to “11” in the power-on state. In response to this, the bus control circuit 233 generates a bus path from the bus 201 to the resource 210. As a result, when the fourth access signals adrB-3 and dataB-3 are transferred to the resource 210 in the cycle T31, the resource 210 inputs the access signal directly from the bus 201.

  As an application example of the second embodiment, communication with an in-vehicle network CAN is given. For example, after the in-resource power is supplied to the car area network communication device unit 8 by the access signal from the CPU 1, the data received by the car area network communication device unit 8 by communication is transferred to the waveform generator unit 16. For this reason, the DMA controller 5 supplies the waveform generator unit 16 with an access signal, thereby supplying the in-resource power source to the waveform generator unit 16 and transferring the data by DMA. Hereinafter, the operation of the power control unit will be described.

  FIG. 11 is a flowchart showing the power supply operation of the car area network communication device unit and the waveform generator unit in the second embodiment. Power-off for resources that do not require operation when power is turned on, such as car area network communication device unit 8 (corresponding to resource 206 in FIGS. 8 and 10) and waveform generator unit 16 (corresponding to resource 210 in FIGS. 8 and 10) Leave the power on and start the microcomputer. Thereafter, the car area network communication device unit 8 is supplied with an access signal from the CPU 1. When the address decoding circuit 220 of the car area network communication device unit 8 detects that the access signal is addressed to the car area network communication device unit 8 (S231), the PMU 203 responds to the power activation signal 246. Then, the switch signals PSW1 and PSW2 are sequentially output, the switches 204 and 205 are sequentially turned on, and the activation of the in-resource power supplied to the car area network communication device unit 8 is started (S232). If the car area network communication device unit 8 is supplied with an access signal from the CPU 1 via the bus while boosting the power in the resource, the bus control circuit 223 is supplied with the access signal from the CPU 1. The bus path connecting the bus 201 and the car area network communication device unit 8 is cut off, the access signal is stored in the instruction buffer 224 (S233), and the buffer counter 225 stores the access signal stored in the instruction buffer 224. Count the number. When the resource power supply is boosted to the reference potential and the activation of the resource power supply is completed (S234), the bus control circuit 223 communicates with the instruction buffer 224 and the car area network communication until the counter value of the buffer counter 225 becomes zero. A bus path connecting the device unit 8 is generated, and the instruction buffer 224 starts to transfer the stored access signal to the car area network communication device unit 8 (S235). When the counter value of the buffer counter 225 reaches 0, that is, when the transfer of the access signal from the instruction buffer 224 to the car area network communication device unit 8 is completed, the bus control circuit 223 performs the car control from the bus 201. A bus route to the area network communication device unit 8 is generated (S236), and the car area network communication device unit 8 starts a normal operation of receiving an access signal directly from the bus 201 (S237).

  After receiving the setting data for the waveform generator unit 16 by communication (S238), the car area network communication device unit 8 issues a data transfer command to the DMA controller 5 with the waveform generator unit 16 (S239). In response to this, the waveform generator unit 16 is supplied with an access signal from the DMA controller 5. When the address decoding circuit 230 of the waveform generator unit 16 detects that the access signal is addressed to the waveform generator unit 16 (S240), it outputs a power source activation signal 265 to the PMU 203 and the activation counter 231. In response to the power supply activation signal 265, the PMU 203 outputs switch signals PSW3 and PSW4, sequentially turns on the switches 208 and 209, and starts activation of the in-resource power supply supplied to the waveform generator unit 16 (S241). . If the waveform generator unit 16 is supplied with an access signal via the bus by the DMA controller 5 while boosting the power in the resource (S240, S243, S246), the bus control circuit 233 receives the access signal from the DMA controller 5. Is interrupted, the access signal is stored in the instruction buffer 234 (S241, S244, S247), and the buffer counter 235 stores the access stored in the instruction buffer 234. Count the number of signals. When the in-resource power supply is boosted to the reference potential and the startup is completed (S248), the bus control circuit 233 generates a bus path that connects the instruction buffer 234 and the waveform generator unit 16, and the counter value of the buffer counter 235 is set to 0. Until this happens, the instruction buffer 234 transfers the stored access signal to the waveform generator unit 16 (S249). When the counter value of the buffer counter 235 reaches 0, that is, when the transfer of the access signal from the instruction buffer 234 to the waveform generator unit 16 is completed, the bus control circuit 233 causes the bus from the bus 201 to the waveform generator unit 16. A path is generated (S250), and the waveform generator unit 16 starts a normal operation of receiving an access signal directly from the bus 201 (S251).

  In this way, the car area network communication device unit 8 and the waveform generator unit 16 can be supplied with in-resource power without problems in response to the access signals from the CPU 1 and the DMA controller 5, respectively. is there.

  As described above, according to the second embodiment, in a resource that remains off when the microcomputer is powered on, each control unit such as a CPU or DMA controller supplies an access signal to the resource. The resource power control unit responds to the access signal addressed to itself and supplies power to the corresponding resource. Therefore, if a control unit such as a CPU normally performs an access operation without performing special power activation control for a resource that remains in a power-off state when the power is activated, the resource to be accessed is activated and the desired resource is activated. The function can be executed.

[Third Embodiment]
In the third embodiment, when the power source of the microcomputer is activated, the power source is activated only for the control unit and the minimum necessary resources, and after the activation, one of the two resources supplied with the access signal from the control unit is activated. The resource is supplied with power in the resource in response to the access signal addressed to itself, and the other resource is supplied with power in the resource in response to the access signal addressed to itself. In-resource power is supplied in response to startup.

  FIG. 12 is a circuit diagram of the power control unit and the in-resource power supply unit in the third embodiment. The power control units 302 and 307 and the in-resource power supply units 303 to 305, 308, and 309 of the resources 306 and 310 and the power source supply units 303 to 305, 308, and 309 provided in the power cut-off area where power can be individually supplied or cut off are the same as in the second embodiment. This corresponds to the power control units 202 and 207 and the in-resource power supply units 203 to 205, 208 and 209. However, the third embodiment is different from the second embodiment in that the power supply control unit 307 includes a continuous activation flag 311, an AND gate 312, and an OR gate 313. Hereinafter, differences from the second embodiment will be described.

  A continuous activation flag 311 that is a 1-bit flag indicates whether or not the power supply control unit 307 supplies power to the resource 310 in response to the power activation of the resource 306. Can be set. When this flag is at the H level, the power control unit 307 supplies power to the resource 310 in response to the power activation of the resource 306, and does not supply it when at the L level.

  The AND gate 312 receives the power activation signal 346 and the continuous activation flag 311 of the power control unit 302 as input signals, and the output signal becomes H level only when both input signals are at H level.

  The OR gate 313 receives the power activation signal 365 output when the address decode circuit 330 detects that the access signal is addressed to itself and the output signal of the AND gate 312 as input signals, and any of the input signals is at the H level. If so, the power activation signal 376 is supplied to the PMU 303 and the activation counter 331. In response to the power activation signal 376, the PMU 303 outputs L level switch signals PSW3 and PSW4 at regular time intervals, and sequentially turns on the power switches 308 and 309. Therefore, if the continuous activation flag is at the H level, the control unit such as CPU 1 starts the power supply operation for both the resources 306 and 310 by supplying the access signal to the resource 306.

  The activation counter 331 starts counting in synchronization with a clock (not shown) in response to the power activation signal 376, and counts the time until the in-resource power supply is boosted to the reference potential, that is, the power activation waiting time. When the activation counter 331 completes the count up to a predetermined count number n, the activation counter 331 outputs a power activation wait signal 366 to the power status circuit 332.

  FIG. 13 is a flowchart illustrating the operation of the power supply control unit according to the third embodiment.

  First, the resources such as the resources 306 and 310 that do not need to be operated when the power is turned on remain in the power-off state, and the microcomputer is turned on. Then, the continuous activation flag 311 is set to the H level from a control unit such as the CPU 1 (S301). Thereafter, the resource 306 is supplied with an access signal from a control unit such as the CPU 1 via the bus 301.

  When the address decoding circuit 320 of the resource 306 detects that the access signal is addressed to the resource 306 (S302), it outputs a power activation signal 346 to the PMU 303, the activation counter 321, the power status circuit 322, and the AND gate 312.

  In response to the power activation signal 346, the PMU 303 sequentially outputs the switch signals PSW1 and PSW2, turns on the switches 304 and 305 in sequence, and starts activation of the in-resource power supplied to the resource 306 (S310).

  On the other hand, the AND gate 312 supplies an H level output signal to the OR gate 313 in response to the power activation signal 346 and the continuous activation flag 311, and the OR gate 313 outputs the power activation signal 376 to the PMU 303. In response to the power activation signal 376, the PMU 303 outputs switch signals PSW3 and PSW4, turns on the switches 308 and 309 in order, and starts activation of the in-resource power supplied to the resource 310 (S320).

  Then, the power control units 302 and 307 perform power supply operations to the resources 306 and 310, respectively, as in the second embodiment (S311 to S315, S321 to S325).

  FIG. 14 is a diagram illustrating a time chart according to the third embodiment. A signal waveform diagram is shown for the operation of the power supply control units 302 and 307 shown in the flowchart of FIG. The power control units 302 and 307 operate in synchronization with the clock 341. An address / data signal 342 and a write signal 344 are supplied from the control unit such as the CPU 1 to the resources 306 and 310 via the bus 301. Hereinafter, based on cycles T1 to T34 of the clock 341, the operation in the power supply control unit will be described.

  As address / data signal 342, address adrA-0 is supplied in cycle T2, and data dataA-0 is supplied in cycle T3. The address decoding circuits 320 and 330 internally latch the address adrA-0 as the address signals 343 and 362 out of the address / data signal 342, and detect whether the address is addressed to itself. In FIG. 14, the address decode circuit 320 detects that the address adrA-0 is addressed to the resource 306, and outputs an H-level address decode signal 345 at cycle T3. In response to this, the power supply activation signal 346 becomes H level in cycle T4, the activation counter 321 starts counting down from n, and the power supply activation waiting time 348 as the counter value of the activation counter is synchronized with the clock 341 from n. It has been decremented. In addition, from the cycle T4, addresses and data as access signals are sequentially stored in the respective buffers 352 in the instruction buffer 324. Thereafter, the power control unit 302 corresponding to the resource 306 performs the same power supply operation as that of the power control unit 202 corresponding to the resource 206 in the second embodiment.

  On the other hand, in the power supply control unit 307 corresponding to the resource 310, the address adrA-0 is not addressed to itself, so the address decode signal 364 does not become H level, but the OR gate 313 responds to the power supply activation signal 346 in cycle T4. The power activation signal 376 becomes H level. As a result, the activation counter 331 starts counting down from n, and the power supply activation waiting time 367, which is the counter value of the activation counter, is decremented from n in synchronization with the clock 341. Then, in cycles T9 and T10, the first address adrB-0 and data dataB-0 are supplied, and addresses and data as access signals are sequentially stored from T11 to each buffer 334 in the instruction buffer 334. . In cycles T13 and T14, the next address and data are supplied, and then in cycles T21 and T22, the addresses and data are sequentially in two clock cycles until the eighth address adrB-7 and data dataB-7 are supplied. Are stored in the instruction buffer 334.

  The power status of the power controller 307 is a wait state from cycle T4 to T14. When the decrement value by the activation counter 331 reaches “0” in cycle T15, the activation counter 331 sets the power activation waiting signal 366 to the H level. As a result, the power supply status state becomes the transfer state. In response to the transfer state “10” of the power status signal 368, the instruction buffer 334 starts to transfer the stored access signal to the resource 310 in order from the read address of the read counter 373. At this time, the bus control circuit 333 generates a bus path from the instruction buffer 334 to the resource 310 according to the transfer state “10” of the power status signal 368.

  When the eighth access signal adrB-7 and data dataB-7 are transferred to the resource 310 in cycle T27, the buffer count number 374 in the buffer counter 335 becomes “0”, and the power status circuit 332 The signal 368 is set to the power-on state “11”. In response to this, the bus control circuit 333 generates a bus path from the bus 301 to the resource 310. As a result, when the ninth access signals adrB-8 and dataB-8 are transferred to the resource 310 in cycle T31, the resource 310 inputs the access signal directly from the bus 301.

  As described above, according to the third embodiment, for the resources that remain shut off when the microcomputer is powered on, the power control unit of each resource has the continuous activation flag so that the access signal addressed to itself is displayed. In addition to responding, it responds to power activation of the related resource and supplies power to the corresponding resource. That is, a control unit such as a CPU can start up the power supply including the related resources only by supplying an access signal to one resource. Therefore, when there is a relationship in which the resource 310 operates due to the operation of the resource 306, the resource 310 is activated without waiting for access to itself in response to the activation of the resource 306 by accessing the resource 306. Therefore, when the resource 310 is subsequently accessed, the power supply has already been activated, and the operation can be started without delay.

[Fourth Embodiment]
In the fourth embodiment, when the microcomputer is activated, only the control unit and the minimum necessary resources are activated. After the activation, one of the two resources supplied with an access signal from the control unit is activated. The resource is supplied with the in-resource power in response to the access signal addressed to itself, and the other resource waits for the in-resource power supply of one resource to increase to the reference potential when the access signal addressed to itself is detected. Power in the resource.

  FIG. 15 is a circuit diagram of the power control unit and the in-resource power supply unit according to the fourth embodiment. The power control units 402 and 407 of the resources 406 and 410 and the in-resource power supply units 403 to 405, 408, and 409 provided in the power cut-off area where power can be individually supplied or cut off are the same as those in the second embodiment. This corresponds to the power control units 202 and 207 and the in-resource power supply units 203 to 205, 208 and 209. However, the fourth embodiment is different from the second embodiment in that the power control unit 407 includes a power activation standby flag 411, an OR gate 412, and an AND gate 413. Hereinafter, differences from the second embodiment will be described.

  The power activation standby flag 411, which is a 1-bit flag, supplies power to the resource 410 after waiting until the power in the resource of the resource 406 increases to the reference potential when the power control unit 407 detects an access signal addressed to itself. It can be set from a control unit such as the CPU 1 based on the execution of the program. When this flag is at H level, the power supply control unit 407 waits for the power supply in the resource of the resource 406 to be boosted to the reference potential when detecting the access signal addressed to itself, and supplies power to the resource 410, Not supplied when at L level.

  The OR gate 412 receives the power activation waiting signal 447 of the power controller 402 and the inverted value of the power activation waiting flag 411 as input signals, and if any of the input signals is H level, the output signal becomes H level. Therefore, when the power activation standby flag is set to H level, the output of the OR gate 412 becomes H level after the power activation waiting signal 447 in the power control unit 402 of the resource 406 rises to H level.

  The AND gate 413 receives the power activation signal 465 output when the address decoding circuit 430 detects that the access signal is addressed to itself and the output signal of the OR gate 412 as input signals, and when both input signals are at the H level. Only the power activation signal 476 is supplied to the PMU 403 and the activation counter 431. In response to the power activation signal 476, the PMU 403 outputs L level switch signals PSW3 and PSW4 at regular time intervals, and sequentially turns on the power switches 408 and 409. In other words, if the power activation standby flag is at the H level, the power supply control unit 407 waits for the completion of boosting of the in-resource power supply of the resource 406 when the access signal addressed to the resource 410 is supplied and detected. The power supply operation 410 is started.

  The activation counter 431 responds to the power activation signal 476, starts counting in synchronization with a clock (not shown), and counts the time until the in-resource power supply is boosted to the reference potential, that is, the power activation waiting time. When the start counter 431 completes the count up to a predetermined count number n, the start counter 431 outputs a power start wait signal 466 to the power status circuit 432.

  FIG. 16 is a flowchart showing the operation of the power supply control unit in the fourth embodiment. First, the resources such as the resources 406 and 410 that do not need to be operated when the power is turned on remain in the power-off state, and the microcomputer is turned on. Then, the power activation standby flag 411 is set to the H level from the control unit such as the CPU 1 (S401). Thereafter, the resources 406 and 410 are supplied with an access signal via a bus 401 from a control unit such as the CPU 1.

  First, when the address decoding circuit 420 of the resource 406 detects that the access signal is addressed to the resource 406 (S402), the address decoding circuit 420 outputs the power activation signal 446 to the PMU 403, the activation counter 421, and the power status circuit 422. .

  In response to the power activation signal 446, the PMU 403 outputs switch signals PSW1 and PSW2, sequentially turns on the switches 404 and 405, and starts activation of the in-resource power supply supplied to the resource 406 (S410). And the power supply control part 402 performs the power supply operation | movement with respect to the resource 406 similarly to the power supply control part 202 in 2nd Embodiment (S411-S415). However, in the fourth embodiment, when the power supply in the resource 406 is boosted to the reference potential and the start-up is completed (S412), the start-up counter 421 uses not only the power supply status circuit 422 but also the OR gate 412 is also supplied.

  On the other hand, when access to the resource 410 occurs following access to the resource 406, the address decoding circuit 430 of the resource 410 detects that the access signal is addressed to the resource 410 (S403), and the AND gate 413 and the power supply status are detected. A power activation signal 465 is output to the circuit. While the output signal of the OR gate 412 is at the L level, that is, while the power activation waiting signal 447 is not at the H level because the power in the resource 406 is not boosted to the reference potential, the power control unit 407 Waits for power activation in the resource 410 (S420). When the power supply in the resource 406 has been boosted to the reference potential and the activation counter 421 sets the power activation wait signal 447 to the H level (S412), the power control unit 407 activates the in-resource power supply to be supplied to the resource 410. Start (S421). Then, the power supply control unit 407 performs a power supply operation to the resource 410, similarly to the power supply control unit 207 in the second embodiment (S422 to S426).

  FIG. 17 is a diagram illustrating a time chart according to the fourth embodiment. A signal waveform diagram is shown for the operation in the power supply control units 402 and 407 shown in the flowchart of FIG. The power control units 402 and 407 operate in synchronization with the clock 441. An address / data signal 442 and a write signal 444 are supplied to the resources 406 and 410 via the bus 401 from a control unit such as the CPU 1. Hereinafter, based on cycles T1 to T34 of the clock 441, the operation in the power supply control unit will be described.

  When the address adrA-0 is supplied as the address / data signal 442 in cycle T2 and the data dataA-0 is supplied in cycle T3, the address decoding circuit 420 detects that the address adrA-0 is addressed to the resource 406, and the cycle T3 The H level address decode signal 445 is output. In response to this, the power activation signal 446 becomes H level in cycle T4, the activation counter 421 starts counting down from n, and the power activation delay 448 that is the counter value of the activation counter 421 is synchronized with the clock 441 from n. Decrement. Further, from cycle T4, addresses and data as access signals are sequentially stored in the respective buffers 452 in the instruction buffer 424. Thereafter, the power control unit 402 corresponding to the resource 406 performs the same power supply operation as that of the power control unit 202 corresponding to the resource 206 in the second embodiment.

  On the other hand, when the power control unit 407 corresponding to the resource 410 is supplied with the first address adrB-0 and data dataB-0 in cycles T9 and T10, the address decoding circuit 430 indicates that the access signal is addressed to the resource 410. And an H-level address decode signal 464 is output. In response to this, the address decode circuit 430 sets the power supply activation signal 465 to the H level in cycle T11. At this time, the power supply in the resource 406 has not completed boosting to the reference potential, and the power supply activation wait signal 447 is Since it is at the L level, the power activation signal 476 that is the output of the AND gate 413 remains at the L level. The power supply control unit 407 stores the address adrB-0 and the data dataB-0 in each buffer 471 in the instruction buffer 434 in the cycle T11, and then the eighth address adrB-7 and the data dataB- in the cycles T21 and T22. Until 7 is supplied, addresses and data are sequentially supplied in two clock cycles, and stored in the instruction buffer 434.

  When the decrement value by the activation counter 421 reaches “0” in cycle T15, the activation counter 421 sets the power activation waiting signal 447 to the H level. In response to this, the AND gate 413 of the power control unit 407 supplies the H level power activation signal 476 to the PMU 403 and the activation counter 431, and the PMU 403 sequentially sets the PSWs 3 and 4 to the L level, and the resource 410 enters the power boosting state. The power status state becomes the wait state. In response to the power activation signal 476, the activation counter 431 starts counting down from n, and the power activation delay 467, which is the counter value of the activation counter, is decremented in synchronization with the clock 441.

  In cycle T26, the decrement value becomes “0”, and the activation counter 431 supplies the power activation wait signal 466 to the power status circuit 432. As a result, the power supply status state becomes the transfer state, and the instruction buffer 434 starts to transfer the stored access signal to the resource 410 in order from the read address of the read counter 473. At this time, the bus control circuit 433 generates a bus path from the instruction buffer 434 to the resource 410 according to the transfer state “10” of the power status signal 468. Thereafter, the power control unit 407 corresponding to the resource 410 performs the same power supply operation as that of the power control unit 207 corresponding to the resource 210 in the second embodiment.

  As described above, according to the fourth embodiment, in the resources that remain off when the microcomputer is powered on, if the related resources have priority in power activation, the power control unit of each resource By setting the power activation standby flag, it becomes possible to activate the power sequentially from the resource with the highest priority. Therefore, when there is a priority of processing among resources, such as when the processing result of the resource 406 is used in the processing of the resource 410, if the resource 410 is powered on first due to a delay in the power activation of the resource 406 due to a failure or the like , The resource 410 may malfunction. Therefore, the power control unit 407 of the resource 410 waits for the power activation of the resource 410 by the power activation standby flag, and performs the power activation of the resource 410 after the power activation of the resource 406, thereby preventing a malfunction of the resource 410. .

  The above embodiment is summarized as follows.

(Appendix 1)
In a microcomputer supplied with power from outside,
A plurality of resources each having a predetermined function, to which power is not supplied when the power supplied from outside is activated;
A control unit connected to the plurality of resources via a bus and supplying an access signal to the resources via the bus;
A plurality of in-resource power supply units that are respectively provided in the plurality of resources and that supply in-resource power to the corresponding resources from the power supplied from outside in response to a power activation signal;
A resource provided to each of the plurality of resources, detecting whether or not an access signal supplied via the bus is addressed to a corresponding resource, and when the access signal is addressed to a corresponding resource, the resource corresponding to the power activation signal A microcomputer having a power control unit capable of outputting to an internal power supply unit.

(Appendix 2)
In Appendix 1,
The in-resource power supply unit boosts the in-resource power supply to a reference potential in response to the power activation signal,
The power control unit has a buffer for temporarily storing the access signal, and is supplied via the bus while the power in the resource is boosted to the reference potential from detection of the access signal addressed to the resource. A microcomputer for storing an access signal in the buffer and transferring the access signal stored in the buffer to the resource after the in-resource power source has boosted the reference potential.

(Appendix 3)
In Appendix 2,
The power control unit includes a transmission line control unit that controls a transmission line that supplies the access signal to the resource;
The transmission line control unit cuts off a transmission line connecting the bus and the resource when detecting an access signal addressed to the resource, and connects the buffer and the resource when the power in the resource is boosted to the reference potential. And a microcomputer that opens the transmission line that connects the bus and the resource when the transfer of the access signal of the buffer to the resource is completed.

(Appendix 4)
In Appendix 1 or 2,
The plurality of resources include first and second resources,
The second power control unit provided in the second resource responds to the power activation signal to the first resource in addition to detecting the access signal addressed to the second resource. A microcomputer that outputs a power activation signal to two resources.

(Appendix 5)
In Appendix 4,
In the second power control unit, a first flag indicating whether or not to output a power activation signal to the second resource in response to a power activation signal to the first resource is output from the control unit. A microcomputer that is configurable.

(Appendix 6)
In Appendix 2,
The plurality of resources include third and fourth resources,
The fourth power control unit (provided in the fourth resource) boosts the in-resource power source of the third resource to the reference potential when detecting an access signal addressed to the fourth resource. And a microcomputer that outputs a power activation signal to the fourth resource.

(Appendix 7)
In Appendix 6,
When the fourth power supply control unit detects an access signal addressed to the fourth resource, the fourth power supply control unit waits for the in-resource power supply of the third resource to be boosted to the reference potential. A microcomputer in which a second flag indicating whether or not to output a power activation signal to can be set from the control unit.

(Appendix 8)
The microcomputer according to claim 1, wherein the power control unit includes an access detection unit that detects an access signal addressed to the resource and outputs the power activation signal.

(Appendix 9)
In the microcomputers according to appendix 3 and appendix 8, the power control unit detects an activation counter that counts an elapsed time since the power supply unit starts boosting the in-resource power source, and detects a boosting state of the in-resource power source Power status detector
The activation counter starts counting in response to the power activation signal, counts up to a predetermined count value, and then outputs a boost completion signal indicating completion of boosting of the in-resource power source to the power status detector And
The power status detector receives the power activation signal and the boost completion signal, and outputs a power status signal indicating a boost status of the power to the buffer and the transmission path controller.
In response to the power status signal, the buffer transfers the access signal stored in the buffer to the resource,
The transmission line control unit generates a transmission line that connects the buffer and the resource in response to the power status signal.

(Appendix 10)
The microcomputer according to appendix 9, wherein the buffer includes a buffer unit that stores the access signal, and a buffer counter unit that counts the amount of data stored in the buffer unit,
The buffer counter unit outputs a supply completion signal indicating that the supply of the access signal from the buffer to the resource is completed when the data amount count reaches zero, to the power status detector.
In response to the supply completion signal, the power status detector outputs an opening command signal to the transmission path controller.
The microcomputer is characterized in that the transmission path control unit opens a transmission path connecting the bus and the resource in response to the opening command signal.

OCD: Debug support unit providing on-chip debugging function FLASH: Non-volatile semiconductor memory XBS: 32-bit wide high-speed internal bus AHB: Internal bus interface DMAC: Direct memory access controller CAN: Communication device unit APB for car area network : 32-bit peripheral bus interface CGEN: Clock generation circuit MFS: Multifunction serial R-BUS: 16-bit peripheral bus interface OCU: Output compare unit FRT: Free-run timer ICU: Input capture unit WD: Watchdog timer Unit PPG: Waveform generator unit RLT: Reload timer unit UDC: Up / down counter RTC: Real time clock Knit PMU: Power Management Unit PSW: power switch signal

Claims (7)

In a microcomputer supplied with power from outside,
A plurality of resources each having a predetermined function, to which power is not supplied when the power supplied from outside is activated;
A control unit connected to the plurality of resources via a bus and supplying an access signal to the resources via the bus;
A plurality of in-resource power supply units that are respectively provided in the plurality of resources and that supply in-resource power to the corresponding resources from the power supplied from outside in response to a power activation signal;
A resource provided to each of the plurality of resources, detecting whether or not an access signal supplied via the bus is addressed to a corresponding resource, and when the access signal is addressed to a corresponding resource, the resource corresponding to the power activation signal A microcomputer having a power control unit capable of outputting to an internal power supply unit. In claim 1,
The in-resource power supply unit boosts the in-resource power supply to a reference potential in response to the power activation signal,
The power control unit has a buffer for temporarily storing the access signal, and is supplied via the bus while the power in the resource is boosted to the reference potential from detection of the access signal addressed to the resource. A microcomputer for storing an access signal in the buffer and transferring the access signal stored in the buffer to the resource after the in-resource power source has boosted the reference potential. In claim 2,
The power control unit includes a transmission line control unit that controls a transmission line that supplies the access signal to the resource;
The transmission line control unit cuts off a transmission line connecting the bus and the resource when detecting an access signal addressed to the resource, and connects the buffer and the resource when the power in the resource is boosted to the reference potential. And a microcomputer that opens the transmission line that connects the bus and the resource when the transfer of the access signal of the buffer to the resource is completed. In claim 1 or 2,
The plurality of resources include first and second resources,
The second power control unit provided in the second resource responds to the power activation signal to the first resource in addition to detecting the access signal addressed to the second resource. A microcomputer that outputs a power activation signal to two resources. In claim 4,
In the second power control unit, a first flag indicating whether or not to output a power activation signal to the second resource in response to a power activation signal to the first resource is output from the control unit. A microcomputer that is configurable. In claim 2,
The plurality of resources include third and fourth resources,
When a fourth power control unit provided in the fourth resource detects an access signal addressed to the fourth resource, the fourth resource control unit determines that the in-resource power supply of the third resource is boosted to the reference potential. A microcomputer that waits and outputs a power activation signal to the fourth resource. In claim 6,
When the fourth power supply control unit detects an access signal addressed to the fourth resource, the fourth power supply control unit waits for the in-resource power supply of the third resource to be boosted to the reference potential. A microcomputer in which a second flag indicating whether or not to output a power activation signal to can be set from the control unit.

Images