JP2013008890A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A semiconductor device having high channel mobility and a method for manufacturing the same are provided.
The substrate has a surface SR made of a semiconductor having a hexagonal single crystal structure of polytype 4H. The surface SR of the substrate is a first surface S1 having a surface orientation (0-33-8), and a second surface having a surface orientation that is connected to the first surface S1 and different from the surface orientation of the first surface S1. S2 and this are provided alternately. The gate insulating film is provided on the surface SR of the substrate. The gate electrode is provided on the gate insulating film.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate electrode and a manufacturing method thereof.

  As a semiconductor device having a gate electrode, for example, there is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Japanese Patent Application Laid-Open No. 2002-261275 discloses a MOS device in which an oxide film is stacked on the upper surface of 4H SiC and a metal electrode is provided on the upper surface of the oxide film.

  One of the performance indexes of MOSFET is channel mobility. The channel mobility represents the ease of movement of carriers in the channel. If the channel mobility can be increased, the on-resistance can be reduced or the operation speed can be increased. It is known that the channel mobility depends on the surface orientation of the channel surface. For this reason, the plane orientation of the semiconductor substrate used for manufacturing the semiconductor device is specified. For example, according to the technique described in the above publication, the surface of 4H SiC on which an oxide film is stacked has a {03-38} plane or a plane having an off angle of 10 ° or less with respect to the {03-38} plane. It is said.

  The reason why the {03-38} plane has high channel mobility is as follows according to the above publication. “As described above, the oxide film is stacked on the {03-38} plane or the SiC plane having an off angle within 10 ° with respect to the {03-38} plane, thereby increasing the channel mobility of the MOS device. This is because, since the {0001} plane of SiC is a hexagonal close-packed plane, the density of dangling bonds per unit area of the constituent atoms is high, and the interface states increase, preventing the movement of electrons. On the other hand, the {03-38} plane is deviated from the hexagonal close-packed plane, which is considered to be because electrons easily move, and the {03-38} plane has a particularly high channel mobility. The reason for this is thought to be that the bonds of atoms appear on the surface relatively periodically even though it is a surface away from the close-packed surface. "

JP 2002-261275 A

  For example, when polytype 4H silicon carbide is used, it is desirable to use the {03-38} plane for the channel as described above in order to improve the performance of the semiconductor device. Further, in the study by the present inventors, it is particularly preferable to use the (0-33-8) plane among the {03-38} planes. However, although the present inventors macroscopically have a (0-33-8) plane, the surface of a normal silicon carbide substrate cut out from the ingot along the plane orientation (0-33-8) is fine. Visually, it has been found that the proportion having the plane orientation (0-33-8) is unexpectedly low. That is, in the conventional method, it was found that the (0-33-8) plane having a high channel mobility was not sufficiently effectively used.

  More generally speaking, the present inventors have found that microscopic control of the surface orientation of the channel surface to be performed in order to increase the channel mobility has not been sufficiently studied so far. Since the performance of the semiconductor device can be improved by increasing the channel mobility, it is desired to further increase the channel mobility by microscopically controlling the channel surface.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a large channel mobility and a method for manufacturing the same.

  A semiconductor device according to one aspect of the present invention includes a substrate, a gate insulating film, and a gate electrode. The substrate has a surface made of a semiconductor having a hexagonal single crystal structure of polytype 4H. As for the surface of a board | substrate, the 1st surface which has a surface orientation (0-33-8), and the 2nd surface which has a surface orientation different from the surface orientation of a 1st surface connected to a 1st surface alternately It is configured by being provided. The gate insulating film is provided on the surface of the substrate. The gate electrode is provided on the gate insulating film.

  In the semiconductor device according to the aforementioned aspect, the second surface preferably has a plane orientation (0-11-1).

In the semiconductor device according to the aforementioned aspect, the semiconductor is preferably silicon carbide.
A semiconductor device according to another aspect of the present invention includes a substrate, a gate insulating film, and a gate electrode. The substrate has a surface made of a semiconductor having a single crystal structure other than a cubic crystal. The single crystal structure periodically includes a structure equivalent to a cubic crystal. The surface of the substrate is alternately composed of a first surface having a plane orientation (001) in an equivalent structure and a second surface having a plane orientation different from the plane orientation of the first plane connected to the first plane. It is configured by being provided. The gate insulating film is provided on the surface of the substrate. The gate electrode is provided on the gate insulating film.

  In the semiconductor device according to the other aspect described above, the single crystal structure is preferably either a hexagonal crystal or a rhombohedral crystal.

  The method for manufacturing a semiconductor device of the present invention includes the following steps. A substrate having a surface made of silicon carbide having a hexagonal single crystal structure of polytype 4H is prepared. The surface of the substrate is chemically treated. Due to the step of chemically treating the surface of the substrate, the first surface having a plane orientation (0-33-8) on the surface of the substrate is different from the plane orientation of the first surface connected to the first surface. Second surfaces having a plane orientation are alternately formed. A gate insulating film is formed on the surface of the substrate. A gate electrode is formed on the gate insulating film.

  In the above method for manufacturing a semiconductor device, the second surface preferably has a plane orientation (0-11-1).

  Preferably, in the semiconductor device manufacturing method, the step of chemically treating the surface includes a step of chemically etching the surface. More preferably, the step of chemically etching the surface includes the step of thermally etching the surface. More preferably, the step of thermally etching the surface includes a step of heating the substrate in an atmosphere containing at least one kind of halogen atom. The at least one kind of halogen atom preferably contains at least one of a chlorine atom and a fluorine atom.

  According to the present invention, channel mobility can be increased.

1 is a cross sectional view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. FIG. 2 is a schematic plan view of the semiconductor device of FIG. 1. FIG. 2 is a partially enlarged view of FIG. 1. It is a figure which shows the crystal structure of the (000-1) plane in the hexagonal crystal of polytype 4H. It is a figure which shows the crystal structure of the (11-20) plane which follows the line VV of FIG. It is a figure which shows the crystal structure in the surface vicinity of the channel which the semiconductor device of FIG. 1 has in the (11-20) plane. It is the figure which looked at the surface of the channel which the semiconductor device of FIG. 1 has seen from (01-10) plane. It is sectional drawing which shows schematically the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 3rd process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 4th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 5th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 6th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 7th process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention. Graph showing an example of the relationship between the channel surface MB and the angle between the channel surface and the (000-1) plane and the channel mobility MB when the thermal etching is performed and when it is not performed FIG. It is a graph which shows an example of the relationship between the angle between a channel direction and the <0-11-2> direction, and channel mobility MB. It is a top view which shows roughly the structure of the semiconductor device of the modification of Embodiment 1 of this invention. It is a graph which shows an example of the relationship between an interface state density and channel mobility. It is a graph which shows an example of the relationship between nitrogen concentration and channel mobility in the interface of a gate insulating film and a channel when nitrogen annealing is performed. It is a graph which shows an example of the profile of nitrogen concentration in the vicinity of the interface of a gate insulating film and a channel when nitrogen annealing is performed. FIG. 23 is a diagram schematically showing a configuration of a semiconductor device in a second embodiment of the present invention, which is a cross-sectional view taken along line XXI-XXI in FIG. 22. FIG. 22 is a schematic plan view of FIG. 21. It is sectional drawing which shows roughly the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the 2nd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the 3rd process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the 4th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the 5th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is a schematic perspective view of FIG. It is sectional drawing which shows schematically the 6th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the 7th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows roughly the 8th process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the present specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number.

(Embodiment 1)
As shown in FIGS. 1 and 2, the semiconductor device of the present embodiment is a silicon carbide semiconductor device, specifically MOSFET 100, and more specifically a vertical DiMOSFET (Double implanted MOSFET). MOSFET 100 has an epitaxial substrate 190, a gate insulating film 113, a gate electrode 117, a source electrode 116, and a drain electrode 118.

  Epitaxial substrate 190 includes single crystal substrate 111, epitaxial layer 112 formed on single crystal substrate 111, and impurity regions 114 and 115. Single crystal substrate 111, epitaxial layer 112, and impurity region 115 have a first conductivity type (in this embodiment, n-type), and impurity region 114 has a second conductivity type (this embodiment) different from the first conductivity type. In the form of p-type). As an impurity for imparting n-type to silicon carbide (n-type impurity), for example, nitrogen (N) or phosphorus (P) can be used. As an impurity (p-type impurity) for imparting p-type to silicon carbide, for example, aluminum (Al) or boron (B) can be used.

  Single crystal substrate 111 is made of silicon carbide having a hexagonal single crystal structure of polytype 4H. The plane orientation of one main surface (upper surface in FIG. 1) of the single crystal substrate 111 is substantially (0-11-2) plane. On one main surface of single crystal substrate 111, epitaxial layer 112 made of silicon carbide is formed. Preferably, the impurity concentration of epitaxial layer 112 is lower than the impurity concentration of single crystal substrate 111. Impurity region 114 is formed on part of epitaxial layer 112. Impurity region 115 is formed on part of impurity region 114 so as to be separated from epitaxial layer 112 by impurity region 114. With this configuration, the impurity region 114 has a channel CH sandwiched between the epitaxial layer 112 and the impurity region 115 on the surface side thereof. Preferably, the channel direction, which is the direction in which carriers flow in channel CH, is parallel to <0-11-2> and orthogonal to <-2110>.

  A drain electrode 118 is formed on the other main surface (the lower surface in FIG. 1) of single crystal substrate 111. Preferably, the drain electrode 118 is an ohmic electrode.

  The gate insulating film 113 is formed on a part of the surface SR of the epitaxial substrate 190, and in particular, is formed on the surface SR of the channel CH. Gate insulating film 113 is, for example, an oxide film. Note that the gate insulating film 113 may have a multilayer structure.

  The gate electrode 117 is formed on the gate insulating film 113. Source electrode 116 is formed on impurity regions 114 and 115.

  Surface SR is made of a semiconductor (silicon carbide in the present embodiment) having a hexagonal single crystal structure of polytype 4H. In the present embodiment, the entire epitaxial substrate 190 has a hexagonal single crystal structure of polytype 4H. Hereinafter, the details of the surface SR will be described.

  As shown in FIG. 3, the surface SR is microscopically different from the plane S1 (first plane) having the plane orientation (0-33-8) and the plane S1 that is connected to the plane S1 and the plane S1. It is a chemically stable surface formed by alternately providing the surface S2 (second surface) having the surface orientation. Here, “microscopic” means that the dimension is about enough to take into account at least a dimension of about twice the atomic interval described later. Preferably plane S2 has a plane orientation (0-11-1). On average, the surface SR formed by the surface S1 and the surface S2 preferably has a surface whose inclination from the surface orientation (0-11-2) is within 5 °. 11-2) is more preferable.

  As shown in FIG. 4, generally, when a silicon carbide single crystal of polytype 4H is viewed from the (000-1) plane, Si atoms (or C atoms) are atoms of A layer (solid line in the figure), B layer atoms (broken line in the figure) located below, C layer atoms (dotted line in the figure) located below, and B layer atoms (not shown) located below this It is provided repeatedly. That is, a periodic laminated structure such as ABCBABCBABCB... Is provided with four layers ABCB as one period.

  As shown in FIG. 5, in the (11-20) plane (cross section taken along line VV in FIG. 4), the atoms in each of the four layers ABCB constituting one cycle described above are (0-11-2). It is not arranged to be completely along the plane. In FIG. 5, the (0-11-2) plane is shown so as to pass through the position of the atoms in the B layer. In this case, the atoms in the A layer and the B layer are separated from the (0-11-2) plane. You can see that it is shifted. For this reason, even if the macroscopic plane orientation of the surface of the silicon carbide single crystal, that is, the plane orientation when the atomic level structure is ignored is limited to (0-11-2), this surface is microscopic. Can take various structures.

  As shown in FIG. 6, in the present embodiment, the surface SR includes a surface S1 having a surface orientation (0-33-8), and a surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1. Are provided alternately. The length of each of the surface S1 and the surface S2 is twice the atomic spacing of Si atoms (or C atoms). Note that the surface on which the surface S1 and the surface S2 are averaged corresponds to the (0-11-2) surface (FIG. 5).

  As shown in FIG. 7, the single crystal structure when the surface SR is viewed from the (01-10) plane periodically includes a structure (part of the plane S1) equivalent to a cubic crystal when viewed partially. Specifically, the surface SR is alternately composed of a plane S1 having a plane orientation (001) in a structure equivalent to the above-described cubic crystal and a plane S2 connected to the plane S1 and having a plane orientation different from the plane orientation of the plane S1. It is configured by being provided. Thus, a plane having a plane orientation (001) in the structure equivalent to a cubic crystal (plane S1 in FIG. 7) and a plane connected to this plane and having a plane orientation different from this plane orientation (plane in FIG. 7). It is also possible to construct the surface by S2) in single crystal structures other than polytype 4H. This single crystal structure is not limited to a hexagonal crystal, and may be a single crystal structure other than a cubic crystal, for example, a rhombohedral crystal. The polytype is not limited to 4H, and may be 6H or 15R, for example. The semiconductor is not limited to silicon carbide (SiC), and may be gallium nitride (GaN), for example.

Next, a method for manufacturing MOSFET 100 will be described below.
As shown in FIG. 8, a single crystal substrate 111 made of silicon carbide and made of silicon carbide having a hexagonal single crystal structure of polytype 4H is prepared. Single crystal substrate 111 has surface SA. The plane orientation of the surface SA is preferably a (0-11-2) plane or a plane whose inclination from this plane is within 5 °. The surface SA can be formed by mechanical polishing or slicing.

  As shown in FIG. 9, epitaxial layer 112 made of silicon carbide is formed on surface SA of single crystal substrate 111. Epitaxial layer 112 has a surface SB that is a growth surface. The surface SB has a polytype 4H hexagonal single crystal structure corresponding to the crystal structure of the surface SA. The plane orientation of the surface SB is preferably a (0-11-2) plane or a plane whose inclination from this plane is within 5 °. The surface SB of the epitaxial layer 112 may be mechanically polished for planarization.

The surface SB is then chemically treated. Specifically, the surface SB is chemically etched. This etching can be performed, for example, by heating the epitaxial substrate 190 in an atmosphere containing at least one or more types of halogen atoms. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl ₂ , BCL ₃ , SF ₆ , or CF ₄ .

  As shown in FIG. 10, the surface SR is self-formed by the above chemical treatment. That is, as shown in FIGS. 6 and 7, the surface S1 having the surface orientation (0-33-8) and the surface S2 connected to the surface S1 and having a surface orientation different from the surface orientation of the surface S1 are alternately self-formed. Is done. Specifically, the plane orientation of the plane S2 has (0-11-1).

  As shown in FIG. 11, an impurity region 114 is formed. Specifically, ions of p-type impurities are selectively implanted into a region to be the impurity region 114. Such selective implantation can be performed by using a mask for ion implantation and selecting energy of ion implantation.

  Note that the above-described chemical treatment (specifically, chemical etching) may be performed after ion implantation for forming the impurity region 114. In this case, it is possible to prevent the atomic arrangement on the surface SR from being disturbed by ion implantation.

  As shown in FIG. 12, impurity region 115 is formed. Specifically, n-type impurity ion implantation for forming the impurity region 115 is performed. This ion implantation may be performed before the ion implantation for forming the impurity region 114 described above.

  Next, an activation annealing process for activating the implanted impurities is performed. For example, heating is performed for 30 minutes at a temperature of about 1700 ° C. in an atmosphere of argon (Ar) gas.

  The above-described chemical treatment (specifically, chemical etching) may be performed after the activation annealing. In this case, it is possible to prevent the atomic arrangement on the surface SR from being disturbed by the activation annealing.

  As shown in FIG. 13, gate insulating film 113 is formed on surface SR. The gate insulating film 113 is formed by, for example, dry oxidation (thermal oxidation). Dry oxidation is performed, for example, by heating in air or oxygen at a temperature of about 1200 ° C. for about 30 minutes.

Next, nitrogen annealing is performed. Thereby, the nitrogen concentration is adjusted so that the maximum value of the nitrogen concentration in the region within 10 nm from the interface between the epitaxial substrate 190 and the gate insulating film 113 is 1 × 10 ²¹ / cm ³ or more. For example, heating is performed for about 120 minutes at a temperature of about 1100 ° C. in an atmosphere of a nitrogen-containing gas such as nitrogen monoxide (NO) gas.

  After this nitrogen annealing treatment, an inert gas annealing treatment may be further performed. For example, heating is performed for about 60 minutes at a temperature of about 1100 ° C. in an argon gas atmosphere. Thereby, high channel mobility can be realized with good reproducibility.

  As shown in FIG. 14, the gate insulating film 113 is patterned. This patterning can be done, for example, using photolithography and etching.

  As shown in FIG. 1, source electrode 116 is formed in contact with the surface of impurity region 115 of epitaxial substrate 190. The material of the source electrode 116 is, for example, nickel (Ni). Preferably, annealing for alloying is performed in order to make the electrical connection between the source electrode 116 and the epitaxial substrate 190 more ohmic. For example, heating is performed for about 2 minutes at a temperature of about 950 ° C. in an atmosphere of an inert gas such as argon gas.

  A gate electrode 117 is formed on the surface of the gate insulating film 113. The material of the gate electrode 117 is, for example, aluminum.

  A drain electrode 118 is formed on the single crystal substrate 111. The material of the drain electrode 118 is, for example, nickel.

Thus, MOSFET 100 is obtained.
According to MOSFET 100 of the present embodiment, surface SR (FIG. 1) of channel CH is connected to surface S1 having a plane orientation (0-33-8) and surface S1, as shown in FIGS. And it is comprised by providing alternately the surface S2 which has a surface orientation different from the surface orientation of surface S1. With this configuration, the ratio of the plane orientation (0-33-8) can be increased on the surface of the channel CH. Thereby, the channel mobility can be increased. Preferably plane S2 has a plane orientation (0-11-1). Thereby, the ratio of the plane orientation (0-33-8) can be further increased on the surface of the channel CH.

  A more general discussion is as follows. As shown in FIG. 7, the single crystal structure of the epitaxial substrate 190 periodically includes a structure (part of the surface S <b> 1) that is partially equivalent to a cubic crystal. Specifically, the surface SR is alternately provided with a plane S1 having a plane orientation (001) in a structure equivalent to a cubic crystal and a plane S2 connected to the plane S1 and having a plane orientation different from the plane orientation of the plane S1. Is made up of. With this configuration, it is possible to increase the proportion of the portion corresponding to the cubic crystal plane orientation (001) on the surface SR. Thereby, the channel mobility can be increased. The single crystal structure having a structure equivalent to a cubic crystal partially as described above is not limited to a hexagonal crystal but may be a single crystal structure other than a cubic crystal, for example, a rhombohedral crystal. May be. The polytype is not limited to 4H, and may be 6H or 15R, for example. The semiconductor is not limited to silicon carbide (SiC), and may be gallium nitride (GaN), for example.

  Further, according to the manufacturing method of MOSFET 100 of the present embodiment, surface SB (FIG. 9) is chemically treated, so that surface SR (FIG. 6) controlled at the atomic level is self-assembled as shown in FIG. Can be formed. More specifically, the surface SR (FIG. 6) can be self-formed by chemically etching the surface SB. The chemical etching is specifically thermal etching, for example, heating is performed in an atmosphere containing at least one or more types of halogen atoms. The at least one or more types of halogen atom may include at least one of a chlorine atom and a fluorine atom.

  Next, the function and effect of the present embodiment will be described with reference to the experimental results shown in the graph of FIG. In the graph of FIG. 15, the horizontal axis indicates the angle D1 formed by the macroscopic plane orientation of the surface SR of the channel CH and the (000-1) plane, and the vertical axis indicates the channel mobility MB. The plot group CM corresponds to the case where the surface SB is thermally etched, and the plot group MC corresponds to the case where the thermal etching is not performed.

  The channel mobility MB in the plot group MC was maximized when the macroscopic plane orientation of the surface of the channel CH was (0-33-8). This is because when the thermal etching is not performed, that is, when the microscopic structure of the channel surface is not particularly controlled, the microscopic plane orientation is set to (0-33-8). This is probably because the ratio of the formation of the visual plane orientation (0-33-8), that is, the plane orientation (0-33-8) when considering even the atomic level is stochastically increased.

  On the other hand, the channel mobility MB in the plot group CM is maximized when the macroscopic surface orientation of the surface of the channel CH is (0-11-2) (in the example indicated by the arrow EX). The reason for this is that, as shown in FIGS. 6 and 7, a large number of surfaces S1 having a plane orientation (0-33-8) are regularly and densely arranged via the surface S2, so that the surface of the channel CH is finely arranged. This is probably because the ratio of the visual plane orientation (0-33-8) is increased.

  Next, factors other than the plane orientation that may affect the channel mobility will be described with reference to FIGS.

  In the graph shown in FIG. 16, the horizontal axis represents the angle D2 between the channel direction and the <0-11-2> direction, and the vertical axis represents the channel mobility MB (arbitrary unit). Dashed lines are added to make the graph easier to see. From this graph, it was found that in order to increase the channel mobility MB, the angle D2 is preferably 0 ° or more and 60 ° or less, and the angle D2 is more preferably approximately 0 °. FIG. 2 shows MOSFET 100 whose channel direction is <0-11-2>.

  In MOSFET 100 (FIG. 2), for example, as shown in the schematic plan view of FIG. 17, the surface of each source electrode 116 is formed in a hexagonal shape, and a region excluding a part of the region surrounding the outer periphery of source electrode 116 is excluded. It can also be formed as the gate electrode 117. In this case, the channel direction can be easily formed within the range of <0-11-2> direction ± 60 ° while increasing the integration degree of the MOSFET 100.

In the graph shown in FIG. 18, the horizontal axis represents the interface state density SD of the interface state 0.2 to 0.3 eV between the gate insulating film 113 and the impurity region 114 (FIG. 1), and the vertical axis represents channel movement. Degree MB. From this graph, it was found that the interface state density SD is preferably 1 × 10 ¹² cm ² / (V · s) or less in order to increase the channel mobility MB.

This interface state density SD can be reduced by annealing. This annealing preferably includes nitrogen annealing. In the graph (FIG. 19) showing the measurement result of channel mobility when nitrogen annealing is performed, the horizontal axis shows the nitrogen concentration CN at the interface between the gate insulating film 113 and the impurity region 114 (FIG. 1). The vertical axis indicates the channel mobility MB. From this graph, it was found that the nitrogen concentration CN is preferably 1 × 10 ²¹ / cm ³ or more in order to increase the channel mobility MB. An example of a nitrogen concentration profile when such a condition is satisfied is shown in FIG. Note that hydrogen annealing can also be used instead of nitrogen annealing.

  The surface SR of the channel CH of the MOSFET 100 may include a portion formed by alternately repeating the surfaces S1 and S2 (FIGS. 6 and 7), and all of the surface SR needs to be configured as such. There is no. In order to sufficiently increase the proportion of the portion configured as described above, it is preferable that the macroscopic plane orientation of the surface SR is close to the (0-11-2) plane. Specifically, the inclination of the macroscopic plane orientation of the surface SR with respect to the (0-11-2) plane is preferably within ± 5 ° in the <0-110> direction. In addition, this inclination is preferably within ± 10 ° in the <−2110> direction, so that a step on the surface SR that affects carriers flowing in the channel can be reduced.

(Embodiment 2)
As shown in FIGS. 21 and 22, the semiconductor device of the present embodiment is a silicon carbide semiconductor device, specifically MOSFET 200, and more specifically a vertical VMOSFET (V-groove MOSFET). MOSFET 200 has a plurality of mesa structures and grooves formed between the mesa structures and having inclined side surfaces. The surface SW forming the side wall of the groove (the side wall of the mesa structure) has substantially the same configuration as the surface SR described in the first embodiment. Thereby, also in this Embodiment, the channel mobility in channel CH can be enlarged similarly to Embodiment 1. FIG.

  In the present embodiment, the macroscopic plane orientation of the surface SW includes the plane orientation (0-11-2) described in the first embodiment and five plane orientations equivalent to this plane orientation. That is, the macroscopic plane orientation of the surface SW is the plane orientation (0-11-2), (01-1-2), (10-1-2), (-101-2), (-110-2). And (1-10-2). These six plane orientations are equivalent to each other in the hexagonal crystal and the index m in the plane orientation (hklm) is negative.

  Next, the details of the structure of the MOSFET 200 will be described. The MOSFET 200 includes an epitaxial substrate 290, a gate insulating film 213, a gate electrode 217, a source electrode 216, a drain electrode 218, and a source wiring 233.

  Epitaxial substrate 290 includes single crystal substrate 211, breakdown voltage holding layer 212, p-type body layer 214, n region 215, and contact region 204. Single crystal substrate 211, breakdown voltage holding layer 212, and n region 215 have n-type, and the contact region has p-type.

  Single crystal substrate 211 is a silicon carbide substrate having hexagonal polytype 4H. The plane orientation of one main surface (upper surface in FIG. 21) of single crystal substrate 211 is approximately (000-1). A breakdown voltage holding layer 212 made of silicon carbide is formed on one main surface of single crystal substrate 111. The impurity concentration of the withstand voltage holding layer 212 is lower than the impurity concentration of the single crystal substrate 111. The p-type body layer 214 is formed on the breakdown voltage holding layer 212. N region 215 is formed on part of p type body layer 214 so as to be separated from breakdown voltage holding layer 212 by p type body layer 214.

  The epitaxial layer is partially removed on the main surface of the single crystal substrate 211, thereby forming a plurality of (four in FIG. 22) mesa structures. Specifically, the mesa structure has a hexagonal shape on the upper surface and the bottom surface, and its side wall is inclined with respect to the main surface of the single crystal substrate 211. Between adjacent mesa structures, a groove having a surface SW formed by the side walls of these mesa structures is formed.

  A gate insulating film 213 is formed on the surface SW. Gate insulating film 213 extends to the upper surface of n region 215. A gate electrode 217 is formed on the gate insulating film 213 so as to fill the inside of the trench (that is, so as to fill a space between adjacent mesa structures). The upper surface of the gate electrode 217 is substantially the same height as the upper surface of the portion of the gate insulating film 213 located on the upper surface of the n region 215.

  Interlayer insulating film 230 is formed so as to cover a portion of gate insulating film 213 that extends to the upper surface of n region 215 and gate electrode 217. Source electrode 216 is formed in contact with p-type contact region 204 and n region 215. Source wiring 233 is formed so as to be in contact with the upper surface of source electrode 216 and to extend on the upper surface of interlayer insulating film 230. A drain electrode 218 is formed on the back surface of the single crystal substrate 211 opposite to the main surface on which the breakdown voltage holding layer 212 is formed. The drain electrode 218 is an ohmic electrode.

Next, a method for manufacturing MOSFET 200 will be described.
As shown in FIG. 23, a single crystal substrate 211 made of silicon carbide having a hexagonal single crystal structure of polytype 4H is prepared. The plane orientation of main surface SN of single crystal substrate 211 is preferably a (000-1) plane or a plane whose inclination from this plane is within 5 °. The main surface SN can be formed by mechanical polishing or slicing.

Next, an epitaxial layer of silicon carbide having an n conductivity type is formed on main surface SN. The epitaxial layer becomes the breakdown voltage holding layer 212. Epitaxial growth for forming the breakdown voltage holding layer 212 is, for example, CVD using a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using hydrogen gas (H ₂ ) as a carrier gas, for example. It can be implemented by law. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as an n-type impurity. The concentration of the n-type impurity in the breakdown voltage holding layer 212 can be, for example, 5 × 10 ¹⁵ / cm ³ or more and 5 × 10 ¹⁶ / cm ³ or less.

  Next, p-type body layer 214 and n region 215 are formed by ion implantation into the upper surface layer of breakdown voltage holding layer 212. In ion implantation for forming p-type body layer 214, for example, p-type impurities such as aluminum (Al) are ion-implanted. At this time, the depth of the region where the p-type body layer 214 is formed can be adjusted by adjusting the acceleration energy of the implanted ions.

  Next, an n region 215 is formed by ion-implanting impurities of n type conductivity into the breakdown voltage holding layer 212 in which the p type body layer 214 is formed. For example, phosphorus (P) can be used as the n-type impurity. In this way, the structure shown in FIG. 24 is obtained.

  As shown in FIG. 25, a mask layer 247 is formed on the upper surface of n region 215. As mask layer 247, for example, an insulating film such as a silicon oxide film can be used. As a method for forming the mask layer 247, for example, the following steps can be used. That is, a silicon oxide film is formed on the upper surface of the n region 215 by using a CVD method or the like. Then, a resist film (not shown) having a predetermined opening pattern is formed on the silicon oxide film by using a photolithography method. Using this resist film as a mask, the silicon oxide film is removed by etching. Thereafter, the resist film is removed. As a result, a mask layer 247 having an opening pattern is formed in a region where a groove having the surface SV is to be formed.

Then, using this mask layer 247 as a mask, part of n region 215, p-type body layer 214, and breakdown voltage holding layer 212 is removed by etching. As an etching method, for example, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used. By such etching, a groove having a surface SV whose side wall is substantially perpendicular to the main surface of single crystal substrate 211 can be formed in the region where the groove in FIG. 21 is to be formed. In this way, the structure shown in FIG. 25 is obtained.

  Next, a thermal etching process for exposing a predetermined crystal plane in the breakdown voltage holding layer 212, the p-type body layer 214, and the n region 215 is performed. Specifically, the side wall of the groove shown in FIG. 25 is etched (thermal etching) using a mixed gas of oxygen gas and chlorine gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. to 1000 ° C. Thus, a groove having a surface SW inclined with respect to the main surface of single crystal substrate 211 can be formed as shown in FIG. At this time, as in the first embodiment, as shown in FIGS. 6 and 7, the surface S1 having the surface orientation (0-33-8) and the surface orientation that is connected to the surface S1 and different from the surface orientation of the surface S1. The surfaces S2 having the same are alternately formed.

Here, with respect to the conditions of the thermal etching step, 0.5 ≦ x ≦ 2 in a reaction formula expressed as SiC + mO ₂ + nCl ₂ → SiCl _x + COy (where m, n, x, and y are positive numbers). The main reaction proceeds when the x and y conditions of 0.0 and 1.0 ≦ y ≦ 2.0 are satisfied, and the reaction (thermal etching) proceeds most when the conditions of x = 4 and y = 2. Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas or the like can be used. When the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower as described above, the SiC etching rate is, for example, about 70 μm / hour. Further, in this case, if silicon oxide (SiO ₂ ) is used as the mask layer 247, the selection ratio of SiC to SiO ₂ can be extremely increased, so that the mask layer 247 made of SiO ₂ is substantially not etched during SiC etching. Not etched.

  Next, the mask layer 247 is removed by an arbitrary method such as etching. Thereafter, a resist film (not shown) having a predetermined pattern is formed by photolithography so as to extend from the inside of the groove to the upper surface of n region 215. As the resist film, a resist film having an opening pattern formed on the bottom of the groove and a part of the upper surface of the n region 215 is used. Then, by using this resist film as a mask, an impurity having a conductivity type of p-type is ion-implanted to form an electric field relaxation region 207 at the bottom of the trench, and a conductivity type of p-type in a partial region of the n-region 215. The contact region 204 is formed. Thereafter, the resist film is removed. As a result, a structure as shown in FIGS. 27 and 28 is obtained. As can be seen from FIG. 28, the planar shape of the groove is a mesh shape in which the planar shape of the unit cell (annular groove surrounding one mesa structure) is a hexagonal shape. In addition, the p-type contact region 204 is disposed substantially at the center of the upper surface of the mesa structure as shown in FIG. The planar shape of the p-type contact region 204 is the same as the outer peripheral shape of the upper surface of the mesa structure, and is a hexagonal shape.

  Then, an activation annealing step for activating the impurities implanted by the above-described ion implantation is performed.

  Next, as shown in FIG. 29, gate insulating film 213 is formed so as to extend from the inside of the trench to the upper surface of n region 215 and p type contact region 204. As gate insulating film 213, for example, an oxide film (silicon oxide film) obtained by thermally oxidizing an epitaxial layer made of silicon carbide can be used. In this way, the structure shown in FIG. 29 is obtained.

  Next, as shown in FIG. 30, a gate electrode 217 is formed on the gate insulating film 213 so as to fill the inside of the trench. As a method for forming the gate electrode 217, for example, the following method can be used. First, on the gate insulating film 213, a conductor film to be a gate electrode extending to the inside of the trench and the region on the p-type contact region 204 is formed by sputtering or the like. As a material of the conductor film, any material such as metal can be used as long as it is a conductive material. Thereafter, the portion of the conductor film formed in a region other than the inside of the trench is removed by using an arbitrary method such as etch back or CMP (Chemical Mechanical Polishing). As a result, a conductor film filling the inside of the trench remains, and the gate electrode 217 is configured by the conductor film. In this way, the structure shown in FIG. 30 is obtained.

  Next, an interlayer insulating film 230 (see FIG. 31) is formed so as to cover the upper surface of the gate electrode 217 and the upper surface of the gate insulating film 213 exposed on the p-type contact region 204. As the interlayer insulating film, any material can be used as long as it is an insulating material. Then, a resist film having a pattern is formed over the interlayer insulating film 230 by using a photolithography method. In this resist film (not shown), an opening pattern is formed in a region located on the p-type contact region 204.

  Then, using this resist film as a mask, interlayer insulating film 230 and gate insulating film 213 are partially removed by etching. As a result, openings (see FIG. 31) are formed in the interlayer insulating film 230 and the gate insulating film 213. At the bottom of the opening, a part of the p-type contact region 204 and the n region 215 is exposed. Thereafter, a conductor film to be the source electrode 216 (see FIG. 31) is formed so as to fill the inside of the opening and cover the upper surface of the resist film described above. Thereafter, by removing the resist film using a chemical solution or the like, the portion of the conductor film formed on the resist film is simultaneously removed (list off). As a result, the source electrode 216 can be formed by the conductive film filled in the opening. The source electrode 216 is an ohmic electrode in ohmic contact with the p-type contact region 204 and the n region 215.

  Further, a drain electrode 218 (see FIG. 31) is formed on the back surface side of the single crystal substrate 211 (the surface side opposite to the main surface on which the breakdown voltage holding layer 212 is formed). As the drain electrode 218, any material can be used as long as it can make ohmic contact with the single crystal substrate 211. In this way, the structure shown in FIG. 31 is obtained.

  Thereafter, a source wiring 233 (see FIG. 21) that contacts the upper surface of the source electrode 216 and extends on the upper surface of the interlayer insulating film 230 is formed using an arbitrary method such as a sputtering method. As a result, MOSFET 200 (FIGS. 21 and 22) is obtained.

  Surface SW is similar to surface SR in the first embodiment, and has a plane (plane S1 in FIG. 7) having a plane orientation (001) in a structure equivalent to a cubic crystal, and is connected to this plane and this plane orientation. And a plane having a different plane orientation (plane S2 in FIG. 7). Such a configuration is also possible in a single crystal structure other than polytype 4H. This single crystal structure is not limited to a hexagonal crystal, and may be a single crystal structure other than a cubic crystal, for example, a rhombohedral crystal. The polytype is not limited to 4H, and may be 6H or 15R, for example. The semiconductor is not limited to silicon carbide (SiC), and may be gallium nitride (GaN), for example.

  Moreover, although VMOSFET (V-groove MOSFET) was demonstrated, the semiconductor device may be UMOSFET (U-groove MOSFET). That is, the macroscopic plane orientation of the surface of the channel CH may be perpendicular to the main surface of the single crystal substrate. In this case, channels facing each other are provided, and the surface orientations of the surfaces of the respective channels are reversed. For example, a channel having a macroscopic plane orientation (0-11-2) and a channel having a macroscopic plane orientation (01-12) are provided.

  Note that the n-channel MOSFET in the above embodiments may be replaced with the n-type and p-type so that the MOSFET may be p-channel. However, n-channel is preferable for higher channel mobility.

  In each of the above embodiments, an epitaxial substrate is used. However, the epitaxial layer portion of the epitaxial substrate may be formed by impurity implantation instead of epitaxial growth.

  Although the MOSFET has been described in detail, the semiconductor device may be a MISFET (Metal Insulator Semiconductor Field Effect Transistor) other than the MOSFET. The semiconductor device is not limited to the MISFET, and may be any device having a channel surface, and may be, for example, an IGBT (Insulated Gate Bipolar Transistor).

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  111, 211 single crystal substrate, 112 epitaxial layer, 113, 213 gate insulating film, 114, 115 impurity region, 116, 216 source electrode, 117, 217 gate electrode, 118, 218 drain electrode, 190, 290 epitaxial substrate, 214 p Type body layer, 215 n region, CH channel, SR, SW surface.

Claims (11)

A substrate having a surface made of a semiconductor having a hexagonal single crystal structure of polytype 4H,
The surface of the substrate has a first surface having a plane orientation (0-33-8), and a second plane connected to the first surface and having a plane orientation different from the plane orientation of the first surface. And a gate insulating film provided on the surface of the substrate; and
A semiconductor device comprising: a gate electrode provided on the gate insulating film.   The semiconductor device according to claim 1, wherein the second surface has a plane orientation (0-11-1).   The semiconductor device according to claim 1, wherein the semiconductor is silicon carbide. A substrate having a surface made of a semiconductor having a single crystal structure other than a cubic crystal,
The single crystal structure periodically includes a structure equivalent to a cubic crystal, and the surface of the substrate includes a first surface having a plane orientation (001) in the equivalent structure, and the first surface. A second surface having a surface orientation different from the surface orientation of the first surface, the gate insulating film being provided on the surface of the substrate; and
A semiconductor device comprising: a gate electrode provided on the gate insulating film.   The semiconductor device according to claim 4, wherein the single crystal structure has one of a hexagonal crystal and a rhombohedral crystal. Preparing a substrate having a surface made of silicon carbide having a hexagonal single crystal structure of polytype 4H;
Chemically treating the surface of the substrate;
By chemically treating the surface of the substrate, a first surface having a plane orientation (0-33-8) is formed on the surface of the substrate, and the first surface is connected to the first surface. A step of alternately forming second surfaces having a surface orientation different from the surface orientation of a surface, and forming a gate insulating film on the surface of the substrate;
A method of manufacturing a semiconductor device, comprising: forming a gate electrode on the gate insulating film.   The method of manufacturing a semiconductor device according to claim 6, wherein the second surface has a plane orientation (0-11-1).   The method of manufacturing a semiconductor device according to claim 6, wherein the step of chemically treating the surface includes a step of chemically etching the surface.   The method for manufacturing a semiconductor device according to claim 8, wherein the step of chemically etching the surface includes a step of thermally etching the surface.   The method for manufacturing a semiconductor device according to claim 9, wherein the step of thermally etching the surface includes a step of heating the substrate in an atmosphere containing at least one or more types of halogen atoms.   The method for manufacturing a semiconductor device according to claim 10, wherein the at least one kind of halogen atom includes at least one of a chlorine atom and a fluorine atom.

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