JP2013008265A - Pipeline arithmetic device - Google Patents

Abstract

The present invention provides a pipeline arithmetic device capable of reducing the circuit scale by reducing the incorporation of overlapping arithmetic units.
A pipeline arithmetic device according to the present invention includes a plurality of arithmetic units 50a, 50b, 50c, an input selector 14, an output selector 15, a buffer 21, and a control unit (image controller 6). Yes. The control unit controls the operation clock of at least one arithmetic unit 50a connected between the input selector 14 and the output selector 15 to be faster than the reference clock for operating the other arithmetic units 50b and 50c. . At least one arithmetic unit 50a connected between the input selector 14 and the output selector 15 performs arithmetic processing in a time division manner for each pipeline.
[Selection] Figure 1

Description

  The present invention relates to a pipeline arithmetic device, and more particularly to a pipeline arithmetic device including a plurality of arithmetic units that perform arithmetic processing on input data by a pipeline arithmetic method.

  Conventionally, as a method of processing image data, a method of processing image data using hardware and a method of processing image data using software are known.

  In the method of processing image data using hardware, a dedicated hardware (pipeline arithmetic device) having a circuit configuration that can perform arithmetic processing on the arithmetic unit that processes specific image data using the hyperline arithmetic method. )is required. Since this dedicated hardware has a circuit configuration optimized for performing specific arithmetic processing on the image data, it is possible to process the image data at high speed. The specific configuration of the pipeline arithmetic device is disclosed in Patent Documents 1-6.

  However, since dedicated hardware designs a circuit configuration to perform specific arithmetic processing on image data, the range in which arithmetic processing can be performed is narrow, and a separate circuit configuration is designed to perform arithmetic processing outside the range. I had to start over.

  The method of processing image data using software performs arithmetic processing by a program using a general-purpose circuit configuration, so that various arithmetic processing can be performed on image data simply by changing the program.

  However, although the method of processing image data using software has a wide range in which arithmetic processing can be performed, the speed of performing arithmetic processing is slower than that of dedicated hardware.

  Therefore, the designer constructs an image processing system by appropriately using a method of processing image data using hardware and a method of processing image data using software.

JP 2008-310649 A JP-A-7-73160 JP-A-57-209564 JP-A-6-195369 Japanese Patent Laid-Open No. 11-41488 JP 2008-108049 A

  There are various types of processing of image data, but the same arithmetic processing is often included even if the processing content is different, or the same arithmetic processing is often included in the processing content. Therefore, the dedicated hardware (pipeline arithmetic device) is provided with an arithmetic unit that executes the same arithmetic processing if the processing contents are different even if the arithmetic processing is the same. In addition, in the dedicated hardware, when a plurality of the same arithmetic processes are included in the processing content, an arithmetic unit that executes the arithmetic processes as many as the included arithmetic processes is provided.

  For this reason, the dedicated hardware incorporates a plurality of overlapping arithmetic units, and there is a problem that the circuit scale increases.

  The pipeline arithmetic device disclosed in Patent Document 1 operates by rearranging the processing order of a plurality of arithmetic units in series and parallel. For this reason, the pipeline arithmetic device disclosed in Patent Document 1 incorporates a plurality of overlapping arithmetic unit circuits because the number of times that arithmetic processing is performed by one arithmetic unit is about once for each input data. As a result, the circuit scale increases.

  In addition, since the operation clock of each arithmetic unit in the pipeline is constant in the conventional pipeline arithmetic unit, even if it is an arithmetic unit capable of high-speed operation, the operation clock is adjusted in accordance with the slowest arithmetic unit. It was necessary to decide. For this reason, in the conventional pipeline arithmetic device, the arithmetic processing capability of the arithmetic unit capable of high-speed operation cannot be fully utilized, and hardware resources are wasted.

  Therefore, the present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a pipeline arithmetic device capable of reducing the circuit scale by reducing the incorporation of overlapping arithmetic units. To do.

  The pipeline arithmetic device according to the present invention includes a plurality of arithmetic units, an input selector, an output selector, a buffer, and a control unit. The arithmetic unit performs arithmetic processing on input data by a pipeline arithmetic method. The input selector is connected to the preceding stage of at least one arithmetic unit that performs arithmetic processing redundantly in a plurality of pipelines among the plurality of arithmetic units, and selects and inputs input data to be subjected to arithmetic processing. The output selector is connected to a subsequent stage of at least one arithmetic unit that performs arithmetic processing redundantly in a plurality of pipelines among the plurality of arithmetic units, and selects an output destination of the input data subjected to the arithmetic processing. The buffers are respectively connected to the previous stage of the input selector and the subsequent stage of the output selector, and temporarily hold the input data and the input data on which the arithmetic processing has been performed. The control unit controls an operation clock of at least one arithmetic unit connected between the input selector and the output selector so as to be faster than a reference clock for operating other arithmetic units. At least one arithmetic unit connected between the input selector and the output selector performs arithmetic processing in a time division manner for each pipeline.

  Preferably, after a predetermined amount of input data is accumulated in the buffer connected to the preceding stage, the input selector inputs the input data to the arithmetic unit connected to the subsequent stage.

  Preferably, the control unit adjusts the first clock for operating the pipeline connected to the previous stage of the input selector and the second clock for operating the pipeline connected to the subsequent stage of the output selector to be different.

  Preferably, the control unit includes a storage unit that stores history information including a delay time from selection of input data by the input selector to selection of an output destination by the output selector, and the output selector is stored in the storage unit. The output destination is selected based on the stored delay time.

  Preferably, the control unit changes the operation clock in order to change the number of time divisions of the arithmetic unit that performs arithmetic processing by time division based on a signal from the outside.

  Preferably, it further includes an extended storage unit connected between the input selector and the buffer and having a plurality of line buffers connected in series.

  Preferably, the pipeline is an asynchronous type that determines the transfer timing of input data based on a request signal and a response signal transmitted and received between a plurality of arithmetic units.

  According to the pipeline arithmetic device according to the present invention, the arithmetic unit that performs the arithmetic processing redundantly in a plurality of pipelines is subjected to the arithmetic processing in a time division manner for each pipeline, so that the overlapping arithmetic units can be incorporated. The circuit scale can be reduced.

It is the schematic which shows the structure of the image information processing apparatus containing the pipeline arithmetic unit which concerns on Embodiment 1 of this invention. It is a wave form diagram which shows the timing signal regarding the reference | standard TG image data which concerns on Embodiment 1 of this invention. It is a wave form diagram which shows the timing signal regarding the LTG image data which concerns on Embodiment 1 of this invention. It is the schematic which shows the structure of the image processor which concerns on Embodiment 1 of this invention. FIG. 3 is a signal wiring diagram illustrating signals input to and output from the image processing controller of the image processing processor according to the first embodiment of the present invention. It is a graph which shows the relationship between the input data amount of the a system pipeline of the image processor which concerns on Embodiment 2 of this invention, and the input data amount of the b system pipeline. 12 is a timing chart for explaining the operation of the image processor according to the third embodiment of the present invention. It is the schematic which shows the structure of the image processor which concerns on Embodiment 4 of this invention. It is the schematic which shows the structure of reference | standard TG, adjustment TG, and adjustment LTG. It is a timing chart which shows the waveform of the signal processed by the a system | strain adjustment TG of the image processor which concerns on Embodiment 4 of this invention. It is the schematic which shows the structure of the image processor which concerns on Embodiment 5 of this invention. It is the schematic which shows the structure of the time division execution unit which concerns on Embodiment 6 of this invention. It is the schematic which shows the structure of the time division execution unit which concerns on Embodiment 7 of this invention. It is the schematic which shows the structure of the time division execution unit which concerns on Embodiment 8 of this invention. It is the schematic which shows the structure of the time division execution unit which concerns on Embodiment 9 of this invention. It is the schematic which shows the structure of the image processor which concerns on Embodiment 10 of this invention.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a schematic diagram showing a configuration of an image information processing apparatus including a pipeline arithmetic device according to Embodiment 1 of the present invention. An image information processing apparatus 100 shown in FIG. 1 includes an image output unit 1 and an image input unit 2, and outputs image data to a display device 3.

  The image input unit 2 is connected to an image generation device that generates image data such as a TV tuner, a DVD (Digital Versatile Disc) playback device, or a Blu-Ray disc playback device, and outputs the generated image data to the image output unit 1 To do.

  The image output unit 1 performs predetermined image processing (for example, gamma correction of image data (RGB digital data) in units of pixels) on the image data input from the image input unit 2, and displays a display device such as a liquid crystal panel 3 outputs image data subjected to predetermined image processing in units of lines. The image output unit 1 includes an image memory 4, an image processor 5, an image processor 6, a microcomputer 7, a reference TG (timing generator) 8, an LTG (local timing generator) 9, an input interface 10, an output interface 11, and an interrupt controller. 16 is included.

  The image memory 4 is a memory for temporarily storing image data to be processed by the image processor 5. The image memory 4 does not need to be provided independently in the image output unit 1, and may be shared with a memory (not shown) that stores data of the microcomputer 7.

  The image processor 5 is an arithmetic device that performs predetermined image processing on image data using an arithmetic unit described later. The image processor 5 is also a pipeline arithmetic device that uses a plurality of arithmetic units to perform arithmetic processing on image data using a pipeline arithmetic method.

  The image processor 5 includes an input selector 14, an output selector 15, and arithmetic units 50a, 50b, and 50c. The input selector 14 is a switching device that is connected to the preceding stage of the arithmetic unit 50a and selects and inputs image data to be subjected to arithmetic processing. The output selector 15 is a switching device that is connected to the subsequent stage of the arithmetic unit 50a and selects an output destination (the arithmetic unit 50b or the arithmetic unit 50c) of the image data that has undergone arithmetic processing.

  The image processing controller 6 is a control device that controls the operation of the image processing processor 5. Specifically, the image processing controller 6 outputs a control signal to the image processing processor 5 in accordance with a command from the microcomputer 7 and controls the image processing processor 5 to determine an image processing operation mode and a path. Yes.

  The microcomputer 7 is a device that controls the operation of the entire image output unit 1 including the image processing controller 6.

  The reference TG 8 is a device that generates a clock signal that determines the operation timing of the image processor 5. For this reason, the device provided in the image processor 5 basically operates based on the clock signal generated by the reference TG 8.

  The LTG 9 is a device that generates a clock signal having a period different from that of the reference TG 8, and determines the operation timing of some devices provided in the image processor 5. The LTG 9 generates a clock signal having a period different from that of the reference TG 8 based on the timing generated by the reference TG 8 based on the clock control signal from the image processing controller 6.

  The input interface 10 is an interface for connecting to the image input unit 2 and inputs image data from the image input unit 2.

  The output interface 11 is an interface for connecting to the display device 3, and outputs image data subjected to predetermined image processing by the image output unit 1 to the display device 3. The image output unit 1 shown in FIG. 1 has two output interfaces 11, and one output interface 11 is connected to the arithmetic unit 50b, and the other output interface 11 is connected to the arithmetic unit 50c. A display device 3 is connected to each output interface 11.

  The interrupt controller 16 is a control device having an interrupt output function for outputting an interrupt signal to the image input unit 2.

  Specifically, the operation of the image information processing apparatus 100 will be described. First, the image input unit 2 inputs image data (frame data) of each frame constituting a video to the input interface 10 of the image output unit 1. The image output unit 1 converts image data (frame data) input to the input interface 10 into image data (line data) for each line based on the line synchronization signal. FIG. 2 is a waveform diagram showing timing signals related to the image data of the reference TG 8 according to Embodiment 1 of the present invention. A plurality of line synchronization signals shown in FIG. 2 are included in one frame synchronization signal. The line synchronization signal shown in FIG. 2 includes a plurality of bit clock signals, and one cycle of the bit clock signal corresponds to one bit of image data.

  The input interface 10 sequentially inputs image data (line data) for each line to the image processor 5 using a parallel bus that secures a bit width corresponding to image data for one line (one cycle of the line synchronization signal). To do. The image input unit 2 inputs the frame synchronization signal and the line synchronization signal to the input interface 10 together with the image data. In the input interface 10, for example, when one dot of image data is 24 bits, the line synchronization signal is a 24-bit bit clock signal and is a signal of one cycle.

  The reference TG 8 outputs an interrupt signal to the image input unit 2 via the interrupt controller 16 in accordance with the frame synchronization signal. As a result, the timing of inputting image data from the image input unit 2 can be synchronized with the timing of the operation clock signal of the reference TG 8.

  The waveform shown in FIG. 2 is input from the image input unit 2 to the input interface 10 of the image output unit 1, and illustrates a timing signal generated by the reference TG8.

  The image processor 5 that has input image data from the image input unit 2 includes a plurality of arithmetic units 50a, 50b, and 50c. Using the arithmetic units 50a, 50b, and 50c, various types of image processing are pipelined. It is the structure which calculates by a system. The image processor 5 performs arithmetic processing on the arithmetic unit 50a that performs arithmetic processing in a plurality of pipelines in a time division manner for each pipeline. Therefore, the operation clock of the arithmetic unit 50a has a different period from the operation clocks of the arithmetic units 50b and 50c, and is based on the clock signal generated by the LTG 9. FIG. 3 is a waveform diagram showing timing signals related to the image data of the LTG 9 according to the first embodiment of the present invention. The timing signal shown in FIG. 3 has a cycle approximately twice that of the timing signal of the reference TG8. Specifically, one cycle of the line synchronization signal of the reference TG8 shown in FIG. 2 corresponds to two cycles of the line synchronization signal of the LTG9 shown in FIG.

  Therefore, the image processor 5 performs time-division processing on the arithmetic unit 50a in the a-system pipeline and in the b-system pipeline in one cycle of the line synchronization signal of the reference TG8. be able to. Specifically, the image processing controller 6 switches the pipeline system that performs arithmetic processing in the arithmetic unit 50a based on the line synchronization signal of the LTG 9 as shown in FIG. In other words, the image processing controller 6 switches between the timing at which the arithmetic unit 50a is arithmetically processed in the a system and the timing of arithmetic processing in the b system during one cycle of the line synchronization signal of the reference TG8.

  Since the image processor 5 is connected to the image memory 4, it is possible to temporarily store the image data processed by the arithmetic units 50 a, 50 b, and 50 c in the image memory 4. Further, the image processor 5 outputs the image processed image data to the display device 3 and causes the display device 3 to display the image data.

  Next, the arithmetic processing of the arithmetic units 50a, 50b, and 50c in the image processor 5 will be described in detail. FIG. 4 is a schematic diagram showing the configuration of the image processor 5 according to Embodiment 1 of the present invention. FIG. 4A is a block diagram showing the processing order of the arithmetic units that perform arithmetic processing in the pipelines of the a system and the b system. FIG. 4B is a schematic diagram showing the configuration of the image processor 5. FIG. 5 is a signal wiring diagram showing signals input to and output from the image processing controller 6 of the image processor 5 according to Embodiment 1 of the present invention.

  The image processor 5 shown in FIG. 4 includes a time division execution unit 50d including an arithmetic unit 50a, and arithmetic units 50b and 50c to which image data arithmetically processed by the time division execution unit 50d are input. Further, the time division execution unit 50 d includes an input selector 14 and an output selector 15. Note that the image processor 5 includes an LTG 9 that generates a timing signal to be processed and performs time division operation, a reference TG 8 that generates a reference timing signal, and an image processing controller 6 that controls switching of pipeline systems. Is connected to.

  The image processing controller 6 sets a pipeline of a system for performing arithmetic processing by selecting input / output by the input selector 14 and the output selector 15, and then inputs an enable signal to the time division execution unit 50d, thereby calculating the arithmetic unit 50a. Can be operated in a time-sharing manner for each pipeline.

  The image processor 5 includes a buffer 12 that is connected to the preceding stage of the input selector 14 and the succeeding stage of the output selector 15 and temporarily holds the image data and the image data that has undergone arithmetic processing. The buffer 12 is a FIFO (First In First Out) buffer for absorbing a difference between the timing of the arithmetic processing in the time division execution unit 50d and the timing of arithmetic processing in other units. In FIG. 4, the buffer 12 provided on the input side of the a system pipeline is FIFOI_a, the buffer 12 provided on the output side of the a system pipeline is FIFOO_a, and the input side of the b system pipeline is shown. The provided buffer 12 is described as FIFOI_b, and the buffer 12 provided on the output side of the b-system pipeline is described as FIFOO_b.

  Next, a specific operation of the image processor 5 will be described in detail. The processing order of the arithmetic unit 50 that performs arithmetic processing in the a-system pipeline shown in FIG. 4A is the arithmetic unit “1” for converting the luminance of the image data, and the arithmetic unit “2” for filtering predetermined data from the image data. ”In this order. The processing order of the arithmetic unit 50 that performs arithmetic processing in the b-system pipeline shown in FIG. 4B is the arithmetic unit “3” for converting the luminance of the image data, and the arithmetic unit “4” for performing gamma correction on the image data. ”In this order.

  The arithmetic unit “1” in the a system pipeline and the arithmetic unit “3” in the b system pipeline are arithmetic processes that convert the luminance of the same image data, and are arithmetic processes that overlap in a plurality of pipelines. . For this reason, the arithmetic unit “1” in the a system pipeline and the arithmetic unit “3” in the b system pipeline perform time-division processing on one arithmetic unit 50a that converts the luminance of the image data. Can be realized. That is, the arithmetic unit “1” and the arithmetic unit “3” are grouped into the time division execution unit 50d, and the input selector 14 and the output selector 15 of the time division execution unit 50d are switched and executed.

  Although delay in each pipeline is allowed, the processing speed needs to be kept constant in each pipeline. In other words, both the time-division execution units 50d are routed, but it is necessary to perform control to keep the speed at which arithmetic processing is performed in the a-system pipeline and the speed at which arithmetic processing is performed in the b-system pipeline. Therefore, as shown in FIG. 5, a delay unit 13 for delaying the timing signal is provided in the middle of the path from the a system reference TG to the arithmetic unit 50b. Similarly, a delay unit 13 for delaying the timing signal is provided in the middle of the path from the b system reference TG to the arithmetic unit 50c. In FIG. 5, the delay unit 13 provided in the path of the a system reference TG is described as a delay unit 13_a, and the delay unit 13 provided in the path of the b system reference TG is described as a delay unit 13_b. It is.

  In the image processor 5 shown in FIG. 4, the first stage arithmetic unit of the a-system pipeline and the first stage arithmetic unit of the b-system pipeline are the common arithmetic unit 50a.

  The buffer 12 (FIFOI_a, FIFOI_b) on the input side of the pipelines a and b shown in FIG. 5 outputs the number of input accumulated data to the image processing controller 6 when the amount of image data to be accumulated exceeds the input reference value. To do.

  The buffer 12 (FIFO_a, FIFO_b) on the output side of the pipelines of the a system and the b system outputs the number of output stored data to the image processing controller 6 when the amount of stored image data exceeds the output reference value.

  The image processor 5 uses the input start reference value and the output start reference value input from the image processing controller 6 instead of the input reference value and the output reference value of the buffer 12 at the initial operation. The image processing controller 6 sets the input start reference value and the output start reference value for the pipeline of each system in accordance with the arithmetic processing in the pipeline. When the operation processing in the a system pipeline and the operation processing in the b system pipeline are performed asynchronously, or when the operation mode is dynamically changed, the image processing controller 6 is in the initial stage of operation. By setting the input start reference value large and then setting it to a low input reference value, the image data can be supplied to the arithmetic unit 50a without stagnation, and the image processor 5 can be operated stably.

  The buffer 12 (FIFO_a, FIFOO_b) outputs the number of output accumulated data to the image processing controller 6 when the output start reference value is exceeded. Thereafter, the image processor 5 starts output from the buffer 12 (FIFO_a, FIFO_b) to the outside. Note that the image processing controller 6 sets a large output start reference value at the initial stage of operation to prevent stagnation of image data output from the buffer 12 (FIFO_a, FIFOOO_b) to stabilize the image processing processor 5. Can be operated.

  The image processing controller 6 is alternately or periodically switched from the pipeline of the system to which the number of output accumulation data is input and the number of input accumulation data is input, and causes the arithmetic unit 50a to execute arithmetic processing. Specifically, the image processing controller 6 outputs a read selector switching signal for selecting a read selector for each line synchronization signal of the LTG 9.

  After an enable signal (unit En) is input to the time division execution unit 50d, image data is input from the buffer 12 (FIFOI_a, FIFOI_b) that requests calculation processing, and the time division execution unit 50d performs image data calculation processing. . The delay time for the arithmetic processing is measured by counting with the clock signal. After switching the input selector 14, the image data input from the buffer 12 (FIFOI_a, FIFOI_b) is input to the time division execution unit 50d after a delay time in the time division execution unit 50d.

  After switching the input selector 14, the image processing controller 6 waits for a delay time and selects a write selector so as to switch the output selector 15 to the pipeline of the system selected by the input selector 14. A switching signal is output. Therefore, the time division execution unit 50d has a time difference between the selection of the input selector 14 and the selection of the output selector 15. The image processing controller 6 includes a storage unit that stores history information including a delay time from selection of image data by the input selector 14 to selection of an output destination by the output selector 15.

  Then, based on the history information stored in the storage unit of the image processing controller 6, the image processing controller 6 outputs an appropriate delay amount to the delay unit 13. The delay unit 13 delays timing signals supplied from the a-system and b-system reference TG to the arithmetic units 50b and 50c based on the delay amount output from the image processing controller 6.

  As described above, the image processor 5 according to Embodiment 1 of the present invention includes the plurality of arithmetic units 50a, 50b, and 50c that perform arithmetic processing on image data (input data) by the pipeline arithmetic method. A buffer 12 and an image processing controller 6 are provided in the preceding stage of the selector 14, the output selector 15, and the input selector 14 and in the subsequent stage of the output selector 15. An arithmetic unit 50a in the pipeline is surrounded by an input selector 14 and an output selector 15, and the arithmetic unit 50a is used with an LTG line synchronization signal (operation clock) having a shorter cycle than the reference TG line synchronization signal (reference clock). Since the arithmetic unit 50a performs arithmetic processing, the arithmetic unit 50a that performs arithmetic processing redundantly in a plurality of pipelines is subjected to time-division arithmetic processing for each pipeline, thereby overlapping the arithmetic units 50a. Can be reduced and the circuit scale can be reduced.

  Since the image processor 5 is an asynchronous FIFO buffer to the buffer 12, the frequency of the operation clock for inputting the image data to the time division execution unit 50d and the operation clock for outputting the image data from the time division execution unit 50d. May be different.

(Embodiment 2)
In the image processor according to the second embodiment of the present invention, the a-system pipeline and the b-system pipeline are independently operated with asynchronous operation clocks. The image processor according to the second embodiment of the present invention is the same as the configuration of the image processor 5 according to the first embodiment. Therefore, the same components are denoted by the same reference numerals and detailed description is repeated. Absent.

  The LTG 9 according to the second embodiment generates a mode switching timing and an enable signal according to the line synchronization signal of the reference TG 8 for each cycle. The cycle of the line synchronization signal of the LTG 9 is accelerated so that arithmetic processing can be performed in the pipelines of the a system and the b system in one cycle of the line synchronization signal of the reference TG8.

  The plurality of pipelines are composed of a pair of an input and an output, and are fixed. That is, the image data input from the buffer 12 (FIFOI_a) is output from the buffer 12 (FIFOO_a), and the image data input from the buffer 12 (FIFOI_b) is output from the buffer 12 (FIFOO_b).

  Specifically, the image processing controller 6 inputs a selector switching signal to the input selector 14 and the output selector 15 and selects the a-line or b-line pipeline for performing the arithmetic processing.

  Data obtained by adding the a system image data input in synchronization with the reference timing of the a system pipeline and the b system image data input in synchronization with the reference timing of the b system pipeline. The amount is input to the time-sharing execution unit 50d and is processed at the LTG timing.

  As shown in FIG. 3, the LTG timing is a high-speed timing because the image data of a plurality of systems transferred by the reference timings of the pipelines of the a system and the b system are processed simultaneously.

  In order to perform arithmetic processing so that image data does not overflow from the input side buffer 12 (FIFOI_a, FIFOI_b) of the pipelines of the a system and the b system, the LTG timing needs to be increased, but the arithmetic unit 50a operates. The possible speed is limited. Therefore, it is desirable to operate the arithmetic unit 50a at the lowest possible frequency.

  In order to generate a timing signal such as a line synchronization signal having a minimum necessary frequency, the LTG 9 sets the transfer frequency of the LTG 9 ≧ a pipeline reference TG transfer frequency + b pipeline reference TG transfer frequency. . Here, the transfer frequency is the frequency of the line synchronization signal. Therefore, the minimum transfer frequency that can be set in the LTG 9 = the transfer frequency of the reference TG of the a system pipeline + the transfer frequency of the reference TG of the b system pipeline.

  If the transfer frequency of the reference TG of the a system pipeline and the transfer frequency of the reference TG of the b system pipeline are the same, the minimum transfer frequency that can be set by the LTG 9 and the reference TG of the a system pipeline The average value of the transfer frequency and the transfer frequency of the reference TG of the b-system pipeline always match. However, in the image processor 5 according to the second embodiment, the a-system pipeline and the b-system pipeline are independently operated with an asynchronous operation clock. The transfer frequency of the reference TG is different from the transfer frequency of the reference TG of the b-system pipeline. For this reason, the minimum transfer frequency that can be set in the LTG 9 varies centering on an average value of the transfer frequency of the reference TG of the a-system pipeline and the transfer frequency of the reference TG of the b-system pipeline.

  A problem that occurs when the minimum transfer frequency that can be set in the LTG 9 varies is when the image data accumulated in the buffer 12 (FIFOI_a, FIFOI_b) is small and at the initial stage of operation. Specifically, if the minimum transfer frequency that can be set by the LTG 9 is fast, the image data stored in the buffer 12 (FIFOI_a, FIFOI_b) is depleted, the supply to the arithmetic unit 50a is delayed, and the image processor 5 is stabilized. Cannot be operated.

  FIG. 6 is a graph showing the relationship between the input data amount of the a system pipeline and the input data amount of the b system pipeline of the image processor 5 according to the second embodiment of the present invention.

  In the upper part of FIG. 6, an a-system external input data amount indicating image data input to the buffer 12 (FIFOI_a) operated at the transfer frequency of the reference TG (a-system reference timing) of the a-system pipeline, The b system external input data amount indicating the image data input to the buffer 12 (FIFOI_b) operated at the transfer frequency (b system reference timing) of the reference TG of the system pipeline is illustrated.

  Further, in the upper part of FIG. 6, the total of the a system external input data amount and the b system external input data amount (a system + b system external input data amount) and the minimum transfer frequency (LTG output timing) that can be set for the LTG 9 are displayed. ) Shows the time-division unit processing, which is the amount of image data that the arithmetic unit 50a performs arithmetic processing.

  The middle part of FIG. 6 illustrates the a-system external input data amount, the FIFOI_a accumulated data that is the amount of image data stored in the buffer 12 (FIFOI_a), and the a-system input start reference value. Similarly, in the lower part of FIG. 6, b system external input data amount, FIFOI_b stored data that is the amount of image data stored in the buffer 12 (FIFOI_b), and b system input start reference value are illustrated. is there.

  In FIG. 6, after the image data is accumulated in the buffer 12 (FIFOI_a, FIFOI_b) up to the a system input start reference value and the b system input start reference value, respectively, the a system is always compared with the data amount of the time division unit processing. + B system external input data amount is lower, the image data stored in the buffer 12 (FIFOI_a, FIFOI_b) is not depleted, the supply to the arithmetic unit 50a is not delayed, and the image processor 5 is stably operated. You can see that

  In addition, the image processor 5 according to the second embodiment of the present invention uses the buffer 12 (FIFOI_a, FIFO) as a reference for selecting which pipeline processing is to be preferentially performed among a plurality of pipelines. A pipeline of a system with a large FIFOI_b) accumulated data amount-input start reference value) is selected.

(Embodiment 3)
The image processor according to the third embodiment of the present invention is not configured to always operate all of a plurality of pipelines, but includes a pipeline that is always operated and a pipeline that is temporarily operated. It is a mixed configuration. The image processor according to the third embodiment of the present invention is the same as the configuration of the image processor 5 according to the first embodiment. Therefore, the same components are denoted by the same reference numerals and detailed description is repeated. Absent.

  When the pipelines of the system to be temporarily operated are mixed, the image processor 5 changes the operation mode, operates only the pipeline of the system to be used, and lowers the operation clock of the time division execution unit 50d. This reduces power consumption.

  Specifically, the image processing controller 6 has a function of selecting an operation mode. For example, in the “normal mode”, only the a system pipeline is operated, and in the “parallel processing mode”, the b system pipe is operated. The line is also operated simultaneously.

  FIG. 7 is a timing chart for explaining the operation of the image processor according to the third embodiment of the present invention. FIG. 7 illustrates the operation of the a system pipeline, the operation of the b system pipeline, and the operation mode. Further, FIG. 7 shows external input data in the first stage of the a-system pipeline, reading (read) of the buffer 12 (FIFOI_a), writing to the buffer 12 (FIFO_a) (write), and the a-system pipeline. The external input data in the second stage is shown. Similarly, FIG. 7 shows external input data in the first stage of the b-system pipeline, reading (read) of the buffer 12 (FIFOI_b), writing to the buffer 12 (FIFO_b) (write), and b-system pipes. External input data in the second stage of the line is shown. FIG. 7 also shows the system selected by the input selector 14 and the system selected by the output selector 15.

  When the mode is switched from “normal mode” “dedicated to a” to “parallel processing mode” “a, b time division”, the operation of the a system pipeline and the operation of the b system pipeline are both Turns on. When the operation of the b-system pipeline is turned on, the system selected by the input selector 14 from the a-system at the falling edge when the external input data “1” in the first stage of the b-system pipeline is input. Switch to b system. Therefore, the external input data “1” is read from the buffer 12 (FIFOI_b), and the read external input data “1” is subjected to arithmetic processing by the arithmetic unit 50a. At the timing when the external input data “1” calculated by the arithmetic unit 50a is output, the system selected by the output selector 15 is switched from the a system to the b system, and the buffer 12 (FIFO_b) is arithmetically processed. External input data “1” is written. The external input data “1” written in the buffer 12 (FIFO_b) is output as external input data in the second stage of the b-system pipeline.

  When the operation mode is “normal mode” “dedicated to a”, the arithmetic unit 50 a does not need to perform arithmetic processing in a time-sharing manner, so the LTG 9 outputs an operation clock having the same cycle as the timing clock of the reference TG 8.

  The image processing controller 6 changes the operation mode based on an operation mode selection signal input from the microcomputer 7. When the operation mode selection signal “parallel processing mode” is input, the image processing controller 6 outputs a clock control signal to the LTG 9. The LTG 9 is generated by the reference TG 8 based on the clock control signal from the image processing controller 6. Based on the determined timing, a clock signal having a period faster than the reference TG8 is generated.

  As described above, the image processor 5 according to the third embodiment of the present invention changes the operation mode and operates the pipeline of the stopped system, so that only the pipeline of the system to be used is operated. The operation clock of the time division execution unit 50d can be lowered, and the power consumption can be reduced.

(Embodiment 4)
The image processor according to the fourth embodiment of the present invention is configured to give a speed difference to the speed (clock) at which the pipeline is operated before and after the time division execution unit. FIG. 8 is a schematic diagram showing a configuration of an image processor according to Embodiment 4 of the present invention. The image processing processor 5a shown in FIG. 8 has the same configuration as that of the image processing processor 5 shown in FIG. . Therefore, the image processor 5a according to the fourth embodiment of the present invention attaches the same reference numerals to the same components as those of the image processor 5 according to the first embodiment, and does not repeat detailed description.

  The output side of the buffer 12 (FIFO_a, FIFOO_b) and the arithmetic units 50b and 50c are driven based on the clock signals generated by the a-system and b-system reference TG8 as in the image processor 5 shown in FIG. However, the input side of the buffer 12 (FIFOI_a, FIFOI_b) is driven based on the clock signal generated by the a system and b system adjustment TG 19, and the buffer 12 (FIFO_a, FIFOO_b) is output from the output side of the buffer 12 (FIFOI_a, FIFOI_b). Is driven based on the clock signal generated by the adjustment LTG 20.

  Therefore, the image processor 5a generates a clock for operating the pipeline before and after the time division execution unit 50d so that an appropriate amount of data is accumulated in the buffer 12 (FIFOI_a, FIFOI_b) and the buffer 12 (FIFO_a, FIFOO_b). Can be changed dynamically.

  The image processor 5 shown in FIG. 5 does not output until an appropriate amount of data is accumulated in the buffer 12 (FIFOI_a, FIFOI_b) and the buffer 12 (FIFO_a, FIFOO_b) at the initial stage of pipeline operation for each system. The amount of data stored in the buffer 12 (FIFOI_a, FIFOI_b) and the buffer 12 (FIFO_a, FIFOOO_b) is adjusted by starting output after waiting for a predetermined delay time.

  However, the image processor 5a adjusts the amount of data stored in the buffer 12 (FIFO_a, FIFOOO_b) during the pipeline operation, and keeps the output speed of the image data from the time division execution unit 50d constant. It is necessary to dynamically change the clock for operating the pipeline before and after the time division execution unit 50d. Therefore, the image processor 5a uses the input side of the buffer 12 (FIFOI_a, FIFOI_b) that is the front side of the time division execution unit 50d as the output side of the buffer 12 (FIFO_a, FIFOOO_b) that is the rear side of the time division execution unit 50d. Driving is performed based on clock signals generated by different a system and b system adjustment TG 19. Further, the image processor 5a is based on the clock signal generated by the adjustment LTG 20 from the output side of the buffer 12 (FIFOI_a, FIFOI_b) corresponding to the time division execution unit 50d to the input side of the buffer 12 (FIFO_a, FIFOOO_b). Driving.

  Next, FIG. 9 is a schematic diagram showing configurations of the reference TG8, the adjustment TG19, and the adjustment LTG20. 9A is a schematic diagram illustrating the configuration of the reference TG 8, FIG. 9B is a schematic diagram illustrating the configuration of the adjustment TG 19, and FIG. 9C is a schematic diagram illustrating the configuration of the adjustment LTG 20. is there. In the following, the a system reference TG8, the a system adjustment TG19, and the a system adjustment LTG20 will be described, but the b system reference TG8, the b system adjustment TG19, and the b system adjustment LTG20 have the same configuration, and thus detailed description will not be repeated. .

  The a system reference TG8 illustrated in FIG. 9A includes an image timing generation unit 80 to which a clock signal clk_a serving as a reference for generating a timing signal is input. The image timing generation unit 80 counts the input clock signal clk_a, generates a timing signal as shown in FIG. 2 according to the image transfer format, and outputs it.

  The a system adjustment TG 19 illustrated in FIG. 9B includes a counter 91, a comparator 92, a selector 93, and an image timing generation unit 94. The a-system adjustment TG 19 has a configuration in which the function of the a-system reference TG8 is expanded, and in addition to the clock signal clk_a serving as a reference for generating a timing signal, the clock signal clk_fast having a period higher than that of the clock signal clk_a and the period of the clock signal clk_a The slow clock signal clk_slow is input to the counter 91.

  FIG. 10 is a timing chart showing waveforms of signals processed by the a system adjustment TG 19 of the image processor 5a according to Embodiment 4 of the present invention. FIG. 10 illustrates a clock signal clk_fast, a clock signal clk_a, a clock signal clk_slow, a counter En indicating the state of the image timing generation unit 94, a controller clock control signal, and a clock signal clk_blend.

  When the image processing controller 6 determines that the amount of image data stored in the buffer 12 (FIFOI_a, FIFOI_b) is insufficient compared to a certain reference value and the clock needs to be changed, the image processing controller 6 controls the controller 92 to control the controller clock. Output a signal. In the a system adjustment TG 19, when the controller clock control signal is input, the counter En is turned on.

  The comparator 92 switches the selector 93 to the clock signal clk_fast if the controller clock control signal is a positive value, and switches the selector 93 to the clock signal clk_slow if the controller clock control signal is a negative value.

  The image timing generation unit 94 counts the clock signal clk_blend (any one clock signal of the clock signal clk_fast, the clock signal clk_a, and the clock signal clk_slow) input via the selector 93 and follows the image transfer format. Generate and output timing signals.

  The a system adjustment TG 19 returns the selector 93 to the clock signal clk_a when the difference between the count value of the clock signal clk_fast and the count value of the clock signal clk_a becomes the value of the controller clock control signal. Specifically, as shown in FIG. 10, the a system adjustment TG 19 switches the selector 93 to the clock signal clk_fast when the value of the controller clock control signal is +5, and the difference from the count value of the clock signal clk_a becomes +5. The selector 93 is returned to the clock signal clk_a.

  The a system adjustment TG 19 also returns the selector 93 to the clock signal clk_a when the difference between the count value of the clock signal clk_slow and the count value of the clock signal clk_a becomes the value of the controller clock control signal.

  Since the a-system adjustment LTG 20 operates in a composite manner with respect to two pipelines, in addition to operating at a frequency equivalent to the sum of the clock signal clk_a and the clock signal clk_b, as well as the LTG 9, a speed higher than the sum is guaranteed. And a clock generation function for outputting at a frequency close to the sum.

  The a system adjustment LTG 20 illustrated in FIG. 9C includes a counter 201, a PLL (Phase-locked loop) circuit 202, a comparator 203, and an image timing generation unit 204. The counter 201 counts the number of periods of the clock signal clk_a and the clock signal clk_b. The comparator 203 compares the sum of the number of periods of the clock signal clk_a and the clock signal clk_b with the period number count of the PLL circuit 202, calculates a correction value, and changes the frequency division setting value of the PLL circuit 202. Note that the comparator 203 may consider the value of the controller clock control signal when comparing the sum of the number of cycles of the clock signal clk_a and the clock signal clk_b with the number of cycles of the PLL circuit 202. The a system adjustment LTG 20 repeats the above processing in units of counts, and controls the clock signal clk_blend output from the PLL circuit 202 to follow the target output (= clock signal clk_a + clock signal clk_b + frequency margin W).

  The image timing generation unit 204 counts the clock signal clk_blend output from the PLL circuit 202, generates a timing signal according to the image transfer format, and outputs it.

  As described above, the image processor 5a according to Embodiment 4 of the present invention has a speed difference (clock) for operating the pipeline before and after the time division execution unit 50d. FIFOI_a, FIFOI_b) and the amount of data stored in the buffer 12 (FIFO_a, FIFOO_b) can be adjusted appropriately.

(Embodiment 5)
The image processor according to the fifth embodiment of the present invention does not operate in accordance with a reference clock signal having an arithmetic process in each system pipeline, but generates a request signal and a response signal transmitted and received between the arithmetic units. It is an asynchronous type that determines the transfer timing of image data based on it.

  FIG. 11 is a schematic diagram showing a configuration of an image processor according to the fifth embodiment of the present invention. The image processor 5b shown in FIG. 11 has the same configuration as that of the image processor 5 shown in FIG. 5 except that it includes a calculation reference TG17 in addition to the a-system and b-system reference TG8. Therefore, the image processor 5b according to the fifth embodiment of the present invention attaches the same reference numerals to the same components as those of the image processor 5 according to the first embodiment, and does not repeat detailed description.

  In the image processor 5b, when the arithmetic processing in the pipeline of each system is asynchronous, the arithmetic units 50a, 50b, and 50c operate with asynchronous transfer times. The image processor 5b includes an a system and a b system reference TG8 in order to generate a clock signal for determining a transfer timing for inputting image data from the outside to the pipeline. Further, the image processor 5b includes a calculation reference TG17 in order to generate a clock signal for determining a transfer timing for outputting image data from the pipeline to the outside.

  When an external output request signal a requesting input of image data from the arithmetic unit 50b is input to the image processing controller 6, the image processing controller 6 outputs the external input request signal a to the a system reference TG8. The image processor 5b supplies image data from an image memory (not shown) to the buffer 12 (FIFOI_a) of the time division execution unit 50d based on the clock signal generated by the a system reference TG8. The a system reference TG 8 outputs the external input response signal a and the external input synchronization signal a to the image processing controller 6.

  When the external input response signal a is input from the a system reference TG8, the image processing controller 6 deletes the external output request signal a input from the arithmetic unit 50b, and the external input synchronization signal a input from the a system reference TG8. Is output to the arithmetic unit 50b together with the external output response signal a.

  The arithmetic unit 50b performs arithmetic processing on the image data output from the buffer 12 (FIFO_a) based on the timing of the input external input synchronization signal a and the arithmetic reference TG17.

  For stable operation, the image processor 5b uses the output side of the buffer 12 (FIFO_a) and the arithmetic unit 50b rather than the clock signal generated by the a system and the b system reference TG8 that drives the input side of the buffer 12 (FIFOI_a). , 50c, the period of the clock signal generated by the calculation reference TG 17 must be increased. The LTG 9 causes the time division execution unit 50d to perform arithmetic processing in a time division manner based on the clock signal generated by the arithmetic reference TG17.

  As described above, the image processor 5b according to the fifth embodiment of the present invention is based on the external input or external output request signal and the external input or external output response signal transmitted and received between the arithmetic units 50a, 50b, and 50c. Since the transfer timing of the image data is determined, stable driving can be performed in accordance with the actual operation of the arithmetic units 50a, 50b, and 50c.

(Embodiment 6)
FIG. 12 is a schematic diagram showing a configuration of a time division execution unit according to Embodiment 6 of the present invention. The time division execution unit 50d shown in FIG. 12 has the same configuration as the time division execution unit 50d shown in FIG. 4 except that the extended storage unit 18 is provided between the buffer 12 (FIFOI_a) and the input selector 14. Therefore, in the time division execution unit 50d according to Embodiment 6 of the present invention, the same components as those of the time division execution unit 50d according to Embodiment 1 are denoted by the same reference numerals, and detailed description thereof will not be repeated.

  When the arithmetic unit 50a performs arithmetic processing for filtering predetermined data from image data, the arithmetic unit 50a needs to fetch and process image data for three lines per cycle, for example.

  However, the buffer 12 (FIFOI_a, FIFOI_b) only holds image data for one line and cannot hold image data for three lines. Therefore, the time division execution unit 50d shown in FIG. 4 includes an extended storage unit 18 having two line buffers that hold image data for one line.

  Since the time division execution unit 50d shown in FIG. 4 includes the extended storage unit 18, the image data for three lines is held together with the buffer 12 (FIFOI_a, FIFOI_b) and supplied to the arithmetic unit 50a. it can. The extended storage unit 18 can connect a plurality of line buffers in series and repeatedly use image data depending on the past. Further, for each system, an extended storage unit 18 is connected between the buffer 12 (FIFOI_a, FIFOI_b) and the input selector 14.

  As described above, the time division execution unit 50d according to the sixth embodiment of the present invention can process the image data for three lines at a time by the arithmetic unit 50a. Therefore, a pipe having a plurality of arithmetic units 50a mounted thereon. An operation equivalent to a line can be realized.

(Embodiment 7)
FIG. 13 is a schematic diagram showing a configuration of a time division execution unit according to Embodiment 7 of the present invention. The time division execution unit 50d shown in FIG. 13 has the same configuration as the time division execution unit 50d shown in FIG. 4 except for a configuration in which a plurality of operation units 50a are connected in series instead of the single operation unit 50a. Therefore, in the time division execution unit 50d according to Embodiment 7 of the present invention, the same components as those of the time division execution unit 50d according to Embodiment 1 are denoted by the same reference numerals, and detailed description thereof will not be repeated.

  In the time division execution unit 50d shown in FIG. 4, an arithmetic unit 50a1 and an arithmetic unit 50a2 are connected in series between the input selector 14 and the output selector 15. Therefore, the arithmetic unit 50a1 for converting the luminance of the image data and the arithmetic unit 50a2 for filtering predetermined data from the image data can be arithmetically processed in a time division manner.

  As described above, the time division execution unit 50d according to the seventh embodiment of the present invention can be configured such that a plurality of arithmetic units 50a are connected in series between the input selector 14 and the output selector 15, so It is possible to further reduce the number of built-in arithmetic units and reduce the circuit scale.

(Embodiment 8)
FIG. 14 is a schematic diagram showing a configuration of a time division execution unit according to the eighth embodiment of the present invention. The time division execution unit 50d shown in FIG. 14 does not have a configuration having a pipeline consisting of only two systems of the a system and the b system, but has a configuration having a pipeline consisting of n systems (n ≧ 2). Note that, in the time division execution unit 50d according to Embodiment 8 of the present invention, the same components as those of the time division execution unit 50d according to Embodiment 1 are denoted by the same reference numerals, and detailed description thereof will not be repeated.

  The time division execution unit 50d shown in FIG. 14 has a pipeline consisting of n systems (n ≧ 2). Therefore, n buffers 12 (FIFO) are provided in the preceding stage of the input selector 14 and downstream of the output selector 15. n buffers 12 (FIFO) are provided.

  As described above, the time division execution unit 50d according to the eighth embodiment of the present invention has a configuration including a pipeline composed of n systems (n ≧ 2). The scale can be reduced.

(Embodiment 9)
FIG. 15 is a schematic diagram showing a configuration of a time division execution unit according to Embodiment 9 of the present invention. The time-sharing execution unit 50d shown in FIG. 15 is the same as the time-sharing execution unit 50d shown in FIG. 4 except that it includes two LUTs (look-up tables) 152 and a switching selector 151 that switches the LUT 152. Therefore, in the time division execution unit 50d according to Embodiment 9 of the present invention, the same components as those of the time division execution unit 50d according to Embodiment 1 are denoted by the same reference numerals, and detailed description thereof will not be repeated.

  The time division execution unit 50d shown in FIG. 15 switches the LUT 152 for each system, rewrites the setting of the arithmetic unit 50a, and executes arithmetic processing.

  After the system is switched, the arithmetic unit 50a transfers the setting parameter stored in the LUT 152 from the LUT 152 to the arithmetic unit 50a at a timing for performing settings for executing another system of arithmetic processing. Therefore, the arithmetic unit 50a can rewrite the setting parameter for each arithmetic processing of each system, and can perform arithmetic processing with different settings for each system.

  As described above, the time division execution unit 50d according to the ninth embodiment of the present invention includes the two LUTs 152 and the switching selector 151 that switches the LUT 152. Can be done.

(Embodiment 10)
FIG. 16 is a schematic diagram showing a configuration of an image processor according to the tenth embodiment of the present invention. The image processor 5c shown in FIG. 16 does not have a configuration in which the a system pipeline and the b system pipeline are equivalently connected in parallel, but the a system pipeline, the b system pipeline, Are connected in series as one pipeline. Note that the image processor 5c according to the tenth embodiment of the present invention attaches the same reference numerals to the same components as those of the image processor 5 according to the first embodiment, and does not repeat detailed description.

  The processing order of the arithmetic unit 50 that performs arithmetic processing in the pipeline shown in FIG. 16A is the arithmetic unit “1” for converting the luminance of the image data, the arithmetic unit “2” for filtering predetermined data from the image data, and the image The arithmetic unit “3” for performing gamma correction on the data and the arithmetic unit “4” for converting the luminance of the image data are in this order.

  For this reason, the image processor 5c shown in FIG. 16 includes an arithmetic unit (“2”, “4”) 50f that converts the luminance of the image data between the input selector 14 and the output selector 15. In the image processor 5c, the arithmetic unit (“1”) 50e is provided at the front stage of the a system pipeline, and the arithmetic unit (“3”) 50g is provided at the rear stage of the a system pipeline and before the b system pipeline. It has.

  As described above, the image processor 5c according to the tenth embodiment of the present invention has a configuration in which the a-system pipeline and the b-system pipeline are connected in series as one pipeline. Arithmetic processing can be executed by combining arithmetic units in various configurations.

  In addition, although the image processing processor according to the present invention has been described with respect to a pipeline arithmetic device that performs arithmetic processing on image data by a pipeline arithmetic method, the present invention is not limited to this. The present invention can be applied to any information processing processor as long as it is a pipeline arithmetic device that performs arithmetic processing on input data by a pipeline arithmetic method.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 image output unit, 2 image input unit, 3 display device, 4 image memory, 5 image processor, 6 image controller, 7 microcomputer, 8 reference TG, 9 LTG, 10 input interface, 11 output interface, 12 buffer , 13 delay unit, 14 input selector, 15 output selector, 16 interrupt controller, 17 calculation reference TG, 18 extended storage unit, 19 adjustment TG, 20 adjustment LTG.

Claims (7)

A plurality of arithmetic units that perform arithmetic processing on input data by a pipeline arithmetic method;
An input selector that is connected to a preceding stage of at least one arithmetic unit that performs arithmetic processing redundantly in a plurality of pipelines among the plurality of arithmetic units, and that selects and inputs the input data for arithmetic processing;
An output selector that is connected to a subsequent stage of at least one arithmetic unit that performs arithmetic processing in a plurality of pipelines among the plurality of arithmetic units, and that selects an output destination of the input data that has undergone arithmetic processing; ,
A buffer that is connected to a preceding stage of the input selector and a subsequent stage of the output selector, and temporarily holds the input data and the input data that has undergone arithmetic processing;
A control unit that controls an operation clock of at least one of the arithmetic units connected between the input selector and the output selector so as to be faster than a reference clock for operating the other arithmetic units;
A pipeline arithmetic device in which at least one arithmetic unit connected between the input selector and the output selector performs arithmetic processing in a time division manner for each pipeline.   2. The pipeline arithmetic device according to claim 1, wherein the input selector inputs the input data to the arithmetic unit connected to a subsequent stage after a predetermined amount of the input data is accumulated in the buffer connected to the previous stage. .   The control unit adjusts a first clock for operating the pipeline connected to the previous stage of the input selector and a second clock for operating the pipeline connected to the subsequent stage of the output selector to be different from each other. The pipeline arithmetic device according to claim 1 or 2. The control unit includes a storage unit that stores history information including a delay time from selection of the input data by the input selector to selection of an output destination by the output selector,
The pipeline operation device according to any one of claims 1 to 3, wherein the output selector selects an output destination based on the delay time stored in the storage unit.   The said control part changes the said operation clock in order to change the number of the time division of the said arithmetic unit which performs arithmetic processing by a time division based on the signal from the outside. The pipeline arithmetic unit described.   The pipeline arithmetic device according to any one of claims 1 to 5, further comprising an extended storage unit that is connected between the input selector and the buffer and includes a plurality of line buffers connected in series. .   The pipeline according to any one of claims 1 to 6, wherein the pipeline is an asynchronous type that determines a transfer timing of the input data based on a request signal and a response signal transmitted and received between the plurality of arithmetic units. Pipeline arithmetic unit.

Images