JP2013098489A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device capable of improving operational stability is provided.
A semiconductor memory device according to an embodiment includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines, a plurality of selection transistors, and a wiring layer. The plurality of memory cells are respectively arranged in a first direction and a second direction orthogonal to the first direction. The plurality of word lines are provided extending in the first direction, respectively. The plurality of bit lines each extend in the second direction and are provided apart from the plurality of word lines in a third direction orthogonal to the first direction and the second direction. The plurality of selection transistors are provided in each of the plurality of strings. The wiring layer is provided at the same potential as the source of the selection transistor. The wiring layer has a plurality of first overlapping portions that overlap with the plurality of word lines as viewed in the third direction. In the unit region where the pattern of the wiring layer is repeated, the areas of the plurality of first overlapping portions are the same.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  A semiconductor memory device includes a memory cell that stores data, and a peripheral circuit that controls operations such as writing, reading, and erasing data with respect to the memory cell. For example, a NAND flash memory has a charge storage layer for storing charges as a memory cell and a cell transistor. In the memory cell region, a plurality of memory cells are arranged in a matrix, and a plurality of word lines and a plurality of bit lines intersecting each other are provided.

In the memory cell region, a string is formed by a plurality of cell transistors connected in series in one direction. A selection transistor is provided in the string, and a source electrode is connected to a source of the selection transistor. Some source electrodes extend over the word lines in order to reduce the electrical resistance.
In a semiconductor memory device having such a source electrode, further improvement in operational stability is desired.

JP 2010-62369 A

  Embodiments of the present invention provide a semiconductor memory device capable of improving operational stability.

The semiconductor memory device according to the embodiment includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines, a plurality of selection transistors, and a wiring layer.
The plurality of memory cells are respectively arranged in a first direction along the main surface of the substrate and a second direction orthogonal to the first direction in the direction along the main surface.
The plurality of word lines are provided to extend in the first direction, respectively.
The plurality of bit lines each extend in the second direction and are provided apart from the plurality of word lines in a third direction orthogonal to the first direction and the second direction.
The plurality of selection transistors are respectively provided in a plurality of strings including a plurality of memory cells serially connected in the second direction among the plurality of memory cells.
The wiring layer is spaced apart from the plurality of word lines and the plurality of bit lines, and is provided at the same potential as the source of the selection transistor.
The wiring layer includes a plurality of first overlapping portions that respectively overlap the plurality of word lines when viewed in the third direction, and a plurality of second overlapping portions that respectively overlap the plurality of bit lines when viewed in the third direction. Have.
In the unit region where the pattern of the wiring layer is repeated, at least one of the areas of the plurality of first overlapping portions is the same or the areas of the plurality of second overlapping portions are the same. It is.

1 is a schematic plan view illustrating a semiconductor memory device according to an embodiment. 1 is a circuit diagram illustrating the configuration of a semiconductor memory device according to an embodiment. It is a typical sectional view which illustrates the composition of a block. (A)-(b) is a typical top view illustrated about a unit field. (A)-(b) is a schematic plan view illustrated about an overlapping area. (A)-(c) is a schematic diagram which shows the repeating example of the pattern of a wiring layer. (A)-(c) is a typical top view which shows the example of a pattern of the wiring layer in relation to a word line. It is a schematic plan view showing a pattern example of a wiring layer in relation to a word line. It is a typical top view which shows the example of a pattern of the wiring layer in relation to a bit line. It is a typical top view which shows the example of a pattern of the wiring layer in relation to a bit line. It is a typical top view which shows the example of a pattern of the wiring layer in relation to a bit line. It is a schematic plan view showing a pattern example of a wiring layer in relation to a word line and a bit line. (A)-(b) is a typical top view which shows the example of a pattern of the wiring layer in the relationship with a word line and a bit line. It is a schematic plan view which shows the example from which the magnitude | size of an opening part differs.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The drawings are schematic or conceptual and are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratio coefficient may be represented differently depending on the drawing.
Further, in the present specification and each drawing, the same reference numerals are given to the same elements as those described above with reference to the previous drawings, and detailed description thereof will be omitted as appropriate.

(Embodiment)
FIG. 1 is a schematic plan view illustrating the semiconductor memory device according to this embodiment.
As shown in FIG. 1, the semiconductor memory device 1 according to the embodiment is a NAND flash memory. A NAND flash memory is a kind of nonvolatile semiconductor memory and is an electrically rewritable memory.

  In the semiconductor memory device 1, for example, a semiconductor substrate 10 made of silicon is provided, and a multilayer wiring film 20 is provided on the semiconductor substrate 10 in almost the entire region. Hereinafter, two directions (first direction and second direction) orthogonal to each other among the directions parallel to the main surface 10a of the semiconductor substrate 10 are referred to as a “row direction” and a “column direction”. In addition, a direction (third direction) orthogonal to the first direction and the second direction is defined as a “stacking direction”.

  A memory cell array 11 is formed above and above the main surface 10 a of the semiconductor substrate 10, and row decoders 12 are formed on both sides of the memory cell array 11 in the row direction. In addition, a switching region 13, a page buffer 14, and a peripheral circuit 15 are arranged in this order on one side in the column direction as viewed from the memory cell array 11.

  In the memory cell array 11, a cell well 16 is formed in the upper layer portion of the semiconductor substrate 10. In the memory cell array 11, the memory cell regions 21 and the shunt regions 22 are alternately arranged along the row direction. In the memory cell region 21, a plurality of element isolation insulators (not shown) extending in the column direction are formed in parallel with each other at a constant period in the upper layer portion of the cell well 16 of the semiconductor substrate 10. A portion between the element isolation insulators 16 is an active area (not shown). A plurality of bit lines (not shown) are provided in the lowermost wiring layer of the multilayer wiring film 20. Each bit line is arranged immediately above each active area.

  In the shunt region 22, the lowermost wiring layer of the multilayer wiring film 20 is provided with a strip-like conductive film (not shown) extending in the column direction, and the lowermost wiring layer in the multilayer wiring film 20. A power supply wiring (not shown) is provided in the upper wiring layer, and a contact is provided between the semiconductor substrate 10 and the conductive film, and a contact is also provided between the conductive film and the power supply wiring. Is provided. The contacts of each layer are arranged in a line along the column direction.

FIG. 2 is a circuit diagram illustrating the configuration of the semiconductor memory device according to the embodiment.
The NAND flash memory, which is a semiconductor memory device according to the present embodiment, includes a plurality of blocks BLK, and data is erased in units of the blocks BLK.

  Each block BLK includes a plurality of memory cell transistors MT arranged in the row direction and the column direction, respectively. Among the plurality of memory cell transistors MT, a plurality of memory cell transistors MT connected in series in the column direction constitute a NAND string (hereinafter simply referred to as “string”) SR. One string SR includes, for example, (n + 1) (n is a natural number of 0 or more) memory cell transistors MT.

  Each block BLK is provided with a plurality of strings SR. For example, (m + 1) (m is a natural number greater than or equal to 0) strings SR are sequentially arranged along the row direction.

  Select transistors ST1 and ST2 are provided at both ends of each string SR. The drain of each select transistor ST1 of each string SR is connected to the bit lines BL0 to BLm. The gates of the select transistors ST1 of the strings SR are commonly connected to the select gate line SGD. The sources of the select transistors ST2 of the strings SR are commonly connected to the common source line SL. The gates of the select transistors ST2 of the strings SR are commonly connected to the select gate line SGS.

  In each string SR, (n + 1) memory cell transistors MT are provided such that their current paths are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2.

  In each string SR, word lines WL0 to WLn are connected to the control gate electrodes of the memory cell transistors MT, respectively. The drain of the memory cell transistor MT connected to the word line WL0 on the most drain side is connected to the source of the selection transistor ST1. The source of the memory cell transistor MT connected to the word line WLn on the most source side is connected to the drain of the selection transistor ST2.

  The word lines WL0 to WLn are commonly connected to the control gate electrodes of the plurality of memory cell transistors MT along the row direction between the plurality of strings SR in the block BLK. That is, the control gate electrodes of the memory cell transistors MT in the same row in the block BLK are connected to the same word line WL. The (m + 1) memory cell transistors MT connected to the same word line WL are handled as one page, and data writing and data reading are performed for each page.

  The bit lines BL0 to BLm are commonly connected to the drain of the select transistor ST1 between a plurality of blocks along the column direction. That is, the strings SR in the same column in a plurality of blocks are connected to the same bit line BL.

FIG. 3 is a schematic cross-sectional view illustrating the configuration of the block.
FIG. 3 shows a cross section (cross section of a plane perpendicular to the row direction) along the column direction in one string SR in the block BLK.
A p-type channel region 17 is formed on the surface of the semiconductor substrate 10. The channel region 17 extends in the column direction. On the channel region 17, a tunnel insulating film 13 a extending in the column direction is provided. The tunnel insulating film 13a is, for example, a silicon oxide film.

A plurality of charge storage layers are provided on the tunnel insulating film 13a. An example of this charge storage layer will be described using a floating gate FG. The floating gate FG is a polycrystalline silicon film to which, for example, phosphorus is added as an impurity imparting conductivity. The charge storage layer may be an insulating charge trap film, for example, a silicon nitride film.
An interlayer insulating film 21 is provided on each of the plurality of floating gates FG. The interlayer insulating film 21 is made of a material having a relative dielectric constant higher than that of the tunnel insulating film 13a.
A control gate CG is provided on each of the plurality of interlayer insulating films 21. The control gate CG can use the same material as the floating gate FG. As a result, the string SR is configured by the plurality of memory cell transistors MT arranged in series in the column direction. The control gate CG of each memory cell transistor MT is connected to the word line WL.

Select transistors ST1 and ST2 are connected to both ends of the string SR.
The drain-side select transistor ST1 is provided between the string and the n ^{+ type} semiconductor region 14b.
The bit line BL is connected to the channel region 17 via the bit line contact CBL and the n ^{+ type} semiconductor region 14b.
The source side select transistor ST2 is provided between the string and the n ^{+ -type} semiconductor region 14a.
The source line SL is connected to the channel region 17 via the source line contact CSL and the n ^{+ type} semiconductor region 14a.
Further, an n ^{+ type} semiconductor region can be provided between the memory cell transistors MT.

  The source line SL is a wiring layer M0 provided in a layer (intermediate layer) between the word line WL and the bit line BL. In order to reduce the electrical resistance of the source line SL, the wiring layer M0 can be extended from the connection position with the source line contact CSL to above the word line WL.

Here, a constant voltage is applied to the word line WL when data is written to and read from the memory cell. Similarly, when data is written and read, a certain amount is applied to the wiring layer M0 that is the source line SL.
Therefore, when the overlapping area of the word line WL and the wiring layer M0 is different for each word line WL in the stacking direction, the electric field between the word line WL and the wiring layer M0 is generated for each word line WL. Differences may occur and cause specific variations in data writing and reading. Similarly, even if the overlapping area of the bit line BL and the wiring layer M0 is different for each bit line BL in the stacking direction, it may cause characteristic variation.

In the semiconductor memory device 1 according to the embodiment, in the unit region where the pattern of the wiring layer M0 is repeated, the overlapping area of the plurality of word lines WL and the wiring layer M0 is substantially the same between the plurality of word lines WL. .
In the semiconductor memory device according to the embodiment, in the unit region, the overlapping area of the plurality of bit lines BL and the wiring layer M0 is substantially the same between the plurality of bit lines BL.

4A to 4B are schematic plan views illustrating unit regions.
The unit region UT shown in FIGS. 4A and 4B is a region in which the pattern shape seen in the stacking direction of the wiring layer M0 is repeated in the row direction and the column direction.
For example, in the unit area shown in FIG. 4A, one block BLK is the unit area UT1. When the pattern shape of the wiring layer M0 is repeated in one block BLK, the block BLK becomes the unit region UT1.

In the unit area shown in FIG. 4B, for example, an area delimited by the shunt area 22 provided in one block BLK is the unit area UT2. As for the pattern shape of the memory cell, the regularity of repetition in the shunt region 22 may be lost. In this case, the area delimited by the shunt area 22 can be the unit area UT2.
If the regularity of repetition of the pattern shape does not collapse in the shunt region 22, as shown in FIG. 4A, one block BLK may be used as the unit region UT1.
In the following description, the unit areas UT1 and UT2 are collectively referred to as a unit area UT.

FIGS. 5A to 5B are schematic plan views illustrating the overlapping area.
5A shows an overlapping area (first overlapping area) between the word line WL and the wiring layer M0, and FIG. 5B shows an overlapping area (second overlapping area) between the bit line BL and the wiring layer M0. ).
In any of the drawings, for easy understanding, the overlapping area of the two word lines WL and the two bit lines BL and the wiring layer M0 is shown. Here, the wiring layer M0 is connected to the source line SL or is a part of the source line SL. Therefore, the potential of the wiring layer M0 is substantially equal to the potential of the source line SL. Here, in the case where the wiring layer M0 (source electrode) is extended on the word line, it is preferable to provide an appropriate opening because the rate of error increases if the source electrode is provided uniformly on the word line. . Similarly, if the source electrode is uniformly provided in the lower layer or the upper layer of the bit line, an error occurrence rate is increased. Therefore, it is preferable to provide an appropriate opening.

  As shown in FIG. 5A, the wiring layer M0 has openings KK1 and KK2. When the wiring layer M0, one word line WL1, and another word line WL2 overlap in the stacking direction, the overlapping area DM1 between the one word line WL1 and the wiring layer M0 has overlapping portions OL11 and OL12. Is the total area. The overlapping area DM2 between the other word lines WL2 and the wiring layer M0 is the total area of the overlapping portions OL21 and OL22. That is, when there are a plurality of portions overlapping the wiring layer M0 along the direction in which one word line WL extends, the total area of these portions becomes the overlapping area.

In the semiconductor memory device 1 according to the embodiment, the overlapping area DM1 of one word line WL1 is the same as the overlapping area DM2 of other word lines WL2 in the unit region UT.
In the semiconductor memory device 1 according to the embodiment, the same applies to three or more word lines WL, and the overlapping areas of the plurality of word lines WL are the same in the unit region UT.
Here, the same overlapping area is a concept including a range of manufacturing errors in addition to the case where they are the same in design. The same applies to the following description.

  As shown in FIG. 5B, the opening KK3 and the opening KK4 are formed in the wiring layer M0. When the wiring layer M0, one bit line BL1, and another bit line BL2 overlap in the stacking direction, the overlapping area DM3 between the one bit line BL1 and the wiring layer M0 has overlapping portions OL31 and OL32. Is the total area. The overlapping area DM4 between the other bit lines BL2 and the wiring layer M0 is the total area of the overlapping portions OL41 and OL42. That is, when there are a plurality of portions overlapping with the wiring layer M0 along the extending direction of the bit line BL, the total area of these portions becomes the overlapping area.

In the semiconductor memory device 1 according to the embodiment, the overlapping area DM3 of one bit line BL1 is the same as the overlapping area DM4 of other bit lines BL2 in the unit region UT.
In the semiconductor memory device 1 according to the embodiment, the same applies to three or more bit lines BL, and the overlapping areas of the plurality of bit lines BL are the same in the unit region UT.

  Here, in order to make the overlapping areas of the plurality of word lines WL and the overlapping areas of the plurality of bit lines BL the same, it is realized by devising the pattern shape of the wiring layer M0.

The pattern of the wiring layer M0 of the semiconductor memory device 1 according to the embodiment includes a first pattern portion Pa and a second pattern portion Pb. The second pattern portion Pb is arranged adjacent to the row direction or the column direction via the first pattern portion Pa and the connecting portion J1 or J2.
For example, the shape of the first pattern portion Pa is the same as the shape of the second pattern portion Pb, but the pattern shape is inverted. Here, that the pattern shape is reversed means that the pattern of the opening and the wiring portion is reversed.

  In the example shown in FIG. 5A, the shape of the pattern is the same as the first pattern portion Pa and the second pattern except for the connecting portion J1 along the column direction between the first pattern portion Pa and the second pattern portion Pb. The pattern portion Pb is reversed.

  In the example shown in FIG. 5B, the pattern shape of the first pattern part Pa and the second pattern part 2 except for the connecting part J2 along the row direction between the first pattern part Pa and the second pattern part Pb. The pattern shape of the pattern portion Pb is inverted from each other.

FIGS. 6A to 6C are schematic views showing repeated examples of wiring layer patterns.
In the example shown in FIG. 6A, the first pattern portion Pa and the second pattern portion Pb of the wiring layer M0 are alternately laid out in the row direction in the unit region UT. If the number of the first pattern portions Pa and the number of the second pattern portions Pb are the same, the overlapping areas of the plurality of word lines WL overlapping the wiring layer M0 are the same.

  In the example shown in FIG. 6B, an example in which a plurality of first pattern portions Pa and a plurality of second patterns Pb of the wiring layer M0 are adjacently laid out in the unit region UT is shown. In this example, three first pattern portions Pa are set as one group, and three second patterns Pb are set as one group, and these groups are arranged adjacent to each other in the row direction. If the number of first pattern portions Pa and second pattern portions Pb in each group is the same, the overlapping areas of the plurality of word lines WL overlapping the wiring layer M0 are the same.

  In the example shown in FIG. 6C, a plurality of first pattern portions Pa1, Pa2, Pa3,..., Pa (n−1), Pa (n) of the wiring layer M0 are arranged in the column direction in the unit region UT. An example of regular deviation is shown. In addition, the lower part from which the 1st pattern part Pa shifted | deviated can be arrange | positioned in the upper part (part above the dotted line of FIG.6 (c)) from which the 1st pattern part Pa shifted | deviated. Further, the first pattern portions Pa1 to Pa (n) have the same size in the column direction, and the positions of the upper end portions of the first pattern portions Pa1 to Pa (n) are shifted so as to circulate in the column direction. I can say that. In this example, depending on the relationship between the shift pitch of the plurality of first pattern portions Pa1, Pa2, Pa3,..., Pa (n−1), Pa (n) and the pitch in the column direction of the plurality of word lines WL, The overlapping areas of the plurality of word lines WL overlapping the wiring layer M0 are the same.

  6A to 6C exemplify the relationship between the pattern of the wiring layer M0 and the word line WL, but the pattern (first pattern portion Pa, second pattern portion Pb) is repeated. By replacing a certain row direction with the column direction, the relationship between the pattern of the wiring layer M0 and the bit line BL becomes the same.

Next, a specific pattern of the wiring layer M0 will be described.
FIG. 7A to FIG. 8 are schematic plan views showing pattern examples of wiring layers in relation to word lines.
FIG. 7A shows a pattern layout example in which the first pattern portion Pa and the second pattern portion Pb of the wiring layer M0 are arranged adjacent to each other in the row direction in the unit region UT.
In the first pattern portion Pa, openings ha having the same size are provided at equal intervals in the row direction and the column direction, respectively.
In the first pattern portion Pa, the width W1 in the column direction of the opening ha is equal to the interval W2 between two openings ha adjacent in the column direction.

The second pattern portion Pb has the same pattern shape as the first pattern portion Pa. That is, the shape of the opening hb provided in the second pattern portion Pb is equal to the shape of the opening ha provided in the first pattern portion Pa. The pitches of the plurality of openings hb in the row direction and the column direction are equal to the pitches of the plurality of openings ha in the row direction and the column direction.
The second pattern portion Pb is arranged with a half-pitch shift in the column direction with respect to the first pattern portion Pa. Further, the width W1 and the width W2 are substantially equal to the pitch of the word lines WL in the column direction.

  When a plurality of word lines WL overlap with such a wiring layer M0, the overlapping area of each word line WL and the wiring layer M0 is the same regardless of the position of the word line WL in the column direction. In the example shown in FIG. 7A, the plurality of word lines WL are arranged so as to cross the three openings ha or the three openings hb, respectively. In any word line WL, the overlapping area of the word line WL and the wiring layer M0 is the same. Further, even when the misalignment between the word line WL and the wiring layer M0 occurs as shown in FIG. 7B and the word line WL covers the ends of the openings ha and hb of the wiring layer M0, The overlapping area of WL and wiring layer M0 is the same.

FIG. 7C shows a pattern layout example in which the first pattern portions Pa and the second pattern portions Pb of the wiring layer M0 are alternately arranged in the row direction in the unit region UT.
In the first pattern portion Pa, openings ha having the same size are provided at equal intervals in the column direction.
In the first pattern portion Pa, the width W1 in the column direction of the opening ha is equal to the interval W2 between two openings ha adjacent in the column direction.

  The second pattern portion Pb has the same pattern shape as the first pattern portion Pa. That is, the shape of the opening hb provided in the second pattern portion Pb is equal to the shape of the opening ha provided in the first pattern portion Pa. The pitch in the column direction of the plurality of openings hb is equal to the pitch in the column direction of the plurality of openings ha. Further, the width W1 and the width W2 are substantially equal to the pitch of the word lines WL in the column direction.

  In the example shown in FIG. 7C, the shape of the first pattern portion Pa and the second pattern portion Pb in the portion excluding the connecting portion J1 provided between the first pattern portion Pa and the second pattern portion Pb. These shapes are reversed from each other. That is, except for the connecting portion J1, the positional relationship between the opening ha and the non-opening portion of the first pattern portion Pa is reversed from the positional relationship between the opening hb and the non-opening portion of the second pattern portion Pb. As a result, the second pattern portion Pb includes a non-opening that reverses the opening ha of the first pattern portion Pa.

  When a plurality of word lines WL overlap with such a wiring layer M0, the overlapping area of each word line WL and the wiring layer M0 is the same regardless of the position of the word line WL in the column direction. In the example shown in FIG. 7C, the plurality of word lines WL are arranged so as to cross the two openings ha or the two openings hb, respectively. In any word line WL, the overlapping area of the word line WL and the wiring layer M0 is the same. Further, even when a misalignment between the word line WL and the wiring layer M0 occurs and the word line WL covers the ends of the openings ha and hb of the wiring layer M0, the word line WL and the wiring layer M0 overlap. The area will be the same.

FIG. 8 shows an example of a layout in which the first pattern portions Pa1 to Pa4 having the same pattern shape are arranged in a state shifted in the column direction in the unit region UT.
That is, in this example, the first pattern portion Pa1 and the first pattern portion Pa3 are shifted by a half pitch in the column direction. In addition, the first pattern portion Pa2 located between the first pattern portion Pa1 and the first pattern portion Pa3 having the same pattern shape is shifted from the first pattern portion Pa1 by less than a half pitch in the column direction. Further, the first pattern portion Pa2 and the fourth pattern portion Pa4 are shifted by a half pitch in the column direction.

  When a plurality of word lines WL overlap with such a wiring layer M0, regardless of the pitch in the column direction of the first pattern portions Pa1 to Pa4 and the pitch in the column direction of the plurality of word lines WL, Also, the overlapping area of the word line WL and the wiring layer M0 is the same.

  As shown in FIG. 8, a set of the first pattern portion Pa1 and the third pattern portion Pa3 inverted with respect to the pattern shape of the first pattern portion Pa1 (first set GP1), and the second pattern portion Pa2 When the set (second set GP2) with the fourth pattern portion Pa4 inverted with respect to the pattern shape of the second pattern portion Pa2 is arranged in the row direction, the column of the first set GP1 and the second set GP2 Regardless of the amount of direction deviation, the overlapping area of each of the plurality of word lines WL and the wiring layer M0 is the same.

9 to 11 are schematic plan views showing pattern examples of the wiring layer in relation to the bit lines.
FIG. 9 shows a pattern layout example in which the first pattern portions Pa and the second pattern portions Pb of the wiring layer M0 are alternately arranged in the column direction in the unit region UT.
The bit lines BL extend in the column direction and are arranged at regular intervals in the row direction.
In the first pattern portion Pa, a plurality of openings ha having the same size are provided at equal intervals in the row direction. Further, the interval between the openings ha is narrower than the interval between the bit lines BL.
In the second pattern portion Pb, a plurality of openings hb having the same size as the openings ha of the first pattern portion Pa are provided at equal intervals in the row direction. Further, the interval between the openings hb is narrower than the interval between the bit lines BL. The width of the opening ha and the opening hb in the row direction is larger than the width of the bit line BL.
The second pattern portion Pb is laid out with a half-pitch shift in the row direction with respect to the first pattern portion Pa.

  In the example shown in FIG. 9, the opening ha of the first pattern portion Pa and the opening hb of the second pattern portion Pb are provided so as to overlap each other when viewed in the column direction. Therefore, by providing the plurality of bit lines BL in accordance with the portions where the openings ha and hb overlap in the column direction, the overlapping area between the bit line BL and the wiring layer M0 in any bit line BL. Are the same.

Since the second pattern portion Pb is arranged with a half-pitch shift in the row direction with respect to the first pattern portion Pa, even in the case where the bit line BL is arranged between the plurality of openings ha, the third direction As a result, the bit line BL is arranged so as to overlap the plurality of openings hb. Even when the bit line BL is disposed between the plurality of openings hb, the bit line BL is disposed so as to overlap with the plurality of openings ha when viewed in the third direction.
Therefore, compared with the case where the second pattern portion Pb and the first pattern portion Pa are arranged without being shifted in the row direction, it is possible to suppress variation in the overlapping area with the wiring layer M0 in each bit line BL. .

Even if the bit line BL is disposed between the plurality of openings hb, the bit line BL is disposed so as to overlap the plurality of openings ha as viewed in the stacking direction.
Therefore, each bit line BL is compared with the case where the second pattern portion Pb and the first pattern portion Pa are arranged without being shifted in the row direction (at least one bit line BL does not overlap the opening hb). Therefore, it is possible to suppress the variation in the overlapping area with the wiring layer M0.

In the example illustrated in FIG. 10, the first pattern portions Pa <b> 1 to Pa <b> 5 are laid out with a shift of less than a half pitch in the row direction.
In the first pattern portions Pa1 to Pa5, a plurality of openings ha are provided at equal intervals (pitch pt1) in the row direction. The first pattern portion Pa1 and the first pattern portion Pa5 are shifted by a half pitch in the row direction. Further, the first pattern portions Pa2 to Pa4 are arranged between the first pattern portion Pa1 and the first pattern portion Pa5 having the same pattern shape. The second first pattern portion Pa2 is shifted in the row direction with respect to the first first pattern portion Pa1 at a pitch pt2 that is less than half the pitch pt1 of the plurality of openings ha. The third first pattern portion Pa3 is shifted in the row direction at a pitch pt2 with respect to the second first pattern portion Pa2. Similarly, the fourth first pattern portion Pa4 and the fifth first pattern portion Pa5 are also sequentially shifted in the row direction at a pitch pt2. That is, pitch pt2 × 5 = pitch pt1.
The pattern of the wiring layer M0 shown in FIG. 10 may be repeated in the column direction with the first pattern portion Pa1 to the first pattern portion Pa5 as one unit.

Here, the pitch in the row direction of the plurality of bit lines BL is defined as pitch pt3. At this time, by making the pitch pt3 an integral multiple of the pitch pt2 (pitch pt3 = n × pitch pt2; n is an integer of 1 or more), the bit line BL and the wiring layer M0 overlap in any bit line BL. The area can be the same.
In the example shown in FIG. 10, five first pattern portions Pa <b> 1 to Pa <b> 5 are provided in one unit region UT, but this is an example and is not limited. The example shown in FIG. 10 can also be applied to the word line WL.

In the example shown in FIG. 11, the first pattern portions Pa1 to Pa4 are laid out with a shift of less than a half pitch in the row direction for each of the blocks BLK1 to BLK4.
The pattern shape of the wiring layer M0 provided in each of the plurality of blocks BLK1 to BLK4 is the same. That is, in each of the first pattern portions Pa1 to Pa4, a plurality of openings ha are provided at predetermined intervals in the row direction and the column direction. Here, the pitch in the row direction of the plurality of openings ha is pt5. The first pattern portion Pa1 and the first pattern portion Pa4 are shifted by a half pitch in the row direction. Further, first pattern portions Pa2 to Pa3 are arranged between the first pattern portion Pa1 and the first pattern portion Pa4 having the same pattern shape.

The first pattern portion Pa2 provided in the second block BLK2 is in the row direction at a pitch pt6 that is less than half the pitch pt5 of the plurality of openings ha with respect to the first pattern portion Pa1 provided in the first block BLK1. It is shifted to.
The first pattern portion Pa3 provided in the third block BLK3 is in the row direction with a pitch pt6 that is less than half the pitch pt5 of the plurality of openings ha with respect to the first pattern portion Pa2 provided in the second block BLK2. It is shifted to.
Similarly, the first pattern portion Pa4 provided in the fourth block BLK4 has a pitch pt6 less than half the pitch pt5 of the plurality of openings ha with respect to the first pattern portion Pa3 provided in the third block BLK3. It is shifted in the row direction.

Here, the pitch in the row direction of the plurality of bit lines BL is defined as a pitch pt7. At this time, by making the pitch pt7 an integral multiple of the pitch pt6 (pitch pt7 = n × pitch pt6; n is an integer of 1 or more), the bit line BL and the wiring layer M0 overlap in any bit line BL. The area can be the same.
In the example shown in FIG. 11, the first pattern portions Pa1 to Pa4 are provided in the four blocks BLK1 to BLK4, respectively, but this is an example and is not limited.

12 to 13B are schematic plan views showing pattern examples of the wiring layer in relation to the word lines and the bit lines.
In the example shown in FIG. 12, a plurality of first pattern portions Pa are laid out with a half-pitch shift in the row direction and the column direction in the unit region UT.
One first pattern portion Pa is rectangular and has an opening ha at the center. The wiring layer M0 shown in FIG. 12 has a pattern shape in which a plurality of first pattern portions Pa are laid out while being shifted by a half pitch in each of the row direction and the column direction.

In such a layout, the word lines WL are arranged almost at the center positions of the plurality of openings ha arranged in the column direction, and the bit lines BL are arranged almost at the center positions of the plurality of openings ha arranged in the row direction. To do. That is, in the stacking direction, the word line WL and the bit line BL intersect at substantially the center position of the opening ha.
Thereby, the overlapping area of the word line WL and the wiring layer M0 is the same between the plurality of word lines WL. In addition, the overlapping area of the bit line BL and the wiring layer M0 is the same between the plurality of bit lines BL.

FIGS. 13A to 13B illustrate a case where the shape of the opening of the first pattern portion Pa shown in FIG. 12 is other than a rectangle.
The shape of the opening ha10 shown in FIG. The shape of the opening ha20 illustrated in FIG. 13B is an ellipse. Even if the shape of the opening is rectangular in design, it may not be rectangular in the actually manufactured state. Even if the openings are other than rectangular, if the word lines WL and bit lines BL are arranged in accordance with the pitch of the plurality of openings, the overlapping area between the word lines WL and the wiring layer M0 between the plurality of word lines WL. Will be the same. In addition, the overlapping area of the bit line BL and the wiring layer M0 is the same between the plurality of bit lines BL.

  In FIGS. 13A to 13B, examples of circular and elliptical openings are shown, but other shapes (for example, hexagons) can be similarly applied. Moreover, even if it is the opening part of the wiring layer M0 represented to Fig.7 (a)-FIG. 11, you may apply circular, an ellipse, and other shapes.

FIG. 14 is a schematic plan view illustrating an example in which the size of the opening is different.
FIG. 14 shows a pattern layout example in which the first pattern portion Pa and the second pattern portion Pb of the wiring layer M0 are arranged adjacent to each other in the row direction in the unit region UT.
The first pattern portion Pa is provided with a plurality of openings ha31 to ha34 having different sizes. The second pattern portion Pb is provided with a plurality of openings hb41 to hb44 having different sizes. The shape of the second pattern portion Pb is the same as the shape of the first pattern portion Pa, but the pattern shape is inverted.

  In the example shown in FIG. 14, the first pattern portion Pa and the second pattern portion Pb are mutually inverted, except for the connecting portion J3 extending in the column direction in the first pattern portion Pa and the second pattern portion Pb. doing. In other words, except for the connecting portion J3, the positional relationship between the opening portions ha31 to ha34 of the first pattern portion Pa and the non-opening portion is reversed from the positional relationship between the opening portions hb41 to hb44 and the non-opening portion of the second pattern portion Pb. doing.

  Specifically, the opening ha31 of the first pattern portion Pa and the opening hb41 of the second pattern portion Pb are shifted from each other by a half pitch in the column direction. The width w31 in the column direction of the opening ha31 and the opening hb41 is substantially equal to the interval w32 between the two openings ha31 and the two openings hb41 adjacent in the column direction.

  Further, the opening ha32 of the first pattern portion Pa and the opening hb42 of the second pattern portion Pb are shifted from each other by a half pitch in the column direction. The width w41 in the column direction of the opening ha32 and the opening hb42 is substantially equal to the interval w42 between the two openings ha32 and the two openings hb42 adjacent in the column direction.

  Further, the opening ha33 of the first pattern portion Pa and the opening hb43 of the second pattern portion Pb are shifted by a half pitch in the column direction. The width w51 in the column direction of the opening ha33 and the opening hb43 is substantially equal to the interval w52 between the two openings ha33 and the two openings hb43 adjacent in the column direction.

  Further, the opening ha34 of the first pattern portion Pa and the opening hb44 of the second pattern portion Pb are shifted by a half pitch in the column direction. The width w61 in the column direction of the opening ha34 and the opening hb44 is substantially equal to the interval w62 between the two openings ha34 and the two openings hb44 adjacent in the column direction.

  Thus, the efficiency of layout design is improved by inverting the pattern shapes of the first pattern portion Pa and the second pattern portion Pb. That is, if the first pattern portion Pa is designed, the first pattern Pb can be automatically generated by the design tool.

  Even if the sizes of the openings (ha31 to ha34, hb41 to hb44) of the first pattern portion Pa and the second pattern portion Pb are different as in the wiring layer M0 illustrated in FIG. When the word lines WL overlap, the overlapping area of the word line WL and the wiring layer M0 is the same between the word lines WL.

By applying the pattern shape of the wiring layer M0 described above to the semiconductor memory device 1 and making the overlapping area of the word line WL and the wiring layer M0 the same between the plurality of word lines WL, the word line WL and the wiring layer The electric field between M0 is made uniform among the plurality of word lines WL.
Further, by making the overlapping area of the bit line BL and the wiring layer M0 the same between the plurality of bit lines BL, the electric field between the bit line BL and the wiring layer M0 is made uniform between the plurality of bit lines BL. The
Thereby, in the semiconductor memory device 1 according to the embodiment, the improvement of the operational stability is achieved.

In addition, although embodiment was described above, this invention is not limited to these examples. For example, even if the pattern shape of the wiring layer M0 applied in relation to the word line WL is applied in relation to the bit line BL, the pattern shape of the wiring layer M0 applied in relation to the bit line BL is also changed to the word line WL. You may apply in relation to. Further, the pattern shape of the wiring layer M0 applied in relation to the word line WL and the pattern of the wiring layer M0 applied in relation to the bit line BL may be combined in the possible range and applied to the semiconductor memory device 1. .
Further, those in which those skilled in the art appropriately added, deleted, and changed the design of the above-described embodiments, and combinations of the features of each embodiment as appropriate, also have the gist of the present invention. As long as it is within the scope of the present invention.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device, 10 ... Semiconductor substrate, 10a ... Main surface, 11 ... Memory cell array, 12 ... Row decoder, 13 ... Switching region, 13a ... Tunnel insulating film, 14 ... Page buffer, 14a ... Type semiconductor region, 14b ... Type semiconductor region, 15 ... peripheral circuit, 16 ... cell well, 17 ... channel region, 21 ... memory cell region, 22 ... shunt region, BL ... bit line, BLK ... block, DM1 ... overlapping area, DM2 ... overlapping area, J1 ... Connection portion, J2 ... connection portion, J3 ... connection portion, M0 ... wiring layer, MT ... memory cell transistor, OL11, OL12 ... overlap portion, OL21, OL22 ... overlap portion, OL31, OL32 ... overlap portion, OL41, OL42 ... overlap Part, Pa ... 1st pattern part, Pb 2nd ... Pattern part, SGD ... Selection gate line, SGS ... -Option gate line, SL ... source line, SR ... strings, ST1, ST2 ... selection transistor, UT ... unit area, WL ... word line, ha ... opening, hb ... opening

Claims (5)

A plurality of memory cells respectively disposed in a first direction along the main surface of the substrate and a second direction orthogonal to the first direction in the direction along the main surface;
A plurality of word lines extending in the first direction;
A plurality of bit lines extending in the second direction and spaced apart from the plurality of word lines in a third direction orthogonal to the first direction and the second direction;
A plurality of select transistors provided in a plurality of strings each including a plurality of memory cells serially connected in the second direction among the plurality of memory cells;
A wiring layer spaced apart from the plurality of word lines and the plurality of bit lines and provided at the same potential as the sources of the plurality of selection transistors;
With
The wiring layer includes a plurality of first overlapping portions that respectively overlap the plurality of word lines when viewed in the third direction, and a plurality of second overlapping portions that respectively overlap the plurality of bit lines when viewed in the third direction. Have
In the unit region where the pattern of the wiring layer is repeated, at least one of the areas of the plurality of first overlapping portions is the same or the areas of the plurality of second overlapping portions are the same. A semiconductor memory device. The wiring layer has a first pattern portion, and a second pattern portion adjacent to the first pattern portion in the first direction,
The semiconductor memory device according to claim 1, wherein the pattern shape of the first pattern portion includes a portion that is inverted from the pattern shape of the second pattern portion. The wiring layer includes a first pattern portion, and a second pattern portion adjacent to the first pattern portion in the first direction,
2. The semiconductor memory according to claim 1, wherein a pattern shape of the first pattern portion is the same as a pattern shape of the second pattern portion, and is shifted in the second direction with respect to a pattern shape of the second pattern portion. apparatus.   4. The semiconductor memory device according to claim 3, wherein a pattern shape of the first pattern portion is shifted by a half pitch in the second direction with respect to a pattern shape of the second pattern portion. A plurality of the unit regions are provided in the second direction,
The semiconductor memory device according to claim 1, wherein a pattern shape of the wiring layer is shifted in the first direction in the plurality of unit regions.

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