JP2013097100A - Driver circuit of display device, display device, and electronic apparatus - Google Patents

Abstract

A display device drive circuit capable of writing a DC voltage having a desired voltage value to a signal line without being affected by charge injection or clock feedthrough during switching of a sampling switch, and display using the drive circuit An apparatus and an electronic device including the display device are provided.
A drive circuit of a display device according to the present disclosure is provided for each signal line wired for each pixel column of a pixel array unit in which pixels are arranged in a matrix, and samples a predetermined DC voltage to be input. And a capacitor that is connected to the input node of the sampling switch and absorbs fluctuations in the potential of the input node caused by switching of the sampling switch.
[Selection] Figure 6

Description

  The present disclosure relates to a display device drive circuit, a display device, and an electronic device, and in particular, a drive circuit that drives a signal line of the display device, a display device using the drive circuit, and an electronic device including the display device. About.

  In a flat-type display device such as an organic EL display device, a predetermined DC voltage is written to a pixel prior to writing a gradation voltage in order to improve image quality defects caused by variations in characteristics of elements constituting the pixel. A correction process for characteristic variation is performed using the DC voltage as a reference voltage (see, for example, Patent Document 1).

  The writing of the predetermined DC voltage is performed via a signal line (data line) wired for each pixel column of the pixel array unit in which pixels are arranged in a matrix. More specifically, a sampling switch is provided for each signal line. The sampling switch samples a predetermined DC voltage supplied from a signal supply source in units of pixel columns, and writes the signal to each signal line. A predetermined DC voltage is written to the pixel via the line.

JP 2007-310311 A

  However, when a DC voltage is written to each pixel via the sampling switch, a phenomenon occurs in which the potential at the input node of the sampling switch fluctuates due to the effects of charge injection and clock feedthrough when the sampling switch is switched. Since the DC voltage fluctuates due to the fluctuation of the potential at the input node of the sampling switch, it becomes impossible to write a DC voltage having a desired voltage value to the pixel. As a result, correction processing for characteristic variations using a direct-current voltage having a desired voltage value as a reference voltage cannot be performed normally.

  Therefore, the present disclosure provides a display device drive circuit capable of writing a DC voltage having a desired voltage value to a signal line without being affected by charge injection or clock feedthrough during switching of a sampling switch, and the drive circuit It is an object of the present invention to provide a display device using the electronic device and an electronic device including the display device.

In order to achieve the above object, a display device drive circuit according to the present disclosure includes:
A sampling switch that is provided for each signal line wired in units of pixel columns of a pixel array unit in which pixels are arranged in a matrix, and that samples a predetermined DC voltage input and writes the signal to the signal line;
A capacitive element connected to the input node of the sampling switch and absorbing fluctuations in the potential of the input node caused by switching of the sampling switch.

  The drive circuit of the present disclosure can be used for driving signal lines wired in units of pixel columns in the pixel array unit in a display device having a pixel array unit in which pixels are arranged in a matrix. In addition, a display device using the drive circuit of the present disclosure can be used as a display unit in various electronic devices including the display unit.

  When a predetermined DC voltage is written to the signal line by sampling by the sampling switch, the potential of the input node of the sampling switch tends to be fluctuated due to the influence of charge injection and clock feedthrough when the sampling switch is switched. At this time, the capacitive element connected to the input node of the sampling switch acts to absorb the effects of charge injection and clock feedthrough. As a result, fluctuations in the potential of the input node of the sampling switch due to the influence of charge injection or clock feedthrough can be suppressed.

  According to the present disclosure, the fluctuation of the potential of the input node of the sampling switch due to the influence of charge injection or clock feedthrough at the time of switching of the sampling switch can be suppressed. A DC voltage can be written to the signal line.

1 is a system configuration diagram illustrating an outline of a configuration of an active matrix organic EL display device according to an embodiment of the present disclosure. It is a circuit diagram which shows an example of the concrete circuit structure of a pixel (pixel circuit). FIG. 5 is a timing waveform diagram for explaining a basic circuit operation of an active matrix organic EL display device according to an embodiment of the present disclosure. FIG. 6 is a characteristic diagram for explaining (A) a problem caused by variation in threshold voltage V _th of a drive transistor and (B) explaining a problem caused by variation in mobility μ of the drive transistor. It is explanatory drawing about the influence of the charge injection at the time of OFF of a sampling switch, and clock feedthrough. FIG. 3 is a circuit diagram illustrating a circuit configuration of a signal line driving circuit according to the first embodiment. FIG. 6 is a timing waveform chart for explaining the circuit operation of the signal line drive circuit according to the first embodiment. FIG. 6 is an operation explanatory diagram of the signal line drive circuit according to the first embodiment. It is a circuit diagram which shows the circuit structure of the signal line drive circuit which concerns on a reference example. It is a timing waveform diagram for explaining the circuit operation of the signal line drive circuit according to the reference example. It is operation | movement explanatory drawing of the signal line drive circuit which concerns on a reference example. FIG. 6 is a circuit diagram illustrating a circuit configuration of a signal line driving circuit according to a second embodiment.

Hereinafter, modes for carrying out the technology of the present disclosure (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The present disclosure is not limited to the embodiments. In the following description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted. The description will be given in the following order.
1. 1. Description of drive circuit, display device, and electronic device of display device of present disclosure in general 2. Active matrix organic EL display device according to embodiments of present disclosure 2-1. System configuration 2-2. Pixel circuit 2-3. Basic circuit operation 2-4. Signal line driving circuit 2-4-1. Example 1
2-4-2. Reference example 2-4-3. Example 2
3. Electronic equipment Composition of the present disclosure

<1. Description of Display Circuit, Display Device, and Electronic Device of Display Device of Present Disclosure>
A display circuit driving circuit according to an embodiment of the present disclosure includes a planar (flat panel type) display device having a pixel array unit in which pixels are arranged in a matrix, and a signal line wired in units of pixel columns of the pixel array unit. It can be used to drive, specifically write a predetermined DC voltage on the signal line.

  Examples of the flat display device include an organic EL display device and a plasma display device that use a self-light emitting element as a light emitting element (electro-optical element) of a pixel. Among these display devices, the organic EL display device utilizes an organic material electroluminescence (EL) and converts an organic EL element that emits light when an electric field is applied to an organic thin film to a pixel light emitting element ( Used as an electro-optic element).

  The organic EL display device has the following features. That is, since the organic EL element can be driven with an applied voltage of 10 V or less, the power consumption is low. In addition, since the organic EL element is a self-luminous element, the visibility of the image is high, and the response speed is as high as several μsec, so that no afterimage is generated when displaying a moving image. The organic EL element is a current-driven electro-optical element. Examples of current-driven electro-optical elements include inorganic EL elements, LED elements, and semiconductor laser elements in addition to organic EL elements.

  A sampling switch provided for each signal line is used for writing a predetermined DC voltage to the signal line. The sampling switch also samples a signal voltage (gradation voltage, that is, a voltage corresponding to the gradation) of the video signal input following a predetermined DC voltage, and writes it to the signal line.

  An amplifier that inputs a predetermined DC voltage to the sampling switch may be connected to the input side of the sampling switch. Further, the sampling switch can have a configuration in which input nodes are commonly connected in units of a plurality of signal lines. At this time, the signal voltage of the video signal corresponding to the plurality of signal lines, that is, the plurality of pixel columns, is input to the sampling switch in time series following the predetermined DC voltage. The sampling switch samples the grayscale voltage input in time series in a time division manner and writes it to the signal line.

  When a predetermined DC voltage is written to the signal line by sampling by the sampling switch, the potential of the input node / output node of the sampling switch tends to be fluctuated due to the influence of charge injection and clock feedthrough when the sampling switch is switched.

  Here, “charge injection” means that when the sampling switch is composed of a MOS transistor, the charge charged in the gate oxide film moves to the input node side and the output node side when the polarity of the gate voltage is reversed. This refers to a phenomenon (transient error factor) in which the transmitted voltage fluctuates. “Clock feedthrough” means that when the sampling switch is turned on / off, the gate voltage is the potential of the input node / output node due to the parasitic capacitance that exists between the gate and drain of the MOS transistor. A phenomenon that affects

  In order to absorb the influence of the charge injection and clock feedthrough, that is, to absorb the fluctuation of the potential of the input node of the sampling switch, the driving circuit of the present disclosure has a configuration in which a capacitive element is connected to the input node of the sampling switch. It has become. The capacitor can be provided for each signal line. Further, when adopting a configuration in which the input nodes of the sampling switch are commonly connected in units of a plurality of signal lines, one capacitive element is connected to the commonly connected input nodes, that is, a plurality of signal lines. It can be set as the structure which provides one with respect to. Further, a capacitor element can be provided also at the output node of the sampling switch.

  The sampling switch can be an analog switch (transfer switch) in which a P-channel MOS transistor and an N-channel MOS transistor are connected in parallel. At this time, a MOS capacitor is preferably used as the capacitor. The MOS capacitor is connected between a transmission line for transmitting selection pulses having opposite phases to the gate electrodes of the P-channel MOS transistor and the N-channel MOS transistor constituting the sampling switch and the input node of the sampling switch. Used.

  The MOS capacitor operates in the opposite phase to the sampling switch composed of the P-channel MOS transistor and the N-channel MOS transistor, thereby absorbing the fluctuation of the potential at the input node of the sampling switch. As for the size of the MOS capacitor, it is preferable that the area of the gate electrode is approximately half of each gate electrode of the P-channel MOS transistor and the N-channel MOS transistor constituting the sampling switch. Here, “half” includes not only exactly half but also substantially half. The presence of various variations in design or manufacturing is allowed.

  In the display device using the driving circuit of the present disclosure, the pixel includes a driving transistor that drives the electro-optic element, a writing transistor connected between the signal line and the gate electrode of the driving transistor, and a gate electrode of the driving transistor. At least a storage capacitor connected between the source / drain electrodes.

  The pixel having the above configuration has a function of correcting the characteristic variation of the elements constituting the pixel, specifically, threshold correction for correcting the variation of the threshold voltage of the driving transistor for each pixel due to a variation in manufacturing process or a change with time. Has function. In the threshold correction process, a predetermined DC voltage sampled by the sampling switch and written to the signal line can be used as a reference voltage for the correction process.

  Specifically, a predetermined DC voltage sampled by the sampling switch and held on the signal line is written (taken in) into the pixel by the writing transistor and applied to the gate electrode of the driving transistor. The DC voltage written at this time becomes an initialization voltage of the gate voltage of the driving transistor. The process of changing the source voltage of the driving transistor toward the voltage obtained by subtracting the threshold voltage of the driving transistor from the initializing voltage with reference to the initializing voltage results in variation in the threshold voltage of the driving transistor for each pixel. This is a threshold correction process for correction.

<2. Active Matrix Organic EL Display Device According to Embodiment of Present Disclosure>
[2-1. System configuration]
FIG. 1 is a system configuration diagram illustrating an outline of a configuration of an active matrix organic EL display device according to an embodiment of the present disclosure.

  The active matrix display device is a display device that controls the current flowing through the electro-optical element by an active element provided in the same pixel as the electro-optical element, for example, an insulated gate field effect transistor. As the insulated gate field effect transistor, a TFT (Thin Film Transistor) is typically used.

  Here, as an example, an active matrix organic EL display that uses, for example, an organic EL element, which is a current-driven electro-optical element whose emission luminance changes according to a current value flowing through the device, as a light emitting element of a pixel (pixel circuit) The case of the apparatus will be described as an example.

  As shown in FIG. 1, the organic EL display device 10 according to the present embodiment includes a pixel array unit 30 in which a plurality of pixels 20 including organic EL elements are two-dimensionally arranged in a matrix, and the pixel array unit 30. And a drive circuit portion disposed in the periphery.

  The drive circuit unit includes a write scan circuit 40, a power supply scan circuit 50, a signal line drive circuit 60, and the like, and drives each pixel 20 of the pixel array unit 30. These circuit units 40, 50, 60 are supplied with various timing signals from a timing signal generation unit (timing generator) (not shown). The signal line drive circuit 60 is a drive circuit according to the present disclosure.

  An active element or the like constituting the pixel 20 is formed on a semiconductor substrate 70 such as a silicon substrate, for example. The write scanning circuit 40, the power supply scanning circuit 50, the signal line driving circuit 60, and the like can be formed on the same semiconductor substrate 70 as the pixel array unit 30 as shown in FIG. It can also be provided as an external circuit.

  In addition, although the case where the form which forms the active element etc. which comprise the pixel 20 on the semiconductor substrate 70 was taken as an example here was taken as an example, it is made to take the form formed on transparent insulating substrates, such as a glass substrate. Is also possible.

  Here, when the organic EL display device 10 supports color display, one pixel (unit pixel) which is a unit for forming a color image is composed of a plurality of sub-pixels (sub-pixels), and each of the sub-pixels is This corresponds to the pixel 20 in FIG. More specifically, in a display device that supports color display, one pixel includes, for example, a sub-pixel that emits red (Red) light, a sub-pixel that emits green (G) light, and blue (Blue). B) It is composed of three sub-pixels of sub-pixels that emit light.

  However, one pixel is not limited to a combination of RGB three primary color subpixels, and one pixel may be configured by adding one or more color subpixels to the three primary color subpixels. Is possible. More specifically, for example, one pixel is formed by adding a sub-pixel that emits white (W) light to improve luminance, or at least emits complementary color light to expand the color reproduction range. It is also possible to configure one pixel by adding one subpixel.

The pixel array unit 30 includes scanning lines 31 _{1 to} 31 _m and power supply lines 32 _{1 to} 32 _m along the row direction (the arrangement direction of the pixels in the pixel row) with respect to the arrangement of the pixels 20 in m rows and n columns. Are wired for each pixel row. Furthermore, signal lines 33 _{1 to} 33 _n are wired for each pixel column along the column direction (pixel arrangement direction of the pixel column) with respect to the arrangement of the pixels 20 in the m rows and the n columns.

The scanning lines 31 _{1 to} 31 _m are connected to the output ends of the corresponding rows of the writing scanning circuit 40, respectively. The power supply lines 32 _{1 to} 32 _m are connected to the output ends of the corresponding rows of the power supply scanning circuit 50, respectively. The signal lines 33 _{1 to} 33 _n are connected to the output ends of the corresponding columns of the signal line drive circuit 60, respectively.

The write scanning circuit 40 is configured by a shift register circuit that sequentially shifts (transfers) the start pulse sp in synchronization with the clock pulse ck. Writing scanning circuit 40, upon a write signal voltage of a video signal to each pixel 20 of the pixel array unit 30, the writing scanning signal WS to the scanning lines 31 (31 ₁ ~31 _m) a (WS ₁ to WS _m) By sequentially supplying the pixels 20, the pixels 20 of the pixel array unit 30 are sequentially scanned (line sequential scanning) in units of rows.

The power supply scanning circuit 50 includes a shift register circuit that sequentially shifts the start pulse sp in synchronization with the clock pulse ck. Power supply scanning circuit 50, in synchronization with the line sequential scanning by the writing scanning circuit 40, capable of a power supply potential switchable to be lower than the first power supply potential V _{cc - H} and the first power supply potential V _{cc - H} second supply potential V _{cc - L} DS (DS ₁ ~DS _m) to be supplied to the power supply line 32 (32 ₁ ~32 _m). As will be described later, light emission / non-light emission (extinction) of the pixel 20 is controlled by switching the power supply potential DS to V _{cc — H} / V _{cc — L.}

The signal line driving circuit 60 is a driving circuit according to the present disclosure, and is a signal voltage of a video signal supplied from a signal supply source (not shown) (hereinafter may be simply referred to as “signal voltage”) V _sig. And a reference voltage V _ofst that is a predetermined DC voltage are selectively written to the signal lines 33 _{1 to} 33 _n . Here, the signal voltage V _sig is a voltage (that is, a gradation voltage) corresponding to the gradation (luminance information). The reference voltage V _ofst is a voltage that _{serves as} a reference for the signal voltage V _sig of the video signal (for example, a voltage corresponding to the black level of the video signal), and is used in threshold correction processing described later.

  A specific circuit configuration of the signal line driving circuit 60 is a feature of the present disclosure, and details thereof will be described later.

The signal voltage V _sig / reference voltage V _ofst of the video signal output from the signal line drive circuit 60, the signal line 33 (33 ₁ ~33 _n) pixels 20 of the pixel array section 30 via the write scan Writing is performed in units of pixel rows selected by scanning by the circuit 40. That is, the signal line driving circuit 60 adopts a line sequential writing driving form in which the signal voltage V _sig is written in units of rows (lines).

[2-2. Pixel circuit]
FIG. 2 is a circuit diagram illustrating an example of a specific circuit configuration of the pixel (pixel circuit) 20. The light-emitting portion of the pixel 20 includes an organic EL element 21 that is a current-driven electro-optical element whose emission luminance changes according to the value of a current flowing through the device.

  As shown in FIG. 2, the pixel 20 includes an organic EL element 21 and a drive circuit that drives the organic EL element 21 by passing a current through the organic EL element 21. The organic EL element 21 has a cathode electrode connected to a common power supply line 34 that is wired in common to all the pixels 20.

  The drive circuit that drives the organic EL element 21 has, for example, a drive transistor 22, a write transistor 23, and a storage capacitor 24. N-channel TFTs can be used as the driving transistor 22 and the writing transistor 23. However, the combination of the conductivity types of the drive transistor 22 and the write transistor 23 shown here is merely an example, and is not limited to these combinations.

The drive transistor 22 has one electrode (source / drain electrode) connected to the anode electrode of the organic EL element 21 and the other electrode (source / drain electrode) connected to the power supply line 32 (32 _{1 to} 32 _m ). ing.

In the write transistor 23, one electrode (source / drain electrode) is connected to the signal line 33 (33 _{1 to} 33 _n ), and the other electrode (source / drain electrode) is connected to the gate electrode of the drive transistor 22. . The gate electrode of the writing transistor 23 is connected to the scanning line 31 (31 _{1 to} 31 _m ).

  In the driving transistor 22 and the writing transistor 23, one electrode refers to a metal wiring electrically connected to one source / drain region, and the other electrode is electrically connected to the other source / drain region. Say the metal wiring. Further, depending on the potential relationship between one electrode and the other electrode, if one electrode becomes a source electrode, it becomes a drain electrode, and if the other electrode also becomes a drain electrode, it becomes a source electrode.

  The storage capacitor 24 has one electrode connected to the gate electrode of the drive transistor 22, and the other electrode connected to the other electrode of the drive transistor 22 and the anode electrode of the organic EL element 21.

  The drive circuit of the organic EL element 21 is not limited to a circuit configuration including two transistors, the drive transistor 22 and the write transistor 23, and one capacitive element of the storage capacitor 24. As an example, a circuit in which one electrode is connected to the anode electrode of the organic EL element 21 and the other electrode is connected to a fixed potential, so that an auxiliary capacitor is provided as necessary to compensate for the insufficient capacity of the organic EL element 21 It is also possible to adopt a configuration.

In the pixel 20 configured as described above, the writing transistor 23 becomes conductive in response to a high active writing scanning signal WS applied to the gate electrode from the writing scanning circuit 40 through the scanning line 31. As a result, the write transistor 23 samples the signal voltage V _sig or the reference voltage V _ofst of the video signal supplied from the signal line driving circuit 60 through the signal line 33 and writes it into the pixel 20 (captures it). ). The signal voltage V _sig or the reference voltage V _ofst written by the write transistor 23 is applied to the gate electrode of the drive transistor 22 and held in the holding capacitor 24.

When the power supply potential DS of the power supply line 32 (32 _{1 to} 32 _m ) is at the first power supply potential _{Vcc_H} , the drive transistor 22 has one electrode as a drain electrode and the other electrode as a source electrode in a saturation region. Operate. As a result, the drive transistor 22 is supplied with current from the power supply line 32 and drives the organic EL element 21 to emit light by current drive. More specifically, the drive transistor 22 operates in the saturation region, thereby supplying the organic EL element 21 with a drive current having a current value corresponding to the voltage value of the signal voltage V _sig held in the storage capacitor 24. The organic EL element 21 is caused to emit light by current driving.

Further, when the power supply potential DS is switched from the first power supply potential _{Vcc_H} to the second power supply potential _{Vcc_L} , the drive transistor 22 operates as a switching transistor with one electrode serving as a source electrode and the other electrode serving as a drain electrode. As a result, the drive transistor 22 stops supplying the drive current to the organic EL element 21 and puts the organic EL element 21 into a non-light emitting state. That is, the drive transistor 22 also has a function as a transistor that controls light emission / non-light emission of the organic EL element 21.

  By the switching operation of the drive transistor 22, a period during which the organic EL element 21 is in a non-light emitting state (non-light emitting period) is provided, and the ratio (duty) of the light emitting period and the non-light emitting period of the organic EL element 21 can be controlled. . This duty control can reduce the afterimage blur caused by the light emission of the pixels over one display frame period, so that the quality of moving images can be particularly improved.

Of the first and second power supply potentials _{Vcc_H} and _{Vcc_L} selectively supplied from the power supply scanning circuit 50 through the power supply line 32, the first power supply potential _{Vcc_H} is a drive current for driving the organic EL element 21 to emit light. The power supply potential is supplied to the driving transistor 22. The second power supply potential V _{cc_L} is a power supply potential for applying a reverse bias to the organic EL element 21. The second power supply potential V _{cc — L} is lower than the reference voltage V _ofst , for example, lower than V _ofst −V _th when the threshold voltage of the driving transistor 22 is V _th , preferably V _ofst −V _th. Is set to a sufficiently lower potential.

[2-3. Basic circuit operation]
Next, a basic circuit operation of the organic EL display device 10 having the above configuration will be described with reference to a timing waveform diagram of FIG. The timing waveform chart of FIG. 3, the writing scanning signal WS, the power supply potential _{DS (V cc_H / V cc_L)} , the potential of the signal line _{33 (V sig / V ofst)} , gate potential V _g and the source potential V of the drive transistor 22 Each change of _s is shown.

(Light emission period of the previous display frame)
In the timing waveform diagram of FIG. 3, the time before time t ₁₁ is the light emission period of the organic EL element 21 in the previous display frame. During the light emission period of the previous display frame, the potential DS of the power supply line 32 is at the first power supply potential (hereinafter referred to as “high potential”) _{Vcc_H} , and the writing transistor 23 is in a non-conduction state.

At this time, the drive transistor 22 is set to operate in a saturation region. As a result, a drive current (drain-source current) I _ds corresponding to the gate-source voltage V _gs of the drive transistor 22 is supplied from the power supply line 32 to the organic EL element 21 through the drive transistor 22. Accordingly, the organic EL element 21 emits light with a luminance corresponding to the current value of the drive current I _ds .

(Initialization period)
At time t _11, it enters a new display frame of line sequential scanning (current display frame). Then, the second power supply potential (hereinafter referred to as “low potential”) in which the potential DS of the power supply line 32 is sufficiently lower than V _ofst −V _{th with} respect to the reference voltage V _ofst of the signal line 33 from the high potential _{Vcc_H. Switch} to _{Vcc_L} .

Here, the threshold voltage of the organic EL element 21 is V _thel , and the potential (cathode potential) of the common power supply line 34 is V _cath . At this time, if the low potential V _{cc_L} is V _{cc_L} <V _thel + V _cath , the source potential V _s of the drive transistor 22 becomes substantially equal to the low potential V _{cc_L} , so that the organic EL element 21 is in a reverse bias state and extinguished. To do.

Next, at time t ₁₂ , the potential WS of the scanning line 31 changes from the low potential side to the high potential side, so that the writing transistor 23 becomes conductive. At this time, since the reference voltage V _ofst is supplied from the signal line driving circuit 60 to the signal line 33, the gate potential V _g of the driving transistor 22 becomes the reference voltage V _ofst . The source potential V _s of the drive transistor 22 is at a potential sufficiently lower than the reference voltage V _ofst , that is, the low potential V _{cc_L} .

At this time, the gate-source voltage V _gs of the driving transistor 22 becomes (V _ofst −V _{cc — L} ). Here, _unless (V _ofst −V _{cc_L} ) is larger than the threshold voltage V _th of the drive transistor 22, threshold correction processing described later cannot be performed, and therefore, a potential relationship of V _ofst −V _{cc_L} > V _th is set. There is a need to.

Thus, the _process of fixing the gate potential V _g of the drive transistor 22 to the reference voltage V _ofst and fixing (determining) the source potential V _s to the low potential V _{cc_L} is a threshold correction process (threshold correction) described later. This is an initialization process before performing (operation). Therefore, the reference voltage V _ofst and the low potential V _{cc_L} become the initialization potentials of the gate potential V _g and the source potential V _s of the driving transistor 22.

(Threshold correction period)
Next, when the potential DS of the power supply line 32 is switched from the low potential V _{cc_L} to the high potential V _{cc_H} at time t ₁₃ , threshold correction is performed in a state where the gate potential V _g of the driving transistor 22 is maintained at the reference voltage V _ofst. Processing begins. That is, the source potential V _s of the drive transistor 22 starts to increase toward the potential obtained by subtracting the threshold voltage V _th of the drive transistor 22 from the gate potential V _g .

For convenience, the initialization potential V _ofst the gate potential V _g of the driving transistor 22 as a reference, the source potential V _s towards the potential obtained by subtracting the threshold voltage V _th of the drive transistor 22 from the initialization potential V _ofst The changing process is called a threshold correction process. As the threshold correction process proceeds, the gate-source voltage V _gs of the drive transistor 22 eventually converges to the threshold voltage V _th of the drive transistor 22. A voltage corresponding to the threshold voltage V _th is held in the holding capacitor 24.

In the period for performing the threshold correction process (threshold correction period), the organic EL element 21 is cut off in order to prevent current from flowing exclusively to the storage capacitor 24 side and not to the organic EL element 21 side. As described above, the potential V _cath of the common power supply line 34 is set.

Next, at time t ₁₄ , the write scan signal WS transitions to the low potential side, so that the write transistor 23 is turned off. At this time, the gate electrode of the driving transistor 22 is electrically disconnected from the signal line 33 to be in a floating state. However, since the gate-source voltage V _gs is equal to the threshold voltage V _th of the drive transistor 22, the drive transistor 22 is in a cutoff state. Accordingly, the drain-source current I _ds does not flow through the driving transistor 22.

(Signal writing & mobility correction period)
Next, at time t ₁₅ , the potential of the signal line 33 is switched from the reference voltage V _ofst to the signal voltage V _sig of the video signal. Subsequently, at time t ₁₆ , the write scan signal WS transitions to the high potential side, whereby the write transistor 23 becomes conductive, and the signal voltage V _sig of the video signal is sampled and written into the pixel 20.

By writing the signal voltage V _sig by the writing transistor 23, the gate potential V _g of the driving transistor 22 becomes the signal voltage V _sig . When the drive transistor 22 is driven by the signal voltage V _sig of the video signal, the threshold voltage V _th of the drive transistor 22 is canceled with the voltage corresponding to the threshold voltage V _th held in the holding capacitor 24. Details of the principle of threshold cancellation will be described later.

At this time, the organic EL element 21 is in a cutoff state (high impedance state). Therefore, the current (drain-source current I _ds ) flowing from the power supply line 32 to the drive transistor 22 in accordance with the signal voltage V _sig of the video signal flows into the equivalent capacitance of the organic EL element 21. Thereby, charging of the equivalent capacity of the organic EL element 21 is started.

As the equivalent capacitance of the organic EL element 21 is charged, the source potential V _s of the drive transistor 22 rises with time. At this time, the pixel-to-pixel variation of the threshold voltage V _th of the drive transistor 22 has already been canceled, and the drain-source current I _ds of the drive transistor 22 depends on the mobility μ of the drive transistor 22. . Note that the mobility μ of the drive transistor 22 is the mobility of the semiconductor thin film constituting the channel of the drive transistor 22.

Here, it is assumed that the ratio of the holding voltage V _gs of the holding capacitor 24 to the signal voltage V _sig of the video signal, that is, the write gain G is 1 (ideal value). Then, the source potential V _s of the drive transistor 22 rises to the potential of (V _ofst −V _th + ΔV), and the gate-source voltage V _gs of the drive transistor 22 is (V _sig −V _ofst + V _th −ΔV). It becomes.

That is, the increase ΔV of the source potential Vs of the driving transistor 22 is subtracted from the voltage (V _sig −V _ofst + V _th ) held in the holding capacitor 24, in other words, the charge stored in the holding capacitor 24 is discharged. Acts like As a result, the increase ΔV of the source potential Vs is negatively fed back to the storage capacitor 24. Therefore, the increase ΔV of the source potential V _s becomes a feedback amount of negative feedback.

Thus, the drain flowing through the driving transistor 22 - gate with the feedback amount ΔV corresponding to the source current I _ds - by applying the negative feedback to the source voltage V _gs, the drain of the driving transistor 22 - the source current I _ds The dependence on mobility μ can be negated. This canceling process is a mobility correction process for correcting the variation of the mobility μ of the driving transistor 22 for each pixel.

More specifically, since the drain-source current I _ds increases as the signal amplitude V _in (= V _sig −V _ofst ) of the video signal written to the gate electrode of the drive transistor 22 increases, the feedback amount of negative feedback The absolute value of ΔV also increases. Therefore, mobility correction processing according to the light emission luminance level is performed.

Furthermore, when a constant signal amplitude V _in of the video signal, since the greater the absolute value of the feedback amount ΔV of the mobility μ is large enough negative feedback of the drive transistor 22, to remove the variation of the mobility μ for each pixel Can do. Therefore, it can be said that the feedback amount ΔV of the negative feedback is a correction amount of the mobility correction process. Details of the principle of mobility correction will be described later.

(Light emission period)
Next, at time t ₁₇ , the write scan signal WS is shifted to the low potential side, so that the write transistor 23 is turned off. As a result, the gate electrode of the driving transistor 22 is electrically disconnected from the signal line 33 and is in a floating state.

Here, when the gate electrode of the driving transistor 22 is in a floating state, the storage capacitor 24 is connected between the gate and the source of the driving transistor 22, so that the driving transistor 22 is interlocked with the variation of the source potential V _s. Thus, the gate potential V _g also varies. That is, the source potential V _s and the gate potential V _g of the drive transistor 22 rise while holding the gate-source voltage V _gs held in the holding capacitor 24. Then, the source potential V _s of the driving transistor 22 rises to the light emission voltage V _oled of the organic EL element 21 corresponding to the saturation current I _{ds of the} transistor.

Thus, the operation in which the gate potential V _g of the drive transistor 22 varies in conjunction with the variation in the source potential V _s is a bootstrap operation. In other words, in the bootstrap operation, the gate potential V _g and the source potential V _s change while holding the gate-source voltage V _gs held in the holding capacitor 24, that is, the voltage across the holding capacitor 24. Is the action.

The gate electrode of the drive transistor 22 is in a floating state, and at the same time, the drain-source current I _{ds of the} drive transistor 22 starts to flow through the organic EL element 21, so that the anode of the organic EL element 21 corresponds to the current I _ds. The potential increases. When the anode potential of the organic EL element 21 exceeds (V _thel + V _cath ), the drive current starts to flow through the organic EL element 21, so that the organic EL element 21 starts to emit light.

The light emission current of the organic EL element 21 is defined by the saturation current I _ds of the drive transistor 22 by the gate-source voltage V _{gs at} this time. For this reason, the drive transistor 22 becomes a constant current source at each signal voltage V _sig .

The increase in the anode potential of the organic EL element 21 is none other than the increase in the source potential V _s of the drive transistor 22. When the source potential V _s of the driving transistor 22 rises, the gate potential V _g of the driving transistor 22 also rises in conjunction with the bootstrap operation of the storage capacitor 24.

At this time, when it is assumed that the bootstrap gain is 1 (ideal value), the increase amount of the gate potential V _g becomes equal to the increase amount of the source potential V _s . Therefore, during the light emission period, the gate-source voltage V _gs of the driving transistor 22 is kept constant at (V _sig −V _ofst + V _th −ΔV).

In the series of circuit operations described above, each processing operation of threshold correction preparation, threshold correction, signal voltage V _sig writing (signal writing), and mobility correction is executed in one horizontal period (1H). Further, the processing operations of the signal writing and mobility correction are parallel executed during the period of time t ₁₆ -t _17.

[Division threshold correction]
Here, the case where the driving method in which the threshold value correction process is executed only once is described as an example, but this driving method is only an example and is not limited to this driving method. For example, in addition to the 1H period in which the threshold correction process is performed together with the mobility correction and the signal writing process, the threshold correction process is executed a plurality of times by dividing it over a plurality of horizontal periods preceding the 1H period. It is also possible to adopt a driving method for performing correction.

  According to this division threshold correction driving method, sufficient time is secured over a plurality of horizontal periods as a threshold correction period even if the time allocated as one horizontal period is shortened due to the increase in the number of pixels accompanying high definition. can do. Therefore, even if the time allocated as one horizontal period is shortened, a sufficient time can be secured as the threshold correction period, so that the threshold correction process can be reliably executed.

[Principle of threshold cancellation]
Here, the principle of threshold cancellation (that is, threshold correction) of the drive transistor 22 will be described. The drive transistor 22 operates as a constant current source because it is designed to operate in the saturation region. As a result, the organic EL element 21 is supplied with a constant drain-source current (drive current) I _ds given by the following equation (1) from the drive transistor 22.
I _ds = (1/2) · μ (W / L) C _ox (V _gs −V _th ) ² (1)
Here, W is the channel width of the driving transistor 22, L is the channel length, and C _ox is the gate capacitance per unit area.

FIG. 4A shows the characteristics of the drain-source current I _ds versus the gate-source voltage V _gs of the driving transistor 22. As shown in the characteristic diagram of FIG. 4A, when the cancel process (correction process) for the variation of the threshold voltage V _th of the driving transistor 22 for each pixel is not performed, the gate is obtained when the threshold voltage V _th is V _th1. - a drain corresponding to the source voltage V _gs - source current I _ds becomes I _ds1.

On the other hand, when the threshold voltage V _th is _{V th2 (V th2> V th1} ), the same gate - drain corresponding to the source voltage V _gs - source current I _{ds I ds2 (I ds2 <I ds1} ) become. That is, when the threshold voltage V _th of the drive transistor 22 varies, the drain-source current I _ds varies even if the gate-source voltage V _gs is constant.

On the other hand, in the pixel (pixel circuit) 20 having the above configuration, as described above, the gate-source voltage V _gs of the driving transistor 22 at the time of light emission is V _sig −V _ofst + V _th −ΔV. Therefore, when this is substituted into the equation (1), the drain-source current I _ds is expressed by the following equation (2).
I _ds = (1/2) · μ (W / L) C _ox (V _sig −V _ofst −ΔV) ² (2)

That is, the term of the threshold voltage V _th of the drive transistor 22 is canceled, and the drain-source current I _ds supplied from the drive transistor 22 to the organic EL element 21 does not depend on the threshold voltage V _th of the drive transistor 22. . As a result, even if the threshold voltage V _th of the drive transistor 22 varies from pixel to pixel due to variations in the manufacturing process of the drive transistor 22 and changes over time, the drain-source current I _ds does not vary. 21 emission luminance can be kept constant.

[Principle of mobility correction]
Next, the principle of mobility correction of the drive transistor 22 will be described. FIG. 4B shows a characteristic curve in a state where a pixel A having a relatively high mobility μ of the driving transistor 22 and a pixel B having a relatively low mobility μ of the driving transistor 22 are compared.

With the mobility μ varying between the pixel A and the pixel B, for example, the signal amplitude V _in (= V _sig −V _ofst ) of the same level is written to both the pixels A and B to the gate electrode of the drive transistor 22. Consider the case. In this case, if no not corrected mobility mu, drain flows to the pixel A having the high mobility mu - source current I _ds1 'and the drain flowing through the pixel B having the low mobility mu - source current I _ds2' and There will be a big difference between the two. As described above, when a large difference occurs between the pixels in the drain-source current I _ds due to the variation of the mobility μ from pixel to pixel, the uniformity of the screen is impaired.

Here, as is clear from the transistor characteristic equation of the equation (1) described above, the drain-source current I _ds increases when the mobility μ is large. Therefore, the feedback amount ΔV in the negative feedback increases as the mobility μ increases. As shown in FIG. 4B, the feedback amount ΔV ₁ of the pixel A having the high mobility μ is larger than the feedback amount ΔV ₂ of the pixel B having the low mobility μ.

Therefore, negative feedback is increased as the mobility μ is increased by applying negative feedback to the gate-source voltage V _gs with a feedback amount ΔV corresponding to the drain-source current I _ds of the driving transistor 22 by mobility correction processing. It will take. As a result, variation in mobility μ for each pixel can be suppressed.

Specifically, when applying a correction of the feedback amount [Delta] V ₁ at the pixel A having the high mobility mu, drain - source current I _ds larger drops from I _ds1 'to I _ds1. On the other hand, since the feedback amount [Delta] V ₂ small pixels B mobility μ is small, the drain - source current I _ds becomes lowered from I _ds2 'to I _ds2, not lowered so much. Consequently, the drain of the pixel A - drain-source current I _ds1 and the pixel B - to become nearly equal to the source current I _ds2, variations among the pixels of the mobility μ is corrected.

In summary, when there are a pixel A and a pixel B having different mobility μ, the feedback amount ΔV ₁ of the pixel A having a high mobility μ is larger than the feedback amount ΔV ₂ of the pixel B having a low mobility μ. . That is, the larger the mobility μ, the larger the feedback amount ΔV, and the larger the amount of decrease in the drain-source current I _ds .

Therefore, the drain of the driving transistor 22 - with the feedback amount ΔV corresponding to the source current I _ds, the gate - by applying the negative feedback to the source voltage V _gs, the drain of pixels having different mobilities mu - source current I _ds The current value is made uniform. As a result, variation in mobility μ for each pixel can be corrected. That is, the feedback amount (correction amount) ΔV corresponding to the current flowing through the drive transistor 22 (drain-source current I _ds ) with respect to the gate-source voltage V _gs of the drive transistor 22, that is, the storage capacitor 24. On the other hand, the process of applying negative feedback is the mobility correction process.

[2-4. Signal line driver circuit]
The signal line drive circuit 60 according to the embodiment, which is a drive circuit according to the present disclosure, uses a sampling line to sample a reference voltage V _ofst and a signal voltage (grayscale voltage) V _sig that are sequentially input from a signal supply source. 33 (33 _{1 to} 33 _n ) is written. At the time of writing, charge injection and clock feedthrough at the time of switching of the sampling switch adversely affect the writing operation of the reference voltage V _ofst .

  Here, for ease of understanding, the case where the sampling switch SW is composed of an N-channel MOS transistor is taken as an example, and the effects of charge injection and clock feedthrough when the sampling switch SW is switched, particularly when the sampling switch SW is turned off, are illustrated in FIG. 5 will be described.

In FIG. 5, a sampling and holding circuit is formed by the sampling switch SW and the load capacitor C. The load capacitance C is a parasitic capacitance of the signal line 33 (33 _{1 to} 33 _n ). In this sample and hold circuit, the voltage sampled by the sampling switch SW is written and held in the signal line 33 at the off timing (that is, hold timing) of the sampling switch SW.

Here, the voltage value of the input signal of the sampling switch SW is V _in , the positive voltage value of the control pulse (selection pulse) EN applied to the gate electrode is V _dd , and the negative voltage value is 0. The channel length of the N-channel MOS transistor is L, the channel width is W, the threshold voltage is V _th , the gate oxide film capacitance is C _ox , and the overlap capacitance is C _ov . The overlap capacitance _Cov is a parasitic capacitance that exists in a region where the gate electrode overlaps with the source region and the drain region.

When the sampling switch SW is turned off, that is, when the control pulse EN transitions from V _dd to 0, the potential fluctuation amount ΔV _ch due to the influence of charge injection is
ΔV _ch = 1/2 × W · L · C _ox (V _dd −V _in −V _th ) / C
It becomes. Also, the potential fluctuation amount ΔV _cl due to the influence of clock feedthrough is
ΔV _cl = V _dd × C _ov / (C _ov + C)
It becomes.

When the potential of the input node of the sampling switch SW fluctuates (fluctuation amount ΔV _ch / ΔV _cl ) due to the influence of charge injection or clock feedthrough when the sampling switch SW is turned off, the reference voltage V _ofst having a desired voltage value is applied to the signal line. 33 will not be able to write. As described above, since the reference voltage V _ofst is a reference voltage for threshold correction processing, the fact that the reference voltage V _ofst having a desired voltage value cannot be written to the signal line 33 means that the threshold correction processing is executed normally. It will be impossible.

  The drive circuit of the present disclosure is a signal line drive circuit that is designed to eliminate problems caused by the effects of charge injection and clock feedthrough when the sampling switch is switched, particularly when the sampling switch is turned off, on the input node side of the sampling switch. is there. Specific examples of the drive circuit according to the present disclosure will be described below.

(2-4-1. Example 1)
FIG. 6 is a circuit diagram illustrating a circuit configuration of the signal line driving circuit according to the first embodiment.

In FIG. 6, the signal line driving circuit 60 _{A according} to the first embodiment uses the i signal lines 33 _{1 to} 33 _i as a unit for the _n signal lines 33 _{1 to} 33 _n in the pixel array unit 30 illustrated in FIG. 1. As shown, the input voltage is applied from the amplifier 61. Here, for simplification of the drawing, a circuit configuration corresponding to _i signal lines 33 _{1 to} 33 _i is illustrated.

The input voltage _supplied from the amplifier 61 is a reference voltage V _ofst which is a predetermined DC voltage, and a signal voltage (grayscale voltage) V _sig for i columns input in time series following the reference voltage V _ofst. . For example, a DA converter (not shown) that converts a digital signal into an analog signal is disposed on the front stage side of the amplifier 61, and the output DAC _{out of the} DA converter is connected to the non-inverting (+) input terminal of the amplifier 61. Entered.

DA converter constitutes a signal source for supplying a reference voltage V _ofst and the signal voltage V _sig to the signal line drive circuit 60 _A. The amplifier 61 has an inverting (−) input terminal and an output terminal electrically connected to each other, and constitutes an output stage of a signal supply source including a DA converter.

Generally, a signal supply source is provided with a one-to-one correspondence with each of the _n signal lines 33 _{1 to} 33 _n of the pixel array unit 30. On the other hand, by providing signal supply sources in units of _i signal lines 33 _{1 to} 33 _i as in this signal line drive circuit 60 _A , the number of signal supply sources, that is, DA converters and amplifiers 61 can be reduced. Since it can be greatly reduced, there is an advantage that the circuit configuration of the system can be simplified.

Signal line drive circuit 60 _A includes a sampling switch 62 ₁ through 62 _i provided for each i of signal lines 33 ₁ ~ 33 _i. The sampling switches 62 _{1 to} 62 _i form a sample and hold circuit together with the parasitic capacitances of the signal lines 33 _{1 to} 33 _i , sample the reference voltage V _ofst input from the amplifier 61 all at once, and turn off timing (hold timing) To hold on the signal lines 33 _{1 to} 33 _i . Further, the sampling switches 62 _{1 to} 62 _i sample the signal voltage V _sig input in time series from the amplifier 61 following the reference voltage V _ofst in a time division manner, and sequentially write the signal voltages to the signal lines 33 _{1 to} 33 _i .

The sampling switches 62 _{1 to} 62 _i are constituted by, for example, analog switches (transfer switches) in which a P channel MOS transistor and an N channel MOS transistor are connected in parallel. The sampling switches 62 _{1 to} 62 _i perform the switching operation (on / off operation) in accordance with the selection pulses SEL and xSEL (SEL _{1 to} SEL _i , xSEL _{1 to} xSEL _i ) having mutually opposite phases. Sample and hold V _ofst / signal voltage V _sig .

Positive phase of the selection pulse SEL (SEL ₁ ~SEL _i) is transmitted by the transmission line L _a (L _a1 ~L _ai) to the gate electrode of the N-channel MOS transistors constituting the sampling switch 62 ₁ through 62 _i . The reverse-phase selection pulses xSEL (xSEL _{1 to} xSEL _i ) are transmitted by the transmission line L _b (L _{b1 to} L _bi ) to the gate electrodes of the P-channel MOS transistors constituting the sampling switches 62 _{1 to} 62 _i. .

A sampling switch 62 ₁ through 62 _i of the input nodes _{N in (N in_1 ~N in_i)} , the transmission line _{L a (L a1 ~L ai)} , L b between the (L _b1 ~L _bi), capacitive element 63 (63 _{1 to} 63 _i ) are connected. The capacitive elements 63 _{1 to} 63 _i are composed of, for example, MOS capacitors. Specifically, the capacitive element 63 ₁ to 63 _i has a P-channel MOS transistor connected between the transmission line L _a and the input node N _in the sampling switches 62 ₁ through 62 _i, the sampling switches 62 ₁ - 62 _i includes an N-channel MOS transistor connected between each input node N _in of 62 _i and the transmission line L _b . The transistor size of the capacitive elements 63 _{1 to} 63 _i is roughly a gate area of the transistors constituting the sampling switches 62 _{1 to} 62 _i .

A sampling switch 62 ₁ through 62 _i of the output node _{N out (N out_1 ~N out_i)} , the transmission line _{L a (L a1 ~L ai)} , L b between the (L _b1 ~L _bi), capacitive element 64 (64 ₁ to 64 _i ) are connected. The capacitive elements 64 ₁ to 64 _i are also composed of MOS capacitors in the same manner as the capacitive elements 63 _{1 to} 63 _i . Specifically, the capacitive element 64 ₁ to 64 _i has a P-channel MOS transistor connected between the transmission line L _a and the output node N _out of the sampling switches 62 ₁ through 62 _i, the sampling switches 62 ₁ - 62 _i is composed of an N channel MOS transistor connected between each output node N _out of 62 _i and the transmission line L _b . As for the transistor size of the capacitive elements 64 ₁ to 64 _i , a gate area which is half that of the transistors constituting the sampling switches 62 _{1 to} 62 _i is a standard.

Next, the circuit operation of the signal line drive circuit 60 _{A according to} the first embodiment having the above configuration will be described with reference to the operation explanatory diagram of FIG. 8 using the timing waveform diagram of FIG. In the timing waveform diagram of FIG. 7, PIX _{1 to} PIX _i represent potentials of the signal lines 33 _{1 to} 33 _i . Here, the operation when the reference voltage V _ofst is _written to the i signal lines 33 _{1 to} 33 _i will be described, and the writing operation of the signal voltage V _sig will be omitted.

In order to write the reference voltage V _ofst , all sampling switches 62 _{1 to} 62 _i are turned on in response to the selection pulses SEL, xSEL (SEL _{1 to} SEL _i , xSEL _{1 to} xSEL _i ). When the writing of the reference voltage V _ofst is completed, all the sampling switches 62 _{1 to} 62 _i are turned off.

At the moment when the sampling switches 62 _{1 to} 62 _i are turned off, the potentials of the input nodes N _{in_1 to} N _{in_i} of the sampling switches 62 _{1 to} 62 _i are affected by the charge injection of the sampling switches 62 _{1 to} 62 _i and the influence of clock feedthrough. (That is, the output potential of the amplifier 61) tends to be shaken. In particular, with respect to the input node N _{IN_1} to N _{IN_i} sampling switch 62 ₁ through 62 _i, as shown by broken line arrow in FIG. 8, affect the N-channel MOS transistor portion of charge injection.

During off the sampling switch 62 ₁ through 62 _i, each input node N _{IN_1} to N _{IN_i} to a capacitor which is connected 63 ₁ to 63 _i of sampling switches 62 ₁ through 62 _i is, the sampling switches 62 ₁ through 62 _i and inverse Works on phase. Due to the action of the capacitive elements 63 _{1 to} 63 _i due to the reverse-phase operation, the influence of charge injection and clock feedthrough generated when the sampling switches 62 _{1 to} 62 _i are turned off, in other words, the input node N _{in_1} to N _{in_i} potential fluctuation is suppressed.

That is, the capacitance elements 63 _{1 to} 63 _{i absorb the fluctuations in} the potentials of the input nodes N _{in_1 to} N _{in_i} (that is, the output potential of the amplifier 61), and the input nodes N _{in_1 to} N _{in_i} have predetermined desired _values. A reference voltage V _ofst is given. As a result, as shown in the timing waveform diagram of FIG. 7, even if there is a slight deviation in the off timing (ie, hold timing) between the selection pulses SEL _{1 to} SEL _i , a desired voltage value is obtained. The reference voltage V _ofst can be written to the signal lines 33 _{1 to} 33 _i .

On the other hand, the capacitive elements 64 ₁ to 64 _i connected to the output nodes N _{out_1 to} N _{out_i} of the sampling switches 62 _{1 to} 62 _i are output nodes for charge injection and clock feedthrough when the sampling switches 62 _{1 to} 62 _i are switched. N _{out_1 to} N _{out_i} are absorbed.

In the first embodiment, the capacitive elements 63 _{1 to} 63 _i and 64 ₁ to 64 _i are provided on both sides of the input node / output node of the sampling switches 62 _{1 to} 62 _i , but this is a preferred embodiment. Thus, the capacitive elements 64 ₁ to 64 _i on the output node side are not essential components. That is, even when the capacitive elements 64 ₁ to 64 _i are not present on the output node side, at least when the capacitive elements 63 _{1 to} 63 _i are present on the input node side, the sampling switches 62 _{1 to} 62 _i are turned off. The intended purpose of suppressing the fluctuation of the potentials of the input nodes N in — _{1 to} N in — _i can be achieved.

Here, a signal line driving circuit in which the capacitive elements 64 ₁ to 64 _i are provided only on the output node side of the sampling switches 62 _{1 to} 62 _i will be described below as a signal line driving circuit according to a reference example.

(2-4-2. Reference example)
FIG. 9 is a circuit diagram illustrating a circuit configuration of a signal line driving circuit according to a reference example. As shown in FIG. 9, the signal line driving circuit 60 _B according to the reference example is provided only on the output node side of the sampling switches 62 _{1 to} 62 _i , that is, the output nodes N _{out_1 to} N _{out_i} and the transmission lines L _{a1 to} L _ai. , L _{b1 to} L _bi and capacitive elements 64 ₁ to 64 _i are connected.

FIG. 10 shows a timing waveform diagram and FIG. 11 shows an operation explanatory diagram of the signal line driving circuit 60 _{B according to} the reference example.

In the case of the signal line drive circuit 60 _{B according to} the reference example, the charge injection of N channels is performed at the timing (hold timing) when the sampling switches 62 _{1 to} 62 _i are turned off, as indicated by the dashed arrows in FIG. Influenced. As a result, the potentials of the input nodes N in — _{1 to} N in — _i (that is, the output potential of the amplifier 61) are _fluctuated as _{indicated by the circles} of _{broken lines} in FIG.

On the other hand, the sampling switches 62 ₁ through 62 _i are controlled by the selection pulse SEL ₁ to SEL _i of each independent timing. In the selection pulses SEL _{1 to} SEL _i , a slight timing shift occurs as shown in the timing waveform diagram of FIG. 10 due to variations in constants of circuit systems and transmission systems that generate these pulses. Then, the selection pulse SEL ₁ to SEL by slight timing shift timing (hold timing) at the time of off of _i, the sampling switches 62 ₁ through 62 _i by the input node N _{IN_1} to N _{IN_i} hold point signal line potential 33 ₁ shifts between ~33 _i.

As a result, as shown in the timing waveform diagram of FIG. 10, variations (ΔV _{1 to} ΔV _i ) occur in the potentials PIX _{1 to} PIN _i of the signal lines 33 _{1 to} 33 _i when the reference voltage V _ofst is written. That is, variations in the voltage value of the reference voltage V _ofst which is held on the signal line 33 ₁ ~ 33 _i between the signal lines 33 ₁ ~ 33 _i. This is because the reference voltage V _ofst having a desired voltage value cannot be sampled and held by the sampling switches 62 _{1 to} 62 _i , that is, the reference voltage V _ofst having a different voltage value is held in the signal lines 33 _{1 to} 33 _i ( It is written).

The reference voltage V _ofst is used as an initialization voltage for the gate voltage of the drive transistor 22 in the threshold correction process. Accordingly, _since the voltage value of the reference voltage V _ofst varies between the signal lines 33 _{1 to} 33 _i , the reference voltage V _ofst having a different voltage value is used in each of the first to i-th pixel columns. A threshold correction process is performed. As a result, _{variations in} the voltage value of the reference voltage V _ofst between the signal lines 33 _{1 to} 33 _i are _{visually recognized} as vertical stripes (streaks in the column direction) on the display screen. Will be invited.

Thus, the error voltage value of the reference voltage V _ofst to be written to the signal lines 33 ₁ ~ 33 _i is dependent on the operation timing of the selection pulse SEL ₁ to SEL _i for controlling the sampling switch 62 ₁ through 62 _i. In the case of the signal line driving circuit 60 _{B according to} the reference example, the image quality is not stable due to absolute variation, relative variation, temperature dependency, power supply dependency, and the like of the semiconductor chip (semiconductor substrate).

Note that the swing of the input nodes N _{IN_1} to N _{IN_i} the potential during off of the sampling switch 62 ₁ through 62 _i, can also be covered by the preceding stage of the amplifier 61 of the sampling switches 62 ₁ through 62 _i. However, when this measure is taken, it is necessary to use a very wideband amplifier, which causes a significant increase in power consumption, which is not a preferable measure.

In contrast, according to the signal line drive circuit 60 _A according to the working example 1, the sampling switch 62 ₁ through 62 _i input node side to the capacitor 63 ₁ to 63 _i disposed only simple construction and easy for the In the operation sequence, the problem of the signal line driver circuit 60 _{B according to} the reference example can be solved. That is, the reference voltage V _ofst having a desired voltage value is set to the signal lines 33 ₁ to 33 without increasing the power consumption of the amplifier 61 in the _{previous stage} and without increasing the size of the semiconductor chip (semiconductor substrate 70 in FIG. 1). 33 _i can be written. As a result, the threshold value correction process can be more reliably performed in each pixel column, and thus a display image with uniform image quality without luminance unevenness can be obtained.

(2-4-3. Example 2)
FIG. 12 is a circuit diagram illustrating the circuit configuration of the signal line driving circuit according to the second embodiment.

In the signal line driving circuit 60 according to Embodiment 1 _A, the sampling switches 62 ₁ through 62 _i input node N _{IN_1} to N _{IN_i} capacitive element 63 ₁ to 63 _i to connect to, i signal lines 33 ₁ ~ 33 _i of The structure provided for every was taken. On the other hand, the signal line drive circuit 60 _{C according to the} second embodiment employs a configuration in which one capacitor element 63 is provided for each unit of _i signal lines 33 _{1 to} 33 _i as a unit.

Specifically, in the signal line driving circuit 60 _{C according to the} second embodiment, the input nodes N _{in_1 to} N _{in_i} of the sampling switches 62 _{1 to} 62 _i are commonly used in units of _i signal lines 33 _{1 to} 33 _i. It is connected. A capacitive element 63 is connected between the commonly connected common input node N in — ₀ and, for example, the transmission lines L _a1 and L _{b1 in the} first column.

The capacitive element 63 is composed of, for example, a MOS capacitor. Specifically, the capacitive element 63 includes a P-channel MOS transistor connected between the common input node N in — ₀ of the sampling switches 62 _{1 to} 62 _i and the transmission line L _a1 , a common input node N in — ₀ and the transmission line L 1. _It consists of an N channel MOS transistor connected between _b1 . The transistor size of the capacitive element 63 is roughly a gate area of half of the transistors constituting the sampling switches 62 _{1 to} 62 _i .

Thus, according to the signal line drive circuit 60 _C according to the second embodiment that employs a configuration in which one capacitive element 63 is provided with i signal lines 33 _{1 to} 33 _i as a unit, the capacitive element 63 is connected to the signal line 33 _1. by a simple circuit configuration than the signal line driver circuit 60 _a according to the working example 1, a configuration is provided for each ~ 33 _i, it is possible to obtain similar actions and effects.

That is, when the sampling switches 62 _{1 to} 62 _i are turned off, the capacitive element 63 connected to the common input node N in — ₀ operates in a phase opposite to that of the sampling switch 62 ₁ . Due to the action of the capacitive element 63 due to the reverse-phase operation, the influence of charge injection and clock feedthrough generated when the sampling switches 62 _{1 to} 62 _i are turned off, in other words, the common input node N in — ₀ due to the influence, and the input The fluctuation of the potential of the nodes N in — _{1 to} N in — _i can be suppressed.

As a result, even if there is a _slight shift in the off timing (ie, hold timing) between the selection pulses SEL _{1 to} SEL _i , the reference voltage V _ofst of the desired voltage value is applied to the signal lines 33 ₁ to 33 ₁ . 33 _i can be written. However, in this example, since the capacitive element 63 is operated by the selection pulses SEL ₁ and xSEL _{1 in the} first column, there are selection pulses that transition at an earlier timing than the selection pulses SEL ₁ and xSEL _1. In this case, the timing shift cannot be absorbed for the pixel column of the selection pulse.

From this point of view, the selection pulse having the earliest transition timing among the selection pulses SEL _{1 to} SEL _i and xSEL _{1 to} xSEL _i corresponding to _i signal lines 33 _{1 to} 33 _i as a unit, It is preferably used as a selection pulse for operating the capacitive element 63. By doing so, even if a slight shift occurs in the hold timing, the timing shift can be absorbed for all the pixel columns.

<3. Electronic equipment>
The drive circuit of the display device of the present disclosure described above is used in electronic devices in all fields having a display unit that displays a video signal input to an electronic device or a video signal generated in the electronic device as an image or a video. It can be used as a drive circuit for the display portion (display device).

As is apparent from the description of the above-described embodiment, the display circuit driving circuit according to the present disclosure can supply the reference voltage V _ofst having a desired voltage value to the signal line with low power consumption without increasing the size of the semiconductor chip. Can be written on. Thereby, in the display device using the drive circuit, the threshold value correction process can be more reliably performed in each pixel column, and thus a display image with uniform image quality without luminance unevenness can be obtained. Therefore, in an electronic device in every field, a more excellent image display can be realized by using a display device having the drive circuit of the present disclosure as its display unit.

  Examples of the electronic device using the display device having the drive circuit of the present disclosure as a display unit include a head mounted display, a digital camera, a video camera, a PDA (Personal Digital Assistant), a portable information device such as a game machine, an electronic book, A mobile communication device such as a mobile phone can be exemplified.

<4. Configuration of the present disclosure>
In addition, this indication can take the following structures.
(1) a sampling switch that is provided for each signal line wired in units of pixel columns of a pixel array unit in which pixels are arranged in a matrix, and that samples a predetermined DC voltage input and writes the signal to the signal line;
And a capacitive element connected to the input node of the sampling switch and absorbing fluctuations in the potential of the input node caused by switching of the sampling switch.
(2) The display circuit drive circuit according to (1), wherein the sampling switch is an analog switch in which a P-channel MOS transistor and an N-channel MOS transistor are connected in parallel.
(3) The capacitor element is a MOS capacitor connected between the input node and a transmission line that transmits selection pulses having opposite phases to the gate electrodes of the P-channel MOS transistor and the N-channel MOS transistor. The drive circuit for the display device according to (2).
(4) The display device driving circuit according to (3), wherein an area of the gate electrode of the MOS capacitor is half of an area of each gate electrode of the P-channel MOS transistor and the N-channel MOS transistor.
(5) An amplifier that inputs the predetermined DC voltage to the sampling switch is connected to an input side of the sampling switch. The display device according to any one of (1) to (4), Driving circuit.
(6) The display device driving circuit according to any one of (1) to (5), wherein the sampling switch has an input node commonly connected in units of a plurality of signal lines.
(7) The display device drive circuit according to (6), wherein one capacitor element is connected to a common input node connected in common with the plurality of signal lines as a unit.
(8) Among the plurality of selection pulses for operating the plurality of sampling switches corresponding to the plurality of signal lines at independent timing, the selection pulse having the earliest transition timing is used for the operation of the capacitor element. A driving circuit of the display device.
(9) The sampling switch samples the signal voltage of the video signal input in time series following the predetermined DC voltage in a time division manner and writes the signal voltage to the signal line. A driving circuit for the display device according to claim 1.
(10) The device according to any one of (1) to (9), further including a capacitive element that is connected to an output node of the sampling switch and absorbs a fluctuation in potential of the output node caused by switching of the sampling switch. A driving circuit of a display device.
(11) The pixel includes a driving transistor for driving an electro-optic element, a writing transistor connected between the signal line and a gate electrode of the driving transistor, and a gate electrode of the driving transistor and one source / drain. The display device driving circuit according to any one of (1) to (10), further including a storage capacitor connected to an electrode.
(12) The pixel uses the gate voltage of the driving transistor when the predetermined DC voltage is written by the writing transistor as an initialization voltage, and a voltage obtained by subtracting the threshold voltage of the driving transistor from the initialization voltage. The drive circuit of the display device according to (11), wherein threshold correction processing is performed to change a source voltage of the drive transistor.
(13) A sampling switch that is provided for each signal line wired in units of pixel columns of a pixel array unit in which pixels are arranged in a matrix, and that samples a predetermined DC voltage input and writes the signal to the signal line;
A display device using a drive circuit, comprising: a capacitor connected to an input node of the sampling switch and absorbing a fluctuation in potential of the input node caused by switching of the sampling switch.
(14) a sampling switch that is provided for each signal line wired in units of pixel columns of a pixel array unit in which pixels are arranged in a matrix, and that samples a predetermined DC voltage input and writes the signal to the signal line;
An electronic apparatus having a display device using a drive circuit, the capacitor including a capacitor connected to an input node of the sampling switch and absorbing a fluctuation in potential of the input node caused by switching of the sampling switch.

DESCRIPTION OF SYMBOLS 10 ... Organic EL display device, 20 ... Pixel, 21 ... Organic EL element, 22 ... Drive transistor, 23 ... Write transistor, 24 ... Retention capacity, 30 ... Pixel array 40, write scanning circuit, 50, power supply scanning circuit, 60, 60 _A , 60 _B , 60 _C, signal line drive circuit, 61, amplifier, 62 (62 _{1 to} 62 _i ) ... sampling _{switch, 63 (63 1 ~63 i)} , 64 (64 1 ~64 i) ··· capacitive element (MOS capacitor), 70 ... semiconductor substrate

Claims (14)

A sampling switch that is provided for each signal line wired in units of pixel columns of a pixel array unit in which pixels are arranged in a matrix, and that samples a predetermined DC voltage input and writes the signal to the signal line;
And a capacitive element connected to the input node of the sampling switch and absorbing fluctuations in the potential of the input node caused by switching of the sampling switch. The display device driving circuit according to claim 1, wherein the sampling switch is an analog switch in which a P-channel MOS transistor and an N-channel MOS transistor are connected in parallel. The capacitive element is a MOS capacitor connected between a transmission line for transmitting selection pulses having opposite phases to the gate electrodes of the P-channel MOS transistor and the N-channel MOS transistor and the input node. Item 3. A drive circuit for a display device according to Item 2. The display device drive circuit according to claim 3, wherein an area of the gate electrode of the MOS capacitor is half of an area of each gate electrode of the P-channel MOS transistor and the N-channel MOS transistor. The display device drive circuit according to claim 1, wherein an amplifier for inputting the predetermined DC voltage to the sampling switch is connected to an input side of the sampling switch. The drive circuit of the display device according to claim 1, wherein the sampling switch has an input node commonly connected in units of a plurality of signal lines. The display device driving circuit according to claim 6, wherein one capacitive element is connected to a common input node connected in common with the plurality of signal lines as a unit. The display device according to claim 7, wherein a selection pulse having the earliest transition timing among a plurality of selection pulses for operating a plurality of sampling switches corresponding to the plurality of signal lines at independent timing is used for the operation of the capacitive element. Drive circuit. 7. The display device driving circuit according to claim 6, wherein the sampling switch samples a signal voltage of a video signal input in time series following the predetermined DC voltage in a time-sharing manner and writes the signal voltage to the signal line. The display device driving circuit according to claim 1, further comprising a capacitor connected to an output node of the sampling switch and absorbing a fluctuation in potential of the output node caused by switching of the sampling switch. The pixel includes a driving transistor for driving an electro-optic element, a writing transistor connected between the signal line and the gate electrode of the driving transistor, and a gate electrode of the driving transistor and one source / drain electrode. The display device driving circuit according to claim 1, further comprising a storage capacitor connected therebetween. The pixel uses the gate voltage of the drive transistor when the predetermined DC voltage is written by the write transistor as an initialization voltage, and is directed toward a voltage obtained by subtracting the threshold voltage of the drive transistor from the initialization voltage. The drive circuit of the display device according to claim 11, wherein threshold correction processing for changing a source voltage of the drive transistor is performed. A sampling switch that is provided for each signal line wired in units of pixel columns of a pixel array unit in which pixels are arranged in a matrix, and that samples a predetermined DC voltage input and writes the signal to the signal line;
A display device using a drive circuit, comprising: a capacitor connected to an input node of the sampling switch and absorbing a fluctuation in potential of the input node caused by switching of the sampling switch. A sampling switch that is provided for each signal line wired in units of pixel columns of a pixel array unit in which pixels are arranged in a matrix, and that samples a predetermined DC voltage input and writes the signal to the signal line;
An electronic apparatus having a display device using a drive circuit, the capacitor including a capacitor connected to an input node of the sampling switch and absorbing a fluctuation in potential of the input node caused by switching of the sampling switch.

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