JP2013089789A - Memory device and manufacturing method therefor - Google Patents

Abstract

A storage device with high reliability and a method for manufacturing the same are provided.
A storage device according to an embodiment includes a lower electrode layer, an insulating core layer provided on the lower electrode layer, and a side surface of the core layer provided on the core layer. An upper electrode layer that is not provided, and a resistance change layer that is provided on a side surface of the core material layer, is in contact with the lower electrode layer and the upper electrode layer, and a plurality of microconductors are gathered through a gap. .
[Selection] Figure 2

Description

  Embodiments described herein relate generally to a storage device and a method for manufacturing the same.

  In recent years, when a voltage is applied to a specific material, a phenomenon in which the material has two states, a low resistance state and a high resistance state, has been discovered depending on the resistivity before the voltage is applied and the magnitude of the applied voltage. A new nonvolatile memory device that has been used has been proposed. This nonvolatile storage device is called a ReRAM (Resistance Random Access Memory). Initially, metal oxide-based materials were known as resistance change materials exhibiting such behavior, but recently, such resistance change materials can also be realized using carbon nanotubes (CNT). It's been found.

  On the other hand, regarding the real device structure of ReRAM, a three-dimensional cross-point structure in which memory cells are arranged at the intersections of WL (word lines) and BL (bit lines) has been proposed from the viewpoint of high integration. In a ReRAM having a three-dimensional cross-point structure, a pillar is provided between WL and BL, and a part of the pillar is constituted by a layer in which CNTs are aggregated. However, there is a problem that the layer in which CNTs are assembled is mechanically fragile and has low reliability.

Special table 2011-508979 gazette

  An object of the present invention is to provide a storage device with high reliability and a manufacturing method thereof.

  The memory device according to the embodiment is provided on a lower electrode layer, an insulating core material layer provided on the lower electrode layer, the core material layer, and provided on a side surface of the core material layer. An upper electrode layer that is not provided, and a variable resistance layer that is provided on a side surface of the core material layer and that is in contact with the lower electrode layer and the upper electrode layer and in which a plurality of microconductors are gathered through a gap.

  The method for manufacturing a memory device according to the embodiment includes a step of laminating a lower electrode layer, an insulating core material layer, and an upper electrode layer in this order, and patterning the upper electrode layer, the core material layer, and the lower electrode layer. Forming a laminated body, and forming a variable resistance layer in which a plurality of microconductors are gathered through a gap on a side surface of the laminated body.

1 is a perspective view illustrating a storage device according to a first embodiment. It is sectional drawing which illustrates the pillar in 1st Embodiment. (A) And (b) is sectional drawing by the A-A 'line shown in FIG. It is sectional drawing which illustrates a resistance change layer. FIGS. 7A and 7B are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. FIGS. FIGS. 7A and 7B are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. FIGS. FIGS. 7A and 7B are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. FIGS. FIGS. 7A and 7B are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. FIGS. It is sectional drawing which illustrates the pillar of the memory | storage device which concerns on a comparative example. It is sectional drawing which illustrates the pillar in 2nd Embodiment. (A) And (b) is a process perspective view which illustrates the manufacturing method of the memory | storage device which concerns on 2nd Embodiment. (A) And (b) is a process perspective view which illustrates the manufacturing method of the memory | storage device which concerns on 2nd Embodiment. 10 is a process perspective view illustrating the method for manufacturing the memory device according to the second embodiment; FIG. 10 is a process perspective view illustrating the method for manufacturing the memory device according to the second embodiment; FIG. 10 is a process perspective view illustrating the method for manufacturing the memory device according to the second embodiment; FIG. 10 is a process perspective view illustrating the method for manufacturing the memory device according to the second embodiment; FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the first embodiment will be described.
FIG. 1 is a perspective view illustrating a storage device according to this embodiment.
FIG. 2 is a cross-sectional view illustrating a pillar in this embodiment.
FIGS. 3A and 3B are cross-sectional views along the line AA ′ shown in FIG.
FIG. 4 is a cross-sectional view illustrating a resistance change layer.
The storage device according to the present embodiment is a ReRAM.

  As shown in FIG. 1, in the storage device 1 according to the present embodiment, a silicon substrate 11 is provided, and a drive circuit (not shown) of the storage device 1 is provided on the upper layer portion and the upper surface of the silicon substrate 11. Is formed. An interlayer insulating film 12 made of, for example, silicon oxide is provided on the silicon substrate 11 so as to embed a drive circuit, and a memory cell portion 13 is provided on the interlayer insulating film 12.

  In the memory cell portion 13, a word line wiring layer 14 including a plurality of word lines WL extending in one direction (hereinafter referred to as “word line direction”) parallel to the upper surface of the silicon substrate 11, and an upper surface of the silicon substrate 11. A bit line wiring layer 15 including a plurality of bit lines BL extending in a parallel direction and intersecting, for example, a direction orthogonal to the word line direction (hereinafter referred to as “bit line direction”) is an interlayer insulating film. 17 (see FIG. 2) are alternately stacked. Further, the word lines WL, the bit lines BL, and the word line WL and the bit line BL are not in contact with each other.

  A pillar 16 extending in a direction perpendicular to the upper surface of the silicon substrate 11 (hereinafter referred to as “vertical direction”) is provided at the closest point between each word line WL and each bit line BL. The pillar 16 is connected between each word line WL and each bit line BL. One pillar 16 forms one memory cell. That is, the storage device 1 is a cross-point type device in which a memory cell is arranged at each closest point between the word line WL and the bit line BL. The word lines WL, the bit lines BL, and the pillars 16 are filled with an interlayer insulating film 17. An insulating film 18 made of, for example, silicon nitride is provided between the pillar 16 and the interlayer insulating film 17.

  As shown in FIGS. 2 and 3A, in each pillar 16, the barrier metal layer 21, the rectifying element layer 22, the silicide layer 23, the lower electrode layer 24, and the core material from the silicon substrate 11 side upward. The layer 25 and the upper electrode layer 26 are laminated in this order. On the side surfaces of the lower electrode layer 24, the core material layer 25, and the upper electrode layer 26, a resistance change layer 27 is provided. The resistance change layer 27 is in contact with the lower electrode layer 24, the core material layer 25, and the upper electrode layer 26, and surrounds the lower electrode layer 24, the core material layer 25, and the upper electrode layer 26. A protective insulating layer 28 is provided around the resistance change layer 27. 2 illustrates an example in which the lower surface of the resistance change layer 27 is positioned at the same height as the interface between the rectifying element layer 22 and the silicide layer 23. 22 may be located at the same height as the inside of the silicide layer 23 or the inside of the lower electrode layer 24.

  The barrier metal layer 21 is in contact with the word line WL, for example, and the upper electrode layer 26 is in contact with the bit line BL, for example. The word line WL includes a wiring main body 31 made of metal and a barrier metal layer 32 that covers the lower surface of the wiring main body 31. For the lowermost word line WL, the barrier metal layer 32 covers the side surface in addition to the lower surface of the wiring body 31. The bit line BL includes a wiring body 33 made of metal and a barrier metal layer 34 that covers the lower surface of the wiring body 33. In FIGS. 1, 3A and 3B, and FIG. 4, the interlayer insulating film 17 and the insulating film 18 are not shown.

The wiring body 31 of the word line WL and the wiring body 33 of the bit line BL are formed of a conductive material such as tungsten (W), for example.
The barrier metal layer 21 is a layer that prevents diffusion between the word line WL and the selection element layer 22 and improves adhesion, and the barrier metal layer 32 includes the interlayer insulating film 12 or 17, the wiring body 31, and the like. The barrier metal layer 34 is a layer between the interlayer insulating film 17 and the wiring body 33, and between the upper electrode layer 26 and the wiring body 33. It is a layer that prevents adhesion and improves adhesion. The barrier metal layers 21, 32, and 34 are made of a conductive material such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

The rectifying element layer 22 is made of, for example, a polysilicon diode, and in order from the lower layer side, an n-type layer having a conductivity type of n ⁺ , an i-type layer made of an intrinsic semiconductor, and a p-type layer having a conductivity type of p ^{+ type} are stacked. Has been. Alternatively, the rectifying element layer 22 may be a Schottky diode. Thereby, for example, the rectifying element layer 22 functions as a selection element layer that passes a current only when a potential higher than that of the word line WL is supplied to the bit line BL and does not flow a reverse current. The area of the rectifying element layer 22 is larger than the area of the resistance change layer 27 when viewed from the direction in which the current flows, that is, the vertical direction.

  The silicide layer 23 is formed of, for example, titanium silicide (TiSi). The lower electrode layer 24 is made of a conductive material such as titanium nitride. The core material layer 25 is formed of an insulating material such as silicon oxide or silicon nitride. The shape of the core material layer 25 is a columnar shape whose axial direction is the vertical direction, and is, for example, a cylindrical shape as shown in FIG. Alternatively, a quadrangular prism shape with rounded corners as shown in FIG. The height of the core material layer 25 is, for example, about 5 to 30 nm. The upper electrode layer 26 is made of a conductive material such as tungsten (W), for example.

  As shown in FIG. 4, the resistance change layer 27 includes, for example, nanoconductors in which carbon nanomaterials having a nanoscale crystal structure such as full conductors, fullerenes, graphene, carbon nanotubes, carbon nanoribbons, and the like are gathered through a gap. It is a material assembly layer. FIG. 4 shows an example in which the minute conductors are CNTs (carbon nanotubes) 41 and are aggregated via the gaps 42. The gap 42 is an air layer. Therefore, the variable resistance layer 27 has a hollow structure. The longitudinal direction of each CNT 41 is substantially parallel to the film surface of the resistance change layer 27, but faces in various directions within the film surface.

  The protective insulating layer 28 is made of an insulating material other than oxide, and is made of, for example, silicon nitride. The insulating film 18 is made of, for example, silicon nitride. The interlayer insulating film 17 is made of, for example, silicon oxide.

Next, a method for manufacturing the storage device according to the present embodiment will be described.
FIGS. 5A and 5B, FIGS. 6A and 6B, FIGS. 7A and 7B, and FIGS. 8A and 8B show the manufacture of the memory device according to this embodiment. It is process sectional drawing which illustrates a method.
First, as shown in FIG. 1, a drive circuit for driving the memory cell unit 13 is formed on the upper surface of the silicon substrate 11. Next, an interlayer insulating film 12 is formed on the silicon substrate 11. Next, a contact (not shown) reaching the drive circuit is formed in the interlayer insulating film 12.

  Next, as shown in FIG. 5A, a plurality of word lines WL extending in parallel with each other in the word line direction are formed in the upper layer portion of the interlayer insulating film 12 by, for example, a damascene method. For example, the barrier metal layer 32 is formed on the inner surface of the groove formed on the upper surface of the interlayer insulating film 12, and the word line WL is then formed by embedding the wiring body 31 in the groove. The word line WL may be formed by an RIE (reactive ion etching) method. A word line wiring layer 14 is formed by the plurality of word lines WL.

  Next, as shown in FIG. 5B, a barrier metal layer 21, a rectifying element layer 22, a lower electrode layer 24, a core material layer 25, and an upper electrode layer 26 are arranged in this order on the entire surface of the word line wiring layer. By forming, the laminated body 50 is formed. Each layer is formed on the entire surface as one continuous film. When the lower electrode layer 24 containing titanium is formed on the rectifying element layer 22 containing silicon, silicon and titanium react to form a silicide layer 23 made of titanium silicide. Next, a hard mask layer 51 made of an insulating material such as silicon oxide or silicon nitride is formed on the stacked body 50, and a resist film is formed thereon. Then, this resist film is patterned by a lithography method, and a plurality of island-like resist patterns 52 are arranged in a matrix form immediately above the word line WL. The resist pattern 52 is formed in a region where the pillar 16 is to be formed.

  Next, as shown in FIG. 6A, anisotropic etching such as RIE is performed using the resist pattern 52 (see FIG. 5B) as a mask. This etching is stopped when it completely penetrates the silicide layer 23 and reaches the upper part of the rectifying element layer 22. For example, when the rectifying element layer 22 is a polysilicon diode in which an n-type layer, an i-type layer, and a p-type layer are stacked in order from the lower side, the etching is stopped in the uppermost p-type layer. As a result, the upper electrode layer 26, the core material layer 25, the lower electrode layer 24, and the silicide layer 23 are selectively removed, and a plurality of island-shaped pillar upper portions 16a arranged in a matrix immediately above the word lines WL. Is formed. On the other hand, at this time, the rectifying element layer 22 and the barrier metal layer 21 are not divided. Note that this etching may be stopped in the silicide layer 23 or the lower electrode layer 24. Next, the whole is washed, and by-products accompanying the etching are removed.

  Next, as shown in FIG. 6B, a resistance change is applied to the entire surface by applying a dispersion of carbon nanomaterials, for example, carbon nanotubes (CNT), dispersed in a solvent, for example, water, drying, and baking. Layer 27 is formed. The resistance change layer 27 covers the pillar upper portion 16a and the hard mask layer 51, and covers a region of the upper surface of the rectifying element layer 22 that is not covered by the pillar upper portion 16a. In the process of drying and baking the dispersion and reducing the thickness, the direction in which the CNT 41 extends approaches the film surface direction. Further, due to the intermolecular force acting between the base and the base, the CNTs 41 are arranged substantially uniformly along the base unevenness. Next, a protective insulating layer 28 is formed on the entire surface so as to cover the resistance change layer 27. The protective insulating layer 28 is formed of an insulating material other than oxide, for example, silicon nitride so as not to oxidize the carbon nanomaterial of the resistance change layer 27, for example, CNT 41.

Next, as shown in FIG. 7A, anisotropic etching such as RIE is performed using the hard mask layer 51 as a mask. This etching is stopped after penetrating the barrier metal layer 21. As a result, the rectifying element layer 22 and the barrier metal layer 21 are selectively removed and remain in the region directly below the pillar upper portion 16a. In the step shown in FIG. 6A, when the etching is stopped in the silicide layer 23 or the lower electrode layer 24, the lower electrode layer 24 and the silicide layer 23 are divided in this step. At this time, the resistance change layer 27 and the protective insulating layer 28 are also selectively removed and remain only on the side surface of the pillar upper portion 16a. Thereby, the pillar 16 is formed. At this time, since the resistance change layer 27 is protected by the protective insulating layer 28, it is not damaged by RIE.
Next, as shown in FIG. 7B, an insulating film 18 is formed on the entire surface. Next, for example, silicon oxide is deposited, and an interlayer insulating film 17 is formed so as to embed the pillars 16.

Next, as shown in FIG. 8A, planarization processing such as CMP (chemical mechanical polishing) is performed using the upper electrode layer 26 as a stopper.
Next, as shown in FIG. 8B, a plurality of bit lines BL extending in the bit line direction are formed at a position connecting the regions directly above the pillars 16 by the damascene method or the RIE method, and between the bit lines BL. An interlayer insulating film 17 is embedded in Thereby, the bit line wiring layer 15 is formed. At this time, at the upper end portion of the resistance change layer 27, the conductive material forming the barrier metal layer 34 penetrates into the gap 42, and an annular soaked portion 27a (see FIG. 2) is formed. However, there is no problem if the soaked portion 27a does not advance below the lower surface of the upper electrode layer 26.

  Next, the pillar 16 is formed on the bit line BL by the same method as described above. When the pillar 16 is formed, the stacking order of the n-type layer, the i-type layer, and the p-type layer in the selection element layer 22 is reversed with respect to the pillar 16 formed on the word line WL. Thereafter, the word line wiring layer 14, the plurality of pillars 16, the bit line wiring layer 15, and the plurality of pillars 16 are repeatedly formed by the same method. Thereby, the storage device 1 according to the present embodiment is manufactured.

Next, the operation of this embodiment will be described.
In the memory device 1 according to the present embodiment, a current path through the resistance change layer 27 is formed between the lower electrode layer 24 and the upper electrode layer 26 in each pillar 16. The resistance change layer 27 can have two states, a “high resistance state” and a “low resistance state”. In addition, since the core material layer 25 is insulative, substantially no current flows in the core material layer 25. However, in order to suppress the leakage current, the electrical resistance value of the core material layer 25 is desirably as high as possible.

The mechanism by which the resistance change layer 27 in which the CNTs 41 are aggregated has a two-level resistance value has not been completely elucidated, but is considered as follows, for example.
When no voltage is applied to the resistance change layer 27, the CNTs 41, the CNT 41 and the lower electrode layer 24, and the CNT 41 and the upper electrode layer 26 are generally separated from each other, and the resistance change layer 27 is in a “high resistance state”. It is in. On the other hand, when a voltage is applied to the resistance change layer 27, a Coulomb force is generated between the CNTs 41 to attract each other. When this voltage is continuously applied for a predetermined time or longer, the CNT 41 is moved and rotated by the Coulomb force, contacts the adjacent CNT 41, the lower electrode layer 24 or the upper electrode layer 26, and the lower electrode layer 24 and the upper electrode layer 26. A current path through a plurality of CNTs 41 is formed. As a result, the resistance change layer 27 is in a “low resistance state”. This state is maintained even when no voltage is applied to the resistance change layer 27. Further, when a short-time pulse voltage of, for example, nanosecond order is applied to the resistance change layer 27, the contact portion between the CNTs 41 generates heat and the CNTs 41 are separated from each other. As a result, the resistance change layer 27 returns to the “high resistance state”. In this way, the resistance change layer 27 can have two states, a “high resistance state” and a “low resistance state”, and can store binary data. In order to realize such an operation, it is necessary that an appropriate gap 42 is formed between the CNTs 41.

Next, the effect of this embodiment will be described.
In this embodiment, the lower electrode layer 24, the core material layer 25, and the upper electrode layer 26 are stacked in the step shown in FIG. 5B, and these are patterned into pillar shapes in the step shown in FIG. 6A. After that, in the step shown in FIG. 6B, the resistance change layer 27 is formed on the side surfaces of the lower electrode layer 24, the core material layer 25, and the upper electrode layer 26. That is, the resistance change layer 27 is formed after the upper electrode layer 26 is formed. For this reason, when the upper electrode layer 26 is formed, the conductive material of the upper electrode layer 26 does not enter the gap 42 of the resistance change layer 27. Accordingly, the lower electrode layer 24 and the upper electrode layer 26 are not short-circuited through the conductive material that has entered the gap 42. Further, the electrical characteristics do not vary between the memory cells due to the conductive material that has entered the gap 42. Thus, according to the present embodiment, a highly reliable storage device can be realized.

  In the present embodiment, since the resistance change layer 27 is formed on the side surface portion of the pillar 16, processing such as lithography and pattern transfer is not performed using the resistance change layer 27 as a base. In the resistance change layer 27, micro roughness on the order of nanometers may occur on the surface due to local aggregation of the carbon nanomaterial. For this reason, when lithography is performed using the resistance change layer 27 as a base, defocusing may occur, exposure accuracy may be reduced, and a pattern may be defective. Further, when pattern transfer is performed using the resistance change layer 27 having micro roughness as a base, there may be a case where a missing portion in the concave portion and a pattern disappearance in the convex portion occur. Furthermore, in the three-dimensional cross-point structure, the roughness of the resistance change layer 27 in each pillar layer is integrated as the layers are stacked. However, in this embodiment, since these processes are not performed using the resistance change layer 27 as a base, the above-described problems do not occur. Further, each resistance change layer 27 roughness is not integrated. For this reason, variations in electrical characteristics between memory cells are small. Also by this, the reliability of the storage device 1 can be improved.

  Furthermore, in the present embodiment, the resistance change layer 27 is formed on the side surface portion of the pillar 16. Therefore, it is not necessary to form a thick film such as the hard mask layer 51 on the resistance change layer 27. In the present embodiment, after the resistance change layer 27 is formed on the entire surface in the step shown in FIG. 6B, the resistance change layer 27 is divided for each pillar 16 in the step shown in FIG. Therefore, the time during which the resistance change layer 27 is a continuous film is short. Thereby, it can suppress that the resistance change layer 27 peels by film | membrane stress.

  Furthermore, in the present embodiment, in the step shown in FIG. 6A, the upper electrode layer 26, the core material layer 25, the lower electrode layer 24, and the silicide layer 23 are etched and then washed to remove byproducts. Then, in the process shown in FIG. 6B, the resistance change layer 27 and the protective insulating layer 28 are formed. 7A, the rectifying element layer 22 and the barrier metal layer 21 are etched. As described above, according to the present embodiment, there is no etching process between the process of forming the resistance change layer 27 and the process of forming the protective insulating layer 28. Therefore, the resistance change layer 27 is generated during etching. The by-product produced does not adhere.

  Furthermore, in the present embodiment, the mechanical strength of the pillar 16 is secured by the core material layer 25. As the material of the core material layer 25, a material that is chemically bonded to the lower electrode layer 24 and the upper electrode layer 26 can be selected. Thereby, the adhesion strength between the core material layer 25, the lower electrode layer 24, and the upper electrode layer 26 can also be increased. Thus, in this embodiment, since the core material layer 25 is provided in the pillar 16, the mechanical strength of the pillar 16 is high and the pillar 16 is hard to collapse. For example, in the drying process after cleaning, the possibility that the pillar 16 collapses due to the surface tension of the cleaning liquid is low. For this reason, the storage device 1 has high reliability.

  Furthermore, in the present embodiment, the area of the rectifying element layer 22 can be determined by the area of the pillar 16 viewed from the vertical direction, and the diameter of the core material layer 25 and the thickness of the resistance change layer 27 viewed from the vertical direction. Thus, the area of the resistance change layer 27 can be determined. As described above, according to the present embodiment, the direction in which the current flows, that is, the area of the rectifying element layer 22 and the area of the resistance change layer 27 viewed from the top and bottom directions can be determined independently of each other. In particular, in this embodiment, since the area of the rectifying element layer 22 is larger than the area of the resistance change layer 27, higher quality rectification can be realized.

  Furthermore, in this embodiment, the height of the core material layer 25 is 5 to 30 nm. By setting the height of the core material layer 25 to 5 nm or more, it is possible to suppress the tunnel current from flowing through the core material layer 25 and reduce the leakage current between the lower electrode layer 24 and the upper electrode layer 26. it can. On the other hand, by setting the height of the core material layer 25 to 30 nm or less, it is possible to suppress the aspect ratio when forming the pillars 16 and to secure the processing accuracy.

Next, a comparative example of this embodiment will be described.
FIG. 9 is a cross-sectional view illustrating a pillar of the memory device according to this comparative example.
As shown in FIG. 9, in the memory device according to this comparative example, each pillar 116 is not provided with the core material layer 25 (see FIG. 2), and the lower electrode layer 124, the resistance change layer 127, and the upper electrode Layer 126 is laminated in this order. In the resistance change layer 127, carbon nanomaterials such as CNT are gathered through a gap. In FIG. 9, the barrier metal layer, the rectifying element layer, and the silicide layer among the layers constituting the pillar 116 are not shown.

  In this comparative example, the lower electrode layer 124, the resistance change layer 127, and the upper electrode layer 126 are stacked in this order, and then patterned to form the pillar 116. As described above, since the upper electrode layer 126 is formed after the variable resistance layer 127 is formed, the conductive material forming the upper electrode layer 126 penetrates into the gaps of the variable resistance layer 127 and changes resistance. The soaking layer 127 a is formed on the upper side of the layer 127. In the infiltrated layer 127a, since the conductive material is filled in the gaps between the carbon nanomaterials, the current flows through the conductive material, and the resistance does not change as a whole. Further, the penetration depth of the conductive material, that is, the thickness of the infiltrating layer 127 a varies for each pillar 116 and varies in one pillar 116. As a result, the electrical characteristics of the resistance change layer 127 vary between the memory cells. Further, when the soaking layer 127a reaches the lower electrode layer 124, the lower electrode layer 124 and the upper electrode layer 126 are short-circuited.

  In addition, as described above, the resistance change layer 127 is a layer in which carbon nanomaterials are loosely gathered through a gap. For example, when an intermolecular force is generated by mixing impurities, the carbon nanomaterial aggregates locally. Micro roughness may occur on the surface. In this comparative example, since the hard mask layer and the resist pattern are stacked on the variable resistance layer 127, this roughness is reflected in the hard mask layer and the resist pattern. As a result, in the lithography for forming the pillar 116, exposure light may be defocused and a pattern may be defective. Further, when transferring the pattern of the resist pattern to the hard mask layer and each layer below the hard mask layer, there may be a case where the remaining portion in the concave portion and the pattern disappearance in the convex portion occur. Furthermore, since the memory device according to this comparative example has a three-dimensional cross point structure, the roughness of the resistance change layer 127 in each stage is integrated as the layers are stacked, and the unevenness becomes larger as the pillar 116 on the upper stage side. End up.

  Furthermore, the carbon nanomaterial forming the resistance change layer 127 and the metal forming the lower electrode layer 124 and the upper electrode layer 126 are not chemically bonded but only bonded by intermolecular force. The resistance change layer 127, the lower electrode layer 124, and the upper electrode layer 126 have low adhesion. In this comparative example, a thick film such as a hard mask layer for patterning the pillar 116 is formed on the variable resistance layer 127 in a continuous film state before patterning. For this reason, the resistance change layer 127 may be peeled off from the lower electrode layer 124 due to the film stress of these films.

  Furthermore, in the present comparative example, a part of the pillar 116 in the longitudinal direction is constituted only by the resistance change layer 127. However, as described above, the resistance change layer 127 is an aggregate of carbon nanomaterials. Low strength. For this reason, the pillar 116 is easily broken at the portion of the resistance change layer 127, and is therefore easily collapsed. In particular, in the drying process after the cleaning process, the pillar 116 is likely to collapse due to the surface tension of the cleaning liquid. Thus, the storage device according to this comparative example has low reliability.

  Furthermore, in this comparative example, when the pillar 116 is formed by etching the upper electrode layer 126, the resistance change layer 127, the lower electrode layer 124, the rectifying element layer (not shown), and the like, Also, it adheres to the side surface of the resistance change layer 127. For this reason, the characteristic of the resistance change layer 127 deteriorates. Note that even if the protective insulating film 128 is formed so as to cover the pillar 116 after the etching, the by-product 130 is generated before that, and thus is formed inside the protective insulating film 128.

  Furthermore, in this comparative example, since the rectifying element layer occupies a part of the pillar 116 in the longitudinal direction and the other part is occupied by the resistance change layer 127, the area of the rectifying element layer viewed from the current direction and The area of the resistance change layer 127 is determined by the thickness of the pillar 116. For this reason, it is difficult to independently determine the area of the rectifying element layer and the area of the resistance change layer 127.

Next, a second embodiment will be described.
FIG. 10 is a cross-sectional view illustrating a pillar in this embodiment.
As shown in FIG. 10, the memory device 2 according to the present embodiment is different from the memory device 1 according to the first embodiment described above (see FIGS. 1 to 4) in the resistance change layer 27 and the protective insulating layer. The difference is that 28 is provided not in the entire circumference of the side surface of the pillar 16 but in only two regions on the opposite sides. That is, the resistance change layer 27 and the protective insulating layer 28 include the word line WL or the bit line BL provided immediately below the side surfaces of the lower electrode layer 24, the core material layer 25, and the upper electrode layer 26, respectively. It is provided on a region substantially parallel to the extending direction.

  Specifically, as shown in FIG. 10, for the pillar 16 provided on the word line WL, the resistance change layer 27 and the protective insulating layer 28 are formed on a region 25a substantially parallel to the word line direction. However, it is not formed on the region 25b parallel to the bit line direction. On the other hand, with respect to the pillar 16 provided on the bit line BL, the resistance change layer 27 and the protective insulating layer 28 are formed on a region substantially parallel to the bit line direction, and substantially in the word line direction. They are not formed on parallel regions.

Next, a method for manufacturing the storage device according to the present embodiment will be described.
FIGS. 11A and 11B, FIGS. 12A and 12B, and FIGS. 13 to 16 are process perspective views illustrating the method for manufacturing the memory device according to this embodiment.
First, as shown in FIG. 1, a drive circuit is formed on the upper surface of the silicon substrate 11. Next, an interlayer insulating film 12 is formed on the silicon substrate 11, and a contact (not shown) reaching the drive circuit is formed.

  Next, as shown in FIG. 11A, a barrier metal layer 32 and a wiring body 31 are formed on the interlayer insulating film 12 as a wiring material layer for forming the word line WL. Next, the laminated body 55 is formed by forming the barrier metal layer 21, the rectifying element layer 22, the lower electrode layer 24, the core material layer 25, and the upper electrode layer 26 in this order. Each layer from the barrier metal layer 32 to the upper electrode layer 26 is formed on the entire surface as one continuous film. At this time, a silicide layer 23 is formed between the rectifying element layer 22 and the lower electrode layer 24.

  Next, a hard mask layer 51 is formed on the stacked body 55, and a resist film is formed thereon. Then, the resist film is patterned by lithography to form a plurality of line-shaped resist patterns 56 extending in the word line direction. The resist pattern 56 is arranged in a line and space (L / S) shape in a region where the word line WL is to be formed.

  Next, as shown in FIG. 11B, anisotropic etching such as RIE is performed using the resist pattern 56 as a mask. This etching is stopped when it completely penetrates the silicide layer 23 and reaches the upper part of the rectifying element layer 22. Thereby, the upper part of the stacked body 55, that is, the upper electrode layer 26, the core material layer 25, the lower electrode layer 24, and the silicide layer 23 are selectively removed, and a plurality of line-shaped upper stacked bodies extending in the word line direction are obtained. The hard mask layer 51 remains on the upper laminate 57 where the 57 is formed. On the other hand, at this point, the rectifying element layer 22, the barrier metal layer 21, the wiring body 31, and the barrier metal layer 32 are not divided. Note that the etching may be stopped in the lower electrode layer 24 or the silicide layer 23. Next, the whole is washed, and by-products accompanying the etching are removed.

  Next, as shown in FIG. 12 (a), a resistance change is applied to the entire surface by applying a carbon nanomaterial, for example, a dispersion of carbon nanotubes (CNT) dispersed in a solvent, for example, water, drying, and baking. Layer 27 is formed. The resistance change layer 27 covers the upper stacked body 57 and the hard mask layer 51, and covers a region of the upper surface of the rectifying element layer 22 that is not covered by the upper stacked body 57. Next, a protective insulating layer 28 is formed on the entire surface so as to cover the resistance change layer 27. The protective insulating layer 28 is formed of an insulating material other than oxide, for example, silicon nitride so as not to oxidize the carbon nanomaterial of the resistance change layer 27.

  Next, as shown in FIG. 12B, anisotropic etching such as RIE is performed using the hard mask layer 51 as a mask. This etching is stopped after penetrating the barrier metal layer 32 and reaching the interlayer insulating film 12. As a result, the lower portion of the stacked body 55, that is, the rectifying element layer 22 and the barrier metal layer 21, and the wiring body 31 and the barrier metal layer 32 are selectively removed and remain in the region directly below the upper stacked body 57. In the step shown in FIG. 11B, when the etching is stopped in the silicide layer 23 or the lower electrode layer 24, the lower electrode layer 24 and the silicide layer 23 are divided in this step. That is, the lower portion of the stacked body 55 is patterned in a self-aligned manner with respect to the upper portion of the stacked body 55 (upper stacked body 57). At this time, the resistance change layer 27 and the protective insulating layer 28 are also selectively removed and remain only on the side surfaces of the upper stacked body 57. Since the resistance change layer 27 is protected by the protective insulating layer 28, it is not damaged by RIE.

  In this manner, the barrier metal layer 21, the rectifying element layer 22, the silicide layer 23, the lower electrode layer 24, the core material layer 25 and the upper electrode layer 26, the resistance change layer 27, and the protective insulating layer 28 extend in the word line direction. The word line stacked body 58 is formed by being divided into lines. Further, the barrier metal layer 32 and the wiring body 31 are divided into lines extending in the word line direction, and a word line WL is formed immediately below the word line stacked body 58. Note that the hard mask layer 51 remains on the word line stacked body 58.

  Next, as shown in FIG. 13, an insulating film 18 is formed on the entire surface. Next, for example, silicon oxide is deposited, and the interlayer insulating film 17 is formed so as to bury the word line stacked body 58. As a result, the interlayer insulating film 17 is also disposed between the word lines WL, and the word line wiring layer 14 including a plurality of word lines WL is formed. Next, a planarization process such as CMP is performed using the upper electrode layer 26 as a stopper. As a result, the hard mask layer 51 is removed, and a flat surface is formed with the upper electrode layer 26, the interlayer insulating film 17 and the like exposed.

  Next, as shown in FIG. 14, a barrier metal layer 34 and a wiring body 33 are formed as a wiring material layer for forming the bit line BL. Next, the second-stage barrier metal layer 21, the rectifying element layer 22, the lower electrode layer 24, the core material layer 25, and the upper electrode layer 26 are formed in this order. Each layer is formed on the entire surface as one continuous film. At this time, a silicide layer 23 is formed between the rectifying element layer 22 and the lower electrode layer 24. A stacked body 59 is formed by the layers from the second-stage barrier metal layer 21 to the upper electrode layer 26.

  Next, a hard mask layer 51 is formed on the stacked body 59, and a resist film is formed thereon. Then, the resist film is patterned by lithography to form a plurality of line-shaped resist patterns 60 extending in the bit line direction. The resist pattern 60 is arranged in a line and space (L / S) shape in a region where the bit line BL is to be formed.

  Next, as shown in FIG. 15, anisotropic etching such as RIE is performed using the resist pattern 60 (see FIG. 14) as a mask. This etching is stopped when it completely penetrates the second-stage silicide layer 23 and reaches the upper part of the second-stage rectifying element layer 22. As a result, the upper portion of the stacked body 59, that is, the upper electrode layer 26, the core material layer 25, the lower electrode layer 24, and the silicide layer 23 in the second stage are divided along the word line direction and extend in the bit line direction. The upper laminate 61 is formed. The hard mask layer 51 remains on the upper stacked body 61. This etching may also be stopped in the lower electrode layer 24 or the silicide layer 23. Next, the whole is washed, and by-products accompanying the etching are removed. Next, the resistance change layer 27 and the protective insulating layer 28 are formed on the entire surface. The protective insulating layer 28 is formed of an insulating material other than oxide.

  Next, as shown in FIG. 16, anisotropic etching such as RIE is performed using the hard mask layer 51 (see FIG. 15) as a mask. This etching is stopped when it reaches the word line WL through the first-stage rectifying element layer 22. As a result, the lower portion of the stacked body 59, that is, the second-stage rectifying element layer 22 and the barrier metal layer 21, and the wiring body 33 and the barrier metal layer 34 are selectively removed and divided along the word line direction. Is done. Further, the word line stacked body 58 is selectively removed and divided along the word line direction. Even when the etching shown in FIG. 15 stops in the lower electrode layer 24 or the silicide layer 23, the lower electrode layer 24 and the silicide layer 23 are divided in this step.

  In the process shown in FIG. 15, the upper portion of the laminate 59 (see FIG. 14), that is, the upper electrode layer 26, the core material layer 25, the lower electrode layer 24, and the silicide layer 23 in the second stage are already along the word line direction. Since the upper laminated body 61 is divided, in this step, the lower part of the laminated body 59, that is, the second-stage rectifying element layer 22 and the barrier metal layer 21 are divided along the word line direction. The entire stacked body 59 is divided along the word line direction, and accordingly, the resistance change layer 27 and the protective insulating layer 28 are also divided. As a result, a bit line stacked body 62 extending in the bit line direction is formed. In the bit line stack 62, the second-stage barrier metal layer 21, the rectifying element layer 22, the silicide layer 33, the lower electrode layer 24, the core material layer 25, and the upper electrode layer 26 are stacked in this order, and the lower electrode layer 24, A resistance change layer 27 and a protective insulating layer 28 are formed on the side surfaces of the core material layer 25 and the upper electrode layer 26.

  Further, the bit body BL is formed by dividing the wiring body 33 and the barrier metal layer 34 along the word line direction. Further, since the word line stacked body 58 is already divided along the bit line direction in the step shown in FIG. 12B, the word line stacked body 58 is divided along the word line direction in this step, so that And a plurality of pillars 16 arranged in a matrix along both the word line direction.

Next, an insulating film 18 is formed on the entire surface, and an interlayer insulating film 17 is formed. As a result, the interlayer insulating film 17 is also disposed between the bit lines BL, and the bit line wiring layer 15 including a plurality of bit lines BL is formed. Next, a planarization process such as CMP is performed using the second-stage upper electrode layer 26 as a stopper.
Thereafter, similarly, the steps shown in FIGS. 11A to 16 are repeated. Thereby, the memory | storage device 2 which concerns on this embodiment is manufactured.
The repeating process is schematically described as <1> to <10> below.

  <1> A barrier metal layer 32 and a wiring body 31 which are materials of the word line WL are laminated, and a barrier metal layer 21, a rectifying element layer 22, a lower electrode layer 24, a core material layer 25 and an upper electrode layer 26 are formed thereon. The stacked body 55 is formed by stacking in this order (FIG. 11A).

  <2> On the stacked body 55, a hard mask layer 51 and a resist pattern 52 are formed, and etching is performed using the hard mask layer 51 and the resist pattern 52 as a mask. Divided into a line-shaped upper laminate 57 extending in the word line direction (FIG. 11B).

  <3> The resistance change layer 27 and the protective insulating layer 28 are formed so as to cover the upper stacked body 57 (FIG. 12A).

  <4> Etching is performed using the hard mask layer 51 as a mask. As a result, the lower portion of the stacked body 55 is divided to form the word line stacked body 58 extending in the word line direction, the wiring body 31 and the barrier metal layer 32 are divided to form the word line WL. The lower bit line stack 62 (see FIG. 16) is divided to form pillars 16 (FIG. 12B).

  <5> The interlayer insulating film 17 is formed so as to cover the word line stacked body 58, and the upper surface is flattened using the upper electrode layer 26 as a stopper (FIG. 13).

  <6> On the word line stacked body 58, the barrier metal layer 34 and the wiring body 33, which are the materials of the bit line BL, are stacked, and the barrier metal layer 21, the rectifying element layer 22, the lower electrode layer 24, and the core material are stacked thereon. The layer 25 and the upper electrode layer 26 are stacked in this order to form a stacked body 59 (FIG. 14).

  <7> The hard mask layer 51 and the resist pattern 60 are formed on the stacked body 59, and etching is performed using the hard mask layer 51 and the resist pattern 60 as a mask, whereby the upper portion of the stacked body 59 is changed to a linear upper stacked body 61 extending in the bit line direction. Divide (FIG. 15).

  <8> The resistance change layer 27 and the protective insulating layer 28 are formed so as to cover the upper laminate 61 (FIG. 15).

  <9> Etching is performed using the hard mask layer 51 as a mask. As a result, the lower portion of the stacked body 59 is divided to form the bit line stacked body 62 extending in the bit line direction, the wiring body 33 and the barrier metal layer 34 are divided to form the bit line BL, and the word lines below The line laminate 58 is divided to form pillars 16 (FIG. 16).

  An interlayer insulating film 17 is formed so as to cover the <10> pillar 16 and the bit line stacked body 62, and the upper surface is planarized (FIG. 16).

Next, the effect of this embodiment will be described.
In the present embodiment, the word line wiring layer 14, the layer composed of a plurality of pillars 16, the bit line wiring layer 15, and the plurality of pillars 16 are formed by a series of steps shown in the above <1> to <10>. A basic structure including four layers can be manufactured. At this time, lithography is performed in the steps (2) and (7) described above. That is, the basic structure described above can be manufactured by two lithography operations.
On the other hand, in the first embodiment described above, lithography is performed when forming the word line wiring layer 14, the layer composed of the plurality of pillars 16, the bit line wiring layer 15, and the layer composed of the plurality of pillars 16. Is going. That is, the above-described basic structure is manufactured by four times of lithography.
Thus, according to the present embodiment, the number of lithography can be reduced and the manufacturing cost of the storage device can be reduced as compared with the first embodiment described above. On the other hand, according to the first embodiment described above, it is possible to suppress the aspect ratio during etching and facilitate processing.

Further, according to the present embodiment, wirings and pillars that are adjacent in the vertical direction can be formed in a self-aligned manner by the same lithography. For this reason, the accuracy of alignment is high.
Other configurations, manufacturing methods, operations, and effects in the present embodiment are the same as those in the first embodiment described above.

  According to the embodiment described above, a highly reliable storage device and a method for manufacturing the same can be realized.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

1, 2: memory device, 11: silicon substrate, 12: interlayer insulating film, 13: memory cell portion, 14: word line wiring layer, 15: bit line wiring layer, 16: pillar, 16a: upper part of pillar, 17: interlayer Insulating film, 18: Insulating film, 21: Barrier metal layer, 22: Rectifying element layer, 23: Silicide layer, 24: Lower electrode layer, 25: Core material layer, 25a, 25b: Region, 26: Upper electrode layer, 27 : Resistance change layer, 27a: soaked part, 28: protective insulating layer, 31: wiring body, 32: barrier metal layer, 33: wiring body, 34: barrier metal layer, 41: CNT, 42: gap, 50: lamination Body: 51: hard mask layer, 52: resist pattern, 55: laminate, 56: resist pattern, 57: upper laminate, 58: word line laminate, 59: laminate, 60: resist pattern, 61: upper laminate body 62: bit line stack 116: pillar, 124: lower electrode layer, 126: upper electrode layer, 127: variable resistance layer, 127a: Somekomiso, 130: by-products, BL: Bit line, WL: wordline

Claims (15)

A word line wiring layer including a plurality of word lines extending in a first direction;
A bit line wiring layer including a plurality of bit lines extending in a second direction intersecting the first direction;
Pillars connected between each word line and each bit line;
An interlayer insulating film provided between the pillars and made of oxide;
A protective insulating layer made of an insulating material other than oxide;
With
The word line wiring layers and the bit line wiring layers are alternately stacked,
The pillar is
A rectifying element layer;
A lower electrode layer provided on the rectifying element layer;
An insulating core layer provided on the lower electrode layer;
An upper electrode layer provided on the core material layer and not provided on a side surface of the core material layer;
A resistance change layer provided on a side surface of the core material layer, surrounding the core material layer, in contact with the lower electrode layer and the upper electrode layer, and a plurality of carbon nanotubes gathered through a gap;
Have
The protective insulating layer is provided between the resistance change layer and the interlayer insulating film,
A memory device in which the area of the rectifying element layer is larger than the area of the variable resistance layer as viewed from above. A lower electrode layer;
An insulating core layer provided on the lower electrode layer;
An upper electrode layer provided on the core material layer and not provided on a side surface of the core material layer;
A variable resistance layer provided on a side surface of the core material layer, in contact with the lower electrode layer and the upper electrode layer, and a plurality of microconductors gathered through a gap;
A storage device.   The storage device according to claim 2, wherein the minute conductor is a carbon nanotube. A word line wiring layer including a plurality of word lines extending in a first direction;
A bit line wiring layer including a plurality of bit lines extending in a second direction intersecting the first direction;
Further comprising
The word line wiring layers and the bit line wiring layers are alternately stacked,
The said lower electrode layer, the said core material layer, the said upper electrode layer, and the said resistance change layer form the pillar connected between each said word line and each said bit line. Storage device. An interlayer insulating film provided between the pillars;
A protective insulating layer provided between the variable resistance layer and the interlayer insulating film;
Further comprising
The interlayer insulating film is made of an oxide,
The memory device according to claim 4, wherein the protective insulating layer is made of an insulating material other than an oxide.   The variable resistance layer is provided on a side surface of the core material layer on a region parallel to a direction in which the word line or the bit line provided immediately below the core material layer extends. The storage device according to 4 or 5.   The storage device according to claim 2, wherein the resistance change layer is provided so as to surround the periphery of the core material layer. Further comprising a rectifying element layer provided below the lower electrode layer,
The storage device according to claim 2, wherein an area of the rectifying element layer is larger than an area of the variable resistance layer as viewed from above. A step of laminating a lower electrode layer, an insulating core layer and an upper electrode layer in this order;
Patterning the upper electrode layer, the core material layer and the lower electrode layer to form a laminate;
Forming a resistance change layer in which a plurality of minute conductors are gathered via a gap on a side surface of the laminate; and
A method for manufacturing a storage device comprising: Forming a word line wiring layer including a plurality of word lines extending in a first direction;
A step of laminating a rectifying element layer, a lower electrode layer, an insulating core layer and an upper electrode layer in this order;
A step of selectively removing the upper electrode layer, the core material layer, and the lower electrode layer to form a plurality of pillar upper portions arranged in a matrix directly above the word line;
Forming a resistance change layer in which a plurality of microconductors are gathered through a gap so as to cover the top of the pillar;
Forming the pillar by selectively removing the rectifying element layer and allowing it to remain in the region directly below the pillar, and selectively removing the resistance change layer and remaining on the side surface of the pillar; When,
Forming an interlayer insulating film between the pillars;
Forming a bit line wiring layer by forming a plurality of bit lines extending in a second direction intersecting the first direction at a position connecting the regions directly above the pillars;
A method for manufacturing a storage device comprising:   The method for manufacturing a memory device according to claim 10, further comprising a step of forming a protective insulating layer covering the variable resistance layer before the step of forming the pillar. The protective insulating layer is formed of an insulating material other than oxide,
The method for manufacturing a memory device according to claim 11, wherein the interlayer insulating film is formed of an oxide. Laminating a first wiring material layer, a first rectifying element layer, a first lower electrode layer, a first core material layer, and a first upper electrode layer;
Selectively removing the first upper electrode layer, the first core material layer, and the first lower electrode layer to form a first line stack extending in a first direction;
Forming a first variable resistance layer in which a plurality of microconductors are gathered via a gap so as to cover the first line stack;
The first rectifying element layer and the first wiring material layer are selectively removed and left in a region immediately below the first line stacked body, whereby the first rectifying element layer and the first rectifying element layer and the first wiring layer are selectively removed. Cutting the line stack to form a first stack, cutting the first wiring material layer to form a word line;
Forming an interlayer insulating film over the entire surface, and performing a planarization process using the first upper electrode layer as a stopper;
A second wiring material layer, a second rectifying element layer, a second lower electrode layer, a second core material layer, and a second upper electrode layer are stacked on the first stacked body and the interlayer insulating film. And a process of
The second upper electrode layer, the second core material layer, and the second lower electrode layer are selectively removed, and a second extending in a second direction intersecting the first direction Forming a line laminate;
Forming a second variable resistance layer in which a plurality of microconductors are gathered through a gap so as to cover the second line stack;
The second rectifying element layer, the second wiring material layer, and the first stacked body are selectively removed and left in a region immediately below the second line stacked body, whereby the second rectifying element layer, the second wiring material layer, and the first stacked body are removed. A rectifying element layer and the second line laminate are divided to form a second laminate, the second wiring material layer is divided to form a bit line, and the first laminate is divided. Forming pillars,
Forming an interlayer insulating film over the entire surface, and performing a planarization process using the second upper electrode layer as a stopper;
A method for manufacturing a storage device comprising: A step of forming a first protective insulating layer after the step of forming the first variable resistance layer and before the step of remaining in the region immediately below the first line stack,
A step of forming a second protective insulating layer after the step of forming the second variable resistance layer and before the step of remaining in the region immediately below the second line stack;
The method for manufacturing a storage device according to claim 13, further comprising: Forming the first and second protective insulating layers with an insulating material other than oxide;
The method for manufacturing a memory device according to claim 14, wherein the interlayer insulating film is formed of an oxide.

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