JP2013080792A - Hall element - Google Patents

Abstract

Provided is a Hall element with little variation in characteristics.
A P-type substrate is provided with an N-type well that is square in plan view. In addition to the four corners of the Hall element 10, a P-type diffusion layer 5 is provided above the N-type well 6, and N-type diffusion layers 1 to 4 are provided above the N-type well 6 at the four corners of the Hall element 10. Then, a voltage at which a depletion layer is generated between the P-type diffusion layer 5 and the N-type well 6 below the P-type diffusion layer 5 is applied to the P-type diffusion layer 5.
[Selection] Figure 1

Description

  The present invention relates to a Hall element.

  A conventional Hall element will be described. 3A and 3B are diagrams showing a conventional Hall element, FIG. 3A is a plan view of the conventional Hall element, FIG. 3B is a YY sectional view of the plan view of the conventional Hall element, and FIG. It is ZZ sectional drawing in the top view of this Hall element.

  A power supply voltage is applied between the N-type diffusion layer 32 and the N-type diffusion layer 33 of the Hall element 30. A current flows from the N-type diffusion layer 32 to the N-type diffusion layer 33 in accordance with the power supply voltage. At this time, when a magnetic field is applied perpendicular to the plane of the Hall element 30, a Hall voltage is generated perpendicular to both the current and the magnetic field. That is, a Hall voltage is generated between the N-type diffusion layer 31 and the N-type diffusion layer 34. (For example, see Patent Document 1)

Japanese Patent Laying-Open No. 2008-008883 (FIG. 17)

Here, in the conventional technique, the current path in the Hall element 30 can be formed on the surface of the N-type well 36 which is the outermost surface of the P-type substrate 37. The surface of the N-type well 36 is affected by dust or the like adhering during cleaning in the manufacturing process of the Hall element 30. That is, the current path in the Hall element 30 is affected by cleaning, dust, and the like. Therefore, the characteristics of the Hall element 30 vary.
This invention is made | formed in view of the said subject, and provides a Hall element with few characteristic dispersion | variation.

  In order to solve the above-described problems, the present invention provides a first conductivity type substrate, a second conductivity type well provided on the first conductivity type substrate, and an upper portion of the second conductivity type well. In the plan view of the second conductivity type well above the second conductivity type well, the first conductivity type diffusion layer to which a voltage generating a depletion layer is applied between the conductivity type well, the depletion layer, and the second conductivity type well. A first second conductivity type diffusion layer provided at an edge, and a second second conductivity type diffusion layer provided at an edge of the second conductivity type well at a top of the second conductivity type well. A third second conductivity type diffusion layer provided on an edge of the plan view of the second conductivity type well above the second conductivity type well and facing the second second conductivity type diffusion layer; An upper portion of the second conductivity type well is provided at an edge of the second conductivity type well in a plan view, and the first second conductivity type expansion is provided. Providing a Hall element, characterized in that it comprises a fourth second-conductive-type diffusion layer facing the layer, the.

  According to the present invention, the current path in the Hall element is not generated on the surface of the second conductivity type well, which is the outermost surface of the first conductivity type substrate, and the first conductivity type diffusion layer and the first conductivity type diffusion layer are not formed. It is formed under a depletion layer generated between the lower second conductivity type well. Therefore, the current path in the Hall element is not affected by cleaning, dust, or the like in the Hall element manufacturing process. Therefore, the Hall element characteristics are less likely to vary.

It is a figure which shows a Hall element, (A) is a top view of a Hall element, (B) is YY sectional drawing in the top view of a Hall element, (C) is ZZ sectional drawing in the top view of a Hall element. is there. It is a figure which illustrates the circuit connection of a Hall element. It is a figure which shows the conventional Hall element, (A) is a top view of the conventional Hall element, (B) is YY sectional drawing in the top view of the conventional Hall element, (C) is the conventional Hall element. It is ZZ sectional drawing in the top view.

Embodiments of the present invention will be described below with reference to the drawings.
First, the structure of the Hall element will be described. FIG. 1 is a view showing a Hall element, (A) is a plan view of the Hall element, (B) is a YY sectional view in the plan view of the Hall element, and (C) is ZZ in the plan view of the Hall element. It is sectional drawing.

  A square N-type well 6 is provided near the surface of the P-type substrate 7 in a plan view as viewed from above the substrate surface. A P-type diffusion layer 5 is provided above the N-type well 6 other than the four corners of the Hall element 10 in FIG. In the four corners of the Hall element 10 in FIG. 1A, N-type diffusion layers 1 to 4 are provided above the N-type well 6. Here, the N-type diffusion layers 1 to 4 are provided at the four corners of the N-type well 6, respectively. The N type diffusion layer 1 and the N type diffusion layer 4 face each other, and the N type diffusion layer 2 and the N type diffusion layer 3 face each other.

  Next, the operation of the Hall element 10 will be described. FIG. 2 is a diagram illustrating the circuit connection of the Hall elements.

  A positive terminal of the power source 21 is connected to the N-type diffusion layer 2. The negative terminal of the power source 21 is connected to the P-type diffusion layer 5 and the N-type diffusion layer 3. The voltmeter 22 is connected between the N-type diffusion layer 1 and the N-type diffusion layer 4.

  Here, since the negative terminal of the power source 21 is connected to the P-type diffusion layer 5, a depletion layer is generated between the P-type diffusion layer 5 and the N-type well 6 below the P-type diffusion layer 5. That is, the power supply 21 applies a voltage to the P-type diffusion layer 5 so that a depletion layer is generated between the P-type diffusion layer 5 and the N-type well 6 below the P-type diffusion layer 5.

  In the Hall element 10, a power supply voltage is applied between the N-type diffusion layer 2 and the N-type diffusion layer 3 from the power supply 21. A current flows from the N-type diffusion layer 2 to the N-type diffusion layer 3 in accordance with the power supply voltage. This current flows under the depletion layer generated between the P-type diffusion layer 5 and the N-type well 6 below the P-type diffusion layer 5. At this time, when a magnetic field is applied perpendicular to the plane of the Hall element 10, a Hall voltage is generated perpendicular to both the current and the magnetic field. That is, a Hall voltage is generated between the N-type diffusion layer 1 and the N-type diffusion layer 4. This Hall voltage is measured by a voltmeter 22.

  Note that an operational amplifier, a comparator, and a reference voltage generation circuit may be provided instead of the voltmeter 22. At this time, the operational amplifier amplifies the Hall voltage. The reference voltage generation circuit generates a reference voltage. The comparator compares the amplified Hall voltage with a reference voltage. When the Hall voltage after amplification is higher than the reference voltage, the output logic of the comparator becomes high level, and when it is low, it becomes low level.

  Further, in the above case, a power supply voltage is applied between the N-type diffusion layer 2 and the N-type diffusion layer 3 and a Hall voltage is generated between the N-type diffusion layer 1 and the N-type diffusion layer 4. A second period in which a power supply voltage is applied between the N-type diffusion layer 1 and the N-type diffusion layer 4 and a Hall voltage is generated between the N-type diffusion layer 2 and the N-type diffusion layer 3. It may be provided. Here, although the Hall element 10 is symmetrical in the vertical and horizontal directions in the plane, the Hall voltages in the first period and the second period do not coincide slightly. That is, the Hall element 10 has an offset voltage. Therefore, by using the sample and hold circuit and averaging the Hall voltages in the first period and the second period, the offset voltage of the Hall voltage can be canceled using the spinning current method.

10 Hall elements 1 to 4 N type diffusion layer 5 P type diffusion layer 6 N type well 7 P type substrate

Claims (3)

A first conductivity type substrate;
A second conductivity type well provided on the substrate and having a quadrangular shape in plan view;
A first conductivity type diffusion layer provided on an upper portion of the well, to which a voltage for generating a depletion layer is applied to the well; and
The depletion layer;
A first second conductivity type diffusion layer provided in the first corner of the well at the top of the well;
A second second conductivity type diffusion layer provided in a second corner adjacent to the first corner of the well at the top of the well;
A third second conductivity type diffusion layer provided at a third corner of the well facing the second corner of the well diagonally above the well;
A fourth second conductivity type diffusion layer provided at a fourth corner of the well facing the first corner of the well diagonally above the well;
Hall element equipped with.   The Hall element according to claim 1, wherein the well has a square shape in plan view.   The Hall element according to claim 1, wherein the well is symmetrical vertically and horizontally in plan view.

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