JP2013076848A - Electro-optical apparatus, method for manufacturing electro-optical apparatus, and electronic equipment - Google Patents

Abstract

To provide an electro-optical device, a method of manufacturing an electro-optical device, and an electronic apparatus that can prevent a global level difference from occurring around a pixel region and obtain high display quality.
A liquid crystal device as an electro-optical device has a pixel electrode 15 on a device substrate 10 as a substrate, and a holding member disposed so as to overlap the pixel electrode 15 in plan view between the pixel electrode 15 and the device substrate 10. A capacitor 16, a third interlayer insulating film 14 formed between the pixel electrode 15 and the storage capacitor 16 and subjected to planarization, and a peripheral region Ec of the pixel region E including the plurality of pixel electrodes 15; And a storage capacitor 16 and a dummy pattern Dp1 formed in the same wiring layer.
[Selection] Figure 9

Description

  The present invention relates to an electro-optical device, a method for manufacturing the electro-optical device, and an electronic apparatus.

  As the electro-optical device, a plurality of data lines and a plurality of scanning lines intersecting each other on a substrate, a plurality of pixel electrodes provided corresponding to the intersection of the plurality of data lines and the plurality of scanning lines, A plurality of transistors electrically connected to each of the pixel electrodes and an image signal supplied to the pixel electrodes through the data lines and the transistors are temporarily provided from the non-opening region to the opening region on the substrate. An electro-optical device having a transparent first holding capacitor that holds the target is known (Patent Document 1).

  According to the electro-optical device disclosed in Patent Document 1, since the first storage capacitor is transparent, the amount of light transmitted through the aperture region is not reduced. Therefore, the electric capacity of the first holding capacitor can be increased without reducing the luminance of the pixel, and the potential holding capability for temporarily holding the image signal can be increased.

JP 2007-3903 A

  In the electro-optical device disclosed in Patent Document 1, a transparent first storage capacitor and a light-transmitting pixel electrode are arranged on a substrate so as to overlap in plan view with an interlayer insulating film interposed therebetween. Further, these first storage capacitors and pixel electrodes are arranged in a matrix in the image display area. The interlayer insulating film is formed not only in the image display area but also in the peripheral area.

In order to ensure the flatness of the pixel electrode formed on the interlayer insulating film, the interlayer insulating film may be subjected to, for example, chemical mechanical polishing (CMP). However, the image display region having the first storage capacitor and the first storage capacitor are affected by the density of the arrangement pattern of the structure between the substrate and the pixel electrode on the surface of the interlayer insulating film after the CMP process. There was a global level difference between the peripheral area and the above-described peripheral area. There has been a problem that display unevenness due to the global level difference occurs around the image display area of the interlayer insulating film.
In order to reduce the global step as much as possible, a method of increasing the film thickness of the interlayer insulating film in the pre-CMP process may be considered, but the influence of the density of the arrangement pattern of the structure in the image display region and the peripheral region is affected. As a result, the variation in the polishing rate in the CMP process increases, and as a result, the film thickness of the interlayer insulating film after polishing may vary. When the film thickness of the interlayer insulating film varies, there is a problem that the light transmittance of the pixel including the first storage capacitor and the pixel electrode arranged with the interlayer insulating film interposed varies.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  [Application Example 1] An electro-optical device according to this application example includes a pixel electrode on a substrate, a storage capacitor disposed between the pixel electrode and the substrate so as to overlap the pixel electrode in plan view, and the pixel electrode Between the first and second storage capacitors and a planarization-processed interlayer insulating film, and a dummy formed in the same wiring layer as the storage capacitor and disposed in the peripheral region of the pixel region including the plurality of pixel electrodes. And a pattern.

According to this configuration, by having a dummy pattern formed in the same wiring layer as the storage capacitor in the peripheral region of the pixel region, the pixel region and the peripheral region when the CMP process is performed as a planarization process on the interlayer insulating film, for example. Variation in polishing rate due to the wiring structure under the interlayer insulating film is suppressed. That is, an interlayer insulating film having a stable film thickness after planarization is obtained. Accordingly, compared to the case where there is no dummy pattern, a global step is less likely to occur around the pixel region, display defects due to the global step are reduced, and an electro-optical device having high display quality can be provided.
Note that forming the dummy pattern in the same wiring layer as the storage capacitor means that the dummy pattern is formed in the same formation process with the same material and the same film thickness in the same wiring layer as the capacitor electrode and the dielectric layer constituting the storage capacitor. Say to form.

Application Example 2 In the electro-optical device according to the application example described above, the step side area per unit area is defined as a step density, the step density of the storage capacitor in the pixel region, and the step of the dummy pattern in the peripheral region. It is preferable that the density is substantially equal.
According to this configuration, since the wiring structure in the lower layer of the interlayer insulating film can be made substantially the same in the pixel region and its peripheral region, an interlayer insulating film having a more stable film thickness after the planarization process can be obtained. That is, the global level difference is eliminated.

Application Example 3 In the electro-optical device according to the application example described above, the step side area per unit area is defined as a step density, and the dummy pattern in the peripheral region is compared with the step density of the storage capacitor in the pixel region. The step density may be larger.
According to this configuration, the occurrence of global steps is reliably suppressed around the pixel region as compared with the case where the step density of the dummy pattern in the peripheral region is smaller than the step density of the storage capacitor in the pixel region. .

Application Example 4 In the electro-optical device according to the application example described above, the storage capacitor includes a first capacitor electrode functioning as a capacitor line extending over a plurality of pixels, and a second capacitor electrode formed independently for each pixel. And a dielectric layer sandwiched between the first capacitor electrode and the second capacitor electrode, wherein the dummy pattern is interposed between the first conductive layer and the first conductive layer via the dielectric layer. A second conductive layer disposed oppositely, wherein the first capacitor electrode and the first conductive layer are continuously formed across the pixel region and the peripheral region in the same wiring layer; It is preferable that the capacitor electrode and the second conductive layer are independently formed in the same wiring layer.
According to this configuration, since the layout pattern of the dummy pattern is matched with the layout pattern of the storage capacitor in the pixel region, the global level difference can be reliably eliminated.

Application Example 5 In the electro-optical device according to the application example described above, the storage capacitor includes a first capacitor electrode functioning as a capacitor line extending over a plurality of pixels, and a second capacitor electrode formed independently for each pixel. And a dielectric layer sandwiched between the first capacitor electrode and the second capacitor electrode, wherein the dummy pattern is interposed between the first conductive layer and the first conductive layer via the dielectric layer. A second conductive layer disposed oppositely, wherein the first capacitor electrode and the first conductive layer are continuously formed across the pixel region and the peripheral region in the same wiring layer; The conductive layer may be formed continuously across the peripheral region in the same wiring layer as the second capacitor electrode.
According to this configuration, not only the occurrence of a global step is surely suppressed, but also a local step between the dummy patterns is prevented from occurring in the peripheral region as compared with the case where at least one of the dummy patterns is independently formed. it can.

Application Example 6 In the electro-optical device according to the application example described above, it is preferable that at least one of the first conductive layer and the second conductive layer is in an electrically floating state.
According to this configuration, the influence of the potential of the dummy pattern on the potential of the pixel electrode is reduced as compared with a case where a specific potential is applied to at least one of the first conductive layer and the second conductive layer of the dummy pattern. Can do. That is, it is possible to reduce the occurrence of display defects due to the influence of the dummy pattern potential.

Application Example 7 In the electro-optical device according to the application example described above, the pixel electrode, the interlayer insulating film, and the storage capacitor each have a light-transmitting property.
According to this configuration, since the interlayer insulating film has a stable film thickness after the planarization process, a stable transmittance characteristic is obtained in the pixel region including the pixel electrode and the storage capacitor that are arranged to face each other with the interlayer insulating film interposed therebetween. can get.

Application Example 8 In the electro-optical device according to the application example described above, the pixel electrode has light reflectivity.
According to this configuration, since the interlayer insulating film has a stable thickness after the planarization process, stable light reflection characteristics can be obtained in a pixel region including a plurality of pixel electrodes formed on the interlayer insulating film.

  Application Example 9 A method for manufacturing an electro-optical device according to this application example includes: a pixel electrode on a substrate; and a storage capacitor disposed between the pixel electrode and the substrate so as to overlap the pixel electrode in plan view. A method for manufacturing the electro-optical device, the step of forming the storage capacitor for each pixel in a pixel region, and forming a dummy pattern in a peripheral region of the pixel region in the same wiring layer as the storage capacitor; Forming an interlayer insulating film covering the storage capacitor and the dummy pattern; performing a planarization process on a surface of the formed interlayer insulating film; and on the interlayer insulating film subjected to the planarization process, And a step of forming a pixel electrode.

  According to this method, by forming a dummy pattern in the same wiring layer as the storage capacitor in the peripheral region of the pixel region, the interlayer insulating film between the pixel region and the peripheral region is subjected to, for example, a CMP process as a planarization process. Variation in polishing rate due to the wiring structure under the insulating film can be suppressed. That is, an interlayer insulating film having a stable film thickness after planarization is obtained. Therefore, compared to a case where no dummy pattern is formed, a global step is less likely to occur around the pixel region, display defects due to the global step are reduced, and an electro-optical device having high display quality can be manufactured.

Application Example 10 In the method of manufacturing the electro-optical device according to the application example described above, the side area of the step per unit area is set as a step density, and the dummy capacitance is set so that the storage capacitor and the step pattern have substantially the same step density. It is preferable to form a pattern.
According to this method, since the wiring structure in the lower layer of the interlayer insulating film before the planarization process can be made substantially the same in the pixel region and its peripheral region, the interlayer insulating film having a more stable film thickness after the planarization process Is obtained. That is, an electro-optical device in which the global level difference is eliminated can be manufactured.

Application Example 11 In the electro-optical device manufacturing method according to the application example described above, the step area per unit area is defined as a step density, and the step density of the dummy pattern is larger than the step density of the storage capacitor. The dummy pattern may be formed as described above.
According to this method, compared to the case where the step density of the dummy pattern in the peripheral region is smaller than the step density of the storage capacitor in the pixel region, it is possible to reliably suppress the occurrence of global steps around the pixel region.

Application Example 12 An electronic apparatus according to this application example includes the electro-optical device according to the application example.
According to this configuration, since the generation of a global step around the pixel region is reduced and the electro-optical device having high display quality is provided, it is possible to provide an electronic apparatus capable of displaying with good appearance.

(A) is a schematic plan view which shows the structure of a liquid crystal device, (b) is a schematic sectional drawing cut | disconnected by the H-H 'line | wire of (a). FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. FIG. 3 is a schematic plan view showing the arrangement of pixels in a liquid crystal device. FIG. 5A is a schematic plan view showing the arrangement of thin film transistors and signal lines in a pixel, and FIG. 5B is a schematic plan view showing the arrangement of a pair of capacitor electrodes and pixel electrodes of a storage capacitor in the pixel. FIG. 5 is a schematic cross-sectional view illustrating the structure of a pixel cut along line A-A ′ in FIG. 4. FIG. 4 is a schematic cross-sectional view illustrating the structure of a pixel cut along line B-B ′ in FIG. 3. FIG. 10 is a schematic cross-sectional view showing a global step of an element substrate in a conventional liquid crystal device. FIG. 2 is a schematic plan view illustrating a dummy pattern arrangement region in the liquid crystal device according to the first embodiment. (A) is a schematic plan view which shows arrangement | positioning of the dummy pattern of Example 1, (b) is a schematic sectional drawing cut | disconnected by the C-C 'line | wire of (a). Schematic for demonstrating level | step difference density. (A) is a schematic plan view which shows arrangement | positioning of the dummy pattern of Example 2, (b) is a schematic sectional drawing cut | disconnected by the D-D 'line | wire of (a). Schematic which shows the structure of the projection type display apparatus as an electronic device.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

  In the following embodiments, for example, when “on the substrate” is described, the substrate is disposed so as to be in contact with the substrate, or is disposed on the substrate via another component, or the substrate. It is assumed that a part is arranged so as to be in contact with each other and a part is arranged via another component.

(First embodiment)
In the present embodiment, an active matrix liquid crystal device including a thin film transistor as a pixel switching element will be described as an example of an electro-optical device. This liquid crystal device can be suitably used as, for example, a light modulation element (liquid crystal light valve) of a projection type display device (liquid crystal projector) described later.

<Liquid crystal device>
First, a liquid crystal device as an electro-optical device according to this embodiment will be described with reference to FIGS. 1 and 2. 1A is a schematic plan view showing the configuration of the liquid crystal device, FIG. 1B is a schematic cross-sectional view taken along line HH ′ of FIG. 1A, and FIG. 2 is an electrical configuration of the liquid crystal device. FIG.

  As shown in FIGS. 1A and 1B, a liquid crystal device 100 as an electro-optical device according to this embodiment includes a liquid crystal device sandwiched between an element substrate 10 and a counter substrate 20 which are arranged to face each other and the pair of substrates. Layer 50. The element substrate 10 and the counter substrate 20 are made of a transparent substrate such as a quartz substrate or a glass substrate.

  The element substrate 10 as a substrate in the present invention is slightly larger than the counter substrate 20, and both the substrates are bonded via a sealing material 40 arranged in a frame shape, and positive or negative dielectric anisotropy is provided in the gap. The liquid crystal layer 50 is configured by enclosing the liquid crystal. For the sealing material 40, for example, an adhesive such as a thermosetting or ultraviolet curable epoxy resin is employed. A spacer (not shown) is mixed in the sealing material 40 to keep the distance between the pair of substrates constant.

  On the inner side of the sealing material 40 arranged in a frame shape, a parting portion 21 is provided in the same frame shape. The parting part 21 is made of, for example, a light-shielding metal or metal oxide, and the inside of the parting part 21 is a pixel region E. In the pixel region E, a plurality of pixels P are arranged in a matrix. The pixel region E may include a plurality of dummy pixels arranged so as to surround a plurality of effective pixels P that contribute to display. Although not shown in FIG. 1, the pixel region E is also provided with a light-shielding portion that divides a plurality of pixels P in a plane.

A data line driving circuit 101 is provided between the sealing material 40 along one side of the element substrate 10 and the one side. Further, an inspection circuit 103 is provided inside the sealing material 40 along the other one side facing the one side. Further, a scanning line driving circuit 102 is provided inside the sealing material 40 along the other two sides orthogonal to the one side and facing each other. A plurality of wirings 105 that connect the two scanning line driving circuits 102 are provided inside the sealing material 40 on the other side facing the one side. Wirings connected to the data line driving circuit 101 and the scanning line driving circuit 102 are connected to a plurality of external connection terminals 104 arranged along the one side.
Hereinafter, the direction along the one side will be referred to as the X direction, and the direction along the other two sides orthogonal to the one side and facing each other will be described as the Y direction.

As shown in FIG. 1B, on the surface of the element substrate 10 on the liquid crystal layer 50 side, a light-transmitting pixel electrode 15 provided for each pixel P and a thin film transistor (TFT; Thin Film) as a switching element. Transistor (hereinafter referred to as TFT) 30, a signal wiring, and an alignment film 18 that covers the plurality of pixel electrodes 15 are formed.
Further, a light shielding structure is employed that prevents light from entering the semiconductor layer in the TFT 30 and causing a light leakage current to flow, resulting in an inappropriate switching operation.

  On the surface of the counter substrate 20 on the liquid crystal layer 50 side, a parting portion 21, an interlayer insulating film 22 formed so as to cover it, and an interlayer insulating film 22 covering at least the pixel region E are provided. The common electrode 23 and an alignment film 24 covering the common electrode 23 are provided.

  As shown in FIG. 1A, the parting portion 21 is provided in a frame shape at a position where it overlaps the scanning line driving circuit 102 and the inspection circuit 103 in a plane. Thus, the light incident from the counter substrate 20 side is shielded, and the malfunction of the peripheral circuits including these drive circuits due to the light is prevented. Further, unnecessary stray light is shielded from entering the pixel region E to ensure high contrast in the display of the pixel region E.

  The interlayer insulating film 22 is made of an inorganic material such as silicon oxide, for example, and is provided so as to cover the parting portion 21 with light transmittance. In addition, the interlayer insulating film 22 also functions as a planarizing layer that alleviates unevenness generated on the substrate by the parting portion 21. As a method for forming the interlayer insulating film 22, for example, a method of forming a film using a plasma CVD method or the like can be given.

  The common electrode 23 is made of, for example, a transparent conductive film such as ITO, covers the interlayer insulating film 22, and, as shown in FIG. 1A, the element substrate 10 side by the vertical conduction portions 106 provided at the four corners of the counter substrate 20. It is electrically connected to the wiring.

  The alignment film 18 covering the pixel electrode 15 and the alignment film 24 covering the common electrode 23 are selected based on the optical design of the liquid crystal device 100. For example, by depositing an organic material such as polyimide and rubbing the surface, liquid crystal molecules having positive dielectric anisotropy are subjected to a substantially horizontal alignment treatment, or SiOx (silicon oxide) Inorganic materials such as those described above are formed by vapor deposition, and liquid crystal molecules having negative dielectric anisotropy are subjected to a substantially vertical alignment treatment.

  As shown in FIG. 2, the liquid crystal device 100 includes a plurality of scanning lines 3a and a plurality of data lines 6a as signal lines that are insulated and orthogonal to each other at least in the pixel region E, and capacitance lines parallel to the scanning lines 3a. 3b.

  A pixel electrode 15, a TFT 30, and a storage capacitor 16 are provided in an area divided by the scanning line 3a and the data line 6a, and these constitute a pixel circuit of the pixel P.

The scanning line 3 a is electrically connected to the gate of the TFT 30, and the data line 6 a is electrically connected to the source of the TFT 30. The pixel electrode 15 is electrically connected to the drain of the TFT 30.
The data line 6a is connected to the data line driving circuit 101 (see FIG. 1), and supplies image signals D1, D2,..., Dn supplied from the data line driving circuit 101 to the pixels P. The scanning line 3a is connected to a scanning line driving circuit 102 (see FIG. 1), and supplies scanning signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 102 to each pixel P. The image signals D1 to Dn supplied from the data line driving circuit 101 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 102 supplies the scanning signals SC1 to SCm to the scanning line 3a in a pulse-sequential manner at a predetermined timing.

In the liquid crystal device 100, the TFT 30 that is a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 15 at a predetermined timing. It is the structure written in. The predetermined level of image signals D1 to Dn written to the liquid crystal layer 50 via the pixel electrode 15 is held for a certain period between the pixel electrode 15 and the common electrode 23 arranged to face each other via the liquid crystal layer 50. The
In order to prevent the held image signals D1 to Dn from leaking, the holding capacitor 16 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 15 and the common electrode 23. The storage capacitor 16 is provided between the drain of the TFT 30 and the capacitor line 3b. As will be described in detail later, in this embodiment, the storage capacitor 16 has a light-transmitting property, and is disposed on the element substrate 10 so as to overlap with the pixel electrode 15 having the same light-transmitting property in a plane. One of a pair of translucent capacitive electrodes constituting the storage capacitor 16 functions as a capacitive line 3b straddling a plurality of pixels P. The capacitor line 3b is connected to a fixed potential such as LCCOM applied to the common electrode 23, for example.

  Note that a data line 6a is connected to the inspection circuit 103 shown in FIG. 1A, and an operation defect or the like of the liquid crystal device 100 is confirmed by detecting the image signal in the manufacturing process of the liquid crystal device 100. Although it can be configured, it is omitted in the equivalent circuit of FIG. The inspection circuit 103 includes a sampling circuit that samples the image signal and supplies it to the data line 6a, and a precharge circuit that supplies a precharge signal of a predetermined voltage level to the data line 6a prior to the image signal. Also good.

  Such a liquid crystal device 100 is a transmission type, and adopts an optical design of a normally black mode in which a dark display is obtained when the pixel P is not driven and a normally white mode in which a bright display is obtained when the pixel P is not driven. Depending on the optical design, polarizing elements are respectively used on the light incident side and the light exit side.

  Next, the planar arrangement and structure of the pixel P will be described with reference to FIGS. 3 is a schematic plan view showing the arrangement of pixels in the liquid crystal device, FIG. 4A is a schematic plan view showing the arrangement of thin film transistors and signal lines in the pixel, and FIG. 3B is a pair of capacitors of the storage capacitors in the pixel. 5 is a schematic plan view showing the arrangement of electrodes and pixel electrodes, FIG. 5 is a schematic cross-sectional view showing the structure of the pixel cut along line AA ′ in FIG. 4, and FIG. 6 is a pixel cut along line BB ′ in FIG. It is a schematic sectional drawing which shows this structure.

  As shown in FIG. 3, the pixel P in the liquid crystal device 100 has, for example, a substantially quadrangular (substantially square) opening region in plan view. The opening area is surrounded by a light-shielding non-opening area extending in the X direction and the Y direction and provided in a lattice shape.

  A scanning line 3a shown in FIG. 2 is provided in the non-opening region extending in the X direction. The scanning line 3a uses a light-shielding conductive member, and at least a part of the non-opening region is constituted by the scanning line 3a.

  Similarly, a data line 6a shown in FIG. 2 is provided in the non-opening region extending in the Y direction. The data line 6a also uses a light-shielding conductive member, and at least a part of the non-opening region is constituted by these.

  The non-opening region is formed not only by the signal lines provided on the element substrate 10 side but also by a light shielding portion patterned in a lattice pattern on the counter substrate 20 side.

  The TFT 30 shown in FIG. 2 is provided near the intersection of the non-opening regions. By providing the TFT 30 in the vicinity of the intersection of the non-opening region having the light shielding property, the optical malfunction of the TFT 30 is prevented and the aperture ratio in the opening region is secured. Although the detailed structure of the pixel P will be described later, the width of the non-opening region in the vicinity of the intersecting portion is wider than that in other portions due to the provision of the TFT 30 near the intersecting portion.

Next, each component such as a thin film transistor in the pixel circuit of the pixel P will be described with reference to FIGS.
As shown in FIG. 4, the pixel P includes a TFT 30 provided at the intersection of the scanning line 3a and the data line 6a. The TFT 30 includes a first source / drain region 30s, a channel region 30c, a second source / drain region 30d, a junction region 30e provided between the first source / drain region 30s and the channel region 30c, a channel The semiconductor layer 30a has an LDD (Lightly Doped Drain) structure having a junction region 30f provided between the region 30c and the second source / drain region 30d. The semiconductor layer 30a is disposed so as to pass through the intersection and overlap the scanning line 3a.

  The scanning line 3a has a substantially quadrilateral expansion portion in a plan view expanded in the X and Y directions at the intersection with the data line 6a. A bent gate electrode 30g having an opening that planarly overlaps the extended portion and does not overlap the junction region 30f and the second source / drain region 30d is provided.

  In the gate electrode 30g, the portion extending in the Y direction overlaps the channel region 30c in a plane. Further, the scanning lines 3a and CNT4 are bent by contact holes CNT3 and CNT4 that are bent from the portion overlapping the channel region 30c and extend in the X direction, and the portions facing each other are provided between the extended portions of the scanning line 3a. Electrically connected.

  The contact holes CNT3 and CNT4 are rectangular (rectangular) having a long X direction in plan view, and are provided on both sides so as to sandwich the junction region 30f along the channel region 30c and the junction region 30f of the semiconductor layer 30a. Yes.

The data line 6a extends in the Y direction, and has a substantially rectangular extension at the intersection with the scanning line 3a. The contact hole CNT1 is provided in the protrusion 6c protruding from the extension in the X direction. Is electrically connected to the first source / drain region 30s. A portion including the contact hole CNT1 is a source electrode 31. On the other hand, the contact hole CNT2 is also provided at the end of the second source / drain region 30d, and the portion including the contact hole CNT2 serves as the drain electrode 32.
Contact holes CNT6, CNT5, and CNT7 are provided adjacent to the contact hole CNT2 in the extending direction (X direction) of the scanning line 3a. The contact hole CNT2 and the contact hole CNT5 are electrically connected via a first relay electrode 6b provided in an island shape. The contact hole CNT6 and the contact hole CNT7 are electrically connected via the second relay electrode 7b provided in the same island shape.

As shown in FIG. 4B, the pixel electrode 15 is arranged so as to overlap the above-described opening region (see FIG. 3) in a plan view and the outer edge portion covers the non-opening region (see FIG. 3). Further, the pixel electrode 15 has a protrusion 15a for electrical connection with the contact hole CNT6. That is, the pixel electrode 15 has a substantially rectangular (substantially square) island shape provided for each pixel P.
The storage capacitor 16 includes a first capacitor electrode 16a and a second capacitor electrode 16c as a pair of translucent capacitor electrodes. The second capacitor electrode 16c is provided for each pixel P so as to overlap the pixel electrode 15 in the above-described opening region (see FIG. 3). The second capacitor electrode 16c has a projecting portion 16ca for electrical connection with the contact hole CNT7. That is, the second capacitor electrode 16 c has a substantially quadrangular (substantially square) island shape like the pixel electrode 15.

  On the other hand, the first capacitor electrode 16a is provided so as to straddle a plurality of pixels P arranged in a matrix in the X direction and the Y direction. The first capacitor electrode 16a has an opening 16ah that is opened for each pixel P in a portion overlapping the scanning line 3a. Inside the opening 16ah, a contact hole CNT6 to which the pixel electrode 15 is electrically connected and a contact hole CNT7 to which the second capacitor electrode 16c is electrically connected are provided. That is, the first capacitor electrode 16a is provided so as to extend over the pixel region E without being electrically connected to the contact holes CNT6 and CNT7, and has the function of the capacitor line 3b common to the plurality of pixels P. Yes. A part of the first capacitor electrode 16a is drawn outside the pixel region E and is electrically connected to a wiring to which a fixed potential is supplied.

  As shown in FIG. 5, the scanning line 3 a is first formed on the element substrate 10. The scanning line 3a also serves as a light-shielding film that shields the semiconductor layer 30a. For example, the scanning line 3a includes a metal simple substance including at least one of metals such as Al, Ti, Cr, W, Ta, and Mo, an alloy, a metal silicide, and a polycrystal. Silicide, nitride, or a laminate of these can be used and has light shielding properties.

  A base insulating film 10a made of, for example, silicon oxide is formed so as to cover the scanning line 3a, and a semiconductor layer 30a is formed in an island shape on the base insulating film 10a. The semiconductor layer 30a is made of, for example, a polycrystalline silicon film, and is implanted with impurity ions to have the first source / drain region 30s, the junction region 30e, the channel region 30c, the junction region 30f, and the second source / drain region 30d. An LDD structure is formed.

  A first insulating film (gate insulating film) 11a made of, for example, silicon oxide is formed so as to cover the semiconductor layer 30a. Further, a gate electrode 30g is formed at a position facing the channel region 30c with the first insulating film 11a interposed therebetween. The gate electrode 30g can be formed using, for example, a polycrystalline silicon film, and at the same time, the scanning line 3a (expanded portion) and the gate electrode 30g are electrically passed through the base insulating film 10a and the first insulating film 11a. Contact holes CNT3 and CNT4 (not shown) to be connected are also formed.

  A second insulating film 11b made of, for example, silicon oxide is formed so as to cover the gate electrode 30g and the first insulating film 11a. A contact hole CNT1 penetrating through the first insulating film 11a and the second insulating film 11b overlapping the first source / drain region 30s of the semiconductor layer 30a is formed. Similarly, a contact hole CNT2 penetrating through the first insulating film 11a and the second insulating film 11b overlapping the second source / drain region 30d of the semiconductor layer 30a is formed. Subsequently, a conductive film made of a light-shielding metal such as Al is formed and patterned so as to cover the second insulating film 11b, thereby electrically connecting the first source / drain region 30s via the contact hole CNT1. A data line 6a connected to is formed. At the same time, the first relay electrode 6b electrically connected to the second source / drain region 30d through the contact hole CNT2 is formed.

  Subsequently, a first interlayer insulating film 12 is formed so as to cover the data line 6a and the first relay electrode 6b. The first interlayer insulating film 12 is made of, for example, silicon oxide, nitride, or oxynitride, and is subjected to a flattening process for flattening the surface unevenness caused by covering the region where the TFT 30 is provided. Examples of the planarization method include chemical mechanical polishing (CMP) and spin coating.

A contact hole CNT5 penetrating the first interlayer insulating film 12 is formed at a position overlapping the first relay electrode 6b. A conductive film made of a light-shielding metal such as Al is formed so as to cover the contact hole CNT5 and cover the first interlayer insulating film 12, and the wiring 7a and the contact hole CNT5 are formed by patterning the conductive film. And a second relay electrode 7b electrically connected to the first relay electrode 6b.
The wiring 7a is formed so as to overlap with the semiconductor layer 30a and the data line 6a of the TFT 30 in a plan view, and functions as a shield layer when given a fixed potential.

  A second interlayer insulating film 13 is formed so as to cover the wiring 7a and the second relay electrode 7b. The second interlayer insulating film 13 can also be formed using, for example, silicon oxide, nitride, or oxynitride, and is subjected to a planarization process such as a CMP process.

  Next, a transparent conductive film such as ITO, for example, is formed so as to cover the second interlayer insulating film 13, and is patterned so as to straddle a plurality of pixels P and have an opening 16 ah for each pixel P. A first capacitor electrode 16a is formed. A contact hole for electrically connecting the wiring 7a and the first capacitor electrode 16a may be provided in the second interlayer insulating film 13. This makes it possible to reduce the electrical resistance of the first capacitor electrode 16a that functions as the capacitor line 3b.

A dielectric layer 16b is formed to cover the first capacitor electrode 16a. As the dielectric layer 16b, a silicon nitride film, a single layer film such as humic oxide (HfO ₂ ), alumina (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), or at least one of these single layer films is used. A multilayer film in which two types of single-layer films are stacked can be used. The thickness is set to 20 nm to 40 nm in consideration of electric capacity. The dielectric layer 16b is such an extremely thin thin film and has high transparency to visible light.

A contact hole CNT7 penetrating the second interlayer insulating film 13 and the dielectric layer 16b is formed at a position overlapping the second relay electrode 7b inside the opening 16ah of the first capacitor electrode 16a. A transparent conductive film such as ITO is formed so as to cover the contact hole CNT7 and cover the dielectric layer 16b. By patterning the transparent conductive film, for example, a second conductive film is provided for each pixel P and has a protrusion 16ca. A capacitor electrode 16c is formed. The second capacitor electrode 16c is electrically connected to the second relay electrode 7b through the protrusion 16ca and the contact hole CNT7.
As a result, the first capacitor electrode 16a and the second capacitor electrode 16c are arranged to face each other with the dielectric layer 16b interposed therebetween, and the translucent storage capacitor 16 is configured.

  A third interlayer insulating film 14 is formed as an interlayer insulating film of the present invention so as to cover the storage capacitor 16. The third interlayer insulating film 14 can also be formed using, for example, silicon oxide, and is subjected to a planarization process such as a CMP process. In addition, chemically stable boron is prevented so that the third interlayer insulating film 14 is not altered or the film thickness is not changed in the formation process of the pixel electrode 15 that is subsequently formed using a photolithography method. It is preferable to cover with a silicon oxide film doped with. That is, the third interlayer insulating film 14 includes a first silicon oxide film on the storage capacitor 16 side and a second silicon oxide film laminated on the first silicon oxide film and doped with boron.

  Next, a contact hole CNT6 penetrating the second interlayer insulating film 13, the dielectric layer 16b, and the third interlayer insulating film 14 is formed at a position overlapping the second relay electrode 7b inside the opening 16ah of the first capacitor electrode 16a. Is done. A transparent conductive film such as ITO, for example, covering the contact hole CNT6 and covering the third interlayer insulating film 14 is formed. By patterning the transparent conductive film, the pixel electrode 15 having the protruding portion 15a is formed. A pixel electrode 15 is formed that is electrically connected to the second relay electrode 7b through the protrusion 15a and the contact hole CNT6.

  According to such a wiring structure of the element substrate 10, the drain electrode 32 of the TFT 30 is electrically connected to the pixel electrode 15 via the first relay electrode 6b, the contact hole CNT5, the second relay electrode 7b, and the contact hole CNT6. Is done. Further, it is electrically connected to the second capacitor electrode 16c of the storage capacitor 16 through the first relay electrode 6b, the contact hole CNT5, the second relay electrode 7b, and the contact hole CNT7.

  As shown in FIG. 6, in the opening region of the pixel P, a base insulating film 10 a, a first insulating film 11 a, a second insulating film 11 b, and a first interlayer insulating film 12 are sequentially formed on the transparent element substrate 10. A second interlayer insulating film 13, a translucent storage capacitor 16, a third interlayer insulating film 14, and a pixel electrode 15 are provided.

The element substrate 10 has a more complicated wiring structure than the counter substrate 20 due to the configuration of the pixel circuit. As described above, the base insulating film 10a, the first insulating film 11a, the second insulating film 11b, the first interlayer insulating film 12, the second interlayer insulating film 13 and the like are made of silicon oxide (silicon oxide film) or Since it is made of nitride or oxynitride, it has substantially the same refractive index (1.4 to 1.5 in the visible light region) as that of, for example, a quartz substrate constituting the element substrate 10. Therefore, since the refractive indexes are almost the same, the visible light transmitted through these layers (films) hardly reflects or refracts at the interface of the layers (films). Rate) is difficult to attenuate.
On the other hand, the structure from the storage capacitor 16 to the pixel electrode 15 includes a first capacitor electrode 16a and a second capacitor made of a transparent conductive film (if ITO, the refractive index is 1.9 to 2.0 in the visible light wavelength region). The dielectric layer 16b is sandwiched between the capacitor electrode 16c, and the third interlayer insulating film 14 is sandwiched between the second capacitor electrode 16c and the pixel electrode 15 which are also made of a transparent conductive film. In other words, since the dielectric layer 16b and the third interlayer insulating film 14 having different (low) refractive index from the transparent conductive film are sandwiched between the transparent conductive films, the layers (films) are transmitted. The visible light that interferes with the reflected light reflected at the interface of the layer (film), and the light intensity (transmittance) may be attenuated. The dielectric layer 16b has a thickness of 20 nm to 40 nm from the viewpoint of securing electric capacity as described above. In this film thickness range, the light transmittance in the aperture region is hardly affected.

  In the present embodiment, the pixel electrode 15 and the first capacitor electrode 16a are set so that the spectral distribution of the light (transmitted light) transmitted through the aperture region of the pixel P is 96% or more in the visible light wavelength region (400 nm to 700 nm). The film thicknesses of the second capacitor electrode 16c and the third interlayer insulating film 14 are set. For example, the pixel electrode 15 has a thickness of 100 nm to 200 nm, the first capacitor electrode 16a and the second capacitor electrode 16c have a thickness of approximately 140 nm, and the third interlayer insulating film 14 has a thickness of approximately 175 nm. In addition, the value of each film thickness is not limited to this.

  Next, the global level difference to be improved by the present invention will be described with reference to FIG. FIG. 7 is a schematic cross-sectional view showing a global level difference of an element substrate in a conventional liquid crystal device. Note that the same components as those of the liquid crystal device 100 of the present embodiment will be described with the same reference numerals.

As shown in FIG. 7, first, a third interlayer insulating film 14 having a film thickness of, for example, 500 nm is formed so as to cover the plurality of storage capacitors 16 arranged in the pixel region E on the element substrate 10. Then, the CMP process is performed on the surface of the formed third interlayer insulating film 14 until the film thickness becomes approximately 175 nm as described above. Then, the difference in the wiring structure under the third interlayer insulating film 14 between the pixel region E where the storage capacitor 16 is formed and the peripheral region Ec where the storage capacitor 16 is not formed (the degree of density of the wiring pattern). Because of this, the polishing rate and the like differ, so that a global step 14b occurs between the pixel region E and the peripheral region Ec of the third interlayer insulating film 14. The size of the global step 14 b is approximately 300 nm corresponding to the total thickness of the storage capacitor 16. Such a global step 14b causes uneven thickness of the liquid crystal layer 50 (see FIG. 1B) and uneven alignment of liquid crystal molecules when the element substrate 10 and the counter substrate 20 are bonded together to enclose the liquid crystal later. The display was uneven.
In order to prevent the global step 14b from occurring after the CMP process, it may be considered that the CMP process is performed after the third interlayer insulating film 14 is formed with a thickness greater than 500 nm, for example, 1000 nm. However, the CMP treatment time required until the film thickness reaches about 175 nm is increased. Further, for example, when the third interlayer insulating film 14 is formed with a film thickness of 1000 nm, the film thickness variation increases, and there is a problem that it is difficult to obtain a stable film thickness after the CMP process. Therefore, it is desired to reduce the film thickness of the third interlayer insulating film 14 before the CMP process as much as possible, and to form the third interlayer insulating film 14 having a desired film thickness while suppressing the time required for the planarization process.

  Therefore, in the manufacturing process of the liquid crystal device 100 of the present embodiment, a dummy pattern is formed in the peripheral region Ec in the same wiring layer as the storage capacitor 16 in the element substrate 10 (dummy pattern forming process). A third interlayer insulating film 14 was formed so as to cover (interlayer insulating film forming step). A planarization process was performed on the formed third interlayer insulating film 14 (a planarization process step). Then, the pixel electrode 15 was formed on the third interlayer insulating film 14 that had been subjected to the planarization process (pixel electrode forming step). Hereinafter, examples will be described.

Example 1
FIG. 8 is a schematic plan view showing an arrangement region of dummy patterns in the liquid crystal device of Example 1, FIG. 9A is a schematic plan view showing arrangement of dummy patterns of Example 1, and FIG. It is the schematic sectional drawing cut by CC 'line of a).

  As shown in FIG. 8, in Example 1, in the element substrate 10, the pixel region E, the plurality of external connection terminals 104, and the four vertical conduction portions 106 provided at positions corresponding to the corners of the counter substrate 20. And the peripheral region Ec (the region hatched with diagonal lines in FIG. 8) excluding the four inspection terminal portions 107 arranged along two opposite sides in the X direction in order to check the element characteristics of the pixel P ) In the same wiring layer as the storage capacitor 16.

As shown in FIGS. 9A and 9B, the dummy pattern Dp1 includes a first capacitor electrode 16a as a first conductive layer, a dielectric layer 16b, and a peripheral region Ec that surrounds the pixel region E. And the second conductive layer 17. The first conductive layer is the same wiring layer as the first capacitor electrode 16a, is configured with the same material and the same film thickness, and the first capacitor electrode 16a is continuously formed up to the peripheral region Ec. Similar to the first capacitor electrode 16a, the dielectric layer 16b is also formed continuously to the peripheral region Ec. The second conductive layer 17 is composed of the same material and the same film thickness in the same wiring layer as the second capacitor electrode 16c, and has the same arrangement pitch and substantially the same shape as the second capacitor electrode 16c in the pixel region E (square in plan view). Are formed independently. Therefore, the second conductive layer 17 is in an electrically floating state.
Further, the dummy pattern Dp1 is formed to have substantially the same step density with respect to the storage capacitor 16.

FIG. 10 is a schematic diagram for explaining the step density. As shown in FIG. 10, the level difference of the storage capacitor 16 in the pixel P is caused by the second capacitor electrode 16 c formed independently for each pixel P. When the arrangement pitch of the pixels P is set to 7 μm, for example, the peripheral length S of the second capacitor electrode 16 c having a quadrangular outer shape overlapping the pixel electrode 15 in plan view is set to about 25 μm. As described above, when the film thickness t of the second capacitor electrode 16c is 140 nm (0.14 μm), the area of the side surface of the second capacitor electrode 16c, that is, the step area, is t × S = 0.14 μm × 25 μm≈3.5 μm. ² The area of one pixel P is the square of the arrangement pitch, that is, 7 μm × 7 μm≈49 μm ² . Step density as a unit area, for example 1 pixel P, which for can be represented by the ratio of the step area, a 3.5μm ² / 49μm ² ≒ 0.071. If the dummy pattern Dp1 is formed so as to be almost equal to the step density, the wiring structure in the lower layer of the third interlayer insulating film 14 can be made substantially equal in the pixel region E and the peripheral region Ec. Specifically, in the peripheral region Ec, the first capacitor electrode 16a is continuously formed from the pixel region E, and the dielectric layer 16b is formed so as to cover the first capacitor electrode 16a, and then the second capacitor electrode 16c. The second conductive layer 17 is formed by patterning so as to have the same film thickness t and the same peripheral length S. Note that the step density need only be substantially equal to the storage capacitor 16 in the pixel P, and thus the planar shape of the second conductive layer 17 does not necessarily have to be the same square as the second capacitor electrode 16c.

A third interlayer insulating film 14 having a film thickness of, for example, 500 nm is formed so as to cover the dummy pattern Dp1 and the storage capacitor 16 arranged based on the step density (interlayer insulating film forming step). Then, a CMP process is performed on the surface of the formed third interlayer insulating film 14, and the thickness of the CMP-processed surface is about 175 nm as described above using a method such as dry etching or wet etching. Etch uniformly (planarization process). Then, as shown in FIG. 9B, a third interlayer insulating film 14 having a substantially flat surface 14a from the pixel region E to the peripheral region Ec can be formed. Then, an ITO film is formed to cover the surface 14a of the third interlayer insulating film 14, and patterned to form a plurality of pixel electrodes 15 (pixel electrode forming step). Therefore, the global level difference 14b as shown in FIG. 7 is reliably eliminated.
Further, according to the trial result of the dummy pattern Dp1, if the step density of the storage capacitor 16 per pixel P in the pixel region E is “1”, the step density of the dummy pattern Dp1 is 0.5 or more. The global level difference 14b can be eliminated. From the viewpoint of eliminating the global step 14b, the step density of the dummy pattern Dp1 is preferably larger than the step density of the storage capacitor 16.

(Example 2)
FIG. 11A is a schematic plan view showing the arrangement of the dummy patterns of Example 2, and FIG. 11B is a schematic cross-sectional view taken along the line DD ′ of FIG. In the second embodiment, a dummy pattern is arranged in the peripheral area Ec shown in FIG.

  As shown in FIGS. 11A and 11B, in Example 2, the dummy pattern Dp2 is arranged in the peripheral region Ec surrounding the pixel region E. The dummy pattern Dp2 is the same wiring layer as the first capacitor electrode 16a as the first conductive layer, the dielectric layer 16b, and the second capacitor electrode 16c formed continuously from the pixel region E to the peripheral region Ec. The second conductive layer 17a has the same material and the same film thickness and is continuously formed across the peripheral region Ec. The second conductive layer 17a is in an electrically floating state.

  A third interlayer insulating film 14 having a film thickness of, for example, 500 nm is formed so as to cover the dummy pattern Dp2 and the storage capacitor 16 (interlayer insulating film forming step). Then, a CMP process is performed on the surface of the formed third interlayer insulating film 14, and the thickness of the CMP-processed surface is about 175 nm as described above using a method such as dry etching or wet etching. Etch uniformly (planarization process). Then, as shown in FIG. 11B, a third interlayer insulating film 14 having a substantially flat surface 14a from the pixel region E to the peripheral region Ec can be formed. Then, an ITO film is formed to cover the surface 14a of the third interlayer insulating film 14, and patterned to form a plurality of pixel electrodes 15 (pixel electrode forming step). Therefore, the global level difference 14b as shown in FIG.

  Furthermore, according to the arrangement of the dummy pattern Dp2 of the second embodiment, the second conductive layer 17a is continuously formed across the peripheral region Ec, so that the second conductive layer 17 is formed independently of the first embodiment. Thus, a local step due to the arrangement of the second conductive layer 17 in the peripheral region Ec can be eliminated.

According to the embodiment described above, the following effects can be obtained.
(1) According to Example 1 or Example 2, for each pixel P, a pixel region in which the translucent storage capacitor 16 and the translucent pixel electrode 15 overlap in plan view through the third interlayer insulating film 14 In the peripheral region Ec of E, a dummy pattern Dp1 or a dummy pattern Dp2 formed of the same wiring layer as the storage capacitor 16 is disposed. Therefore, the wiring structure under the third interlayer insulating film 14 covering the storage capacitor 16 and the dummy pattern Dp1 or the dummy pattern Dp2 is substantially the same, and the third interlayer insulating film 14 is flattened by performing the planarization process. A surface 14a is formed. That is, the global level difference 14b that has conventionally occurred around the pixel region E can be eliminated. Therefore, display unevenness due to the global level difference 14b is reduced, and the liquid crystal device 100 having high display quality can be provided or manufactured.
(2) According to the dummy pattern Dp2 of the second embodiment, since the second conductive layer 17a is continuously formed in the peripheral region Ec, a plurality of second conductive layers are independently formed in an island shape as in the first embodiment. In contrast to the case where the layer 17 is formed, the local step in the peripheral region Ec can be eliminated.
(3) In Example 1 or Example 2, when the second conductive layers 17 and 17a constituting the dummy pattern Dp1 and the dummy pattern Dp2 are in an electrically floating state, a specific potential is applied. Compared to the above, there is no unnecessary electrical influence on the potential of the pixel electrode 15. Therefore, stable display quality can be obtained in the pixel region E.

(Second Embodiment)
<Electronic equipment>
FIG. 12 is a schematic diagram illustrating a configuration of a projection display device as an electronic apparatus. As shown in FIG. 12, a projection display apparatus 1000 as an electronic apparatus according to this embodiment includes a polarization illumination apparatus 1100 arranged along the system optical axis L, and two dichroic mirrors 1104 and 1105 as light separation elements. Three reflection mirrors 1106, 1107, 1108, five relay lenses 1201, 1202, 1203, 1204, 1205, three transmissive liquid crystal light valves 1210, 1220, 1230 as light modulation means, and a light combining element As a cross dichroic prism 1206 and a projection lens 1207.

  The polarized light illumination device 1100 is generally configured by a lamp unit 1101 as a light source composed of a white light source such as an ultra-high pressure mercury lamp or a halogen lamp, an integrator lens 1102, and a polarization conversion element 1103.

  The dichroic mirror 1104 reflects red light (R) and transmits green light (G) and blue light (B) among the polarized light beams emitted from the polarization illumination device 1100. Another dichroic mirror 1105 reflects the green light (G) transmitted through the dichroic mirror 1104 and transmits the blue light (B).

The red light (R) reflected by the dichroic mirror 1104 is reflected by the reflection mirror 1106 and then enters the liquid crystal light valve 1210 via the relay lens 1205.
Green light (G) reflected by the dichroic mirror 1105 enters the liquid crystal light valve 1220 via the relay lens 1204.
The blue light (B) transmitted through the dichroic mirror 1105 enters the liquid crystal light valve 1230 via a light guide system including three relay lenses 1201, 1202, 1203 and two reflection mirrors 1107, 1108.

  The liquid crystal light valves 1210, 1220, and 1230 are disposed to face the incident surfaces of the cross dichroic prism 1206 for each color light. The color light incident on the liquid crystal light valves 1210, 1220, and 1230 is modulated based on video information (video signal) and emitted toward the cross dichroic prism 1206. In this prism, four right-angle prisms are bonded together, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface thereof. The three color lights are synthesized by these dielectric multilayer films, and the light representing the color image is synthesized. The synthesized light is projected on the screen 1300 by the projection lens 1207 which is a projection optical system, and the image is enlarged and displayed.

  The liquid crystal light valve 1210 is the one to which the liquid crystal device 100 of the first embodiment described above is applied. The liquid crystal device 100 is arranged with a gap between a pair of polarizing elements arranged in crossed Nicols on the incident side and the emission side of colored light. The same applies to the other liquid crystal light valves 1220 and 1230.

  According to such a projection display device 1000, the liquid crystal device 100 that can obtain high transmittances for red, green, and blue color light in the opening region of the pixel P is used as the liquid crystal light valves 1210, 1220, and 1230. Therefore, bright display quality is realized by effectively using the light emitted from the polarization illumination device 1100.

  In addition, the fact that a high transmittance can be obtained in the opening area of the pixel P means that the reflectance of light transmitted through the opening area is lowered. As a result, the probability that the reflected light is transmitted again through the liquid crystal layer 50 is reduced. (Light degradation) is improved.

Of the polarized light beams emitted from the polarization illumination device 1100 as the light source, the pixel P is compared with the peak wavelength of the light intensity in the spectral distribution of red light (R), green light (G), and blue light (B). The film thicknesses and ranges of the first capacitor electrode 16a, the second capacitor electrode 16c, the pixel electrode 15, and the third interlayer insulating film 14 in the liquid crystal device 100 are set so that the peak wavelengths of the transmittance of light transmitted through Each is preferably set and used. According to this, the light utilization efficiency can be further enhanced. Note that “substantially match” refers to a state in which the peak of the transmittance of the color light transmitted through the pixel P appears in a wavelength range within ± 5% with respect to the peak wavelength of the light intensity of the color light emitted from the light source.
Further, for example, when the spectral distribution of blue light (B) is cut to 430 nm to 500 nm by cutting ultraviolet light having a wavelength shorter than 430 nm, and the light resistance lifetime of the liquid crystal device 100 is further improved, the transmittance falls within the wavelength range. The film thicknesses and ranges of the first capacitor electrode 16a, the second capacitor electrode 16c, the pixel electrode 15, and the third interlayer insulating film 14 are set so that the peaks of the first and second capacitor electrodes 16a, 16c, 15c and 14 are reached.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification. The manufacturing method of the electro-optical device and the electronic apparatus to which the electro-optical device is applied are also included in the technical scope of the present invention. Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

  (Modification 1) The configuration of the dummy patterns Dp1, Dp2 arranged in the peripheral region Ec surrounding the pixel region E is not limited to this. For example, the first conductive layer in the same wiring layer as the first capacitor electrode 16a and the second conductive layer in the same wiring layer as the second capacitor electrode 16c may be formed independently in an island shape in the peripheral region Ec. According to this, both the first conductive layer and the second conductive layer can be brought into an electrically floating state.

  (Modification 2) In the above embodiment, the configuration of the storage capacitor 16 is not limited to this. For example, one capacitor electrode that functions as the capacitor line 3b across a plurality of pixels P is disposed on the side close to the pixel electrode 15, and is formed for each pixel P with the dielectric layer 16b sandwiched between the one capacitor electrode and the lower layer. The other capacitor electrode may be arranged.

(Modification 3) The electro-optical device to which the dummy patterns Dp1, Dp2 of the above embodiment can be applied is not limited to the transmissive liquid crystal device 100. For example, the present invention can also be applied to a reflective liquid crystal device in which the pixel electrode 15 is formed using Al (aluminum), Ag (silver), or an alloy thereof having light reflectivity. According to this, since the third interlayer insulating film 14 is flat and the film thickness variation is small, a reflective liquid crystal device having stable light reflection characteristics in the pixel region E can be provided.
Furthermore, the present invention is not limited to the light receiving type liquid crystal device 100, and can be applied to an organic EL device provided with a self-luminous type, for example, an organic electroluminescence (EL) element. Thereby, stable optical characteristics (light emission characteristics) can be obtained.

  (Modification 4) An electronic apparatus to which the liquid crystal device 100 of the above embodiment can be applied is not limited to the projection display device 1000 of the above embodiment. For example, projection-type HUD (head-up display), direct-view type HMD (head-mounted display), electronic book, personal computer, digital still camera, LCD TV, viewfinder type or monitor direct-view type video recorder, car navigation system It can be suitably used as a display unit of an information terminal device such as an electronic notebook or POS.

  3b ... capacitor line, 10 ... element substrate as substrate, 14 ... third interlayer insulating film as interlayer insulating film, 15 ... pixel electrode, 16 ... retention capacitor, 16a ... first capacitor electrode, 16b ... dielectric layer, 16c ... second capacitance electrode, 17, 17a ... second conductive layer, 100 ... liquid crystal device as electro-optical device, 1000 ... projection type display device as electronic device, Dp1, Dp2 ... dummy pattern, E ... pixel region, Ec ... Peripheral area, P ... pixel.

Claims (12)

A pixel electrode on the substrate;
A storage capacitor disposed between the pixel electrode and the substrate so as to overlap the pixel electrode in plan view;
An interlayer insulating film formed between the pixel electrode and the storage capacitor and subjected to planarization;
An electro-optical device, comprising: a dummy pattern disposed in a peripheral region of a pixel region including a plurality of the pixel electrodes and formed in the same wiring layer as the storage capacitor. The step area per unit area is defined as the step density,
The electro-optical device according to claim 1, wherein the step density of the storage capacitor in the pixel region is substantially equal to the step density of the dummy pattern in the peripheral region. The step area per unit area is defined as the step density,
The electro-optical device according to claim 1, wherein the step density of the dummy pattern in the peripheral region is larger than the step density of the storage capacitor in the pixel region. The storage capacitor includes a first capacitor electrode that functions as a capacitor line across a plurality of pixels, a second capacitor electrode formed independently for each pixel, the first capacitor electrode, and the second capacitor electrode. Consisting of sandwiched dielectric layers,
The dummy pattern includes a first conductive layer and a second conductive layer disposed to face the first conductive layer via the dielectric layer,
The first capacitor electrode and the first conductive layer are continuously formed across the pixel region and the peripheral region in the same wiring layer,
4. The electro-optical device according to claim 1, wherein the second capacitor electrode and the second conductive layer are independently formed in the same wiring layer. 5. The storage capacitor includes a first capacitor electrode that functions as a capacitor line across a plurality of pixels, a second capacitor electrode formed independently for each pixel, the first capacitor electrode, and the second capacitor electrode. Consisting of sandwiched dielectric layers,
The dummy pattern includes a first conductive layer and a second conductive layer disposed to face the first conductive layer via the dielectric layer,
The first capacitor electrode and the first conductive layer are continuously formed across the pixel region and the peripheral region in the same wiring layer,
The electro-optical device according to claim 1, wherein the second conductive layer is continuously formed across the peripheral region in the same wiring layer as the second capacitor electrode.   The electro-optical device according to claim 4, wherein at least one of the first conductive layer and the second conductive layer is in an electrically floating state.   The electro-optical device according to claim 1, wherein each of the pixel electrode, the interlayer insulating film, and the storage capacitor has a light-transmitting property.   The electro-optical device according to claim 1, wherein the pixel electrode has light reflectivity. A method of manufacturing an electro-optical device comprising: a pixel electrode on a substrate; and a storage capacitor that is disposed between the pixel electrode and the substrate in a plan view so as to overlap the pixel electrode,
Forming the storage capacitor for each pixel in the pixel region, and forming a dummy pattern in a peripheral region of the pixel region in the same wiring layer as the storage capacitor;
Forming an interlayer insulating film covering the storage capacitor and the dummy pattern;
A step of planarizing the surface of the formed interlayer insulating film;
And a step of forming the pixel electrode on the interlayer insulating film that has been subjected to planarization. A method for manufacturing an electro-optical device, comprising: The step area per unit area is defined as the step density,
The method of manufacturing the electro-optical device according to claim 9, wherein the dummy pattern is formed so that the step density of the storage capacitor and the dummy pattern are substantially equal. The step area per unit area is defined as the step density,
The method of manufacturing an electro-optical device according to claim 9, wherein the dummy pattern is formed so that the step density of the dummy pattern is larger than the step density of the storage capacitor.   An electronic apparatus comprising the electro-optical device according to claim 1.

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