JP2013074044A - Chip resistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chip resistor capable of reducing damage due to a heat shock in a solder joint.SOLUTION: A rear electrode 3 of a chip resistor 1 includes a first electrode layer 3a consisting of sintered silver fixed to the rear surface of a ceramic substrate 2, and a second electrode layer 3b consisting of sintered silver laminated in an area crossing a central part of the first electrode layer 3a. A step 12 extending from the side surface of the second electrode layer 3b to the surface of the first electrode layer 3a is formed and a step 13 corresponding to the step 12 is formed in a part of a plated layer (a nickel plated layer 9 and a solder plated layer 10) covering the rear electrode 3. Accordingly, since there is not a risk that thickness of the solder joint (solder 32) interposed between the rear electrode 3 and a land 31 is increased in a part of the step 13 when the chip resistor 1 is mounted on a circuit board 30, and thermal stress is concentrated in a boundary part between the first and second electrode layers 3a and 3b, damage due to a heat shock in the solder joint can be reduced.

Description

  The present invention relates to a chip resistor, and more particularly to improvement of a back electrode provided on a back surface of a ceramic substrate, which is soldered at the time of mounting.

  FIG. 6 is a cross-sectional view schematically showing a conventional general chip resistor. The chip resistor 21 shown in the figure is made of a rectangular parallelepiped ceramic substrate 22, a pair of surface electrodes 23 made of sintered silver or the like provided at both ends in the longitudinal direction of the upper surface of the ceramic substrate 22, and ruthenium oxide or the like. A resistor 24 provided between the pair of surface electrodes 23, an insulating protective layer 25 covering the resistor 24, and provided at both ends in the longitudinal direction of the lower surface of the ceramic substrate 22 made of sintered silver or the like. A pair of back surface electrodes 26 and a pair of end surface electrodes 27 provided on both end surfaces in the longitudinal direction of the ceramic substrate 22 to bridge the front surface electrode 23 and the back surface electrode 26. A plating layer 28 is attached to the front surface electrode 23, the end surface electrode 27, and the back surface electrode 26 that are continuous in a shape.

  In the chip resistor 21, the ceramic substrate 22 is obtained by dividing a large substrate along a vertical and horizontal dividing groove, and a large number of ceramic substrates 22 are obtained. The back electrode 26, the protective layer 25, and the like are collectively formed. The resistance value of the chip resistor 21 is adjusted by forming a trimming groove (not shown) in the resistor 24. The protective layer 25 generally has a two-layer structure, and an undercoat layer formed before adjusting the resistance value for trimming the resistor 24 and an overcoat layer formed after adjusting the resistance value are laminated. ing. The end surface electrode 27 is formed on a split surface of a strip-shaped substrate obtained by first dividing a large substrate on which a large number of protective layers 25 are formed. After the end surface electrode 27 is formed, the strip-shaped substrate is separated into pieces ( The chip layer is divided into two parts, and the plated layer 28 is deposited on each chip. This plating layer 28 includes an innermost nickel (Ni) plating layer in close contact with the base electrode layer, and an outermost solder (Sn / Pb) plating layer or tin (Sn) plating layer exposed on the outer surface. It has a laminated structure of more than one layer.

  By the way, this type of chip resistor 21 is surface-mounted by mounting a back electrode 26 on a land provided on a circuit board and soldering, but the thermal environment changes to the chip resistor 21 after mounting. Is repeated (hereinafter referred to as heat shock), the solder joints are easily damaged by thermal stress and cracks are likely to occur. When a crack due to heat shock occurs in the solder joint, the solder joint is a place where the back electrode 26 of the chip resistor 21 and the land of the circuit board are electrically and mechanically connected. It sometimes led to poor continuity.

  Therefore, conventionally, a chip resistor has been proposed in which the back electrode has a two-layer structure of an inner layer made of baked silver and an outer layer made of a conductive resin so that thermal stress acting on the solder joint can be reduced (for example, , See Patent Document 1). In such a conventional chip resistor, since the outer layer of the back electrode that contacts the solder joint on the land of the circuit board is made of a conductive resin, it acts on the solder joint compared to the case where the back electrode is made only of sintered silver. The effect of relaxing the thermal stress is expected.

JP 2008-84905 A

  However, when the present inventors have scrutinized, even if the outer layer of the back electrode is formed of a conductive resin like the chip resistor described in Patent Document 1, the boundary between the outer layer and the inner layer made of sintered silver It has been found that if the portion is in contact with the solder joint, thermal stress concentrates on the solder joint at this boundary portion, and cracks are likely to occur. Furthermore, when the outer layer of the back electrode is formed of a conductive resin, outgas is generated from the resin component due to heating during solder bonding, and voids are formed in the joint due to this outgas. A decline is forced. Also, if the outer layer made of conductive resin completely covers the inner layer made of baked silver, the boundary between the two will not come into contact with the solder joint, but this will increase the amount of outgas generated from the resin, It is not preferable because the occurrence of explosion and the fixing property are weakened. Therefore, even if the conventional technique of forming the outer layer of the back electrode with a conductive resin is employed, the effect of preventing damage to the solder joint due to heat shock is insufficient, greatly increasing the useful life of the chip resistor. It is difficult to extend, and there is a demerit that solder explosion occurs and adhesion is weakened.

  The present invention has been made in view of the situation of the prior art as described above, and an object of the present invention is to provide a chip resistor in which a solder joint is less likely to be damaged by heat shock.

  In order to achieve the above object, the present invention provides a pair of surface electrodes provided at both longitudinal ends of the surface of the ceramic substrate, and the surface of the ceramic substrate so as to be connected to the pair of surface electrodes. A resistor, a pair of backside electrodes provided at both ends in the longitudinal direction of the back surface of the ceramic substrate, an insulating protective layer covering the resistor, and the surface provided at both end surfaces of the ceramic substrate. In a chip resistor comprising a pair of end face electrodes bridging an electrode and the back electrode, and surface-mounted by mounting the back electrode on a land provided on a circuit board and soldering, The back electrode is composed of a first electrode layer fixed to the back surface of the ceramic substrate and a second electrode layer laminated in a partial region deviating from at least the edge of the first electrode layer. Preliminary second electrode layer has the configuration that is one formed by any baked silver.

  Thus, in the back electrode formed by laminating the second electrode layer in a partial region of the first electrode layer, a step is formed from the side surface of the second electrode layer to the surface of the first electrode layer. Can be used to increase the thickness of the solder joint. Further, since both the first electrode layer and the second electrode layer are made of baked silver, there is no possibility that thermal stress is concentrated on the boundary portion between both electrode layers, and the manufacturing process of the back electrode is not particularly complicated. Therefore, this chip resistor is unlikely to be damaged by a heat shock at the solder joint interposed between the back electrode and the circuit board land, and it is easy to avoid an increase in cost.

  In the above configuration, the first electrode layer and the second electrode layer may be formed using different materials having different compositions as long as they are baked silver, but the first electrode layer and the second electrode layer have the same composition. When the same material is used, the first electrode layer and the second electrode layer can be formed using the same Ag paste or the like, so that the workability including the exchange of the Ag paste is improved.

  In the chip resistor according to the present invention, the second electrode layer is laminated on a partial region off the edge of the first electrode layer to form a back electrode, and both the first and second electrode layers are formed of sintered silver. Therefore, there is no risk of thermal stress concentrating on the boundary portion between the two electrode layers, and the thickness of the solder joint is increased by using a step from the side surface of the second electrode layer to the surface of the first electrode layer. Can do. Therefore, the possibility that the solder joint interposed between the back electrode and the land of the circuit board is damaged by heat shock is reduced. In addition, this chip resistor does not need to complicate the manufacturing process of the back electrode, and thus it is easy to avoid an increase in cost. Therefore, a chip resistor that is resistant to heat shock and has a long service life can be provided at low cost.

It is principal part sectional drawing which shows typically the mounting state of the chip resistor which concerns on the example of embodiment of this invention. It is explanatory drawing which shows the manufacturing process of this chip resistor. It is explanatory drawing which shows the manufacturing process of this chip resistor. It is explanatory drawing which shows the manufacturing process of this chip resistor. It is explanatory drawing which shows the manufacturing process of this chip resistor. It is sectional drawing which shows the conventional common chip resistor typically.

  Hereinafter, embodiments of the invention will be described with reference to the drawings. The chip resistor 1 according to the embodiment of the present invention is manufactured through the respective steps shown in FIGS. 2 to 4 and used by being surface-mounted on a circuit board 30 as shown in FIG. A completed product of the chip resistor 1 is shown at the bottom of FIG.

  The chip resistor 1 includes a rectangular parallelepiped ceramic substrate 2, a pair of back surface electrodes 3 provided at both ends in the longitudinal direction of the back surface (the lower surface in FIG. 1) of the ceramic substrate 2, and the front surface (see FIG. 1, a pair of surface electrodes 4 provided on both ends of the longitudinal direction of the upper surface), a resistor 5 provided on the surface of the ceramic substrate 2 with both ends overlapped with the pair of surface electrodes 4, and the ceramic substrate 2. A pair of end surface electrodes 6 provided on both end surfaces in the longitudinal direction of the substrate and bridging the back surface electrode 3 and the front surface electrode 4, and a protective layer (undercoat layer 7 and overcoat layer) covering the resistor 5 Layer 8) and a surface electrode 4 continuous in a U-shape as a base electrode layer and a two-layered plating layer (nickel plating layer 9 and solder plating layer 10) deposited on the end surface electrode 6 and the back surface electrode 3 Constitution It has been.

  The ceramic substrate 2 is an insulating substrate mainly composed of alumina, and is obtained by dividing a large-sized substrate 40 (see FIGS. 2 and 3), which will be described later, along a vertical and horizontal dividing grooves 41 and 42 and taking a large number. The main component of the back electrode 3 and the front electrode 4 is silver, and the main component of the end face electrode 6 is nickel and chromium. The resistor 5 is made of ruthenium oxide or the like, and the resistance value of the chip resistor 1 is adjusted by forming a trimming groove 11 (see FIG. 3) in the resistor 5. When manufacturing the chip resistor 1, a large number of front surface electrodes 4, resistors 5, back surface electrodes 3, undercoat layers 7, overcoat layers 8, and the like are collectively formed on the large substrate 40.

  Further, the back electrode 3 of the chip resistor 1 includes a first electrode layer 3a fixed to the back surface of the ceramic substrate 2, and a second electrode layer 3b stacked in a region crossing the central portion of the first electrode layer 3a. The first and second electrode layers 3a and 3b are both made of baked silver. Although a detailed manufacturing method will be described later, after the Ag paste is printed and the unfired first electrode layer 3a and the second electrode layer 3b are sequentially formed, the first and second Ag sintered bodies are obtained by firing at a high temperature. Second electrode layers 3a and 3b are formed. The second electrode layer 3b may be laminated in a region other than the central portion of the first electrode layer 3a to form the back electrode 3. In short, the surface of the first electrode layer 3a is formed from the side surface of the second electrode layer 3b. It is only necessary that the second electrode layer 3b is laminated in a partial region away from the edge of the first electrode layer 3a so that the step 12 leading to is formed.

  As shown in FIG. 1, the chip resistor 1 is surface-mounted by mounting a back electrode 3 on a land 31 provided on a circuit board 30 and joining with a solder 32. Since a step 13 corresponding to the step 12 is formed in a portion covering the back electrode 3 in the plating layer (nickel plating layer 9 and solder plating layer 10) of the chip resistor 1, this step 13 in the mounted state. Therefore, the thickness of the solder 32 is increased. Therefore, the solder joint (solder 32) interposed between the back electrode 3 and the land 31 is less likely to crack even when thermal stress is applied.

  Next, the manufacturing process (1st process-16th process) of this chip resistor 1 is demonstrated in detail, referring FIGS. The first to fifth steps will be described with reference to FIG. 2, the sixth to twelfth steps will be described with reference to FIG. 3, and the thirteenth to sixteenth steps will be described with reference to FIG. The description will be given with reference. In these drawings, a schematic sectional view corresponding to one chip region is shown on the left side, and a schematic plan view corresponding to a plurality of chip regions on the right side (however, in the first and second steps). A plan view on the back side) is shown.

  First, as a first step, an unfired first electrode layer 3a is formed by screen-printing and drying an Ag paste on the back surface 40a of a large substrate 40 on which a large number of ceramic substrates 2 are taken. The large-sized substrate 40 is provided with a primary dividing groove 41 and a secondary dividing groove 42 in a lattice shape in advance, and each of the squares divided by both the dividing grooves 41 and 42 is one chip. The first electrode layer 3a is continuously formed at one end in the longitudinal direction of one adjacent chip region and the other end in the longitudinal direction of the other chip region via the primary dividing groove 41.

  After the first electrode layer 3a is printed and dried in this way, as a second step, Ag paste is screen-printed in a region crossing the central portion of each first electrode layer 3a and dried, so that the unfired first electrode layer 3a is dried. A two-electrode layer 3b is formed. At this time, if the first electrode layer 3a and the second electrode layer 3b are formed using an Ag paste having the same composition, workability including exchanging of the Ag paste is improved. Then, these first and second electrode layers 3a and 3b form a laminated body having a reverse convex shape in sectional view at both ends in the longitudinal direction of each chip region, and this laminated body becomes the back electrode 3 in a fourth step to be described later. .

  Further, as a third step, the unfired surface electrode 4 is formed by screen-printing and drying the Ag / Pd paste on the surface 40b opposite to the back surface 40a of the large substrate 40. The formation position of the front electrode group 4 on the front surface 40b of the large substrate 40 substantially corresponds to the formation position of the first electrode layer 3a group on the rear surface 40a.

  Next, as the fourth step, the first and second electrode layers 3a and 3b and the surface electrode 4 are baked at a high temperature of about 850 ° C. If the first and second electrode layers 3a and 3b and the surface electrode 4 are fired at the same time as described above, the firing process can be reduced to reduce the cost. Thus, the first electrode layer 3a made of baked silver fixed in close contact with the back surface 40a of the large substrate 40, and the second electrode made of baked silver fixed in close contact with a partial region of the first electrode layer 3a. Since the electrode layer 3b is obtained, the first and second electrode layers 3a and 3b form the back electrode 3 having a reverse convex shape in sectional view made of sintered silver. A surface electrode 4 made of baked silver containing palladium is formed on the surface 40b of the large substrate 40. About this surface electrode 4, it becomes effective in a sulfidation-resistant characteristic by containing palladium.

  Thereafter, as a fifth step, a resistor paste such as ruthenium oxide is screen-printed on the surface 40b of the large substrate 40 and dried to form the unfired resistor 5 in each chip region. At that time, both ends in the longitudinal direction of the resistor 5 are overlapped with the surface electrodes 4 provided at both ends in the longitudinal direction of each chip region. In the next sixth step, the resistor 5 is fired at a high temperature of about 850 ° C. The firing in the fourth step described above may be omitted, and the first and second electrode layers 3a and 3b, the surface electrode 4 and the resistor 5 may be fired at the same time in this sixth step. It is possible to further reduce costs by further reducing the cost.

  Next, as a seventh step, after a glass paste is screen-printed in a region covering the resistor 5, the glass paste is baked at a high temperature of about 600 ° C. in the eighth step, so that the primary protection covering the resistor 5 is performed. An undercoat layer 7 corresponding to the coat is formed. The undercoat layer 7 is for preventing the vicinity of the trimming groove 11 of the resistor 5 from being damaged by the heat of the laser irradiated in the next step.

  Next, as a ninth step, the undercoat layer 7 and the resistor 5 are irradiated with a laser to form the trimming groove 11, thereby adjusting to a desired resistance value.

  Next, as a tenth step, a glass paste or an epoxy-based resin paste is screen-printed so as to cover the undercoat layer 7 and the trimming groove 11 and then baked in the eleventh step (for example, the glass paste is about 600 ° C. And the resin paste is heated and cured at about 200 ° C.) to form the overcoat layer 8 corresponding to the secondary protective coat covering the resistor 5 and the primary protective coat. This overcoat layer 8 is for protecting the resistor 5 from the external environment. By forming the undercoat layer 7 and the overcoat layer 8 in this way, a protective layer having a two-layer structure covering the resistor 5 is obtained.

  The process up to this point is a batch process for the large-sized substrate 40 for taking a large number of pieces. However, in the next twelfth step, the large-sized substrate 40 is divided into strips along the primary dividing grooves 41 by a break. Processing. As a result, a strip-shaped substrate 43 provided with a plurality of chip regions is obtained.

  Then, in the next thirteenth step, the end face electrode 6 is formed by sputtering Ni / Cr on the divided surface of the strip-shaped substrate 43. At this time, sputtering is performed in a state where a plurality of strip-shaped substrates 43 are overlapped. As shown in FIG. 5, the second electrode layer 3b of the upper strip-shaped substrate 43 is over the lower strip-shaped substrate 43. If it forms so that the coating layer 8 may be avoided, it can sputter | spatter in the state which the attitude | position of each strip-shaped board | substrate 43 was stabilized. As a result, the wraparound amount of the left and right spatters can be made uniform, so that it is difficult to cause electrode dimension defects. Then, the back electrode 3 and the front electrode 4 are bridged by this end face electrode 6, and a base electrode layer is obtained in which both 3 and 4 are continuous in a U-shape.

  Thereafter, as a fourteenth step, a secondary break process is performed in which the strip-shaped substrate 43 is divided along the secondary dividing grooves 42 by a break. Thereby, an individual piece (chip alone) having the same size as the chip resistor 1 is obtained.

  Next, as a fifteenth step, the nickel plating layer 9 is applied to the individual base electrode layer of each chip, and as a sixteenth step, the solder plating layer 10 is applied to the nickel plating layer 9. . Thereby, a plating layer having a two-layer structure covering the base electrode layer is obtained, and the chip resistor 1 is completed. The nickel plating layer 9 is for preventing silver erosion, and the solder plating layer 10 is for improving solder wettability. Although these plating layers 9 and 10 are formed by performing electrolytic plating, the solder plating layer 10 may be replaced with a tin plating layer. Alternatively, a copper (Cu) plating layer may be used instead of the nickel plating layer 9, and both a nickel plating layer and a copper plating layer may be formed to form a three-layer plating layer.

  As described above, the back electrode 3 of the chip resistor 1 according to this embodiment crosses the first electrode layer 3a fixed to the back surface of the ceramic substrate 2 and the central portion of the first electrode layer 3a. A step 12 is formed from the side surface of the second electrode layer 3b to the surface of the first electrode layer 3a. Therefore, a step 13 corresponding to the step 12 is formed in a portion covering the back electrode 3 in the plating layer (nickel plating layer 9 and solder plating layer 10) of the chip resistor 1. Therefore, when the chip resistor 1 is mounted on the circuit board 30, the thickness of the solder joint (solder 32) interposed between the back electrode 3 and the land 31 becomes a step as shown in FIG. It increases at 13 portions, and it is difficult for cracks to occur even when thermal stress is applied.

  In addition, since both the first electrode layer 3a and the second electrode layer 3b constituting the back electrode 3 are made of sintered silver, there is no possibility that thermal stress concentrates on the boundary portion between the electrode layers 3a and 3b. The manufacturing process is not particularly complicated. Therefore, the chip resistor 1 is unlikely to damage the solder joint (solder 32) interposed between the back electrode 3 and the land 31 of the circuit board 30 by heat shock, and avoids an increase in cost. Cheap. Therefore, the chip resistor 1 having a long useful life and inexpensive can be mass-produced.

  In the above embodiment, the second electrode layer 3b is stacked in a region crossing the central portion of the first electrode layer 3a. However, the second electrode layer 3b is formed at the edge of the first electrode layer 3a. As long as it is a partial region that is out of the region, the central portion is not necessarily required, and a plurality of second electrode layers may be dispersedly arranged in the first electrode layer.

DESCRIPTION OF SYMBOLS 1 Chip resistor 2 Ceramic substrate 3 Back surface electrode 3a 1st electrode layer 3b 2nd electrode layer 4 Surface electrode 5 Resistor 6 End surface electrode 7 Undercoat layer (protective layer)
8 Overcoat layer (protective layer)
9 Nickel plating layer 10 Solder plating layer 11 Trimming groove 12, 13 Step 30 Circuit board 31 Land 32 Solder (solder joint)
40 Large substrate 41, 42 Dividing groove

Claims (2)

A pair of surface electrodes provided at both longitudinal ends of the surface of the ceramic substrate, a resistor provided on the surface of the ceramic substrate so as to be connected to the pair of surface electrodes, and a longitudinal direction of the back surface of the ceramic substrate A pair of back electrodes provided at both ends, an insulating protective layer covering the resistor, and a pair provided on both ends of the ceramic substrate to bridge the surface electrode and the back electrode A chip resistor that is surface-mounted by mounting and soldering the back electrode on a land provided on a circuit board,
The back electrode is composed of a first electrode layer fixed to the back surface of the ceramic substrate and a second electrode layer laminated in a partial region deviating from at least the edge of the first electrode layer. A chip resistor characterized in that both the second electrode layer and the second electrode layer are formed of sintered silver.   2. The chip resistor according to claim 1, wherein the first electrode layer and the second electrode layer are formed of the same material having the same composition.

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