JP2013070035A - Multilayer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board which inhibits warpage while having inductors.SOLUTION: Inductors L1, L2 are formed in a core substrate 30 by a first conductor pattern and a first via conductor. First insulation layers 30M, 30A, 30B, 30C, 30D, 30E, 30F that form the core substrate 30 include an inorganic fiber reinforcement material. In other words, the inorganic fiber reinforcement material for improving rigidity is provided at the layers where the inductors L1, L2 are formed. Thus, the inorganic fiber reinforcement material allows thermal shrinkage of the insulation layers to be easily inhibited.

Description

The present invention relates to a multilayer printed wiring board in which a build-up layer having an insulating layer, a conductor pattern on the insulating layer, and a via conductor formed inside the insulating layer and connecting the conductor patterns to each other is provided on a core substrate It is about.

In Patent Document 1, an inductor is formed on a wiring board by electrically connecting conductor patterns formed in different layers. By using this technique, it is possible to suppress an increase in impedance.

JP 2009-16504 A

However, in the inductor as disclosed in Patent Document 1, a conductor cannot be arranged in the vicinity including the inside of the spiral conductor pattern because it affects the obtained inductance. For this reason, in the layer where the inductor is formed, the ratio of the resin to the conductor inevitably increases. As a result, for example, when a heat history by a reliability test or the like is applied to the wiring board, the influence of the heat shrinkage of the resin is increased, which may cause the wiring board to warp.

The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer printed wiring board that can suppress warpage while having an inductor. .

The invention according to claim 1 is a first embodiment in which a plurality of first insulating layers, a first conductor pattern on the first insulating layer, and a first conductor pattern formed inside the first insulating layer are connected to each other. A core substrate having one via conductor;
A second insulating layer provided on the core base material and not including an inorganic fiber reinforcing material; a second conductive pattern on the second insulating layer; and the second conductive pattern formed inside the second insulating layer. A buildup layer having a second via conductor connecting each other;
A multilayer printed wiring board comprising:
The plurality of first insulating layers include an inorganic fiber reinforcing material,
The core base material includes an inductor formed by the first conductor pattern and the first via conductor.

In the multilayer printed wiring board according to claim 1, the core substrate is formed inside the plurality of first insulating layers, the first conductor pattern on the first insulating layer, and the first insulating layer, and connects the first conductor patterns to each other. And a first via conductor. Further, an inductor is formed in the core base material by the first conductor pattern and the first via conductor. This inductor is provided inside the core base material for the purpose of supplying a low loss voltage to the semiconductor element. Each first insulating layer includes an inorganic fiber reinforcing material (for example, glass cloth, glass nonwoven fabric, aramid cloth, aramid nonwoven fabric, etc.).
That is, the layer where the inductor is formed is provided with an inorganic fiber reinforcing material for increasing rigidity. For this reason, the thermal contraction of the insulating layer is easily suppressed by the inorganic fiber reinforcing material. As a result, even when a thermal history is applied to the wiring board in a manufacturing process or a reliability test, for example, it is considered that the warping of the wiring board is suppressed. As a result, the height of the bumps becomes uniform, and the mountability of the semiconductor element is improved.

It is sectional drawing of the multilayer printed wiring board which concerns on 1st Embodiment of this invention. It is a figure which shows the structure of the conductor pattern of the inductance which concerns on 1st Embodiment. It is a schematic diagram which shows arrangement | positioning of the 2nd via conductor in a buildup layer. It is a schematic diagram which shows arrangement | positioning of the 2nd via conductor in a buildup layer. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Embodiment. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Embodiment. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Embodiment. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Embodiment. It is process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Embodiment. It is sectional drawing of the multilayer printed wiring board of 2nd Embodiment.

[First embodiment]
FIG. 1 is a cross-sectional view of the multilayer printed wiring board according to the first embodiment.
The multilayer printed wiring board 10 has a core substrate 30. The core substrate 30 includes a plurality of first insulating layers 30M, 30A, 30B, 30C, 30D, 30E, and 30F, and first conductor patterns 34Ma, 34Mb, 34A, 34B, 34C, 34D, and 34E on the first insulating layer. , 34F and first via conductors 36M, 36A, 36B, 36C, 36D, 36E, 36F formed inside the first insulating layer and connecting the first conductor patterns to each other.
The 1st insulating layer which forms the core base material 30 contains the inorganic fiber reinforcement material. Although it does not specifically limit as this inorganic fiber reinforcement material, For example, a glass cloth, a glass nonwoven fabric, an aramid cloth, an aramid nonwoven fabric etc. are mentioned.
In the present embodiment, the first conductor pattern forming the core substrate 30 has eight layers, but the number of layers is not particularly limited as long as a desired inductance can be obtained in an inductor described later.

A first conductor pattern 34Ma is formed on the surface of the first insulating layer 30M located in the center in the thickness direction among the first insulating layers constituting the core substrate 30, and the back surface of the first insulating layer 30M on the opposite side thereof. Is formed with a first conductor pattern 34Mb. A first via conductor 36M is formed inside the first insulating layer 30M, and the first conductor pattern 34Ma and the first conductor pattern 34Mb are connected by the first via conductor 36M.

On the surface of the first insulating layer 30M, first insulating layers 30A, 30C, and 30E are sequentially stacked. First conductor patterns 34A, 34C, and 34E are formed on the first insulating layers 30A, 30C, and 30E, respectively. The first conductor pattern 34A and the first conductor pattern 34Ma are connected by the first via conductor 36A, the first conductor pattern 34A and the first conductor pattern 34C are connected by the first via conductor 36C, and the first conductor pattern 34C and the first conductor pattern 34E are connected by a first via conductor 36E.

  On the other hand, first insulating layers 30B, 30D, and 30F are sequentially stacked on the back surface of the first insulating layer 30M. First conductor patterns 34B, 34D, and 34F are formed on the first insulating layers 30B, 30D, and 30F, respectively. The first conductor pattern 34B and the first conductor pattern 34Mb are connected by the first via conductor 36B, the first conductor pattern 34B and the first conductor pattern 34D are connected by the first via conductor 36D, and the first conductor pattern 34D and the first conductor pattern 34F are connected by a first via conductor 36F.

The core base material 30 has a first surface on which a semiconductor element (not shown) is mounted, and a second surface opposite to the first surface. On the first surface and the second surface of the core substrate 30, the second conductor pattern formed on the second insulating layer, the second conductor pattern on the second insulating layer, and the second insulating layer are connected to each other. Build-up layers 501 and 502 having second via conductors are provided.
The second insulating layer forming the build-up layers 501 and 502 does not include an inorganic fiber reinforcing material.
A second conductor pattern 58A is provided on the second insulating layer 50A that forms the build-up layer 501 on the first surface of the core substrate 30. The second conductor pattern 58A and the first conductor pattern 34E are connected by the second via conductor 60A. Second insulating layers 50C, 50E, and 50G are sequentially stacked on the second insulating layer 50A and the second conductor pattern 58A. Second conductor patterns 58C, 58E, and 58G are formed on the second insulating layers 50C, 50E, and 50G, respectively. The upper and lower second conductor patterns are connected to each other by second via conductors 60C, 60E, and 60G provided inside the second insulating layers.

  On the other hand, the second conductor pattern 58B is provided on the second insulating layer 50B that forms the build-up layer 502 on the second surface of the core substrate 30. The second conductor pattern 58B and the first conductor pattern 34F are connected by the second via conductor 60B. Second insulating layers 50D, 50F, and 50H are sequentially stacked on the second insulating layer 50B and the second conductor pattern 58B. Second conductor patterns 58D, 58F, and 58H are formed on the second insulating layers 50D, 50F, and 50H, respectively. The upper and lower second conductor patterns are connected to each other by second via conductors 60D, 60F, and 60H provided in the respective second insulating layers.

A solder resist layer 70 having an opening 71 is provided on the outermost interlayer resin insulation layer 50G on the upper surface side. Inside the opening 71, solder bumps 76U for connecting semiconductor elements are formed. A solder resist layer 70 having an opening 71 is provided on the outermost interlayer resin insulation layer 50H on the lower surface side. Inside the opening 71, solder bumps 76D for connection to a mother board or the like which is an external substrate are formed.

An inductor is formed in the core substrate 30.
As shown in FIG. 2, the inductor of this embodiment includes a spiral first conductor pattern group formed on the surface of each first insulating layer, and a spiral first conductor pattern group positioned above and below. And a first via conductor connecting the two. In FIG. 2, among the first conductor pattern groups forming the inductor, the lower outermost layer first conductor pattern group 34F, the upper first conductor pattern group 34D, and the uppermost outermost layer first conductor. The pattern 34E and the first conductor pattern group 34C below them are disclosed. The first conductor pattern group other than these is omitted.
In this embodiment, at least a pair of adjacent inductors L1 and L2 are provided. The pair of inductors L1 and L2 are electrically connected. As a result, the voltage converted by the switching unit inside the semiconductor element is smoothed through the inductors L1 and L2 and the capacitor (not shown).
The design of the conductor pattern that forms the inductors L1 and L2 is not particularly limited. The number of inductors is not particularly limited.

As shown in FIG. 1, a plane layer is provided on each of the first insulating layers 30M, 30A, 30B, 30C, 30D, 30E, and 30F forming the core substrate 30. These plane layers function as a power source or a ground. Each plane layer has a recess at a location where the first conductor pattern forming the inductors L1 and L2 is formed. As a result, the inductors L1 and L2 and the plane layer are separated from each other in the plane direction, and a desired inductance is easily obtained.

The first via conductors positioned around the inductors L <b> 1 and L <b> 2 are linearly stacked in the thickness direction of the core base material 30. Note that “straightly stacked” means a state in which at least a part of the upper and lower first via conductors adjacent in the thickness direction overlap in the planar direction. If such a first via conductor functions as a power supply system, the power supply line is shortened, and the loss of the voltage supplied to the semiconductor element is suppressed as much as possible.

  In the present embodiment, the inductors L1 and L2 are provided immediately below a region where the semiconductor element is mounted (a region where the bump 76U is formed). In this case, it becomes easy to supply a voltage without loss to the semiconductor element.

In the multilayer printed wiring board of the present embodiment, the first insulating layer 30M located between the conductor patterns vertically adjacent to each other among the conductor patterns 34E, 34C, 34A, 34Ma, 34Mb, 34B, 34D, and 34F forming the inductor. , 30A, 30B, 30C, 30D, 30E, and 30F contain an inorganic fiber reinforcing material. For this reason, the thermal contraction of the first insulating layer is easily suppressed by the inorganic fiber reinforcing material having high rigidity. As a result, even when a thermal history is applied to the wiring board in a manufacturing process or a reliability test, for example, it is considered that the warping of the wiring board is suppressed.

In the multilayer printed wiring board of the present embodiment, inductors L 1 and L 2 are formed in the core base material 30. If the inductors L1 and L2 are formed only on one of the buildup layers on the first surface and the second surface of the core base material 30, the volume of the conductor in the upper buildup layer 501 and the lower buildup layer 502 are formed. The difference between the conductor volume and the conductor volume increases. In this case, there is a difference in the amount of heat shrinkage when the heat history is applied to the wiring board, and warping is likely to occur. However, in the configuration of the present embodiment, since the inductors L1 and L2 are formed in the core base material 30, it is easy to maintain the symmetry between the upper and lower buildup layers, and it is considered that warpage is less likely to occur.

In the multilayer printed wiring board of the present embodiment, via conductors 36E, 36C, 36A, 36M, 36B, 36D provided inside the plurality of first insulating layers 30E, 30C, 30A, 30M, 30B, 30D, 30F, respectively. The electrical connection of the front and back of the core base material 30 is ensured by 36F. For this reason, the depth (aspect ratio) with respect to the opening of one via conductor is smaller than a through hole penetrating the core substrate having the same thickness. For this reason, even if the opening of the via conductor has a small diameter, the liquid flow of the plating solution becomes good when the plating is filled. As a result, voids are difficult to enter, and the reliability of individual via conductors is increased, and the connection reliability on the front and back surfaces of the core substrate is improved. By suppressing the generation of voids in the via conductor forming the inductor, the performance (Q value) of the inductor can be improved.

  The diameter d1 of the first via conductor of the core substrate 30 is larger than the diameter d2 of the second via conductor of the buildup layers 501 and 502. For example, the diameter d1 of the first via conductor of the core substrate 30 is 80 μm, and the diameter d2 of the second via conductor of the buildup layer is 50 μm. That is, it is possible to further improve the performance (Q value) of the inductor by increasing the diameter of the first via conductor in the core base material 30 that functions as an inductor.

In the multilayer printed wiring board of the present embodiment, the thickness s1 of the first conductor pattern that forms the inductors L1 and L2 is larger than the thickness s2 of the second conductor pattern 58B of the buildup layers 501 and 502. For example, the thickness s1 of the first conductor pattern of the core substrate 30 is 20 to 40 μm, and the thickness s2 of the second conductor pattern of the buildup layer is 10 to 18 μm. By increasing the thickness of the first conductor pattern forming the inductors L1 and L2, the performance of the inductor is improved. Furthermore, the core base material 30 can be given rigidity.
On the other hand, by making the thickness of the second conductor pattern of the build-up layers 501 and 502 relatively small, it is possible to realize a fine pitch of the conductor pattern on the build-up layers 501 and 502 side, and to suppress the thickness of the entire wiring board. However, multilayering is possible.

In the multilayer printed wiring board of the present embodiment, the thickness t1 of the first insulating layers 30E, 30C, 30A, 30M, 30B, 30D, and 30F that form the core substrate 30 is the second that forms the build-up layers 501 and 502. It is larger than the thickness t2 of the insulating layers 50G, 50E, 50C, 50A, 50B, 50D, 50F, and 50H. For example, the thickness of the first insulating layer is about 60 μm, and the thickness of the second insulating layer is about 40 μm. By increasing the thickness of the plurality of first insulating layers forming the core base material 30, it is possible to ensure the rigidity of the core base material 30. Further, the depth of the first via conductors forming the inductors L1 and L2 becomes relatively large, and it becomes easy to ensure the inductance.
On the other hand, by making the thickness of the second insulating layer relatively thin, it is possible to realize a fine pitch of the conductor pattern on the buildup layer side, and it is possible to make a multilayer while suppressing the overall thickness.

In the multilayer printed wiring board of the present embodiment, among the first via conductors of the core substrate 30, the first via conductors 36E, 36C, 36A, 36M, 36B, 36D, and 36F that do not form the inductors L1 and L2 are in the thickness direction. Are stacked in a straight line. For this reason, the power supply line or the signal line can be minimized. Moreover, the rigidity of the core base material 30 can be ensured by laminating the first via conductors.

In the present embodiment, a plurality of second via conductors connecting the uppermost first conductor pattern 34E forming the inductors L1 and L2 and the second conductor pattern 58G located in the uppermost layer of the buildup layer 501. Are stacked in a straight line. “Laminated in a straight line” means a state in which at least part of the upper and lower second via conductors adjacent in the thickness direction overlap in the plane direction. Here, a power (ground) plane layer 50AE is provided on the second insulating layer 50A forming the build-up layer 501.
As shown in FIG. 3A, when the upper and lower second via conductors 60A and 60C are displaced in the plane direction, the recess 50Z for insulating the plane layer 50AE and the second conductor pattern 58A (via land). Increases in volume, and the magnetic field easily leaks (see FIG. 3B). For this reason, an inductance may become small. On the other hand, as shown in FIG. 4A, when a plurality of second via conductors (for example, 60A and 60C) in the build-up layer are laminated in a straight line, the plane layer 50AE and the second conductor pattern 58A (via land) The volume of the concave portion 50Z for insulating the two becomes relatively small. As a result, leakage of the magnetic field is suppressed, and a desired inductance is easily obtained.

[Method for Manufacturing Multilayer Printed Wiring Board of First Embodiment]
5 to 9 show a method for manufacturing a multilayer printed wiring board according to the first embodiment.
A double-sided copper-clad laminate (CCL-HL832NSLC) in which copper foils 32 and 32 are laminated on both sides of an insulating layer 30M made of a prepreg in which a glass cloth core is impregnated with an epoxy resin is used as a starting material (FIG. A)).

Via openings 31 for vias penetrating the copper foil 32 and the insulating layer 30M on one side are formed by the laser (FIG. 5B). Next, an electroless plating film 33 is formed (FIG. 5C). An electrolytic plating process is performed, and an electrolytic plating film 35 is formed on the surface of the insulating layer and in the opening 31 (FIG. 5D). Then, an etching resist 37 having a predetermined pattern is formed on the electrolytic plating film (FIG. 5E), and the portions of the electrolytic plating film 35, the electroless plating film 33, and the copper foil 32 where the etching resist is not formed are removed. (FIG. 5F). The etching resist is removed to form via conductors 36M made of electroless plated film 33 and electrolytic plated film 35, and conductive patterns 34Ma and 34Mb made of electroless plated film 33, electrolytic plated film 35 and copper foil 32 (FIG. 5). (G)).

An insulating layer 30A having a copper foil 32a is laminated on the upper surface of the insulating layer 30M, and an insulating layer 30B having a copper foil 32b is laminated on the lower surface of the insulating layer 30M (FIG. 6A). After the copper foils 32a and 32b are etched to reduce their thickness, a via opening 31A reaching the via conductor 36M is formed on the insulating layer 30A side by the laser, and the via reaching the via conductor 36M on the insulating layer 30B side. An opening 31B is formed (FIG. 6B). Electroless plating films 33a and 33b are formed (FIG. 6C). Electrolytic plating is performed, and electrolytic plating films 35a and 35b are formed on the insulating layer surface and in the openings 31A and 31B (FIG. 6D). Etching resists 37a and 37b having a predetermined pattern are formed on the electrolytic plating film (FIG. 6E). The portions of the electroplating films 35a and 35b, the electroless plating films 33a and 33b, and the copper foils 32a and 32b where the etching resist is not formed are removed, and then the etching resist is removed, and the electroless plating film 33a and the electroplating film A via conductor 36A made of 35a and a conductor pattern 34A made of electroless plated film 33a, electrolytic plated film 35a and copper foil 32a are formed. Further, a via conductor 36B composed of the electroless plating film 33b and the electrolytic plating film 35b and a conductor pattern 34B composed of the electroless plating film 33b, the electrolytic plating film 35b and the copper foil 32b are formed (FIG. 6F). .

The process shown in FIG. 6 is repeated, and the insulating layer 30C including the via conductor 36C and the conductor pattern 34C and the insulating layer 30D including the via conductor 36D and the conductor pattern 34D are stacked. Furthermore, the insulating layer 30E including the via conductors 36E and the conductor patterns 34E and the insulating layer 30F including the via conductors 36F and the conductor patterns 34F are laminated, and the core substrate 30 of the present embodiment is completed (FIG. 7A). ).

On the first surface and the second surface of the core substrate 30, a resin film for an interlayer insulating layer that does not include an inorganic fiber reinforcing material (such as a glass cloth core material) is laminated, and the interlayer resin insulating layers 50A and 50B are formed by thermosetting. It is formed (FIG. 7B).

An opening 51A reaching the conductor pattern 34E and the via conductor 36E is provided inside the interlayer resin insulation layer 50A by the CO2 gas laser, and an opening 51B reaching the conductor pattern 34F and the via conductor 36F inside the interlayer resin insulation layer 50B. Is provided (FIG. 7C). By immersing in an oxidizing agent such as chromic acid or permanganate, the surfaces of the interlayer resin insulating layers 50A and 50B are roughened (not shown).

Electroless plating films 53a and 53b are provided in the range of 0.1 to 5 μm by applying a catalyst such as palladium to the surface layers of the interlayer resin insulation layers 50A and 50B and immersing them in the electroless plating solution for 5 to 60 minutes. (FIG. 7D).

A commercially available photosensitive dry film is attached to the laminate after the above treatment, a photomask film is placed and exposed, and then developed with sodium carbonate to provide plating resists 54a and 54b having a thickness of 15 μm. (FIG. 8A). Electrolytic plating films 56a and 56b having a thickness of 15 μm are formed by the electrolytic plating process (FIG. 8B).

After the plating resist is peeled and removed with 5% NaOH, the electroless plating films 53a and 53b under the plating resist are dissolved and removed by etching using a mixed solution of nitric acid, sulfuric acid and hydrogen peroxide. As a result, conductive patterns 58A and 58B and via conductors 60A and 60B having a thickness of about 15 μm, which are made of electroless plating films 53a and 53b and electrolytic plating films 56a and 56b, are formed (FIG. 8C). The surfaces of the conductor patterns 58A and 58B and the via conductors 60A and 60B are roughened by an etching solution containing a cupric complex and an organic acid (not shown).

7B to 8C are repeated, the buildup layer 501 is provided on the first surface of the core base material 30, and the buildup layer 502 is provided on the second surface (FIG. 8). (D)).

Next, a commercially available solder resist composition is applied, and this is exposed and developed to form a solder resist layer 70 having an opening 71 (FIG. 9A).

The laminate is immersed in an electroless nickel plating solution, and a nickel plating layer 72 is formed in the opening 71. Further, the laminate is immersed in an electroless gold plating solution, and a gold plating layer 74 is formed on the nickel plating layer 72 (FIG. 9B). In addition to the nickel-gold layer, a nickel-palladium-gold layer may be formed.

Solder balls are mounted inside the openings 71 and reflowed to form solder bumps 76U on the upper surface side and solder bumps 76D on the back surface side. Thereby, the multilayer printed wiring board 10 is completed (FIG. 9C and FIG. 1).

[Second Embodiment]
FIG. 10 is a cross-sectional view of the multilayer printed wiring board according to the second embodiment.
In the multilayer printed wiring board of the second embodiment, inductors L3 and L4 are further formed in the buildup layer 502 immediately below the inductors L1 and L2 provided on the core substrate 30.
The inductors L3 and L4 are formed of a conductor pattern 58B, a conductor pattern 58D, a conductor pattern 50F, a via conductor 60B, a via conductor 60D, a via conductor 60F, and a via conductor 60F. The inductors L3 and L4 provided in the buildup layer 502 may have the same design as the inductors L1 and L2 in the core base material 30, or may have different designs.

According to this, since an inductor is also formed in the buildup layer 502, it is possible to secure a further inductance component regardless of only the inductance in the core base material 30. Further, it is considered that the difference in conductor volume between the build-up layers 501 and 502 on the front and back sides of the core base material 30 can be adjusted, and the warpage of the wiring board can be reduced.

10 multilayer printed wiring board 30 core substrate 30M, 30A, 30B, 30C, 30D, 30E, 30F first insulating layer 34Ma, 34Mb, 34A, 34B, 34C, 34D, 34E, 34F first conductor pattern 36M, 36A, 36B , 36C, 36D, 36E, 36F First via conductor 50G, 50E, 50C, 50A, 50B, 50D, 50F, 50H Second insulating layer 58A, 58B, 58C, 58D, 58E, 58F, 58G, 58H, second conductor Pattern 60A, 60B, 60C, 60D, 60E, 60F, 60G, 60H, second via conductor

Claims (12)

A core substrate having a plurality of first insulating layers, a first conductor pattern on the first insulating layer, and a first via conductor that is formed inside the first insulating layer and connects the first conductor patterns to each other. When,
A second insulating layer provided on the core base material and not including an inorganic fiber reinforcing material; a second conductive pattern on the second insulating layer; and the second conductive pattern formed inside the second insulating layer. A buildup layer having a second via conductor connecting each other;
A multilayer printed wiring board comprising:
The plurality of first insulating layers include an inorganic fiber reinforcing material,
The core substrate has an inductor formed by the first conductor pattern and the first via conductor. The multilayer printed wiring board of claim 1, wherein:
At least a portion of the first via conductor located around the inductor is laminated linearly in the thickness direction of the core base material. The multilayer printed wiring board of claim 1, wherein:
The thickness of the first conductor pattern is greater than the thickness of the second conductor pattern. The multilayer printed wiring board of claim 1, wherein:
The diameter of the first via conductor is larger than the diameter of the second via conductor. The multilayer printed wiring board of claim 1, wherein:
The first insulating layer is thicker than the second insulating layer. The multilayer printed wiring board of claim 1, wherein:
A bump for connecting a semiconductor element is provided on the second conductor pattern located on the outermost layer of the second conductor pattern, and the inductor is provided immediately below a region where the bump is formed. The multilayer printed wiring board of claim 6, wherein:
The core substrate has a first surface on which the semiconductor element is mounted and a second surface opposite to the first surface;
A plurality of second via conductors connecting the first conductor pattern provided on the first surface and forming the inductor and the second conductor pattern located on the outermost layer are laminated in a straight line. . The multilayer printed wiring board of claim 1, wherein:
Of the buildup layer provided on the second surface of the core substrate, an inductor formed by the second conductor pattern and the second via conductor is further provided immediately below the inductor formation region. It has been. The multilayer printed wiring board of claim 1, wherein:
The core substrate has a first conductor pattern having six or more layers. A core substrate having a plurality of first insulating layers, a first conductor pattern on the first insulating layer, and a first via conductor that is formed inside the first insulating layer and connects the first conductor patterns to each other. Forming
A second insulating layer provided on the core base material and not including an inorganic fiber reinforcing material; a second conductive pattern on the second insulating layer; and the second conductive pattern formed inside the second insulating layer. Forming a buildup layer having a second via conductor connecting each other;
A method for producing a multilayer printed wiring board comprising:
The first insulating layer includes an inorganic fiber reinforcing material,
An inductor is formed by the first conductor pattern and the first via conductor. A method of manufacturing a multilayer printed wiring board according to claim 10, wherein:
The thickness of the first conductor pattern is made thicker than that of the second conductor pattern. A method of manufacturing a multilayer printed wiring board according to claim 10, wherein:
The first conductor pattern is formed by a subtractive method, and the second conductor pattern is formed by a semi-additive method.

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