JP2013069998A - Manufacturing method of semiconductor device - Google Patents

Abstract

A semiconductor device manufacturing method capable of ensuring good characteristics, avoiding an increase in element size, and simplifying a manufacturing process is provided.
A step of forming an oxide film 112 including a LOCOS oxide film 112b on a main surface of a Si substrate 111, and a source / gate formation region 113a and a drain formation region 113b on the main surface side of the Si substrate 111 are provided. A step of forming ions 117 through a trench 114 which is not covered with the LOCOS oxide film 112b on the main surface side of the Si substrate 111 using the resist 116 as a mask, and forming an ion implantation layer 118; and a LOCOS oxidation Forming a gate electrode 119 so as to partially cover the film 112b and the source / gate formation region 113a, and an end portion of the ion implantation layer 118 on the gate electrode 119 side and the ion implantation layer of the gate electrode 119 Each step is performed so that a gap 121 exists between the end portion on the 118 side.
[Selection] Figure 3

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a conventional method for manufacturing a high voltage device (for example, a high voltage MOS transistor), for example, as shown in FIG. 1A, an oxide film 12 (LOCOS oxide film) is formed on the main surface side of a silicon (Si) substrate 11. 12a and 12b), a source / gate formation region 13a, and a drain formation region 13b.

  Next, as shown in FIG. 1B, the opening 14a is formed on the LOCOS oxide film 12b by using a known photolithography technique and ion implantation (ion implantation) technique. A resist (ion implantation resist) 14 for P-type ion implantation is formed. Next, using the resist 14 as a mask, P-type ions 15a are implanted to form a P-type ion implantation layer (P-type implantation layer) 15 immediately below the LOCOS oxide film 12b.

  Next, as shown in FIG. 1C, polysilicon (gate electrode) is formed on the LOCOS oxide film 12b by using known techniques such as CVD (Chemical Vapor Deposition), photolithography, and etching. PolySi) electrode 16 is formed. The polysilicon electrode 16 is formed so as to partially cover the source / gate formation region 13a and the LOCOS oxide film 12b. The end (the right end in FIG. 1C) 16a of the polysilicon electrode 16 and the end 14b of the resist 14 (the end facing the opening 14a in FIG. 1B) 14b are the same in the drawing process of the manufacturing drawings. Although drawn on the line, a portion where the polysilicon electrode 16 and the P-type ion implantation layer 15 are overlapped in the horizontal direction parallel to the main surface due to misalignment between layers in the photolithography process (alignment misalignment in photolithography). In other words, an overlap region 17 is formed.

However, the conventional manufacturing method has the following problems (1) to (5).
(1) Since the overlap region 17 between the P-type ion implantation layer 15 and the polysilicon electrode 16 is formed, the potential applied to the polysilicon electrode 16 acts on the P-type ion implantation layer 15, and FIG. There is a problem that a walk-out phenomenon occurs in the BVsd (source / drain) breakdown voltage characteristics as shown. Here, the walk-out phenomenon is a phenomenon in which the BVsd characteristic is unstable in the first measurement (1st), but exhibits a normal characteristic in the second and subsequent times (repeated remeasurement) (2nd).

(2) In the drawing process, if the photolithography alignment standard is set so that the P-type ion implantation layer 15 and the polysilicon electrode 16 do not overlap, the width of the P-type ion implantation layer 15 is reduced, and the BVsd breakdown voltage is reduced. Problems such as increased resistance arise.

(3) If the photolithography alignment standard is set so that the P-type ion implantation layer 15 and the polysilicon electrode 16 do not overlap in the drawing process, the element size increases, and further, the on-resistance increases. Arise.

(4) The photolithographic alignment accuracy at the time of forming the P-type ion implantation layer 15 and the polysilicon electrode 16 is highly sensitive to fluctuations in the BVsd characteristics, so that the photolithographic alignment standard is set to a value very close to zero in the manufacturing process. However, there is a problem that strict process control is required.

(5) Since ion implantation is performed through the LOCOS oxide film 12b, a high-energy ion implantation apparatus is required to form the P-type ion implantation layer 15, and the resist 14 has a high-energy ion. There is a problem that there is a great problem in the manufacturing process, such as the necessity of a thick film to prevent ion implantation.

JP 2002-353448 A US Pat. No. 6,168,983

  As described above, the conventional method for manufacturing a semiconductor device has problems with characteristics such as the occurrence of a walkout phenomenon and an increase in on-resistance, an element size, and a manufacturing process.

  Accordingly, the present invention has been made to solve the above-described problems of the prior art, and its object is to provide a semiconductor device capable of ensuring good characteristics, avoiding an increase in element size, and simplifying a manufacturing process. It is to provide a manufacturing method.

  In the method for manufacturing a semiconductor device according to the present invention, a step of forming an oxide film including at least a LOCOS oxide film on a main surface of a silicon substrate, and a source and a gate are formed on the main surface side of the silicon substrate. Forming a source / gate forming region as a region and a drain forming region as a region where a drain is formed, forming a resist, and using the resist as a mask, the source on the main surface side of the silicon substrate Forming an ion implantation layer by performing ion implantation through a region not covered with the LOCOS oxide film in a region between the gate formation region and the drain formation region; and on the LOCOS oxide film and the source Forming a gate electrode so as to partially cover the gate formation region, and an end of the ion implantation layer on the gate electrode side and the And an end portion of the ion implantation layer side of the over gate electrode is to have no area overlapping in a direction parallel to the main surface, is characterized by performing the steps.

  According to the semiconductor device manufacturing method of the present invention, a small-sized semiconductor device having good characteristics can be manufactured by a simplified manufacturing process.

(A)-(C) are longitudinal cross-sectional views which show schematically the manufacturing method of the conventional semiconductor device. It is a figure which shows an example of a walkout phenomenon with a graph. (A)-(D) are longitudinal cross-sectional views which show schematically the main processes of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a longitudinal cross-sectional view which shows roughly an example of the semiconductor device manufactured using the manufacturing method of the semiconductor device which concerns on 1st Embodiment. (A)-(C) are longitudinal cross-sectional views which show schematically the main processes of the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(D) are longitudinal cross-sectional views which show schematically the main processes of the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention.

<< 1 >> First Embodiment << 1-1 >> Manufacturing Process of First Embodiment FIGS. 3A to 3D are main steps of a method of manufacturing a semiconductor device according to the first embodiment of the present invention. FIG.

  In the method of manufacturing the semiconductor device according to the first embodiment (for example, a high breakdown voltage device such as a 200 to 700 V high breakdown voltage MOS transistor), for example, as shown in FIG. 3A, a silicon (Si) substrate An oxide film 112 (including at least LOCOS oxide films 112a and 112b), and a source and a gate by impurity implantation are formed on the main surface of 111 using a LOCOS (Local Oxidation of Silicon) isolation technique which is a known technique. A source / gate formation region 113a which is a region and a drain formation region 113b which is a region where a drain is formed are formed. The thickness of the LOCOS oxide films 112a and 112b is, for example, about 8000 mm (angstrom). The Si substrate 111 is, for example, a P-type silicon substrate, and the source / gate formation region 113a and the drain formation region 113b are N-type wells.

  Next, as shown in FIG. 3B, the LOCOS oxide film 112b and the Si substrate 111 are partially etched using a known photolithography technique and etching technique to form a trench 114. Next, as shown in FIG. Although three trenches 114 are shown in FIG. 3B, the number, depth, arrangement, and shape of the trenches are not limited to the illustrated example.

  Next, as shown in FIG. 3C, the inner wall of the trench 114 is oxidized to form a trench oxide film 115. Next, a resist 116 for P-type ion implantation is formed using a photolithography technique and an ion implantation (ion implantation) technique which are publicly known techniques. The resist 116 is formed except for the trench 114 formation region of the LOCOS oxide film 112b. Next, using the resist 116 as a mask, P-type ions 117 are implanted to form a P-type ion implantation layer 118 around the bottom of the trench 114 of the Si substrate 111. P-type ions are, for example, boron. Then, the resist 116 is removed.

  Next, as shown in FIG. 3D, the source / gate formation region on the LOCOS oxide film 112b and (with the oxide film interposed) using the known CVD technique, photolithography technique, and etching technique. A polysilicon electrode 119 as a gate electrode is formed on 113 a and a buried polysilicon 120 is formed in the trench 114. At this time, the layout is performed so that the polysilicon electrode 119 and the buried polysilicon 120 do not contact each other (so that the interval 121 is formed).

<< 1-2 >> Semiconductor Device Manufactured According to First Embodiment FIG. 4 is a longitudinal sectional view schematically showing an example of a semiconductor device manufactured using the manufacturing method according to the first embodiment. The semiconductor device shown in FIG. 4 is, for example, a 200V or 700V breakdown voltage power MOSFET. In FIG. 4, LOCOS oxide films 112a and 112b formed on the main surface of the P-type semiconductor substrate 111, a polysilicon electrode 119, a P-type impurity layer 118, a BPSG (Boron Phosphorus Silicon Glass) 130, a source electrode 131, a drain An electrode 132 is formed.

<< 1-3 >> Effects of First Embodiment As described above, according to the method for manufacturing a semiconductor device according to the first embodiment, the P-type ion implantation layer 118 is formed at the bottom of the trench 114. As a result, the following effects can be expected.

(1) According to the manufacturing method according to the first embodiment, the interval 121 between the polysilicon electrode 119 and the P-type ion implantation layer 118 can be ensured relatively stably on the layout. Further, by forming the P-type ion implantation layer 118 at a position away from the LPCOS oxide film 118 immediately below the LOCOS oxide film 112b, the P-type ion implantation layer 118 is formed in a horizontal direction (a direction horizontal to the main surface of the Si substrate 111) on the polysilicon electrode 119. The effect on the P-type ion implantation layer 118 due to the overlapping potential can be reduced, and the improvement effect of the walk-out phenomenon of the BVsd breakdown voltage (source / drain breakdown voltage) can be expected.

(2) Since the manufacturing method according to the first embodiment can reduce the BVsd breakdown voltage characteristic variation sensitivity with respect to the photolithography alignment accuracy when forming the trench 114, the P-type ion implantation layer 118, and the polysilicon electrode 116. It becomes possible to relax the photolithography alignment standard.

(3) According to the manufacturing method according to the first embodiment, ions 117 are implanted through the trench 114 when the P-type ion implantation layer 118 is formed. For this reason, it is not necessary to implant ions through a thick oxide film as in the case of FIG. 1B, a high energy ion implanter is not necessary for ion implantation, and a low energy ion implanter is used. Can be used.

(4) According to the manufacturing method according to the first embodiment, the position of the P-type ion implantation layer 118 can be adjusted by changing the depth of the trench 114, and the BVsd breakdown voltage characteristics, the on-resistance of the high-voltage MOS transistor, etc. There is an advantage that the degree of freedom increases when adjusting the characteristics.

<< 2 >> Second Embodiment << 2-1 >> Manufacturing Process of Second Embodiment FIGS. 5A to 5C are main steps of a method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG.

  In the method for manufacturing a semiconductor device according to the second embodiment (for example, a high voltage device such as a 200 to 700 V specification high voltage MOS transistor), for example, as shown in FIG. On the surface, a well-known LOCOS isolation technique is used to form an oxide film 212 (including at least LOCOS oxide films 212a and 212b), and a source / gate formation region 213a which is a region where a source and a gate are formed by impurity implantation. A drain formation region 213b, which is a region where a drain is formed, and a P-type ion implantation layer formation region 213c are formed. The thickness of the LOCOS oxide films 212a and 212b is, for example, about 8000 mm.

  Next, as shown in FIG. 5B, the LOCOS oxide film 212a is covered and the LOCOS oxide film 212b is partially covered using a known photolithography technique and ion implantation (ion implantation) technique. Thus, a P-type ion implantation resist 214 is formed. Next, using the P-type ion implantation resist 214 and the LOCOS oxide films 212a and 212b as a mask, P-type ions 215 are implanted to form a P-type ion implantation layer 216. Thereafter, the resist 214 is removed.

  Next, as shown in FIG. 5C, a polysilicon electrode 217 as a gate electrode is formed by using known techniques such as CVD, photolithography, and etching. The polysilicon electrode 217 forms the buried polysilicon 120 in the trench 114 on the LOCOS oxide film 212b and on the source / gate formation region 213a (with the oxide film interposed). At this time, the polysilicon electrode 217 and the P-type ion implantation layer 216 are laid out so as not to overlap each other (so that the interval 221 is formed).

<< 2-2 >> Effects of Second Embodiment As described above, according to the method of manufacturing a semiconductor device according to the second embodiment, the P-type ion implantation resist 214 and the LOCOS oxide films 212a and 212b are masked. The following effects can be expected by forming the P-type ion implantation layer 216 in the P-type ion implantation layer formation region 213c by self-alignment.

(1) According to the semiconductor device of the second embodiment, the distance 221 between the P-type ion implantation layer 216 and the polysilicon electrode 217 is stably formed, and the BVsd (source / drain breakdown voltage) walkout phenomenon is It can be expected that the breakdown voltage characteristics between BVsd will be improved.

(2) According to the semiconductor device of the second embodiment, the BVsd (source / drain breakdown voltage) characteristic variation sensitivity with respect to the photolithography alignment accuracy when forming the P-type ion implantation layer 216 and the polysilicon electrode 217 is reduced. Therefore, the photolithographic alignment standard can be relaxed.

(3) According to the semiconductor device of the second embodiment, when forming the P-type ion implantation layer 216, it is necessary to implant ions through the thick oxide film as in the case of FIG. Therefore, a high energy ion implantation apparatus is not necessary for ion implantation, and a low energy ion implantation apparatus can be used.

<< 3 >> Third Embodiment << 3-1 >> Manufacturing Process of Third Embodiment FIGS. 6A to 6D are main steps of a method of manufacturing a semiconductor device according to the third embodiment of the present invention. FIG.

  In the method for manufacturing a semiconductor device according to the third embodiment (for example, a high breakdown voltage device such as a 200 to 700 V specification high breakdown voltage MOS transistor), for example, as shown in FIG. On the surface, using a LOCOS isolation technique which is a known technique, an oxide film 312 (including at least LOCOS oxide films 312a and 312b), and a source / gate formation region 313a which is a region where a source and a gate are formed by impurity implantation. A drain formation region 313b, which is a region where a drain is formed, is formed. The thickness of the LOCOS oxide films 312a and 312b is, for example, about 8000 mm.

  Next, as shown in FIG. 6B, the source / gate formation region is formed on the LOCOS oxide film 312b (with the oxide film interposed) by using known techniques such as CVD, photolithography, and etching. A polysilicon electrode 314a as a gate electrode is formed on 313a, and a polysilicon electrode 314b as a dummy electrode is formed on the LOCOS oxide film 312b and the drain formation region 313b (with an oxide film interposed).

  Next, as shown in FIG. 6C, the polysilicon electrode 314a and the polysilicon electrode 314b are partially covered by using a known photolithography technique and etching technique, and the polysilicon electrode 314a and the polysilicon electrode are then covered. A resist 315 for P-type ion implantation is formed so as not to cover the space between the electrodes 314b. Next, the P-type ion implantation layer forming region 316 is opened by etching the LOCOS oxide film 312b using the P-type ion implantation resist 315, the polysilicon electrode 314a, and the polysilicon electrode 314b as a mask. The P-type ions 317 are implanted using the ion implantation technique, thereby forming the P-type ion implantation layer 318. Thereafter, the resist 315 is removed.

<< 3-2 >> Effects of Third Embodiment As described above, according to the method of manufacturing a semiconductor device according to the third embodiment, after the polysilicon electrode 314a and the polysilicon electrode 314b are formed first, By using the P-type ion implantation resist 315, the polysilicon electrode 314a, and the polysilicon electrode 314b as a mask, the P-type ion implantation layer 318 is formed by self-alignment in the region 316 where the LOCOS oxide film 312b is etched. The following effects can be expected.

(1) According to the manufacturing method according to the third embodiment, the distance between the P-type ion implantation layer 318 and the polysilicon electrode 314a as the gate electrode is stably formed almost on-line, and both are horizontally ( There is almost no overlap (in a direction parallel to the main surface of the Si substrate 311). For this reason, it is expected that the BVsd (source / drain breakdown voltage) walkout phenomenon is reduced and the BVsd characteristics are improved.

(2) Since the manufacturing method according to the third embodiment can reduce the BVsd characteristic variation sensitivity with respect to the photolithography alignment accuracy when forming the P-type ion implantation resist 315 and the polysilicon electrode (gate) 314a. The photolithographic alignment standard can be relaxed.

(3) According to the semiconductor device of the third embodiment, when forming the P-type ion implantation layer 318, it is necessary to implant ions through the thick oxide film as in the case of FIG. Therefore, a high energy ion implantation apparatus is not necessary for ion implantation, and a low energy ion implantation apparatus can be used.

<< 4 >> Modifications In the first to third embodiments, the case where P-type ions are implanted as impurities into the N-type well of the P-type silicon substrate has been described. It is also possible to adopt.

111, 211, 311 Si substrate, 112, 212, 312 oxide film, 112a, 112b, 212a, 212b, 312a, 312b LOCOS oxide film, 113a, 213a, 313a Source / gate formation region, 113b, 213b, 313b Drain formation region , 114 trench, 115 trench oxide film, 116, 214, 315 resist, 117, 215, 317 P-type ion, 118, 216, 318 ion implantation layer, 119, 217, 314a polysilicon electrode (gate), 120 embedded polysilicon 314b Polysilicon electrode (dummy).

Claims (9)

Forming an oxide film including at least a LOCOS oxide film on the main surface of the silicon substrate;
Forming a source / gate formation region, which is a region where a source and a gate are formed, and a drain formation region, which is a region where a drain is formed, on the main surface side of the silicon substrate;
Using the resist as a mask, a region not covered with the LOCOS oxide film is passed through the region between the source / gate formation region and the drain formation region on the main surface side of the silicon substrate. Performing ion implantation to form an ion implantation layer;
Forming a gate electrode so as to partially cover the LOCOS oxide film and the source / gate formation region, and
The respective steps are performed so that the end of the ion implantation layer on the gate electrode side and the end of the gate electrode on the ion implantation layer side do not have a region overlapping in a direction parallel to the main surface. A method for manufacturing a semiconductor device. Partially etching the LOCOS oxide film and the silicon substrate to form a trench that penetrates the LOCOS oxide film and reaches the silicon substrate;
And oxidizing the inner wall of the trench to form a trench oxide film,
The method for manufacturing a semiconductor device according to claim 1, wherein the region not covered with the LOCOS oxide film in the step of forming the ion implantation layer is a region where the trench is formed.   The method of manufacturing a semiconductor device according to claim 2, wherein the gate electrode is formed in a region away from the trench.   4. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of forming a buried polysilicon layer in the trench. The step of forming the oxide film includes a step of forming two LOCOS oxide films spaced from each other between the source / gate formation region and the drain formation region,
The region that is not covered with the LOCOS oxide film in the step of forming the ion implantation layer is a region between the two LOCOS oxide films that are spaced apart from each other. The manufacturing method of the semiconductor device of description.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the gate electrode is formed in a region away from a region between the two LOCOS oxide films arranged at a distance from each other.   The method for manufacturing a semiconductor device according to claim 1, wherein the gate electrode is a polysilicon electrode. A first electrode is formed so as to partially cover the LOCOS oxide film and the source / gate formation region, and a second electrode is formed so as to partially cover the LOCOS oxide film and the drain formation region. And a process of
Forming a resist, and using the resist and the first and second electrodes as a mask, removing a portion of the LOCOS oxide film not covered with the first and second electrodes,
The region not covered with the LOCOS oxide film in the step of forming the ion implantation layer is a region formed by removing portions of the LOCOS oxide film that are not covered with the first and second electrodes. The method of manufacturing a semiconductor device according to claim 1. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the first and second electrodes are polysilicon electrodes.

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