JP2013065924A - Analog-digital conversion circuit, imaging device, and method of inspecting analog-digital conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriately detect a delay in a count signal supplied to a memory which is caused by a fault in a signal path for transmitting the count signal to the memory from a counter in a column ADC in which a counter supplies a common count signal to a plurality of memories.SOLUTION: The analog-digital conversion circuit comprises a test latch signal supply section for supplying to the memories a latch signal to hold a count signal in the memories in response to a timing of change in a signal value of the count signal.

Description

  The present invention relates to an analog / digital conversion circuit, an imaging apparatus, and an inspection method for an analog / digital conversion circuit.

Conventionally, a plurality of columns of comparators for comparing analog signals and reference signals are provided, and a memory and a comparator are electrically connected to convert analog signals into digital signals. An analog-to-digital conversion circuit is referred to as ADC (Analog Digital Converter), and a column parallel type ADC is referred to as a column ADC). As an example of a column ADC, there is known a configuration in which a plurality of columns of memories are electrically connected in common to a counter that counts clock pulses and outputs a count signal, and the plurality of columns of memory holds a count signal output from the counter. It has been.
Patent Document 1 describes a column ADC having a diagnostic logic unit that diagnoses the operation of the column ADC. The column ADC described in Patent Document 1 is described as a configuration in which a count signal is supplied from a control logic and an external system interface to a double buffer. In addition, the diagnosis logic unit includes a diagnosis A mode for diagnosing whether the control logic and the external system interface unit are operable, a diagnosis B mode for diagnosing whether the comparator is operable, and a diagnosis C mode for examining the operation of the memory. Yes.

Japanese Patent Laid-Open No. 11-331883

Japanese Patent Application Laid-Open No. 2005-228561 does not disclose checking the delay of the count signal caused by a defective signal path through which the count signal is transmitted.
An object of the present invention is to suitably detect a delay of a count signal supplied to a memory caused by a failure in a signal path for transmitting a count signal from the counter to the memory.

  The present invention has been made in view of the above problems, and one aspect provides a comparison result signal indicating a comparison result of a comparison between a memory that holds a digital signal and an analog signal and a reference signal that changes with time. A plurality of circuit units each including a comparator for supplying a memory; and counting a clock pulse signal in parallel with a change in the reference signal to generate a count signal having a plurality of bit signals; and A counter for outputting, and a plurality of count signal transmission lines for supplying the count signal to the plurality of memories, and the memory outputs the count signal when the comparison result signal of the corresponding comparator changes. An analog-digital conversion circuit that converts the analog signal into the digital signal by holding it as a signal, the analog-digital conversion circuit The conversion circuit operates in a test mode, and further includes a test latch signal supply unit and a signal comparison unit. In the test mode, the comparator does not supply the comparison result signal to the memory, and The counter further supplies the count signal to the test latch signal supply unit, and the test latch signal supply unit selects a test latch signal for holding the count signal in the plurality of memories from among the plurality of bit signals. The bit signal is supplied to a plurality of memories according to the timing at which the signal level of the bit signal is changed, the count signal held by the plurality of memories is supplied to the signal comparison unit, and the test latch signal is supplied. The signal value of the digital signal held by the memory and the count signal are supplied from the counter to the memory without delay. In the analog-digital conversion circuit, the count signal transmission line is inspected by comparing the signal value of the digital signal held by the memory at the timing when the test latch signal is supplied. is there.

  Another aspect is an imaging apparatus having a plurality of columns of pixels including a photoelectric conversion unit that generates a charge by photoelectric conversion, and an analog-digital conversion circuit, wherein the analog-digital conversion circuit holds a digital signal. A plurality of circuit units each including a memory and a comparison result signal indicating a comparison result obtained by comparing the analog signal with a reference signal that changes with time; and a clock pulse signal of the reference signal Counting in parallel with the change, generating a count signal having a plurality of bit signals, outputting the count signal, and a plurality of count signal transmission lines supplying the count signal to the plurality of memories, And when the comparison result signal of the corresponding comparator changes, the memory holds the count signal as the digital signal. In the analog-digital conversion circuit that converts the analog signal into the digital signal, each of the plurality of comparators is connected to each column of the plurality of columns, and the imaging device operates in the inspection mode, The imaging apparatus further includes a test latch signal supply unit and a signal comparison unit. In the inspection mode, the comparator does not supply the comparison result signal to the memory, and the counter further includes the counter The test latch signal supply unit supplies the count signal to the test latch signal supply unit, and the test latch signal supply unit stores a test latch signal that holds the count signal in the plurality of memories. According to the timing at which the signal level of the signal is changed, the signal is supplied to the plurality of memories, and the signal comparison unit holds the plurality of memories. When the count signal is supplied from the counter to the memory without delay, the test latch signal is supplied when the count signal is supplied to the memory without delay. In this imaging device, the count signal transmission line is inspected by comparing the signal value of the digital signal held in the memory at the timing of the signal.

  According to another aspect, a plurality of memories, a count signal transmission line, and a count signal having a plurality of bit signals obtained by counting clock pulse signals are supplied to the plurality of memories via the count signal transmission line. A test latch signal for holding the count signal in the plurality of memories, and the signal level of any one of the plurality of bit signals is a signal level of the bit signal. The signal is supplied to the plurality of memories according to the changed timing, and the count signal held by the memory to which the test latch signal is supplied, and the count signal is supplied from the counter to the memory without delay. In this case, the count signal held by the memory at the timing when the test latch signal is supplied. By comparing the issue value, a is an inspection method of the analog-to-digital converter and performs inspection of the count signal transmission line.

  According to the present invention, it is possible to suitably detect a delay of a count signal caused by a defect in a signal path through which the count signal is transmitted.

1 is a diagram illustrating an example of a configuration of an imaging apparatus according to Embodiment 1. FIG. FIG. 6 is a diagram illustrating an example of the configuration and operation of a pixel portion according to the first embodiment. The figure showing an example of composition of a comparison part, a counter, and a test latch signal supply part concerning Example 1. FIG. 6 is a diagram illustrating an example of normal operation mode and inspection mode operation of the imaging apparatus according to the first embodiment. 6 is a flowchart illustrating an example of an inspection mode of the imaging apparatus according to the first embodiment. The figure showing an example of composition and operation of a test latch signal supply part concerning Example 2. The figure showing an example of composition of an AD conversion part in connection with Example 3 The figure showing an example of composition of an AD conversion part in connection with Example 4 The figure showing an example of operation | movement of the inspection mode of the imaging device in connection with Example 4. The figure showing an example of the composition of the counter concerning Example 5, and operation of the inspection mode of an imaging device The figure showing an example of the imaging system concerning Example 6

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating an imaging apparatus having a column ADC according to the present embodiment.

  Reference numeral 10 denotes a pixel unit, 20 denotes a vertical scanning unit, 30 denotes an AD conversion unit, and 40 denotes a horizontal scanning unit. 50 is a timing signal supply unit, 60 is a signal processing unit, 70 is a setting unit, and 80 is a communication unit.

  The present embodiment includes a pixel unit 10 and a vertical scanning unit 20 as an imaging unit. The pixel unit 10 includes a plurality of columns and a plurality of rows of pixels that convert light incident on the imaging device into an electrical signal that is an analog signal. A signal output from the pixel to the vertical signal line 39 is hereinafter referred to as a pixel signal PIXIG.

  An example of the pixel unit 10 that outputs the pixel signal PIXIG will be described with reference to FIG. 2A partially illustrates the pixels 11 to 18, 21 to 28, the vertical scanning unit 20, and the vertical signal line 39 in the 2 rows and 8 columns of the pixel unit 10 shown in FIG. . A specific configuration of a pixel included in the pixel portion 10 is shown in the pixel 11. The pixel includes a photoelectric conversion unit 501, a transfer MOS transistor 502, a reset MOS transistor 503, a floating diffusion unit (hereinafter referred to as an FD unit) 504, an amplification MOS transistor 505, and a selection MOS transistor 506. The photoelectric conversion unit 501 converts incident light into electric charges. Here, a photodiode is shown as an example. The transfer MOS transistor 502 transfers the charge of the photodiode 501 to the FD unit 504. A transfer signal PTX is supplied from the vertical scanning unit 20 to the gate of the transfer MOS transistor 502.

  The FD portion 504 is electrically connected to the gate of the amplification MOS transistor 505. The amplification MOS transistor 505 amplifies and outputs a signal based on the charge of the FD unit 504. The power supply voltage Vdd is supplied to the drain of the amplification MOS transistor 505, and the source is electrically connected to the drain of the selection MOS transistor 506. The selection MOS transistor 506 is provided in an electrical path between the amplification MOS transistor 505 and the vertical signal line 39, and the selection signal PSEL is supplied from the vertical scanning unit 20 to the gate. The vertical scanning unit 20 supplies a selection signal PSEL for each pixel row, and scans the pixel row.

  The reset MOS transistor 503 has a source electrically connected to the FD unit 504 and a drain supplied with the power supply voltage Vdd. That is, the drain voltages of the amplification MOS transistor 505 and the reset MOS transistor 503 are set to a common power supply voltage Vdd. The reset signal PRES is supplied from the vertical scanning unit 20 to the gate of the reset MOS transistor 503. The reset MOS transistor 503 resets the potential of the FD unit 504 when a reset pulse is applied from the vertical scanning unit 20. The signal output from the amplification MOS transistor 505 is output as the pixel signal PIXIG to the vertical signal line 39 via the selection MOS transistor 506.

Next, the operation of the pixels included in the pixel portion 10 will be described with reference to the timing chart illustrated in FIG.
In FIG. 2B, Vfd indicates the potential of the FD unit 504, and Vline indicates the potential of the vertical signal line 39.

  At time t_a, PRES is at H level and PTX is at L level. By turning on the selection MOS transistor 506 by setting the PSEL in the row of the selected pixel to the H level, the pixel signal PIXIG amplified by the amplification MOS transistor 505 is output to the vertical signal line 39 via the selection MOS transistor 506.

  At time t_a, since the reset signal PRES is in the H level, the FD unit 504 is reset. A signal based on the reset potential of the FD unit 504 is amplified and output by the amplification MOS transistor 505. The signal output from the amplification MOS transistor 505 is output as the pixel signal PIXIG to the vertical signal line 39 via the selection MOS transistor 506.

  The reset of the FD unit 504 is released by setting the reset signal PRES to L level at time t_b.

  The charge accumulated in the photodiode 501 is transferred to the FD unit 504 by setting the transfer signal PTX to the H level at time t_c. Thereafter, the transfer signal PTX is set to the L level at time t_d to complete the charge transfer.

  A signal based on the potential of the FD unit 504 at this time is amplified and output by the amplification MOS transistor 505. The signal output from the amplification MOS transistor 505 is output to the vertical signal line 39 as a pixel signal PIXIG.

  By resetting the reset signal PRES to H level again at time t_e, the potential of the FD portion 504 is reset. The vertical scanning unit 20 selects the pixels 11 to 18 in the first row and outputs the pixel signal PIXIGIG, and then sets the selection signal PSEL supplied to the pixels 21 to 28 in the second row to the H level. Pixels 21-28 are selected. Then, the same operation as the pixels 11 to 18 in the first row is performed, and the pixel signals PIXIG are output to the pixels 21 to 28 in the second row.

  Next, referring to FIG. 1 again, the image pickup apparatus of the present embodiment will be described.

  The AD conversion unit 30 includes a ramp signal supply unit 31, a counter 32, and a test latch signal supply unit 33, and includes a plurality of columns of circuit units 29 having a comparison unit 34, an OR circuit 35, and a memory 36. The comparison unit 34 compares the pixel signal PIXIGG input from the pixel unit 10 with the ramp signal RMP supplied from the ramp signal supply unit 31. The ramp signal RMP is a reference signal that is compared with the pixel signal PIXIG. The comparison unit 34 outputs the latch signal LAT to the OR circuit 35 when the latch permission signal LATEN transferred from the timing signal supply unit 50 is at the H level. The comparison unit 34 outputs the latch signal LAT to the OR circuit 35 when the magnitude relationship between the ramp signal RMP that changes with time by the ramp signal supply unit 31 and the pixel signal PIXSIG is reversed.

  The OR circuit 35 sends the memory write signal WEN to the memory 36 when any one of the latch signal LAT from the comparison unit 34 and the test latch signal COMLAT from the test latch signal supply unit 33 described later becomes H level. Output.

  The counter 32 outputs a count signal CNT having a plurality of bit signals obtained by counting the clock pulse signal CLK supplied from a clock pulse supply unit (not shown) from the output start of the ramp signal RMP of the ramp signal supply unit 31. That is, the counter 32 counts the clock pulse signal CLK in parallel with the change in the signal value of the ramp signal RMP, and generates and outputs a count signal CNT having a plurality of bit signals. Hereinafter, the bit signal of the nth bit of the count signal CNT is expressed as a bit signal CNT (n). The count signal CNT is supplied in common to the memory 36 of each column through the count signal transmission line 46. The number of count signal transmission lines 46 is the same as the number of bits of the count signal CNT. The counter 32 is not limited to a binary counter, and may be a gray code counter.

  The test latch signal supply unit 33 includes a synchronization signal generation unit 33-1. The synchronization signal generation unit 33-1 is electrically connected to the counter 32 and a clock pulse supply unit (not shown). The test latch signal supply unit 33 selects a bit signal to be inspected based on the bit selection signal BITSEL supplied from the timing signal supply unit 50 among the plurality of bit signals of the count signal CNT. The synchronization signal generation unit 33-1 generates the test latch signal COMLAT synchronized with the timing of signal change of the bit signal selected from the plurality of bit signals based on the latch mask signal LATMASK. That is, the test latch signal COMLAT synchronized with the timing at which the signal value of the bit signal selected from the count signal CNT changes from 0 → 1 or 1 → 0 is generated. The test latch signal supply unit 33 supplies the test latch signal COMLAT to the OR circuit 35 in each column. A detailed configuration of the test latch signal supply unit 33 will be described later with reference to FIG.

  The memory 36 is supplied with a count signal CNT through a count signal transmission line 46. Further, each column is provided corresponding to the comparison unit 34 of each column. The memory 36 holds the count signal CNT during the period when the memory write signal WEN supplied from the OR circuit 35 is at the H level. The count signal CNT held by the memory 36 when the memory write signal WEN becomes H level is hereinafter referred to as a memory holding signal.

  The horizontal scanning unit 40 sequentially scans the memory 36 of each column based on the horizontal scanning signal HSCAN supplied from the timing signal supply unit 50, and the signal holding unit 60 stores the memory holding signal held in the memory 36 of each column. Forward to.

  A clock pulse signal CLK ′ is supplied to the timing signal supply unit 50. The clock pulse signal CLK ′ may have the same frequency as the clock pulse signal CLK supplied to the counter 32. However, since the timing signal supply unit 50 measures a period longer than the period measured by the counter 32, the frequency of the clock pulse signal CLK ′ is lower than that of the clock pulse signal CLK. The timing signal supply unit 50 supplies timing signals to the test latch signal supply unit 33, the counter 32, the comparison unit 34, the ramp signal supply unit 31, the vertical scanning unit 20, and the horizontal scanning unit 40, respectively. The test latch signal supply unit 33 is supplied with a bit selection signal BITSEL and a latch mask signal LATMAK. When the signals supplied to the test latch signal supply unit 33 are collectively expressed, they are expressed as a timing signal SIG33. The timing signal supply unit 50 supplies a timing signal SIG33 based on a signal supplied from a timing setting unit 71 included in a setting unit 70 described later. The counter 32 is supplied with a timing signal SIG32 including a count permission signal CNTEN and a count reset signal CNTRST. The comparison unit 34 is supplied with a latch permission signal LATEN. The timing signal supply unit 50 supplies the latch permission signal LATEN to the comparison unit 34 and simultaneously supplies the ramp start signal SIG 31 to the ramp signal supply unit 31. The vertical scanning unit 20 is supplied with a vertical scanning start signal SIG20, and the vertical scanning unit 20 scans a plurality of rows of pixels included in the pixel unit 10 as described above. The horizontal scanning unit 40 is supplied with the horizontal scanning start signal HSCAN and causes the horizontal scanning unit 40 to scan the memory 36 in a plurality of columns as described above.

  The signal processing unit 60 performs processing such as converting the memory holding signal transferred from the horizontal scanning unit 40 from, for example, a gray value into a binary value, and outputs an image signal PICOUT. The image signal PICOUT is an image pickup signal output from the image pickup apparatus 1 of this embodiment in order to form an image. The signal processing unit 60 includes a signal comparison unit 61. The signal comparison unit 61 holds in the memory 36 when there is no delay between the signal value of the memory holding signal transferred from each of the memories 36 via the horizontal scanning unit 40 and the count signal CNT output from the counter 32 to the memory 36. Compare the expected value, which is the signal to be done. Then, the signal comparison unit 61 determines whether there is a difference between the signal value of the memory holding signal and the expected value, and outputs the determination result as the comparison result signal TOUT. The expected value used for this determination is a value set by an expected value / error range setting unit 72 described later. The expected value is a digital signal held by the memory 36 at the timing when the test latch signal COMLAT is supplied when the count signal CNT is supplied from the counter 32 to the memory 36 without delay. The expected value / error range setting unit 72 outputs a signal SIG 60 including the expected value to the signal processing unit 60. When the error range between the signal value of the memory holding signal and the expected value is set by the expected value / error range setting unit 72, the predetermined signal range including the error range in the expected value is compared with the memory holding signal. The determination result is output as a comparison result signal TOUT.

  The setting unit 70 includes a timing setting unit 71 and an expected value / error range setting unit 72. The timing setting unit 71 supplies a signal having supply settings for each timing signal to the timing signal supply unit 50. The expected value / error range setting unit 72 sets an expected value and an error range value used by the signal comparison unit 61 for comparison based on a signal from the communication unit 80. Further, the expected value / error range setting unit 72 supplies the signal processing unit 60 with a signal having information on expected value and error range setting. Further, a supply timing setting for supplying a timing signal to each of the vertical scanning unit 20, the ramp signal generation unit 31, the counter 32, the latch signal supply unit 33, and the horizontal scanning unit 40 is output to the timing signal supply unit 50. The timing setting unit 71 outputs a supply timing setting based on the expected value set by the expected value / error range setting unit 72. The timing signal supply unit 50 outputs a timing signal SIG33 having the supply timing setting to the test latch signal supply unit 33. As a result, the test latch signal supply unit 33 outputs the test latch signal COMLAT to the memory 36 via the OR circuit 35 at a timing based on the expected value.

  FIG. 3A is a block diagram illustrating an example of a detailed configuration of the comparison unit 34. The comparison unit 34 includes a comparator 34-1, a signal inversion detection circuit 34-2, and an AND circuit 34-3. The comparator 34-1 compares the pixel signal PIXIG with the ramp signal RMP that changes with time, and inverts the level of the output signal when the magnitude relationship between the ramp signal RMP and the pixel signal PIXIG is reversed. The signal inversion detection circuit 34-2 detects the inversion of the level of the output signal of the comparator 34-1 and generates a pulse that becomes H level with a length of about one cycle of the clock pulse signal CLK. The AND circuit 34-3 outputs a logical product of the output signal of the signal inversion detection circuit 34-2 and the latch permission signal LATEN from the timing signal supply unit 50 as a latch signal LAT.

  FIG. 3B is a block diagram illustrating an example of a detailed configuration of the counter 32. The counter 32 includes a binary counter 32-1 and a gray code conversion circuit 32-2. The binary counter 32-1 sets the count signal CNT to an initial value when the counter reset signal CNTRST is at the H level, and outputs the count signal CNT obtained by counting the clock pulse signal CLK when the count permission signal CNTEN is at the H level. The gray code conversion circuit 32-2 converts the binary signal output from the binary counter 32-1 into a gray value signal, and outputs the signal as a count signal CNT.

  FIG. 3C is a circuit diagram illustrating an example of a detailed configuration of the test latch signal supply unit 33. The latch signal supply unit 33 includes a synchronization signal generation unit 33-1, a selector SEL1, and an AND circuit AND2. The selector SEL1 receives the bit selection signal BITSEL from the timing signal supply unit 50 and selects a bit signal to be tested from the n-bit count signal CNT. The synchronization signal generator 33-1 includes three flip-flop circuits FF1 to FF3, an inverter INV, and AND circuits AND1 and AND2 that are electrically connected in series. In response to the rising edge of the bit signal selected by the selector SEL1, a signal in which one cycle of the clock pulse signal CLK becomes H level is output from the AND circuit AND1 as the signal SIG-AND1. The AND circuit AND2 ANDs the signal SIG-AND1 and the latch mask signal LATMAK from the timing signal supply unit 50. That is, the AND circuit AND2 outputs the test latch signal COMLAT during a period in which both the signal SIG-AND1 and the latch mask signal LATMSK are at the H level. Thus, when the signal SIG-AND1 becomes H level a plurality of times, the timing for supplying the test latch signal COMLAT can be selected from the plurality of times when the signal AND-SIG1 becomes the H level. it can. That is, the AND circuit AND2 is a mask unit that switches whether the signal SIG-AND1 supplied from the synchronization signal generation unit 33-1 is supplied to the plurality of memories 36 as the test latch signal COMLAT.

  The imaging apparatus illustrated in FIG. 1 has two modes, a normal operation mode and an inspection mode. First, the normal operation mode will be described.

  FIG. 4A is a timing diagram illustrating the normal operation mode of the imaging apparatus illustrated in FIG. The count signal CNT of this embodiment is a 6-bit signal, and six count signal transmission lines 46, 46-0 to 46-5 (not shown), are provided. In addition, the notation of the count signal transmission line 46 represents the count signal transmission line that transmits the bit signal of the nth bit as the count signal transmission line 46-n.

  At time t10, the timing signal supply unit 50 sets the count reset signal CNTRST to H level to reset the count value. When the count reset signal CNTRST becomes H level, the counter 32 sets the count signal CNT to an initial value (here, 0). Thereafter, the count reset signal CNTRST is set to L level to prepare for the count of the clock pulse signal CLK starting at time t11.

  At time t11, the latch permission signal LATEN and the count permission signal CNTEN are set to the H level. At the same time, the ramp start signal supplied to the ramp signal supply unit 31 is set to the H level, and the signal level of the ramp signal RMP starts increasing in proportion to the time. In the counter 32, when the count permission signal CNTEN becomes H level, the binary counter 32-1 starts counting the clock pulse signal CLK. Further, the gray code conversion circuit 32-2 outputs the count signal CNT obtained by converting the binary count value to the gray value to the count signal transmission lines 46-0 to 46-5.

  Next, at time t12, the signal level of the ramp signal RMP becomes higher than the pixel signal PIXIG. At this time, the comparison unit 34 outputs the latch signal LAT to the OR circuit 35 as the H level. When the latch signal 35 is supplied, the OR circuit 35 outputs the memory write signal WEN to the memory 36 as the H level. The memory 36 holds the count signal CNT when the memory write signal WEN is input as a memory holding signal. In the timing diagram illustrated in FIG. 4A, the memory 36 holds a count signal CNT having a gray value corresponding to the binary value 35.

  Next, at time t13, the ramp signal supply unit 31 returns the signal level of the ramp signal RMP to the signal level at time t11 at which the time change of the ramp signal RMP is started. At the same time, the count permission signal CNTEN is set to the L level, and the count of the clock pulse signal CLK is finished for the count signal CNT. The latch permission signal LATEN is also set to L level.

  At time t <b> 14, the timing signal supply unit 50 supplies the horizontal scanning unit 40 with the H level horizontal scanning signal HSCAN. The horizontal scanning unit 40 to which the horizontal scanning signal HSCAN is input scans the memory 36 in order, and transfers the memory holding signal to the signal processing unit 60.

  At time t15, the count reset signal CNTRST is set to H level, and the count signal CNT is set to an initial value to prepare for the next AD conversion.

  The inspection mode is to inspect the count signal CNT for delays and defects.

  FIG. 4B is a timing diagram illustrating the inspection mode of the imaging apparatus illustrated in FIG. The inspection mode illustrated in FIG. 4B is a mode for inspecting the bit signal CNT (4) illustrated in FIG.

  This test mode is different from the normal operation mode in that the test latch signal COMLAT is supplied from the test latch signal supply unit 33 to the OR circuit 35 instead of the latch signal LAT from the comparison unit 34.

  From time t20 to time t30, the operations of the count reset signal CNTRST, the count permission signal CNTEN, and the count signal CNT supplied to the count signal transmission line 46 can be the same as in the normal operation mode. That is, the operation can be performed by sequentially matching the times t20, t21, t28, and t30 in the inspection mode with the times t10, t11, t13, and t15 in the normal operation mode, respectively.

  The selector SEL1 of the test latch signal supply unit 33 outputs the bit signal CNT (4) to the flip-flop circuit FF1 in accordance with the signal value of the bit selection signal BITSEL. The flip-flop circuit FF1 outputs to the flip-flop circuit FF2 a signal SIG-FF1 that becomes H level with a delay of one cycle of the clock pulse signal CLK with respect to the timing of the signal change of the bit signal CNT (4). When the H-level signal SIG-FF1 is input, the flip-flop circuit FF2 further outputs the H-level signal SIG-FF2 to the flip-flop circuit FF3 and the AND circuit AND1 with a delay of one cycle of the clock pulse signal CLK. When the H level signal SIG-FF2 is input, the flip-flop circuit FF3 outputs an H level signal to the inverter INV with a delay of one cycle of the clock pulse signal CLK. The inverter INV outputs a signal SIG-INV obtained by inverting the signal level of the signal input from the flip-flop circuit FF3 to the AND circuit AND1. The AND circuit AND1 outputs a logical product of the signal SIG-FF2 and the signal SIG-INV to the AND circuit AND2. Therefore, the signal SIG-AND1 output from the AND circuit AND1 becomes H level at time t23 and becomes L level at time t24. When the signal SIG-AND1 is at the H level and the latch mask signal LATMASK supplied from the timing signal supply unit 50 is at the H level, the AND circuit AND2 outputs the test latch signal COMLAT at the H level. Since the latch mask signal LATMASK is at the H level from time t22 to t25, the test latch signal COMLAT at the H level is changed from the AND circuit AND2 to the OR circuit 35 between time t23 and time t24 when the signal SIG-AND1 is at the H level. Is output. The OR circuit 35 that has received the test latch signal COMLAT at H level outputs the memory write signal WEN to the memory 36. The memory 36 holds the count signal CNT when the memory write signal WEN is input as a memory holding signal.

  Here, when there is a defect in the count signal transmission line 46-4 for transmitting the bit signal CNT (4), for example, when there is a place where the resistance is higher than usual, as shown in the period p21, the bit signal A delay occurs in CNT (4). If there is no delay in the bit signal CNT (4), the memory holding signal held in the memory 36 to which the memory write signal WEN is input during the time t23 to t24 is a gray value corresponding to the binary value 18. On the other hand, when the delay of the period p21 occurs in the bit signal CNT (4), the memory holding signal held in the memory 36 becomes a gray value corresponding to the binary value 13.

  Subsequently, the timing signal supply unit 50 supplies the horizontal scanning signal HSCAN to the horizontal scanning unit 40. The horizontal scanning unit 40 to which the horizontal scanning signal HSCAN is input scans the memory 36 in order, and transfers the memory holding signal to the signal processing unit 60. The signal comparison unit 61 included in the signal processing unit 60 is a predetermined value including the signal value of the memory holding signal transferred by the horizontal scanning unit 40 and the error range in the expected value according to the setting of the expected value / error range setting unit 72. The signal range is compared to determine the presence or absence of deviation. For example, when the expected value is 18 binary values and the error range is set to ± 1 binary values, it is determined to be normal if the binary value of the memory holding signal is in the range of 17 to 19, and 17 to 19 When it is out of the range, it is determined as a failure and the comparison result signal TOUT is output. When the delay exemplified as the period p21 occurs in the bit signal CNT (4), the memory holding signal is a gray value corresponding to 13 binary values, and therefore the comparison result signal TOUT is output.

  So far, in the inspection mode, the method of inspecting the delay by selecting the bit signal CNT (4) as an example in the 6-bit count signal CNT has been described. In the inspection mode of this embodiment, each bit signal of the count signal CNT is selected in order, and each count signal is delayed and delayed to the count signal CNT output by the counter by sequentially checking whether or not a defect occurs. It is possible to comprehensively check for defects. This inspection method will be described with reference to the flowchart illustrated in FIG.

When the inspection is started (step 1-1), first, as the setting of the timing signal supply unit 50, a bit to be inspected is selected from the count signal CNT, and the timing setting for the inspection is performed (step 1-2). Next, as the setting of the signal comparison unit 61, an expected value and an error range corresponding to the bit signal to be inspected among the count signals CNT are set (step 1-3). Next, the count of the counter 32 is started (step 1-4), and the test latch signal COMLAT is generated (step 1-5). Then, the counter 32 finishes counting (step 1-6), and the horizontal scanning unit 40 transfers the memory holding signal to the signal processing unit 60 (step 1-7). Next, the signal comparison unit 61 of the signal processing unit 60 compares the memory holding signal transferred from the memory 36 with a predetermined signal range including an error range in the expected value (step 1-8), and transfers from the memory 36. If the stored memory retention signal is outside the predetermined signal range, it is determined that there is a failure (step 1-9). If the memory holding signal transferred from the memory 36 is within the error range, step 1-7 to step 1-8 are repeated until the memory holding signal is transferred from the memory 36 in the last column. Then, when it is determined that the memory holding signal is in the last column, the inspection of the 1-bit signal of the count signal CNT is finished. (Step 1-10). Then, the inspection of all the bit signals of the count signal CNT is executed (repeating step 1-2 to step 1-10), and the inspection of all the bit signals is finished. (Step 1-11)
In step 1-7, the memory holding signal of the column farthest from the counter 32 may be simply transferred. This is due to the following two reasons. One reason is that the delay of the count signal CNT tends to increase as the distance from the counter 32 increases, and the column farthest from the counter 32 has the greatest delay of the count signal CNT. The other is that if a break occurs on the count signal transmission line 46 (n), the count signal transmission line 46 (n) can be transferred only by transferring the memory holding signal of the column farthest from the counter 32. This is because it is possible to inspect for the presence of disconnection. Further, when transferring the memory holding signal of an arbitrary column, it is not necessary to determine whether or not the memory holding signal of the last column of step 1-10 has been transferred.

  By inspecting each bit signal for a deviation from the expected value, it is possible to inspect each count signal transmission line 46 that transmits each bit signal for a defect. In addition, the delay of the count signal can be accurately detected by supplying the test latch signal according to the signal change of the bit signal to be inspected. When the test latch signal is supplied without depending on the signal change of the bit signal, for example, even if the test latch signal COMLAT is supplied to the OR circuit 35 at time t25 in this embodiment, the signal value of the memory holding signal is the same as the expected value. It becomes. Therefore, the delay of p21 of the bit signal CNT (4) cannot be detected. Therefore, in the imaging apparatus of the present embodiment, the delay of the count signal CNT can be accurately detected by supplying the test latch signal COMLAT according to the signal change of the bit signal, that is, the signal change of the count signal CNT. . Further, even when there is a bit signal whose signal value does not change at all and a bit defect occurs in the count signal CNT, the bit defect can be detected. In the imaging apparatus of the present embodiment, since the comparison unit 34 does not output the latch signal LAT in the inspection mode, when the signal comparison unit 61 detects a signal value deviation between the expected value and the memory holding signal in the inspection mode. Indicates that the signal path of the count signal is defective.

  In this embodiment, the image pickup apparatus is described as an example of the apparatus having the column ADC. The present invention is not limited to the image pickup apparatus, and is a common counter type of the analog-digital conversion circuit that converts an analog signal into a digital signal. The counter supplies a count signal CNT in common to the memory 36 of each column. Any row ADC may be used. In other words, any device having a common counter type column ADC and a structure in which an analog signal is supplied to each of the vertical signal lines 39 may be used.

  Further, in this embodiment, the synchronization signal generator 33-1 uses three flip-flop circuits FF1 to FF3, and two cycles of the clock pulse signal CLK with respect to the signal change timing of the selected bit signal among the count signals CNT. A delayed test latch signal COMLAT was generated. When the test latch signal COMLAT is a signal delayed by one clock pulse period with respect to the signal change timing of the selected bit signal of the count signal CNT, the flip-flop circuit FF1 can be omitted. In other words, the selector SEL1 may output the signal to the flip-flop circuit FF2.

  In the present embodiment, the mode in which the test latch signal COMLAT is output in accordance with the signal change timing from the L level to the H level of the bit signal CNT (n) has been described. However, by making the AND circuit AND1 of the synchronization signal generation unit 33-1 a NOR circuit, the H level at time t26 and the L level at time t27 according to the signal change from the H level to the L level of the bit signal CNT (4). It is possible to output a test latch signal COMLAT that becomes a level. A case will be described in which the test latch signal COMLAT is supplied in response to signal changes from the L level to the H level and from the H level to the L level of the bit signal CNT (n). In this case, the latch test signal supply unit 33 includes the synchronization signal generation unit 33-1 illustrated in FIG. 3C and another synchronization signal generation unit provided with a NOR circuit instead of the AND circuit AND1. It ’s fine. Then, the output of the AND circuit AND2 included in each synchronization signal generation unit may be supplied to the count signal transmission line 46.

  In the present embodiment, the mode in which the memory holding signal is compared with the count signal CNT when the memory 36 holds the memory holding signal has been described. However, the comparison between all the bit signals of the memory holding signal and the count signal CNT is performed. It can also be set as the form which does not perform. For example, when the count signal CNT is a 6-bit signal and the memory holding signal is 5 bits, the signal comparison unit 61 uses a signal obtained by selecting 5 bits from the 6-bit signal of the count signal CNT as an expected value. Compare and judge. That is, when a b-bit imaging signal having a smaller number of bits than the a-bit count signal CNT is output from the memory 36, the comparison between the memory holding signal and the count signal CNT is performed between the same bits of b bits. Good.

  The test latch signal COMLAT supplied by the test latch signal supply unit 33 of this embodiment is output in synchronization with the rising edge of the clock pulse signal CLK. Therefore, the time from when the signal value of the bit signal CNT (n) to be inspected to when the test latch signal COMLAT is supplied is an integral multiple of the clock pulse signal CLK. The present embodiment is not limited to this form. When supplying the test latch signal COMLAT with a delay from the rising edge of the clock pulse signal CLK, a means for delaying the signal, such as a resistor or a delay buffer, may be provided between the AND circuit AND1 and the AND circuit AND2. As a result, the time from when the signal value of the bit signal CNT (n) to be inspected to when the test latch signal COMLAT is supplied can be a period that is not an integral multiple of the clock pulse signal CLK.

  The signal comparison unit 61 may be provided on the same substrate as the substrate on which the AD conversion unit 30 is provided, or may be provided on a different substrate.

  In addition, the imaging apparatus of the present embodiment does not need to have the signal comparison unit 61, and can have a form having a terminal to which a memory holding signal is supplied. In this mode, when the test holding mode is used, the memory holding signal and the memory 36 hold the memory holding signal by electrically connecting a test device having the signal comparison unit 61 that stores the expected value to this terminal. And the count signal CNT can be compared and determined.

  In this embodiment, the signal comparison unit 61 has been described based on a mode in which a predetermined signal range including an error range in the expected value is compared with the memory holding signal. As another form, the expected value and the memory holding signal are compared to detect a signal value deviation, and the signal value deviation is within a predetermined signal range that is an error range set by the expected value / error range setting unit 72. It may be determined based on whether or not there is, and a determination result TOUT may be output.

  In this embodiment, there is provided an OR circuit 35 for supplying the memory write signal WEN to the memory 36 when either the latch signal LAT from the comparison unit 34 or the test latch signal COMLAT from the test latch signal supply unit 33 becomes H level. Was. The present embodiment is not limited to this form. That is, the latch signal LAT from the comparison unit 34 is not supplied to the memory 36 in the inspection mode, and the test latch signal COMLAT from the test latch signal supply unit 33 may be supplied, and the OR circuit 35 is provided. It does not have to be. In this embodiment, the memory 36 is provided in each column corresponding to the comparison unit 34 in each column. However, a form in which a plurality of memories 36 are electrically connected in parallel to one column comparison unit 34, a form in which one memory 36 is electrically connected in parallel to a plurality of columns comparison unit 34, etc. Various modifications can be made to the electrical connection between the comparison unit 34 and the memory 36. It can be said that the comparison unit 34 is provided corresponding to the memory 36, including various forms of electrical connection between the comparison unit 34 and the memory 36.

  In this embodiment, the common clock pulse signal CLK is supplied to the counter 32 and the test latch signal supply unit 33. However, the counter 32 and the test latch signal supply unit 33 independently supply the clock pulse signal CLK. Form may be sufficient. Also in this embodiment, it is preferable that the frequency of the clock pulse signal CLK supplied to the counter 32 and the test latch signal supply unit 33 is the same, and the timing of the pulse signal change is synchronized. Thus, the test latch signal COMLAT can be supplied with high accuracy in a predetermined period according to the timing at which the count signal CNT changes.

  In order to accurately detect the delay of the count signal CNT, it is preferable that the count signal transmission line 46 and the test latch signal transmission line for transmitting the test touch signal COMLAT to the OR circuit 35 have the same delay characteristics. For example, there is a form in which the count signal transmission line 46 and the test latch signal transmission line have the same wiring width. Further, when the count signal transmission line 46 is provided with a relay buffer, the test latch signal transmission line is preferably provided with the same number of relay buffers as the count signal transmission line 46.

  As described above, in the imaging apparatus having the column ADC in this embodiment, the test latch signal COMLAT corresponding to the signal change of each bit signal of the count signal CNT is supplied to the OR circuit 35, and the memory holding signal is supplied to the memory 36. Hold. By supplying the test latch signal COMLAT and inspecting the memory holding signal held in the memory 36, the delay of the count signal CNT can be detected with high accuracy. Further, it is possible to detect a bit loss of the count signal CNT.

  The present embodiment will be described with reference to the drawings. Below, it demonstrates centering on difference with Example 1. FIG.

  FIG. 6A is a block diagram in which the test latch signal supply unit 33 shown in FIG. 1 is extracted. The latch signal supply unit 33 of the present embodiment is different from the first embodiment in the configuration of the synchronization signal generation unit 33-1. In the first embodiment, the synchronization signal generating unit 33-1 includes three FF1 to FF3, an inverter INV, and two AND circuits AND1 and AND2 that are electrically connected in series. In addition, the signal SIG-AND1 which becomes H level only for one cycle after two cycles of the clock pulse signal CLK with respect to the rising edge of the bit signal selected from the count signal CNT based on the bit selection signal BITSEL by the selector SEL1 It was the structure output from the part 33-1. In contrast, the synchronization signal generator 33-1 illustrated in FIG. 6A includes two FF1, FF2, an inverter INV, and two AND circuits electrically connected in series to the output terminal of the selector SEL1. AND1 and AND2. Further, it has four FFs 4 to 7 and a selector SEL2 electrically connected in series to the output terminal of the AND circuit AND1. The selector SEL2 selects one of the signals SIG-AND1 and SIG-FF4-7 based on the delay amount selection signal DELAYSEL supplied from the timing signal supply unit 50. A signal SIG-SEL2 output from the selector SEL2 is a signal output from the synchronization signal generator 33-1.

  Next, the operation of the synchronization signal generation unit 33-1 of this embodiment will be described with reference to the timing diagram illustrated in FIG.

  First, at time t40, the selector SEL1 outputs the bit signal CNT (n) selected by the bit selection signal BITSEL. Subsequently, the signal SIG-FF1 is set to the H level at time t41, which is the time one cycle after the clock pulse signal CLK from time t40. Subsequently, the output signal of the flip-flop circuit FF2 is set to the H level and output to the inverter INV at time t42, which is the time one cycle after the clock pulse signal CLK from time t41. Since the signal SIG-INV from the inverter INV is a signal obtained by inverting the output signal from the flip-flop circuit FF2, it becomes L level at time t42. Therefore, the signal SIG-AND1 output from the AND circuit AND1 is at the H level during the period from time t41 to t42. A signal SIG-AND1 that is H level for one cycle of the clock pulse signal CLK is output to the selector SEL2 and the flip-flop circuit FF4. The signal SIG-FF4 output from the flip-flop circuit FF4 is a signal delayed by one cycle of the clock pulse with respect to the signal SIG-AND1, and is output to the selector SEL2 and the flip-flop circuit FF5. Similarly, each of the signals SIG-FF5, SIG-FF6, and SIG-FF7 is a signal that is sequentially delayed by one cycle of the clock pulse signal CLK with respect to the signals SIG-FF4, SIG-FF5, and SIG-FF6. Then, it is output from the AND circuit AND2 as a test latch signal COMLAT that is a logical sum of the signal SIG-SEL2 output from the synchronization signal generating unit 33-1 and the latch mask signal LATMASK.

  By using the test latch signal supply unit 33 according to the present embodiment, it is possible to arbitrarily set a delay amount from the signal change of the bit signal to be tested in the count signal CNT to the supply of the test latch signal COMLAT. . Therefore, an error range for the delay of the count signal CNT can be set also by the test latch signal supply unit 33.

  The present embodiment will be described with reference to the drawings. Below, it demonstrates centering on difference with Example 1. FIG.

  FIG. 7A is a block diagram in which the AD conversion unit 30 and the timing signal supply unit 50 are extracted from the imaging apparatus illustrated in FIG. Below, it demonstrates centering on difference with Example 1. FIG.

  In the first embodiment, the count signal CNT output from the counter 32 is configured to be output to the memory 36 through the count signal transmission line 46. On the other hand, in the configuration according to this embodiment illustrated in FIG. 7A, the count signal CNT is input to the count signal output unit 37. The count signal CNT 2 output from the count signal output unit 37 is output to the memory 36 through the count signal transmission line 46.

  FIG. 7B is a circuit diagram illustrating an example of a detailed configuration of the count signal output unit 37. The count signal output unit 37 includes n clock synchronous output circuits 37-1. The clock synchronous output circuit 37-1 includes a flip-flop circuit FF-n and a buffer circuit 37-11 (n). The input n-bit count signal CNT is output as an n-bit count signal CNT2 after being synchronized with the clock pulse signal CLK by the clock synchronous output circuit 37-1. Since the count signal CNT2 is output in synchronization with the rising edge of the clock pulse signal CLK generated after the count signal CNT is input to the flip-flop circuit FF-n, one cycle of the clock pulse signal CLK with respect to the count signal CNT. The signal is delayed by a minute.

  The test latch signal supply unit 33 of this embodiment has the configuration described in the first embodiment with reference to FIG. Therefore, the test latch signal COMLAT generated by the synchronization signal generation unit 33-1 of this embodiment is two cycles of the clock pulse signal CLK with respect to the bit signal CNT (n) input to the selector SEL1, as in the first embodiment. The signal is delayed by a minute. Therefore, the test latch signal COMLAT is a signal delayed by one cycle of the clock pulse signal CLK with respect to the count signal CNT2. For this reason, in the image pickup apparatus of the present embodiment, when a delay larger than one cycle of the clock pulse signal CLK has occurred in the count signal CNT2, this can be detected. Since the count signal CNT2 is generated by the count signal output unit 37 based on the count signal CNT, the count signal CNT supplied to the count signal output unit 37 has a delay greater than one cycle of the clock pulse signal CLK. Cases can also be detected.

  In the configuration of the first embodiment, the count signal CNT is supplied to the test latch signal supply unit 33 in addition to the count signal transmission line 46 to the memory 36. Accordingly, the bit signal to be tested is also used in the test latch signal supply unit 33, while the bit signal other than the bit signal to be tested is not used in the test latch signal supply unit 33. Therefore, there may be a variation in load between the bit signal to be tested and the bit signal not to be tested. In the configuration of this embodiment, the count signal CNT <b> 2 is supplied from the count signal output unit 37 to the memory 36. Therefore, the count signal CNT2 synchronized with the clock pulse signal CLK can be supplied to the memory 36 regardless of variations in the output load of the counter 32. For this reason, it is possible to obtain an effect that the bit signal delay variation of the count signal caused by the output of the count signal CNT from the counter 32 to the test latch signal supply unit 33 can be suppressed.

  The present embodiment will be described with reference to the drawings. FIG. 8A is a block diagram in which the AD conversion unit 30 and the timing signal supply unit 50 are extracted from the configuration shown in FIG. Below, it demonstrates centering on difference with Example 1. FIG.

  In the first embodiment, the count signal CNT output from the counter 32 is supplied to the test latch signal supply unit 33 and supplied to the memory 36 through the count signal transmission line 46.

  On the other hand, in the configuration of this embodiment illustrated in FIG. 8A, the count signal CNT is temporarily input to the bit signal selection unit 38. The count signal CNT3 output from the bit signal selection unit 38 is output to the test latch signal supply unit 33 and also supplied to the memory 36 through the count signal transmission line 46. Further, the timing signal supply unit 50 supplies the test signal TESTSIG and the test selection signal TESTSEL to the bit signal selection unit 32.

  FIG. 8B is a circuit diagram illustrating an example of a detailed configuration of the bit signal selection unit 38. The bit signal selection unit 38 includes n selectors 38-1. When the test selection signal TESTSEL is at L level, the count signal CNT output from the counter 32 is selected and output as the count signal CNT3. When the test selection signal TESTSEL is at H level, the test signal TESTSIG is selected and output as the count signal CNT3.

  Next, an example of an operation for inspecting the bit signal CNT3 (4) in the count signal CNT3 transmitted by the count signal transmission line 46 will be described using the timing chart of FIG.

  First, at the time of inspection, the latch permission signal LATEN is set to L level so that the H level latch signal LAT is not output from the comparison unit 34.

  Next, when the timing signal supply unit 50 sets the test selection signal TESTSEL to the H level at time t30, the bit signal selection unit 38 selects the test signal TESTSIG and outputs the test signal TESTSIG to the count signal transmission line 46. At time t31, the timing signal supply unit 50 changes the test signal TESTSIG from “0” to “16”, that is, sets the bit signal TESTSIG (4) of the test signal TESTSIG to the H level.

  On the other hand, according to the bit selection signal BITSEL output from the timing signal supply unit 50, the selector SEL1 in the test latch signal supply unit 33 illustrated in FIG. 3C outputs the bit signal CNT3 (4) of the count signal CNT3. The signals SIG-FF1, SIG-FF2, and SIG-INV output from the flip-flop circuits FF1 and FF2 of the synchronization signal generation unit 33-1 and the inverter INV are sequentially equivalent to one cycle of the clock pulse signal CLK from the bit signal CNT3 (4). The signal is delayed one by one. That is, the signal SIG-FF1 is a signal delayed from the bit signal CNT3 (4) by one clock pulse, the signal SIG-FF2 is delayed by the same two periods, and the signal SIG-INV is delayed by the same three periods. The signal output from the synchronization signal generating unit 33-1, that is, the signal SIG-AND1 output from the AND circuit AND1, is the logical product of the signal SIG-FF2 and the signal SIG-INV, and thus becomes H level at time t32. It becomes L level at time t33. As a result, the test latch signal COMLAT becomes H level at time t32, becomes L level at time t33, and the memory write signal WEN similarly becomes H level at time t32 and becomes L level at time t33.

  Here, when the count signal transmission line 46-4 for transmitting the bit signal CNT3 (4) of the count signal CNT3 is defective, for example, there is a location where the resistance is higher than usual, and the bit signal CNT3 (4) is stored in the memory 36. A case where a delay of the period p31 occurs in the arrival time will be described. In this case, the digital value held in the memory 36 is a gray value memory holding signal corresponding to the binary value 0. However, the bit signal CNT3 (4) has no delay and the data to be held in the memory 36 is a gray value memory holding signal corresponding to the binary value 16, and is converted to a binary value 16 by the delay of the bit signal CNT3 (4). A small memory holding signal is held.

  Through the above operation, illegal data generated by the delay of the bit signal CNT3 (4) is written in the memory 36.

  At time t35, the timing signal supply unit 50 sets the test selection signal TESTSEL to the L level.

  At time t36, the horizontal scanning signal HSCAN is set to the H level, and the memory holding signal is transferred to the signal processing unit 60. The signal comparison unit 61 in the signal processing unit 60 compares the transferred memory holding signal with the expected value, determines whether or not there is a deviation, and ends the inspection of the bit signal CNT3 (4).

  By checking each bit signal according to the flowchart illustrated in FIG. 5 described in the first embodiment, it is possible to check whether a delay or a missing bit has occurred in the count signal CNT3.

  As described above, according to the configuration of the present embodiment, it is possible to inspect whether the count signal CNT3 is delayed or missing bits without operating the counter 32. Further, by using the test signal TESTSIG without operating the counter 32, the output of bit signals other than those to be inspected is not performed. Accordingly, the inspection time can be shortened when a bit signal other than the bit signal CNT3 (0) of the 0th bit is inspected. Therefore, the time required for the inspection of all the bit signals can be shortened in the configuration of this embodiment as compared with the case where the inspection is performed using the count signal output from the counter 32.

  The configuration of the present embodiment differs from the configuration of the AD conversion unit of the third embodiment in that the counter 32 is a binary counter and the test latch signal supply unit 33 has the configuration of the second embodiment. When the counter 32 is a binary counter, the memory holding signal held in the memory 36 is a gray counter even when the bit signal CNT (n) of the count signal CNT is delayed for one cycle of the clock pulse signal CLK. Compared to certain cases, it is significantly different from normal values. As illustrated in FIG. 10A, the counter 32 which is a binary counter is not provided with the Gray code conversion circuit 32-2 in the counter 32 illustrated in FIG. CNTs can be output.

  With reference to the timing diagram illustrated in FIG. 10B, the inspection of the count signal CNT2 (4) output from the count signal output unit 37 according to the present embodiment will be described with a focus on differences from the third embodiment. .

  First, at time t50, the count permission signal CNTEN becomes H level, and in response to this, the binary counter of the counter 32 starts counting. At time t51, the count signal output unit 37 outputs a count signal CNT2 delayed by one cycle of the clock pulse signal CLK with respect to the count signal CNT from the counter 32.

  The bit signal CNT2 (4) of the count signal CNT2 changes to H level at time t53, but the bit signal CNT (4) of the count signal CNT changes to H level at time t52 before the clock pulse signal CLK1 period. In the test latch signal supply unit 33, the signal SIG-AND1 is selected by DELAYSEL, and the test latch signal COMLAT becomes H level at time t53, and becomes L level after one cycle of the clock pulse signal CLK. Similarly, the memory write signal WEN becomes H level simultaneously with the test latch signal COMLAT and then becomes L level at the same time.

  Here, a case where a delay of the period p51 (one cycle of the clock pulse signal CLK) occurs in the bit signal CNT2 (4) and the waveform of the dotted line illustrated in FIG. 10B is described. In this case, when there is no delay, the binary value of the memory holding signal to be held in the memory 36 is 16, whereas the memory holding signal of the binary value 0 is held in the memory 36.

  The memory holding signal of binary value 0 is different from the memory holding signal of binary value 16, which is a normal value. For example, assume that the expected value / error range setting unit 72 sets the binary value of the expected value to 16 and the binary value of the error range to ± 1. In this case, when a memory holding signal having a binary value 0 is input to the signal processing unit 60, the signal comparison unit 61 outputs a comparison result indicating that there is a deviation from the expected value as the comparison result signal TOUT. Since it is clear that there is a difference between the expected value and the memory holding signal, it can be inferred that the bit signal CNT2 (4) has a delay.

  In the imaging apparatus of the present embodiment, the test latch signal COMLAT and the count signal CNT2 are signals that are delayed by one cycle of the clock pulse signal CLK with respect to the count signal CNT. That is, the test latch signal and the count signal CNT2 are synchronized signals. Therefore, this embodiment can be suitably implemented when it is desired to detect a slight delay of the count signal CNT2. Further, for example, low-bit bit signals such as the bit signals CNT2 (0) and CNT2 (1) have a shorter pulse period than a high-bit bit signal. When the low-bit bit signal is inspected, if the test latch signal COMLAT is delayed with respect to the count signal CNT2, the delay of the bit signal may not be detected suitably. In the case where the count signal CNT2 and the test latch signal COMLAT are synchronized as in the present embodiment, it is possible to suitably inspect the presence or absence of a bit signal delay even when inspecting a low-bit bit signal. Further, the presence or absence of a bit defect in the count signal CNT2 can also be inspected.

  As described above, even if the counter 32 is a binary counter, the bit signal CNT2 (n) can be inspected for any delay or loss.

  An embodiment in which the imaging apparatus described so far is applied to an imaging system will be described. Examples of the imaging system include a digital still camera, a digital camcorder, and a surveillance camera. FIG. 11 shows a block diagram when a solid-state imaging device is applied to a digital still camera as an example of the solid-state imaging system.

  In FIG. 11, reference numeral 111 denotes a barrier for protecting the lens, 112 denotes a lens that forms an optical image of a subject on the imaging apparatus 1, and 113 denotes a diaphragm for changing the amount of light passing through the lens 112. Reference numeral 115 denotes an imaging signal processing unit that processes an output signal output from the imaging apparatus 1.

  Since the imaging signal which is the signal output from the imaging device 1 is a digital signal as in the first to fifth embodiments, the imaging signal processing unit 115 includes a digital signal processing unit and is output from the imaging device 1. The signal is output after being subjected to various corrections and compression as necessary.

  In FIG. 11, 116 is a buffer memory unit for temporarily storing image data, 118 is an interface unit for recording or reading data on a recording medium, and 119 is a semiconductor for recording or reading image data. A removable recording medium such as a memory. Reference numeral 117 denotes an interface unit for communicating with an external computer or the like. Reference numeral 1110 denotes an overall control / arithmetic unit that controls various calculations and the entire digital still camera, and 1111 denotes a timing generation unit that outputs various timing signals to the imaging apparatus 1 and the imaging signal processing unit 115. Here, the timing signal or the like may be input from the outside, and the imaging system may include at least the imaging device 1 and the imaging signal processing unit 115 that processes the imaging signal output from the imaging device 1.

  Although the imaging device described in the first to fifth embodiments includes the signal comparison unit 61, the imaging device signal processing unit 115 may include the signal comparison unit 61.

  As described above, the imaging system of the present embodiment can perform an imaging operation by applying the imaging device 1.

  The imaging system of the present embodiment includes any one of the imaging devices 1 described in the first to fifth embodiments. When manufacturing the imaging system by performing the process of incorporating the imaging device 1 into the imaging system, it is preferable to operate the imaging device 1 in the inspection mode before incorporating the imaging device 1 into the imaging system in advance. Thereby, when operated in the inspection mode, the imaging device 1 determined by the signal comparison unit 61 included in the imaging device 1 to be normal can be incorporated into the imaging system. Therefore, an imaging system with few failures can be manufactured and provided.

DESCRIPTION OF SYMBOLS 1 Imaging device 10 Pixel part 20 Vertical scanning part 29 Circuit part 30 AD conversion part 31 Ramp signal supply part 32 Counter 33 Test latch signal supply part 34 Comparison part 35 OR circuit 36 Memory 39 Vertical signal line 40 Horizontal scanning part 50 Timing signal supply Unit 60 signal processing unit 61 signal comparison unit 70 setting unit 80 communication unit

Claims (27)

A plurality of circuit units each including a memory that holds a digital signal, and a comparator that supplies a comparison result signal indicating a comparison result of comparing an analog signal and a reference signal that changes with time, to the memory;
A counter that counts a clock pulse signal in parallel with a change in the reference signal, generates a count signal having a plurality of bit signals, and outputs the count signal;
A plurality of count signal transmission lines for supplying the count signal to the plurality of memories;
An analog-to-digital conversion circuit that converts the analog signal into the digital signal by holding the count signal as the digital signal when the comparison result signal of the corresponding comparator changes.
The analog-digital conversion circuit operates in an inspection mode,
A test latch signal supply unit;
A signal comparison unit;
Further comprising
In the inspection mode,
The comparator does not supply the comparison result signal to the memory;
The counter further supplies the count signal to the test latch signal supply unit,
The test latch signal supply unit includes a plurality of test latch signals for holding the count signal in the plurality of memories according to a timing at which a signal level of any one of the plurality of bit signals changes. Of the memory,
The count signal held by a plurality of the memories is supplied to the signal comparison unit,
The memory receives the signal value of the digital signal held by the memory to which the test latch signal is supplied and the timing at which the test latch signal is supplied when the count signal is supplied from the counter to the memory without delay. An analog-to-digital conversion circuit characterized in that the count signal transmission line is inspected by comparing a signal value of the digital signal to be held.   2. The analog digital according to claim 1, wherein a period from when the signal level of any one of the plurality of bit signals changes to when the test latch signal is supplied is variable. Conversion circuit.   The test latch signal supply unit has a pulse period of the clock pulse signal from the timing at which the signal level of any one of the bit signals changes to the supply of the test latch signal. 3. The analog-digital conversion circuit according to claim 1, wherein the analog-digital conversion circuit is an integer multiple. The test latch signal supply unit changes the signal level by delaying a time that is an integral multiple of the pulse period of the clock pulse signal with respect to the timing at which the signal level of any one of the plurality of bit signals changes. Generate multiple pulse signals with different delay times,
4. The analog-digital conversion circuit according to claim 3, wherein a signal selected from a plurality of the pulse signals is supplied as the test latch signal.   The test latch signal supply unit includes the test latch signal in a period within two cycles of the pulse period of the clock pulse signal from the timing when the signal level of the bit signal of any of the plurality of bit signals of the count signal changes. 5. The analog-digital conversion circuit according to claim 1, wherein a signal is supplied. Each of the plurality of bit signals is transmitted by each of the plurality of count signal transmission lines,
6. The analog-digital conversion circuit according to claim 1, wherein the test latch signal is supplied in accordance with a timing at which any one of the plurality of count signal transmission lines changes. The clock pulse signal is further supplied to the test latch signal supply unit,
The test latch signal supply unit supplies the test latch signal in synchronization with a timing at which a signal level of the supplied clock pulse signal changes. Analog-digital conversion circuit.   7. The analog-digital conversion circuit according to claim 1, wherein a clock pulse signal different from the clock pulse signal supplied to the counter is supplied to the test latch signal supply unit. The number of bits of the count signal is a bit;
The number of bits of the digital signal held by the memory is b bits which is smaller than the a bits;
The signal comparison unit is
The digital signal held by the memory to which the test latch signal is supplied, and the memory held by the memory at a timing when the test latch signal is supplied when the count signal is supplied from the counter to the memory without delay. 9. The analog-to-digital conversion circuit according to claim 1, wherein a comparison with a signal value of a digital signal is performed between the same digits of the b bits. The test latch signal supply unit includes a synchronization signal generation unit and a mask unit,
The synchronization signal generation unit performs an operation of supplying a signal to the mask unit according to a timing at which a signal level of the bit signal of any of the plurality of bit signals changes,
Whether the signal supplied from the synchronization signal generator is supplied to the plurality of memories is switched by the mask unit,
The analog-digital conversion circuit according to claim 1, wherein the signal supplied to the plurality of memories by the mask unit is the test latch signal.   The analog / digital signal according to claim 1, wherein the count signal is further supplied from the counter to the test latch signal supply unit through a signal path different from the count signal transmission line. Conversion circuit. The count signal transmission line further includes a count signal output unit that supplies a signal obtained by delaying the count signal to the plurality of memories.
Of the plurality of bit signals, the time from when the signal level of any one of the bit signals changes to the time when the test latch signal is supplied, and the count signal of the signal output by the count signal output unit 12. The analog-digital conversion circuit according to claim 11, wherein the delay time is equal. The count signal is supplied from the counter to the test latch signal supply unit via a bit signal selection unit,
The bit signal selection unit selects the bit signal to be supplied to the test latch signal supply unit from among the plurality of bit signals included in the count signal,
The test latch signal supply unit supplies the test latch signal according to a timing at which the bit signal selected by the bit signal selection unit is supplied. Analog-digital conversion circuit. Instead of the count signal supplied from the counter, a test signal corresponding to at least a part of the bit signals included in the count signal is supplied to the test latch signal supply unit,
11. The analog-to-digital conversion circuit according to claim 1, wherein the test latch signal is supplied to the plurality of memories in accordance with a timing at which a signal level of the test signal changes.   15. The delay characteristic of the count signal transmission line is the same as the delay characteristic of the transmission line that transmits the test latch signal from the test latch signal supply unit to the plurality of memories. Any one of the analog-digital conversion circuits.   The analog / digital conversion circuit according to claim 1, wherein the test latch signal supply unit supplies the test latch signal to all of the plurality of memories. The signal comparison unit is
The memory receives the signal value of the digital signal held by the memory to which the test latch signal is supplied and the timing at which the test latch signal is supplied when the count signal is supplied from the counter to the memory without delay. The analog-to-digital conversion circuit according to claim 1, wherein a predetermined signal range including a signal value of the digital signal to be held is compared. The signal comparison unit supplies the test latch signal when the signal value of the digital signal held by the memory to which the test latch signal is supplied and the count signal is supplied from the counter to the memory without delay. Comparing the signal value of the digital signal held by the memory at a timing to detect a signal value shift,
The analog-to-digital conversion circuit according to claim 1, wherein it is determined whether or not the deviation of the signal value is within a predetermined signal range. An imaging apparatus comprising the analog-digital conversion circuit according to claim 1,
The imaging apparatus further includes a plurality of columns of pixels including a photoelectric conversion unit that generates a charge by photoelectric conversion,
An imaging apparatus, wherein each of the plurality of comparators is connected to each column of the plurality of columns of pixels. An imaging device having a plurality of columns of pixels including a photoelectric conversion unit that generates electric charge by photoelectric conversion, and an analog-digital conversion circuit,
The analog-digital conversion circuit is:
A plurality of circuit units each including a memory that holds a digital signal, and a comparator that supplies a comparison result signal indicating a comparison result of comparing an analog signal and a reference signal that changes with time, to the memory;
A counter that counts a clock pulse signal in parallel with a change in the reference signal, generates a count signal having a plurality of bit signals, and outputs the count signal;
A plurality of count signal transmission lines for supplying the count signal to the plurality of memories;
An analog-to-digital conversion circuit that converts the analog signal into the digital signal by holding the count signal as the digital signal when the comparison result signal of the corresponding comparator changes.
Each of the plurality of comparators is connected to each column of the plurality of columns of pixels,
The imaging device operates in an inspection mode;
The imaging apparatus further includes a test latch signal supply unit and a signal comparison unit,
In the inspection mode,
The comparator does not supply the comparison result signal to the memory;
The counter further supplies the count signal to the test latch signal supply unit,
The test latch signal supply unit includes a plurality of test latch signals for holding the count signal in the plurality of memories according to a timing at which a signal level of any one of the plurality of bit signals changes. Of the memory,
The count signal held by a plurality of the memories is supplied to the signal comparison unit,
The memory receives the signal value of the digital signal held by the memory to which the test latch signal is supplied and the timing at which the test latch signal is supplied when the count signal is supplied from the counter to the memory without delay. An image pickup apparatus, wherein the count signal transmission line is inspected by comparing a signal value of the digital signal to be held. Multiple memories,
A count signal transmission line;
A counter for counting a clock pulse signal, and supplying a count signal having a plurality of bit signals to the plurality of memories via the count signal transmission line;
An analog-digital conversion circuit inspection method having
A test latch signal for holding the count signal in the plurality of memories is supplied to the plurality of memories according to the timing at which the signal level of any one of the bit signals changes,
The memory receives the signal value of the count signal held by the memory to which the test latch signal has been supplied and the timing at which the test latch signal is supplied when the count signal is supplied from the counter to the memory without delay. An inspection method for an analog-digital conversion circuit, wherein the count signal transmission line is inspected by comparing with a signal value of the count signal to be held. The number of bits of the count signal is a bit, and the digital signal held by the memory is b bits smaller than the a bits,
The digital signal held by the memory to which the test latch signal is supplied, and the memory held by the memory at a timing when the test latch signal is supplied when the count signal is supplied from the counter to the memory without delay. The method for inspecting an analog-to-digital conversion circuit according to claim 21, wherein a comparison with a signal value of a digital signal is performed between the same digits of the b bits. The timing at which the signal level of any one of the plurality of bit signals has changed is a plurality of times within the period in which the counter operates,
A pulse signal generation operation is performed according to each of the timings when the signal level of the bit signal of any of the plurality of bit signals has changed,
23. The analog-digital conversion circuit inspection method according to claim 21, wherein one of the generated plurality of pulse signals is supplied as the test latch signal. Change the delay time of a pulse signal whose signal level changes by delaying a time that is an integral multiple of the pulse period of the clock pulse signal with respect to the timing at which the signal level of any one of the plurality of bit signals changes. To generate multiple
24. The inspection method for an analog-digital conversion circuit according to claim 21, wherein one of the plurality of pulse signals is selected and supplied as the test latch signal. Instead of the count signal, a signal obtained by delaying the count signal is supplied to the plurality of memories,
The delay time from the timing when the count signal is changed until the test latch signal is supplied is made equal to the delay time between the signal supplied to the plurality of memories and the count signal. Item 25. A method for inspecting an analog-digital conversion circuit according to any one of Items 21 to 24. Selecting any one of the plurality of bit signals included in the count signal;
26. The test method for an analog-digital conversion circuit according to claim 21, wherein the test latch signal is supplied in accordance with a timing at which a signal level of the selected bit signal is changed. An imaging system manufacturing method including an imaging device and an imaging signal processing unit that processes an imaging signal output from the imaging device,
The imaging device includes an analog-digital conversion circuit and a pixel unit,
The analog-digital conversion circuit is:
A plurality of memory units, a comparator for supplying a comparison result signal, which is a signal indicating a comparison result obtained by comparing a reference signal that changes with time and an analog signal, to the memory; a plurality of circuit units; and a count signal transmission line When,
A counter for counting a clock pulse signal, and supplying a count signal having a plurality of bit signals to the plurality of memories via the count signal transmission line;
Have
The pixel unit includes a plurality of columns of pixels including a photoelectric conversion unit that generates charge by photoelectric conversion.
In the imaging device, the circuit unit is provided in each column of the pixels in a plurality of columns, and the pixel outputs a pixel signal that is the analog signal to the comparator,
27. A method for manufacturing an imaging system, comprising the method for inspecting an analog-digital conversion circuit according to claim 21.

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