JP2013062415A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

A breakdown voltage in an array end pattern between a memory cell array and a peripheral circuit is improved.
A floating gate is provided on a first insulating film on a semiconductor substrate. The intergate insulating film is provided on the floating gate, and the control gate is provided on the intergate insulating film. The memory cell includes a first insulating film, a floating gate, an inter-gate insulating film, and a control gate. The peripheral circuit is provided around the memory cell array. The first dummy cell includes a first insulating film, a floating gate, an inter-gate insulating film, and a control gate, and is provided at the end of the memory cell array. The second dummy cell includes a second insulating film thicker than the first insulating film, and is provided between the first dummy cell and the peripheral circuit. In the first dummy cell, the inter-gate insulating film and the control gate are provided on the upper surface and two side surfaces of the floating gate.
[Selection] Figure 3

Description

  Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.

  A NAND flash EEPROM is known as a nonvolatile semiconductor memory device that can be electrically rewritten and highly integrated. The memory cell transistor of the NAND flash EEPROM has a stack gate structure including a floating gate for accumulating charges and a control gate for controlling the voltage of the floating gate.

  In recent years, with the high integration of memory cells, the pattern of the memory cell array is miniaturized. As the memory cell array is further miniaturized, it becomes difficult to process the floating gate and STI (Shallow Trench Isolation) of the memory cell array even by the line space by the lithography technique. Therefore, when processing the floating gate of the memory cell array and the STI trench, a sidewall transfer process using the sidewall as a mask is used. The sidewall transfer process is a technique for forming a sidewall film on a side surface of a core material, removing the core material, and then processing the material using the sidewall film as a mask.

  When a memory is manufactured using such a sidewall transfer process, the memory cell array and the peripheral circuit are processed separately. When the memory cell array and the peripheral circuit are processed individually, a relatively thick line pattern (also referred to as an array end pattern) is provided between the memory cell array and the peripheral circuit in order to draw a fine pattern of the memory cell array. The array end pattern is arranged adjacent to the memory cell array with a space approximately equal to the interval between adjacent memory cells in order to sufficiently expose the pattern of the memory cells close to the end of the memory cell array. Along with the miniaturization of the memory cell array, the interval between the memory cell array and the array end pattern becomes narrow as is the interval between the memory cells.

  Conventionally, when forming a sidewall mask of the sidewall transfer process in the memory cell array region, the boundary of the photoresist covering the peripheral circuit is located between the memory cell array and the array end pattern. Using this photoresist as a mask, the core material on the memory cell array side is removed by wet etching to form a sidewall mask.

  However, if the space between the memory cell array and the array end pattern becomes narrow due to element miniaturization, it becomes technically difficult to position the boundary of the photoresist between the memory cell array and the array end pattern.

  In addition, the solvent for wet etching easily penetrates into the array end pattern, and a part of the core material in the array end pattern is etched, and this core material may be deformed. In this case, the shape of the core material is transferred to the floating gate and the semiconductor substrate, and a desired shape may not be obtained for the STI in the array end pattern. This reduces the reliability of the memory.

  Further, in the array end pattern, the floating gate and the STI trench are processed while leaving the core material as in the peripheral region. Therefore, in the array end pattern, the floating gate faces the control gate on its upper surface, so that the coupling capacitance ratio between the floating gate, the control gate, and the channel is reduced. This causes a decrease in the breakdown voltage between the floating gate and the control gate or the breakdown voltage between the floating gate and the substrate in the array end pattern.

JP 2008-27978 A

  Provided is a semiconductor memory device capable of improving the breakdown voltage in an array end pattern between a memory cell array and a peripheral circuit even when miniaturized, and which can be manufactured more easily than in the past.

  The semiconductor memory device according to the present embodiment includes a semiconductor substrate. A first insulating film is provided on the semiconductor substrate. The charge storage layer is provided on the first insulating film and can store charges. The inter-gate insulating film is provided on the charge storage layer. The control gate is provided on the inter-gate insulating film and controls the voltage of the charge storage layer. The plurality of memory cells include a first insulating film, a charge storage layer, an inter-gate insulating film, and a control gate. The memory cell array has a plurality of memory cells. The peripheral circuit is provided around the memory cell array. The first dummy cell includes a first insulating film, a charge storage layer, an inter-gate insulating film, and a control gate, and is provided at the end of the memory cell array. The second dummy cell includes a second insulating film that is provided on the semiconductor substrate and is thicker than the first insulating film, and is provided between the first dummy cell and the peripheral circuit. In the first dummy cell, the inter-gate insulating film and the control gate are provided on the upper surface and two side surfaces of the charge storage layer.

FIG. 2 is a plan view showing a configuration of a memory according to the first embodiment. 1 is a configuration diagram of a memory cell array MCA according to a first embodiment. FIG. FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. 1. Sectional drawing which shows the manufacturing method of the memory by 1st Embodiment. FIG. 5 is a cross-sectional view illustrating the method for manufacturing the memory following FIG. 4. FIG. 6 is a cross-sectional view illustrating the method for manufacturing the memory following FIG. 5. FIG. 7 is a cross-sectional view illustrating the method for manufacturing the memory following FIG. 6. FIG. 8 is a cross-sectional view illustrating the method for manufacturing the memory following FIG. 7. FIG. 9 is a cross-sectional view showing the memory manufacturing method following FIG. 8. FIG. 10 is a cross-sectional view illustrating the method for manufacturing the memory following FIG. 9. FIG. 11 is a cross-sectional view showing the memory manufacturing method following FIG. 10. Sectional drawing which shows the structure of the memory according to 2nd Embodiment. Sectional drawing which shows the manufacturing method of the memory by 2nd Embodiment. FIG. 14 is a cross-sectional view illustrating the method for manufacturing the memory following FIG. 13. Sectional drawing which shows the structure of the memory according to 3rd Embodiment. Sectional drawing which shows the manufacturing method of the memory by 3rd Embodiment. FIG. 17 is a cross-sectional view showing the memory manufacturing method following FIG. 16.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a plan view showing a configuration of a NAND flash EEPROM (hereinafter also simply referred to as a memory) according to the first embodiment. The memory includes a memory cell array MCA, a peripheral circuit PRI, a first dummy cell DC1, and a second dummy cell DC2.

  The memory cell array MCA has a plurality of memory cells MC formed on the active area AA. A detailed configuration of the memory cell array MCA is shown in FIG. The peripheral circuit is formed around the memory cell array MCA and includes a plurality of semiconductor elements (not shown) provided for controlling the memory cell array MCA.

  The first and second dummy cells DC1, DC2 are formed in the region of the array end pattern AEP. The array end pattern AEP is a line pattern provided between the memory cell array MCA and the peripheral circuit PRI in order to draw a fine pattern of the memory cell array MCA. In the present embodiment, in order for the first dummy cell DC1 to sufficiently expose the pattern of the memory cell MC close to the end of the memory cell array MCA, the memory cell array is spaced by an interval S0 that is approximately the same as the interval between adjacent memory cells MC. It is arranged to be adjacent to.

  A boundary ZL as a first boundary shown on the region of the array end pattern AEP indicates a boundary between a high breakdown voltage transistor having a thick gate insulating film and a low breakdown voltage transistor having a thin gate insulating film. A high breakdown voltage gate insulating film is provided on the peripheral circuit PRI side with the boundary ZL as a boundary, and a low breakdown voltage gate insulating film (tunnel gate insulating film) is provided on the memory cell array MCA side. Therefore, the tunnel gate insulating film of the memory cell MC is a thin gate insulating film for a low breakdown voltage transistor. The gate insulating film of the transistor of the peripheral circuit PRI is a thick gate insulating film for a high voltage transistor.

  In the present embodiment, the boundary ZL is located between the first dummy cell DC1 and the second dummy cell DC2. Therefore, the first dummy cell DC1 has a gate insulating film for low breakdown voltage (reference number 20 in FIG. 3). The second dummy cell DC2 has a high breakdown voltage gate insulating film (reference numeral 30 in FIG. 3).

  The boundary AP as the second boundary is a boundary of the photoresist that covers the peripheral circuit PRI when the sidewall mask is formed in the memory cell array MCA by using the sidewall transfer process. It is difficult for the lithography technique to position the boundary AP between the memory cell array MCA and the array end pattern AEP (interval S0) due to element miniaturization. On the other hand, in the present embodiment, the boundary AP is positioned in an area of the array end pattern AEP (between the first dummy cell DC1 and the second dummy cell DC2) wider than the interval S0. Therefore, the photoresist boundary AP can be easily positioned by lithography. When there is a boundary AP in the region of the array end pattern AEP, the core material in the array end pattern AEP does not remain deformed and is removed (see FIG. 7). For this reason, the dummy cells DC1 and DC2 in the array end pattern AEP are formed to have substantially the same size as the memory cell MC.

  The boundary EB as the third boundary is a boundary of the photoresist that covers the peripheral circuit PRI when the element isolation STI is etched back. In the region of the memory cell array MCA, when the element isolation STI is formed, the element isolation STI is etched back to expose the side surface of the floating gate FG (charge storage layer), and an IPD (Inter-Poly Dielectric) film is formed on the side surface of the floating gate FG. A control gate CG is provided. At the time of etching back the element isolation STI, the peripheral circuit PR is protected with a photoresist. The boundary EB is located between the first dummy cell DC1 and the second dummy cell DC2. Accordingly, the IPD film and the control gate CG are provided on both side surfaces of the floating gate FG of the first dummy cell DC1. On the other hand, the IPD film and the control gate CG are hardly provided on both side surfaces of the floating gate FG of the second dummy cell DC1, and the element isolation STI is left. A more detailed configuration and manufacturing method of the memory cell MC and the first and second dummy cells DC1 and DC2 will be described later.

  FIG. 2 is a configuration diagram of the memory cell array MCA according to the first embodiment. The memory cell array includes a plurality of memory blocks BLOCK. FIG. 2 shows a configuration of a certain block BLOCKi (i is an integer). The block BLOCKi is a unit of data erasure and includes a plurality of NAND strings NS0 to NS5 connected to the bit line BL of each column. The NAND strings NS0 to NS5 include a plurality of memory cells MC connected in series and select gate transistors SGS and SGD connected to both ends of these memory cells MC. The NAND string NS is provided on the active area AA formed in a stripe shape as shown in FIG. In this example, five memory cells MC are connected in series in each NAND string NS, but usually 32 or 64 memory cells MC are connected in series. One ends of the NAND strings NS0 to NS5 are connected to the corresponding bit lines BL0 to BL5, and the other ends are connected to the common source line SL.

  The control gate CG of the memory cell MC is connected to the word lines WL0 to WL4 corresponding to the page to which the memory cell MC belongs. For example, the control gates of the memory cells MC belonging to the page j (j = 0 to 4) are connected to the word line WLj. The gates of the selection gate transistors SGD and SGS are connected to the selection gate line SGL1 or SGL2. A page is a unit of data reading or data writing.

  The plurality of word lines WL extend in the row direction, and the plurality of bit lines BL extend in the column direction so as to be substantially orthogonal to the row direction.

  As shown in FIG. 2, the memory cell MC is provided corresponding to a lattice-shaped intersection formed by the word line WL and the bit line BL. For example, the lattice-shaped intersections constituted by the word lines WL0 to WL4 and the bit lines BL0 to BL5 are located in a 5 × 6 matrix. The memory cells MC are two-dimensionally arranged in a 5 × 6 matrix so as to correspond to these intersections. The block of this embodiment has 5 × 6 (30) memory cells MC, but the number of memory cells MC in one block is not limited to this.

  The memory cell MC is composed of an n-type FET (Field-Effect Transistor) having a floating gate FG and a control gate CG. By applying a voltage to the control gate CG by the word line WL, charges (electrons) are injected into the floating gate FG, or charges (electrons) are discharged from the floating gate FG. As a result, data is written to the memory cell MC or data in the memory cell MC is erased. The memory cell MC has a threshold voltage corresponding to the amount of charges (number of electrons) accumulated in the floating gate FG. The memory cell MC can electrically store binary data (1 bit) or multi-value data (2 bits or more) as a difference in threshold voltage.

  FIG. 3 is a cross-sectional view taken along line 3-3 in FIG. FIG. 3 shows a configuration of the memory cell array MCA, the array end pattern AEP, and the peripheral circuit PRI.

  The memory according to the present embodiment includes a semiconductor substrate 10. Memory cell MC includes a tunnel gate insulating film 20, a floating gate FG, an inter-gate insulating film IPD, and a control gate CG.

  A tunnel gate insulating film 20 as a first insulating film is provided on the semiconductor substrate 10. The tunnel gate insulating film 20 is a low breakdown voltage gate insulating film, and is formed using, for example, a silicon oxide film. The floating gate FG is provided on the tunnel gate insulating film 20, and can store data by accumulating or discharging charges (electrons). The floating gate FG is formed using, for example, polysilicon. The inter-gate insulating film IPD is provided on the floating gate FG. The inter-gate insulating film IPD is formed using, for example, a silicon oxide film, a silicon nitride film, or a high-k film having a dielectric constant higher than that of the silicon oxide film. The control gate CG is provided on the inter-gate insulating film IPD and controls the voltage of the floating gate FG. The control gate CG is formed using, for example, polysilicon.

  The control gate CG and the inter-gate insulating film IPD are dropped toward the element isolation STI (semiconductor substrate 10) between a plurality of adjacent memory cells MC, and are formed on two side surfaces of the floating gate FG facing the row direction. Facing. As a result, the facing area between the control gate CG and the floating gate FG is increased, so that the coupling capacitance ratio Cr between the control gate CG, the floating gate FG and the channel is increased. Thereby, the voltage of the floating gate FG can be easily controlled by the control gate CG.

  The array end pattern AEP between the memory cell array MCA and the peripheral circuit PRI is provided with first and second dummy cells DC1 and DC2. The size of the first and second dummy cells DC1 and DC2 in the planar layout is substantially the same as that of the memory cell MC.

  The first dummy cell DC1 has a configuration similar to that of the memory cell MC. That is, the first dummy cell DC1 includes the tunnel gate insulating film 20, the floating gate FG, the inter-gate insulating film IPD, and the control gate CG. The first dummy cell DC1 is provided adjacent to the end of the memory cell array MCA at a position separated from the memory cell array MCA by the interval S0. The interval S0 is set so that the memory cell array MCA can be finely processed, and may be approximately the same as or larger than the interval between the memory cells MC.

  Since the boundary EB is between the first dummy cell DC1 and the second dummy cell DC2, in the first dummy cell DC1, the control gate CG and the inter-gate insulating film IPD are not only the upper surface of the floating gate FG, but also the row It is also provided on two side faces that face the direction. In other words, the control gate CG and the inter-gate insulating film IPD are dropped toward the element isolation STI (semiconductor substrate 10) on both sides of the floating gate FG in the row direction. As a result, the control gate CG faces not only the upper surface of the floating gate FG but also the two side surfaces, so that the coupling capacitance ratio Cr increases. As a result, even when a voltage is applied to the control gate CG (word line WL) in data writing or data erasing, the intergate insulating film IPD or the tunnel gate insulating film 20 is destroyed in the first dummy cell DC1. It becomes difficult to be done.

  The second dummy cell DC2 is provided between the first dummy cell DC1 and the peripheral circuit PRI, and includes a gate insulating film 30 as a second insulating film thicker than the tunnel gate insulating film 20. This is because the boundary ZL is between the first dummy cell DC1 and the second dummy cell DC2. Further, the second dummy cell DC2 includes a floating gate FG formed on the gate insulating film 30, an inter-gate insulating film IPD provided on the floating gate FG, and a control gate provided on the inter-gate insulating film IPD. CG.

  In the second dummy cell DC2, the control gate CG and the inter-gate insulating film IPD are provided on the upper surface of the floating gate FG, but are dropped toward the element isolation STI (semiconductor substrate 10) on both sides of the floating gate FG. Not. Two side surfaces of the floating gate FG facing the row direction face the element isolation STI. This is because the boundary EB is located between the first dummy cell DC1 and the second dummy cell DC2. However, since the second dummy cell DC2 includes the gate insulating film 30 for high breakdown voltage, the breakdown voltage of the second dummy cell DC2 does not matter.

  According to this embodiment, in the first dummy cell DC1, the control gate CG and the inter-gate insulating film IPD are provided not only on the upper surface of the floating gate FG but also on the two side surfaces facing the row direction. Since the control gate CG faces not only the upper surface of the floating gate FG but also two side surfaces, the coupling capacitance ratio Cr increases. As a result, even when a voltage is applied to the control gate CG (word line WL) in data writing or data erasing, the intergate insulating film IPD or the tunnel gate insulating film 20 is destroyed in the first dummy cell DC1. It becomes difficult to be done. That is, the breakdown voltage of the first and second dummy cells DC1 and DC2 in the array end pattern AEP can be increased.

  4 to 11 are cross-sectional views illustrating the method for manufacturing the memory according to the first embodiment. First, as shown in FIG. 4, a tunnel gate insulating film 20 as a first insulating film and a gate insulating film 30 as a second insulating film are formed on the semiconductor substrate 10. The tunnel gate insulating film 20 is formed on the memory cell array MCA side with the boundary ZL as the first boundary, and the gate insulating film 30 is formed on the peripheral circuit PRI side. The tunnel gate insulating film 20 is several nm, for example, and the gate insulating film 30 is thicker than the tunnel gate insulating film 20, for example, about 30 nm.

  The tunnel gate insulating film 20 and the gate insulating film 30 are formed using, for example, a silicon oxide film formed by thermally oxidizing the semiconductor substrate 10. The surface of the semiconductor substrate 10 on the peripheral circuit PRI side is etched in advance so that the surface of the tunnel gate insulating film 20 and the surface of the gate insulating film 30 are the same surface.

  Here, the boundary ZL is located between the first dummy cell DC1 and the second dummy cell DC2 to be formed later, and is not located between the memory cell MC and the first dummy cell DC1. That is, the boundary ZL is set so as to overlap with the array end pattern AEP wider than the interval S0 between the memory cell MC and the first dummy cell DC1. An interval S0 between the memory cell MC and the first dummy cell DC1 is, for example, about 50 to 150 nm, and an interval between the first dummy cell DC1 and the second dummy cell DC2 (interval of the array end pattern AEP). Is, for example, about 500 nm. Therefore, according to the present embodiment, alignment is relatively easy in the lithography process for etching the semiconductor substrate 10 and forming the gate insulating films 20 and 30.

  Next, as shown in FIG. 5, a material for the floating gate FG is deposited on the tunnel gate insulating film 20 and the gate insulating film 30. The floating gate FG is formed using, for example, polysilicon.

  Next, the material of the first mask material 41, the material of the second mask material 42, and the material of the core material 50 are deposited on the material of the floating gate FG. The first mask material 41 is formed using an insulating film such as a silicon oxide film. The second mask material 41 is formed using, for example, an insulating film different from the first mask material and the core material 50, such as an amorphous silicon film or a silicon nitride film. The core material 50 is formed using an insulating film such as a silicon oxide film, for example. Next, the material of the core material 50 is processed using a lithography technique and an RIE (Reactive Ion Etching) method. At this time, as shown in FIG. 6, the core material 50 of the array end pattern AEP overlaps the boundary ZL. Subsequently, the material of the sidewall mask 60 is deposited on the upper surface and side surfaces of the core material 50 and the material of the second mask material 42. The material of the sidewall mask 60 is formed using an insulating film different from the core material 50, for example, a silicon nitride film or amorphous silicon. The material of the sidewall mask 60 is formed so as to cover the upper surface and the side surface of the core material 50 with the material of the sidewall mask 60. Next, the material of the sidewall mask 60 is anisotropically etched using the RIE method. Thereby, as shown in FIG. 6, the sidewall mask 60 is left on the side surface of the core member 50.

  Next, using the lithography technique, the region on the peripheral circuit PRI side is covered with the photoresist PR with the boundary AP as the second boundary as the boundary. Similarly to the boundary ZL, the boundary AP is located between the first dummy cell DC1 and the second dummy cell DC2, and is set to overlap the array end pattern AEP.

  Next, using the photoresist PR as a mask, the exposed core member 50 is selectively etched while leaving the sidewall mask 60 left. At this time, the core material 50 is removed using isotropic etching such as wet etching or CDE (Chemical Dry Etching). The boundary AP overlaps the array end pattern AEP, and a part of the upper surface of the core member 50 in the array end pattern AEP is exposed. Accordingly, the core material 50 of the array end pattern AEP is also removed at the same time. The core material 50 on the peripheral circuit PRI side covered with the photoresist PR is left. Thereby, the structure shown in FIG. 7 is obtained.

  Since the core member 50 is left on the peripheral circuit PRI side from the boundary AP (array end pattern AEP), the core member 50 and the sidewall mask 60 are element electrode patterns (gate electrode or capacitor electrode, etc.) in the peripheral circuit PRI. ). On the other hand, since the core material 50 is removed on the memory cell array MCA side from the boundary AP, the sidewall mask 60 is formed in the pattern of the floating gate FG. Further, since the core member 50 is removed also on the peripheral circuit PRI side from the boundary AP in the array end pattern AEP, the sidewall mask 60 is formed in the pattern of the floating gate FG.

  Next, after removing the photoresist PR, the second mask material 42 is processed by the RIE method using the sidewall mask 60 or the core material 50 as a mask. The first mask material 41 is processed by the RIE method using the second mask material 42 as a mask. Using the first mask material 41 as a mask, the material of the floating gate FG, the tunnel gate insulating film 20, the gate insulating film 30, and the semiconductor substrate 10 are processed by the RIE method. Thus, as shown in FIG. 8, the floating gate FG is formed and the trench 70 used for the element isolation STI is formed.

  The tunnel gate insulating film 20 and the gate insulating film 30 having different thicknesses are adjacent to each other with the boundary ZL as a boundary. When etching the insulating films 20 and 30 (for example, silicon oxide film), the etching selectivity of the insulating films 20 and 30 is higher than that of the semiconductor substrate 10 (for example, silicon single crystal). At the time when the etching of the insulating films 20 and 30 is finished and the etching of the semiconductor substrate 10 is started, the step of the semiconductor substrate 10 at the ZL boundary portion remains. The etching rate of the semiconductor substrate 10 does not change in any of the memory cell MCA, the array end pattern AEP, and the peripheral circuit PRI. Therefore, a step ST is formed at the bottom of the trench 70 in the array end pattern AEP with the boundary ZL as a boundary.

  Next, the element isolation insulating film 80 is filled in the trench 70. Subsequently, the element isolation insulating film 80 is planarized until the upper surface of the floating gate FG is exposed. Thereby, the structure shown in FIG. 9 is obtained.

  Next, as shown in FIG. 10, using the lithography technique, the region on the peripheral circuit PRI side is covered with the photoresist PR2 with the boundary EB as the third boundary as a boundary, and the region on the memory cell array MCA side is exposed. . Next, as shown in FIG. 10, the element isolation insulating film 80 in the memory cell array MCA is etched back to expose the upper part of the side surface of the floating gate FG. The boundary EB is between the first dummy cell DC1 and the peripheral circuit PRI. In the present embodiment, the boundary EB overlaps the array end pattern AEP. Therefore, the side surface of the floating gate FG of the first dummy cell DC1 is also exposed.

  On the other hand, in the present embodiment, since the second dummy cell DC2 is covered with the photoresist PR2, the side surface of the second dummy cell DC2 remains covered with the element isolation insulating film 80.

  After the removal of the photoresist PR2, as shown in FIG. 11, an inter-gate insulating film IPD is deposited on the upper surface and side surfaces of the floating gates FG of the memory cell MC and the first dummy cell DC1, respectively. That is, the inter-gate insulating film IPD is dropped toward the element isolation STI (semiconductor substrate 10) between adjacent memory cells MC. Further, the inter-gate insulating film IPD is formed so as to cover the upper surface and the side surface of the first dummy cell DC1, and is dropped toward the element isolation STI (semiconductor substrate 10) on both sides of the first dummy cell DC1. Yes. Further, since the side surface of the second dummy cell DC2 remains covered with the element isolation insulating film 80, the inter-gate insulating film IPD is deposited on the upper surface of the second dummy cell DC2, but not on the side surface. .

  The film thickness of the inter-gate insulating film IPD is set to be less than a half of the interval between the memory cells MC so that the inter-gate insulating film IPD does not embed between adjacent memory cells MC.

  Next, in the peripheral circuit PRI, a part of the inter-gate insulating film IPD is removed in order to electrically connect the floating gate FG and the control gate CG. Further, also in the memory cell array MCA, a part of the inter-gate insulating film IPD of the selection gate transistor portion (not shown) is removed as necessary.

  Next, a material for the control gate CG is deposited on the inter-gate insulating film IPD. The control gate CG is formed using, for example, polysilicon or metal silicide. The control gate CG is formed on the top and side surfaces of the floating gates FG of the memory cell MC and the first dummy cell DC1 via the inter-gate insulating film IPD. In other words, the control gate CG is dropped toward the element isolation STI (semiconductor substrate 10) on both sides of the floating gate FG of each of the memory cell MC and the first dummy cell DC1, similarly to the inter-gate insulating film IPD. Yes. After processing the control gate CG, an interlayer insulating film, a bit line BL, and the like are formed, thereby completing the memory shown in FIG.

  According to the present embodiment, the boundary ZL is set between the first dummy cell DC1 and the second dummy cell DC2 of the array end pattern AEP. Usually, the interval between the first dummy cell DC1 and the second dummy cell DC2 is larger than the interval S0 between the memory cell array MCA and the first dummy cell DC1. Therefore, in this embodiment, alignment of the lithography process when forming the high breakdown voltage gate insulating film 30 and the low breakdown voltage tunnel gate insulating film 20 is easy. The same can be said for the boundaries AP and EB.

  According to the present embodiment, the boundary ZL is set between the first dummy cell DC1 and the second dummy cell DC2 of the array end pattern AEP. As a result, the second dummy cell DC <b> 2 includes a gate insulating film 30 that is thicker than the tunnel gate insulating film 20. Therefore, the second dummy cell DC2 is a high breakdown voltage transistor having a higher breakdown voltage than the memory cell MC.

  On the other hand, the first dummy cell DC1 includes a tunnel gate insulating film 20. However, the boundary AP and the boundary EB are set between the first dummy cell DC1 and the second dummy cell DC2. Therefore, the core material 50 in the array end pattern AEP can be removed, the element isolation STI can be formed between the first dummy cell DC1 and the second dummy cell DC2, and the floating gate of the first dummy cell DC1. The element isolation insulating film 80 on both sides of the FG can be etched back. As a result, the control gate CG faces both side surfaces of the floating gate FG of the first dummy cell DC1 via the inter-gate insulating film IPD. As a result, the coupling capacitance ratio Cr increases, and it is possible to prevent the intergate insulating film IPD or the tunnel gate insulating film 20 of the first dummy cell DC1 from being destroyed during data writing or data erasing. That is, the breakdown voltage of the first and second dummy cells DC1 and DC2 in the array end pattern AEP can be increased.

(Second Embodiment)
FIG. 12 is a cross-sectional view showing the configuration of the memory according to the second embodiment. The second embodiment differs from the first embodiment in that the boundary EB is set to overlap the second dummy cell DC2. Thereby, the inter-gate insulating film IPD and the control gate CG are provided on one side surface F1 of the floating gate FG of the second dummy cell DC2, and the element isolation insulating film 80 is provided on the other side surface F2. As a result, the breakdown voltage of the second dummy cell DC2 is further increased as compared with the first embodiment. Other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment. Therefore, the second embodiment has the same effect as the first embodiment.

  The manufacturing method of the second embodiment includes the steps shown in FIGS. 13 and 14 after obtaining the steps shown in FIGS.

  In the second embodiment, since the boundary EB overlaps the second dummy cell DC2, when the element isolation insulating film 80 is etched back, as shown in FIG. 13, one side of the floating gate FG of the second dummy cell DC2 The side surface F1 is exposed.

  Accordingly, as shown in FIG. 14, the inter-gate insulating film IPD is also formed on the upper surface and the one side surface F1 of the floating gate FG of the second dummy cell DC2. The other side surface F2 of the floating gate FG of the second dummy cell DC2 remains covered with the element isolation STI. The control gate CG is formed on the upper surface and one side surface F1 of the floating gate FG of the second dummy cell DC2 via the inter-gate insulating film IPD. Thereafter, an interlayer insulating film, a bit line, and the like are formed as in the first embodiment, thereby completing the memory according to the second embodiment.

(Third embodiment)
FIG. 15 is a cross-sectional view showing a configuration of a memory according to the third embodiment. The third embodiment is different from the first embodiment in that the boundary EB is set so as to overlap in the element isolation STI between the second dummy cell DC2 and the peripheral circuit PRI. Thereby, the inter-gate insulating film IPD and the control gate CG are provided on both side surfaces F1, F2 of the floating gate FG of the second dummy cell DC2. As a result, the breakdown voltage of the second dummy cell DC2 is further increased compared to the second embodiment. Other configurations of the third embodiment may be the same as the corresponding configurations of the first embodiment. Therefore, the third embodiment has the same effect as the first embodiment.

  The manufacturing method of the third embodiment includes the steps shown in FIGS. 16 and 17 after obtaining the steps shown in FIGS.

  In the third embodiment, since the boundary EB overlaps the element isolation STI between the second dummy cell DC2 and the peripheral circuit PRI, when the element isolation insulating film 80 is etched back, as shown in FIG. Both side surfaces F1 and F2 of the floating gate FG of the second dummy cell DC2 are exposed.

  Accordingly, as shown in FIG. 17, the inter-gate insulating film IPD is also formed on the upper surface and both side surfaces F1, F2 of the floating gate FG of the second dummy cell DC2. The control gate CG is formed on the upper surface and both side surfaces F1, F2 of the floating gate FG of the second dummy cell DC2 via the inter-gate insulating film IPD. Thereafter, an interlayer insulating film, a bit line, and the like are formed as in the first embodiment, thereby completing the memory according to the third embodiment.

  According to the first to third embodiments, the boundary EB is provided at an arbitrary position between the first dummy cell DC1 and the peripheral circuit PRI, in other words, closest to the memory cell array MCA side with respect to the boundary ZL. It is only necessary to set between the side wall 60 and the peripheral circuit PRI.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

MCA ... memory cell array, PRI ... peripheral circuit, MC ... memory cell, DC1 ... first dummy cell, DC2 ... second dummy cell, AEP ... array end pattern, STI ... -Element isolation, AA ... active area, FG ... floating gate, CG ... control gate, IPD ... IPD film, 10 ... semiconductor substrate, 20 ... tunnel gate insulating film, 30 ..Gate insulation film

Claims (8)

A semiconductor substrate;
A first insulating film provided on the semiconductor substrate; a charge storage layer provided on the first insulating film capable of storing charges; an intergate insulating film provided on the charge storage layer; A memory cell array having a plurality of memory cells including a control gate provided on the inter-gate insulating film and controlling a voltage of the charge storage layer;
Peripheral circuits provided around the memory cell array;
A first dummy cell provided at an end of the memory cell array, including the first insulating film, the charge storage layer, the inter-gate insulating film, and the control gate;
A second dummy cell provided on the semiconductor substrate, including a second insulating film thicker than the first insulating film, and provided between the first dummy cell and the peripheral circuit;
In the first dummy cell, the inter-gate insulating film and the control gate are provided on an upper surface and two side surfaces of the charge storage layer,
The intergate insulating film and the control gate of the first dummy cell are dropped toward the semiconductor substrate on both sides of the charge storage layer,
In the second dummy cell, the charge storage layer is provided on the second insulating film, the intergate insulating film is provided on the charge storage layer, and the control gate is provided on the intergate insulating film. And
An element isolation insulating film is provided on both side surfaces of the charge storage layer of the second dummy cell. A semiconductor substrate;
A first insulating film provided on the semiconductor substrate; a charge storage layer provided on the first insulating film capable of storing charges; an intergate insulating film provided on the charge storage layer; A memory cell array having a plurality of memory cells including a control gate provided on the inter-gate insulating film and controlling a voltage of the charge storage layer;
Peripheral circuits provided around the memory cell array;
A first dummy cell provided at an end of the memory cell array, including the first insulating film, the charge storage layer, the inter-gate insulating film, and the control gate;
A second dummy cell provided on the semiconductor substrate, including a second insulating film thicker than the first insulating film, and provided between the first dummy cell and the peripheral circuit;
In the first dummy cell, the inter-gate insulating film and the control gate are provided on an upper surface and two side surfaces of the charge storage layer.   3. The semiconductor memory device according to claim 2, wherein the inter-gate insulating film and the control gate of the first dummy cell are dropped toward the semiconductor substrate on both sides of the charge storage layer. In the second dummy cell, the charge storage layer is provided on the second insulating film, the intergate insulating film is provided on the charge storage layer, and the control gate is provided on the intergate insulating film. And
3. The semiconductor memory device according to claim 2, wherein element isolation insulating films are provided on both side surfaces of the charge storage layer of the second dummy cell. In the second dummy cell, the charge storage layer is provided on the second insulating film, the intergate insulating film is provided on the charge storage layer, and the control gate is provided on the intergate insulating film. And
The inter-gate insulating film and the control gate are provided on one side surface of the charge storage layer of the second dummy cell,
3. The semiconductor memory device according to claim 1, wherein an element isolation insulating film is provided on the other side surface of the charge storage layer of the second dummy cell. In the second dummy cell, the charge storage layer is provided on the second insulating film, the intergate insulating film is provided on the charge storage layer, and the control gate is provided on the intergate insulating film. And
3. The semiconductor memory device according to claim 1, wherein the inter-gate insulating film and the control gate are provided on both side surfaces of the charge storage layer of the second dummy cell.   6. The semiconductor memory device according to claim 1, wherein the first and second dummy cells have substantially the same size as the memory cell. A memory cell array including a plurality of memory cells, a peripheral circuit provided around the memory cell array, a first dummy cell provided at an end of the memory cell array, and between the first dummy cell and the peripheral circuit And a second dummy cell provided in the semiconductor memory device, comprising:
A first insulating film is formed on the semiconductor substrate on the memory cell array side with a first boundary between the first dummy cell and the second dummy cell as a boundary, and the periphery is formed with the first boundary as a boundary. Forming a second insulating film thicker than the first insulating film on the semiconductor substrate on the circuit side;
Forming a charge storage layer material on the first and second insulating films;
Forming a mask material and a core material on the material of the charge storage layer;
Forming a sidewall mask on the side surface of the core material;
Removing the core material on the memory cell array side while leaving the core material on the peripheral circuit side, with the second boundary between the first dummy cell and the second dummy cell as a boundary,
Using the core material and the sidewall mask as a mask, processing the charge storage layer, forming a trench for element isolation,
Filling the element isolation trench with an element isolation insulating film,
The element isolation insulating film on the memory cell array side is etched with a third boundary between the first dummy cell and the peripheral circuit as a boundary, and each of the memory cell and at least the first dummy cell is etched. Exposing at least part of the side surface of the charge storage layer;
Forming an inter-gate insulating film on the upper and side surfaces of the charge storage layer of each of the memory cell and the first dummy cell;
A method of manufacturing a semiconductor memory device, comprising: forming a control gate on an upper surface and a side surface of the charge storage layer of each of the memory cell and the first dummy cell via the inter-gate insulating film.

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