JP2013062451A - Flexible wiring board and manufacturing method of the same - Google Patents

Abstract

An electrical resistance in an interlayer connection portion is reduced, and it can be applied to a large current application.
An insulating film, a first metal layer and a second metal layer formed on both surfaces of the insulating film, and a via hole penetrating the insulating film and the first metal layer, respectively. An interlayer connection portion 50v formed in the via hole 30 and electrically connecting the first metal layer 21 and the second metal layer 42, and the thickness of the first metal layer 21 is 0.08 mm or more In addition, the diameter of the via hole 30 is 0.1 mm or more, and the interlayer connection portion 50v includes a plated portion 50 filled in the via hole 30 so as to fill the via hole 30.
[Selection] Figure 1

Description

  The present invention relates to a flexible wiring board having an interlayer connection portion for electrically connecting a first metal layer and a second metal layer formed on both surfaces of an insulating film, and a method for manufacturing the flexible wiring board.

  Flexible wiring such as TAB (Tape Automated Bonding) method and TCP (Tape Carrier Package) method in which a wiring pattern is formed on a flexible insulating film with copper foil or the like on a wiring board on which a semiconductor chip or the like is mounted There is a substrate (hereinafter, these are referred to as TAB tapes as representative). Currently, TAB tape is used in some applications such as IC packages and is mass-produced.

  The above-mentioned TAB tape is generally a single-layer TAB tape in which an insulating film such as a polyimide tape is used as a base material and a wiring pattern is formed on one side. However, the frequency of a semiconductor chip mounted on a personal computer is increased. Along with this, the necessity of a circuit having a high transmission rate is increasing. In order to meet such needs, a two-layer TAB tape in which a wiring pattern is formed on both surfaces of an insulating film has been put into practical use. For the electrical connection between the layers, for example, an interlayer connection portion in which plating is performed along the wall surface of the via hole with respect to the via hole penetrating the insulating film is used. For example, Patent Document 1 discloses a double-sided wiring TAB tape having an electric copper (Cu) plating layer formed on an inner wall surface of a blind via hole and a blind surface of a blind layer (wiring layer that closes the blind via hole).

Japanese Patent Laid-Open No. 11-102937

  In recent years, the development of TAB tape suitable for high current applications has progressed, and by increasing the thickness of the wiring pattern, etc. compared to the conventional TAB tape, and increasing the cross-sectional area of the conductor constituting the wiring pattern, a large current can be obtained. Supplying or transmitting to a desired location.

  However, when the interlayer connection as described above is applied to a TAB tape for a large current application, a large current is applied to a thin plating layer having a thickness of about 0.01 mm to 0.02 mm, for example, provided along the wall surface of the via hole. It will flow and the electrical resistance will increase.

  An object of the present invention is to provide a flexible wiring board and a manufacturing method of the flexible wiring board which can reduce electrical resistance in an interlayer connection portion and can be applied to a large current application.

  According to the first aspect of the present invention, the insulating film, the first metal layer and the second metal layer respectively formed on both surfaces of the insulating film, and the insulating film and the first metal layer are penetrated. And a via hole formed in the via hole and electrically connecting the first metal layer and the second metal layer, and the thickness of the first metal layer is 0.08 mm. As described above, a flexible wiring board is provided in which the via hole has a diameter of 0.1 mm or more, and the interlayer connection portion includes a plated portion filled in the via hole so as to fill the via hole.

  According to the second aspect of the present invention, the thickness Tf of the insulating film, the thickness Tm of the first metal layer, and the diameter D of the via hole satisfy (Tf + Tm) / D <0.75. The flexible wiring board as described in the 1st aspect comprised so that a relationship may be satisfy | filled is provided.

  According to the third aspect of the present invention, the plated portion is filled such that the depth of the depression formed on the upper surface of the plated portion is a substantially flat upper surface that is 10% or less of the depth of the via hole. A flexible wiring board according to the first or second aspect is provided.

  According to the 4th aspect of this invention, the said plating part provides the flexible wiring board in any one of the 1st-3rd aspect which consists of two or more plating layers.

  According to the fifth aspect of the present invention, a first metal layer forming step of forming a first metal layer having a thickness of 0.08 mm or more on the first main surface of the insulating film; A second metal layer forming step of forming a second metal layer on the two main surfaces; and a penetrating step of penetrating the insulating film and the first metal layer, the insulating film and the first metal A via hole forming step of forming a via hole having a diameter of 0.1 mm or more through which the second metal layer is exposed, and electrically connecting the first metal layer and the second metal layer in the via hole. An interlayer connection forming step for forming an interlayer connection to be connected to the substrate. In the interlayer connection forming step, an electric current is applied to the second metal layer to perform electroplating, and the first via is formed in the via hole. A first plating layer forming step of forming a plating layer; A second plating layer forming step of applying current to the metal layer and the second metal layer to perform electroplating, and forming a second plating layer on the first plating layer and on the first metal layer And a plating portion filled in the via hole so as to fill the via hole with the first plating layer and a portion of the second plating layer formed on the first plating layer. There is provided a method of manufacturing a flexible wiring board that is configured to form the interlayer connection portion formed of the plating portion.

  According to the sixth aspect of the present invention, the thickness Tf of the insulating film, the thickness Tm of the first metal layer, and the diameter D of the via hole are set such that (Tf + Tm) / D <0.75. The manufacturing method of the flexible wiring board as described in the 5th aspect set to satisfy | fill a relationship is provided.

  According to the seventh aspect of the present invention, before the second plating layer forming step, the conductive treatment is performed on the first plating layer, the wall surface of the via hole, and the first metal layer. The manufacturing method of the flexible wiring board as described in the 5th or 6th aspect which has the electrically conductive process process which performs is provided.

  According to the present invention, the electrical resistance in the interlayer connection portion is reduced, and it can be applied to large current applications.

It is a figure which shows a part of flexible wiring board concerning one Embodiment of this invention, Comprising: It is sectional drawing which mainly shows an interlayer connection part. It is process drawing which shows each process of the manufacturing method of the flexible wiring board which concerns on one Embodiment of this invention with sectional drawing of the same direction side as sectional drawing of FIG.

<One Embodiment of the Present Invention>
Below, the manufacturing method of the flexible wiring board which concerns on one Embodiment of this invention, and a flexible wiring board is demonstrated.

(1) Structure of Flexible Wiring Board First, the structure of the flexible wiring board according to one embodiment of the present invention will be described with reference to FIG. FIG. 1 is a view showing a part of the flexible wiring board according to the present embodiment, and is a cross-sectional view mainly showing an interlayer connection portion 50v.

  As shown in FIG. 1, the TAB tape as a flexible wiring board has, for example, an insulating film 10 and a first metal layer 21 and a second metal layer 42 formed on both surfaces of the insulating film 10, respectively. ing. Further, the TAB tape is formed in the via hole 30 penetrating the insulating film 10 and the first metal layer 21, and the interlayer connection for electrically connecting the first metal layer 21 and the second metal layer 42. Part 50v.

  The insulating film 10 is made of a flexible resin, for example, polyimide (PI) having a thickness of 0.1 mm or less. A first metal layer 21 is formed on the first major surface 10 a of the insulating film 10. The first metal layer 21 is made of, for example, a copper foil having a thickness of 0.08 mm to 0.5 mm. Further, the first metal layer 21 has in part a first wiring pattern 21p in which the copper foil or the like is patterned. Moreover, on the 1st wiring pattern 21p, it has the plating pattern 52p by which the copper plating etc. which comprise the 2nd plating layer 52 mentioned later were patterned in the position which overlaps with the 1st wiring pattern 21p. A second metal layer 42 is formed on the second main surface 10 b of the insulating film 10. The second metal layer 42 is made of, for example, a copper foil having a thickness of about 0.012 mm. Further, the second metal layer 42 has in part a second wiring pattern 42p in which the copper foil or the like is patterned.

  Thus, the 1st metal layer 21 is formed comparatively thick compared with the 2nd metal layer 42 so that it can apply to a large current use. In addition, by causing the first wiring pattern 21p and the plating pattern 52p to function as a wiring through which a large current flows, the electrical resistance of the wiring portion can be further reduced when a large current flows through the TAB tape. Further, in consideration of workability when forming a first wiring pattern 21p by processing a part of the copper foil or the like constituting the first metal layer 21, the first metal layer 21 is formed in a predetermined manner as described above. It is preferable that the thickness be equal to or less than the thickness.

  The via hole 30 that penetrates the insulating film 10 and the first metal layer 21 has a diameter of, for example, 0.1 mm or more and 0.8 mm or less. The interlayer connection portion 50v formed in the via hole 30 includes a plated portion 50 that fills the via hole 30 so as to fill the via hole 30.

  The plating part 50 consists of two or more plating layers. In other words, a first plating layer 51 made of, for example, copper plating is formed in the via hole 30. The first plating layer 51 is formed at a height that does not reach the first metal layer 21 in the via hole 30. A second plating layer 52 made of, for example, copper plating is formed on the first plating layer 51 and the first metal layer 21. The plated portion 50 is configured by the first plated layer 51 and the portion of the second plated layer 52 that fills the via hole 30, that is, the portion formed on the first plated layer 51. As described above, the second plating layer 52 has the plating pattern 52p at a position overlapping the first wiring pattern 21p.

  Thus, by setting the diameter of the via hole 30 to a predetermined value or more and filling the plated portion 50 so as to fill the via hole 30, the electrical resistance in the interlayer connection portion 50v can be reduced, and a large current Applicable to usage. In addition, since the mass of the conductor such as copper plating constituting the interlayer connection 50v is increased, the electrical connection reliability is improved. In consideration of productivity when filling the first plating layer 51 and the second plating layer 52, it is preferable that the diameter of the via hole 30 is set to a predetermined value or less as described above.

  Moreover, the plating part 50 has a substantially flat upper surface. That is, in the plated portion 50, the depth of the recess 52 d generated on the upper surface of the plated portion 50, that is, the upper surface of the second plated layer 52 located substantially in the center of the via hole 30 is, for example, 10% or less of the depth of the via hole 30. It is filled so that it may become a flat upper surface.

  In such a plated portion 50 having a substantially flat upper surface, for example, the thickness Tf of the insulating film 10, the thickness Tm of the first metal layer 21, and the diameter D of the via hole 30 are (Tf + Tm) / D. It is obtained by being configured to satisfy the relationship <0.75. The specific method will be described later. As specific examples of the above numerical values, the thickness Tf of the insulating film 10 is 0.05 mm, the thickness Tm of the first metal layer 21 is 0.1 mm, and the diameter D of the via hole is 0.2 mm. Can do.

  As described above, since the upper surface of the plating part 50 is configured to be substantially flat, for example, various structures formed on the interlayer connection part 50v and the bondability of the interlayer connection part 50v can be improved. Examples of the structure on the interlayer connection 50v include a ball pad on which a solder ball is mounted.

  In a TAB tape in which a thin plating layer is formed and an interlayer connection portion is not filled as in the conventional example described above, it is difficult to form a ball pad or the like on the interlayer connection portion. Further, even if a ball pad is formed, it is difficult to obtain good bonding with the solder ball or the pad of the semiconductor chip to be bonded to the solder ball because the ball pad is bent into the via hole.

  However, in this embodiment, since the via hole 30 is filled and the plated portion 50 has a substantially flat upper surface, even the position directly above the interlayer connection portion 50v is included in the ball pad formation position. Thus, the degree of freedom in wiring design can be improved.

(2) Manufacturing method of flexible wiring board Next, the manufacturing method of the TAB tape as a flexible wiring board which concerns on one Embodiment of this invention is demonstrated using FIG. FIG. 2 is a process diagram showing each process of the TAB tape manufacturing method according to the present embodiment in a cross-sectional view on the same direction side as the AA cross section of FIG.

(Via hole formation process)
First, a via hole forming step including a first metal layer forming step, a second metal layer forming step, and a penetrating step is performed to penetrate through the insulating film 10 and the first metal layer 21 as follows. The via hole 30 having a diameter of, for example, 0.1 mm or more and 0.8 mm or less is formed in which the two metal layers 42 are exposed.

(First metal layer forming step)
As shown to Fig.2 (a), the 1st metal layer 21 whose thickness is 0.08 mm or more and 0.5 mm or less is formed on the 1st main surface 10a of the insulating film 10, for example. That is, for example, a copper foil or the like that becomes the first metal layer 21 having a thickness of 0.08 mm or more and 0.5 mm or less is bonded onto the first main surface 10a of the insulating film 10 with an adhesive not shown.

(Penetration process)
Next, as shown in FIG. 2B, the insulating film 10 and the first metal layer 21 are penetrated by, for example, pressing.

(Second metal layer forming step)
Further, as shown in FIG. 2C, the second metal layer 42 is formed on the second main surface 10 b of the insulating film 10. That is, for example, a copper foil or the like that becomes the second metal layer 42 is attached to the second main surface 10b of the insulating film 10 with an adhesive (not shown).

  Thereby, the via hole 30 having a diameter of, for example, 0.1 mm or more and 0.8 mm or less is formed through which the second metal layer 42 is exposed through the insulating film 10 and the first metal layer 21.

(Interlayer connection part formation process)
Subsequently, an interlayer connection portion forming step including a first plating layer forming step, a conductive treatment step, and a second plating layer forming step is performed as follows, and the first metal layer 21 is formed in the via hole 30. An interlayer connection 50v that electrically connects the second metal layer 42 is formed.

(First plating layer forming step)
As shown in FIG. 2D, an electric current is applied to the second metal layer 42 to perform electroplating, and a first plating layer 51 is formed in the via hole 30. Such electroplating can be, for example, electrolytic copper plating using a copper plating solution. The first plating layer 51 grows from the upper surface of the second metal layer 42 exposed in the via hole 30 using the second metal layer 42 to which the current is applied as an electrode. Thus, by continuing the electrolytic copper plating or the like for a predetermined time, the first plating layer 51 made of copper plating or the like is formed without reaching the first metal layer 21 in the via hole 30.

  At this time, when the insulating film 10 is thickened, the diameter of the via hole 30 is increased so that the aspect ratio of the via hole 30 (ratio of the depth of the via hole 30 / the diameter of the via hole) does not become too high. Specifically, the thickness Tf of the insulating film 10, the thickness Tm of the first metal layer 21, and the diameter D of the via hole 30 satisfy, for example, a relationship of (Tf + Tm) / D <0.75. It is preferable to set. By setting each numerical value in this way, it is possible to prevent the copper plating solution or the like from being included in the via hole 30 and the growth rate of the first plating layer 51 from being lowered inside the via hole 30. be able to.

  When the diameter of the via hole 30 is increased, the applied current is increased and the electroplating time is lengthened. The same applies to the second plating layer forming step described later. Thereby, the plating part 50 can be filled so that the inside of the via hole 30 may be filled.

(Conductive treatment process)
Next, as shown in FIG. 2 (e), a conductive treatment is performed on the first plating layer 51 formed in the via hole 30, the wall surface of the via hole 30, and the first metal layer 21. . Specifically, for example, by electroless copper plating, the exposed surface in the via hole 30 and in the vicinity of the via hole 30, that is, on the first plating layer 51, the wall surface of the via hole 30, and the first metal layer 21. A conductive film M is formed.

(Second plating layer forming step)
Next, as shown in FIG. 2F, an electric current is applied to the first metal layer 21 and the second metal layer 42 to perform electroplating, and the first metal layer 21 and the first metal layer 21 are A second plating layer 52 is formed on the top. Such electroplating can be, for example, electrolytic copper plating using a copper plating solution. By continuing the electrolytic copper plating for a predetermined time, the second plating layer 52 made of copper plating or the like can be formed. The electrolytic copper plating or the like is continued until at least the inside of the via hole 30 is filled with the height of the upper surface of the first metal layer 21 by the second plating layer 52.

As described above, in the second plating layer forming step, not only the second metal layer 42 but also the first metal layer 21 is applied with current to form the second plating layer 52, so that there is no electrical connection. The first metal layer 21 and the second metal layer 42 are connected via the first plating layer 51 and the second plating layer 52. Prior to the second plating layer forming step, a conductive coating step is performed to form the conductive coating M. Thereby, the current applied from the first metal layer 21 and the second metal layer 42 is transmitted to the conductive coating M, and on the first plating layer 51, the wall surface of the via hole 30, the first metal layer 21, From these three directions, the second plating layer 52 can be grown so as to fill the via hole 30 while suppressing the deviation of the growth direction and growth rate.

  However, at this time, a recess 52 d may be formed at the approximate center in the via hole 30. The electrolytic copper plating or the like is preferably continued until the depth of the recess 52d of the second plating layer 52 becomes, for example, 10% or less of the depth of the via hole.

  As described above, the plated portion 50 filled in the via hole 30 is configured to fill the via hole 30 with the first plated layer 51 and the portion of the second plated layer 52 formed on the first plated layer 51. Then, the interlayer connection portion 50v made of the plating portion 50 can be formed.

(Wiring pattern formation process)
Thereafter, as shown in FIG. 2G, wiring patterns 21p and 42p are formed. That is, a resist pattern (not shown) is formed on the second plating layer 52, and the second plating layer 52 and the first metal layer 21 are etched using the resist pattern as a mask. Thereby, the 1st wiring pattern 21p is formed with the plating pattern 52p. On the other hand, a resist pattern (not shown) is formed on the second metal layer 42, and the second metal layer 42 is etched using the resist pattern as a mask. Thereby, the second wiring pattern 42p is formed.

  As described above, the flexible wiring board according to this embodiment is manufactured.

<Other Embodiments of the Present Invention>
As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, It can change variously in the range which does not deviate from the summary.

  For example, in the above-described embodiment, the second plating layer 52 is made of copper plating or the like, but may be nickel (Ni) plating or the like.

  In the above-described embodiment, the plated portion 50 is configured by the first plated layer 51 and the portion of the second plated layer 52 formed on the first plated layer 51. You may be comprised from the several plating layer of 3 or more layers.

  In the above-described embodiment, the via hole forming process is performed in the order of the first metal layer forming process, the penetration process, and the second metal layer forming process. However, the process order is not limited thereto. For example, the first metal layer formation step and the second metal layer formation step are performed (in no particular order) as in the above-described embodiment to form an insulating film having the first metal layer and the second metal layer, and then laser processing. The via hole may be formed by performing a penetration process of penetrating the insulating film and the first metal layer while leaving the second metal layer. It is also possible to use an insulating film having copper foil or the like already attached to one or both sides as a starting material. In this case, for example, an adhesive tape for TAB manufactured by Yodogawa Paper can be used.

  Moreover, in the above-mentioned embodiment, although the 1st metal layer 21 and the 2nd metal layer 42 decided to stick to the insulating film 10 via an adhesive material, it is copper foil by thermocompression bonding without using an adhesive material. Alternatively, a conductive material such as copper may be directly formed on the insulating film by sputtering or plating.

In the above-described embodiment, the conductive treatment process is performed by electroless copper plating. However, a conductive film may be formed by sputtering, vapor deposition, or the like, and conductive by a palladium (Pd) catalyst or the like. Processing may be performed. Alternatively, since the current is also applied to the first metal layer 21 in the second plating layer forming step, the conductive treatment step can be omitted.

  In the above-described embodiment, the insulating film 10 is made of polyimide (PI) or the like, but is not limited thereto. For example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS). ), Polyamideimide (PAI), liquid crystal polymer (LCP), aramid, glass epoxy resin, or other organic resin.

DESCRIPTION OF SYMBOLS 10 Insulating film 10a 1st main surface 10b 2nd main surface 21 1st metal layer 30 Via hole 42 2nd metal layer 50 Plating part 50v Interlayer connection part 51 1st plating layer 52 2nd plating layer

Claims (7)

An insulating film;
A first metal layer and a second metal layer respectively formed on both surfaces of the insulating film;
A via hole penetrating the insulating film and the first metal layer;
An interlayer connection part formed in the via hole and electrically connecting the first metal layer and the second metal layer;
The thickness of the first metal layer is 0.08 mm or more,
The via hole has a diameter of 0.1 mm or more,
The interlayer connection portion is
A flexible wiring board comprising a plated portion filled in the via hole so as to fill the via hole. The thickness Tf of the insulating film, the thickness Tm of the first metal layer, and the diameter D of the via hole are configured to satisfy a relationship of (Tf + Tm) / D <0.75. The flexible wiring board according to claim 1, wherein The plating part is
3. The flexible wiring board according to claim 1, wherein the recess is formed so as to have a substantially flat upper surface having a depth of 10% or less of the depth of the via hole. The flexible wiring board according to claim 1, wherein the plated portion is composed of two or more plated layers. Forming a first metal layer having a thickness of 0.08 mm or more on the first main surface of the insulating film; and forming a second metal layer on the second main surface of the insulating film. A second metal layer forming step and a penetrating step for penetrating the insulating film and the first metal layer, and the second metal layer penetrates the insulating film and the first metal layer. A via hole forming step of forming an exposed via hole having a diameter of 0.1 mm or more;
An interlayer connection forming step for forming an interlayer connection for electrically connecting the first metal layer and the second metal layer in the via hole;
In the interlayer connection part forming step,
Applying a current to the second metal layer to perform electroplating, and forming a first plating layer in the via hole;
Second plating for applying an electric current to the first metal layer and the second metal layer to perform electroplating to form a second plating layer on the first plating layer and on the first metal layer A layer forming step is performed, and the via hole is filled with the first plating layer and a portion of the second plating layer formed on the first plating layer so as to fill the via hole. A method of manufacturing a flexible substrate, comprising a plated portion and forming the interlayer connecting portion formed of the plated portion. The thickness Tf of the insulating film, the thickness Tm of the first metal layer, and the diameter D of the via hole are set so as to satisfy a relationship of (Tf + Tm) / D <0.75. The manufacturing method of the flexible wiring board of Claim 5. Before the second plating layer forming step,
7. The flexible according to claim 5, further comprising a conductive treatment step of performing a conductive treatment on the first plating layer, the wall surface of the via hole, and the first metal layer. 8. A method for manufacturing a wiring board.

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