JP2013058960A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve the linear log characteristics having high sensitivity linear characteristics, and log characteristics with small variation.SOLUTION: Upon acquisition of an image signal D1 having linear characteristics by driving a pixel in reverse bias mode within one frame period, an image sensor control unit 122 acquires an image signal D2 having log characteristics by driving a pixel in zero bias mode. An image signal processing unit 121 selects the image signal D1 as an output image signal D3 when the level of the image signal D1 goes below a threshold TH corresponding to the level of an image signal at an inflection point, otherwise selects the image signal D2 as the output image signal D3.

Description

  The present invention relates to a solid-state imaging device having a linear log characteristic in which a linear characteristic and a log characteristic are switched at an inflection point.

  In recent years, in order to expand the dynamic range, a solid-state imaging device having a linear characteristic on a low luminance side and a log characteristic on a high luminance side with an inflection point as a boundary is known. Such photoelectric conversion characteristics are called linear log characteristics, and for example, Patent Document 1 is known. Hereinafter, in the linear log characteristics, an area having linear characteristics is described as a linear area, and an area having log characteristics is described as a log area.

  In Patent Document 1, for the purpose of reproducing a wide DR image without reducing the frame rate, when the pixel signal from the pixel unit is a signal in a linear region, it is amplified with an analog gain corresponding to the linear characteristic, A solid-state imaging device having a photoelectric conversion characteristic of a linear log characteristic that is amplified by an analog gain corresponding to the log characteristic when the pixel signal from the pixel unit is a signal in the log area is disclosed.

  Patent Document 2 discloses an image sensor that can obtain a logarithmic characteristic output with no variation by driving a light receiving element constituting a pixel circuit in a zero bias mode (solar cell mode).

  Japanese Patent Application Laid-Open No. 2004-228667 aims to suppress generation of false signals and saturation unevenness, and has a large size and high sensitivity first light receiving element (SH) and a small size and low sensitivity second light receiving element (SL). ) Are arranged in a honeycomb shape, the saturation level of the first light receiving element (SH) is adjusted, and a CCD solid-state imaging device that combines with the second light receiving element (SL) is disclosed.

JP 2008-263546 A European Patent No. 1354360 JP 2000-125209 A

  However, in Patent Document 1, since each pixel is driven in a reverse bias mode, which is a driving method generally used in solid-state imaging devices, there is a problem in that log characteristics vary. .

  In Patent Document 2, since only the pixel circuits in which the light receiving elements are driven in the zero bias mode are arranged, there is a problem that linear log characteristics cannot be realized. Therefore, although a dynamic range can be secured, there is a problem that an image signal with high sensitivity to the amount of incident light cannot be output.

  Patent Document 3 relates to a CCD and does not have a photoelectric conversion characteristic of a linear log characteristic.

  An object of the present invention is to provide a solid-state imaging device having a linear log characteristic having a highly sensitive linear characteristic and a log characteristic with little variation.

  (1) A solid-state image pickup device according to the present invention is a solid-state image pickup device having a photoelectric conversion characteristic of a linear log characteristic in which a linear characteristic and a log characteristic are switched at an inflection point, and is an image pickup composed of a plurality of pixels including a light receiving element. A reverse bias mode for resetting and exposing the light receiving element in a reverse bias state and outputting a first image signal having linear characteristics from the pixel; and resetting and exposing the light receiving element in a zero bias state An image sensor control unit for driving the pixel so that a zero bias mode for outputting a second image signal having log characteristics from the pixel is switched in one frame period; and the first image signal or the second image signal And an image signal processing unit that switches and outputs the first image signal and the second image signal based on the level of the image signal.

  According to this configuration, the pixels constituting the image sensor are driven in two modes, the reverse bias mode and the zero bias mode, in one frame period. Therefore, in one frame period, a first image signal having a highly sensitive linear characteristic and a second image signal having a log characteristic with little variation are obtained.

  Then, it is determined from the level of the first image signal or the second image signal whether the subject has high luminance or low luminance, and the first image signal or the second image signal is output according to the determination result.

  Accordingly, it is possible to provide a solid-state imaging device having a photoelectric conversion characteristic in which a highly sensitive linear characteristic and a log characteristic with little variation are switched at an inflection point.

  (2) It is preferable that the image sensor control unit drives the pixel in the zero bias mode after driving the pixel in the reverse bias mode in the one frame period.

  Since an image signal having a linear characteristic has time integration, it is necessary to secure a certain exposure time. On the other hand, since the log characteristic image signal does not have time integration, it is not necessary to secure the exposure time unlike the linear characteristic image signal. In this configuration, in one frame period, the pixels are first driven in the reverse bias mode to obtain a first image signal having linear characteristics, and then driven in the zero bias mode to obtain a second image signal having log characteristics. It has been. Therefore, it is possible to secure a sufficient time for driving the pixels in the reverse bias mode in one frame period, and it is possible to obtain a highly accurate first image signal.

  (3) When the level of the first image signal is equal to or lower than a threshold value indicating the level of the image signal at the inflection point, the image signal processing unit outputs the first image signal, and the level of the first image signal When is larger than the threshold, it is preferable to output the second image signal.

  According to this configuration, if the first image signal is equal to or lower than the threshold value, it is determined that a low-luminance subject has been captured, and the first image signal is output. If the first image signal is greater than the threshold value, the high-luminance subject is determined. Is captured, and the second image signal is output. Therefore, a photoelectric conversion characteristic having linear characteristics on the low luminance side and log characteristics on the high luminance side can be obtained.

  (4) The pixel preferably includes a primary color filter.

  According to this configuration, an image signal having primary color (for example, R, G, B) color components is obtained.

  (5) The pixel preferably includes a complementary color filter.

  According to this configuration, since the complementary color filter is provided, a highly sensitive image signal can be obtained.

  (6) The light receiving element is preferably a surface-type photodiode.

  According to this configuration, since the light receiving element of the pixel is configured by a surface-type photodiode, it is easy to drive the pixel in the zero vice mode.

  (7) The light receiving element is preferably an embedded photodiode.

  According to this configuration, since the light receiving element of the pixel is configured by an embedded photodiode, high quality first and second image signals can be obtained.

  According to the present invention, the pixels constituting the imaging device are driven in two modes, the reverse bias mode and the zero bias mode, in one frame period. Therefore, in one frame period, a first image signal having a highly sensitive linear characteristic and a second image signal having a log characteristic with little variation are obtained.

  Then, it is determined from the level of the first image signal or the second image signal whether the subject has high luminance or low luminance, and the first image signal or the second image signal is output according to the determination result.

  Accordingly, it is possible to provide a solid-state imaging device having a photoelectric conversion characteristic in which a highly sensitive linear characteristic and a log characteristic with little variation are switched at an inflection point.

1 is a block diagram showing an overall configuration of a solid-state imaging device according to Embodiment 1 of the present invention. It is a block diagram which shows the detailed structure of the image pick-up element shown in FIG. It is a circuit diagram of the pixel which comprises the pixel array part by Embodiment 1 of this invention. 4 is a timing chart of the pixel circuit shown in FIG. 3. It is the graph which showed an example of the photoelectric conversion characteristic of the pixel driven by reverse bias mode, the vertical axis | shaft shows the signal component signal and the horizontal axis shows the incident light intensity. It is the graph which showed the photoelectric conversion characteristic of the pixel driven by the zero bias mode, the vertical axis | shaft shows the signal component signal and the horizontal axis shows the incident light intensity. FIG. 2 is a circuit diagram illustrating a detailed configuration of an image signal processing unit illustrated in FIG. 1. It is the graph which showed the photoelectric conversion characteristic of the output image signal, The vertical axis | shaft shows the signal component signal and the horizontal axis shows the incident light intensity. It is a circuit diagram of the pixel which comprises the pixel array part by Embodiment 2 of this invention. 10 is a timing chart of the pixel circuit shown in FIG. 9.

(Embodiment 1)
FIG. 1 is a block diagram showing an overall configuration of a solid-state imaging apparatus according to Embodiment 1 of the present invention. The solid-state imaging device illustrated in FIG. 1 is a solid-state imaging device having a photoelectric conversion characteristic of a linear log characteristic in which a linear characteristic and a log characteristic are switched at an inflection point. Specifically, the solid-state imaging device according to the present embodiment is a solid-state imaging device having a linear log characteristic photoelectric conversion characteristic having a linear characteristic on the low luminance side and a log characteristic on the high luminance side from the inflection point.

  The solid-state imaging device includes an imaging element 110 and an image processing unit 120. The image sensor 110 and the image processing unit 120 may be configured in one IC chip or may be configured as separate IC chips.

  The image processing unit 120 includes an image signal processing unit 121 and an image sensor control unit 122. The image sensor control unit 122 outputs SYSCLK and the register control signal to the image sensor 110 to control the image sensor 110. SYSCLK is a clock signal having a predetermined frequency (for example, 54 MHz) generated by an oscillation circuit (not shown), for example. The register control signal is a signal for writing data to various registers included in the timing control unit 22 shown in FIG.

  The image sensor 110 outputs two-channel image signals of the first channel signal CH1 and the second channel signal CH2 to the image signal processing unit 121. Here, the first channel signal CH1 is an image signal output from an odd number of columns of the pixel array unit 21 shown in FIG. The second channel signal CH <b> 2 is an image signal output from the pixels in the even-numbered columns of the pixel array unit 21. Each of the first and second channel signals CH1 and CH2 includes an image signal D1 having linear characteristics and an image signal D2 having log characteristics.

  The image signal processing unit 121 performs various image processing on the first channel signal CH1 and the second channel signal CH2, and finally either one of the image signal D1 and the image signal D2 is used as the output image signal D3. Output to an external device. Here, the external device corresponds to, for example, a display device such as a liquid crystal panel or an organic EL panel, a memory that holds the output image signal D3, and the like.

  FIG. 2 is a block diagram showing a detailed configuration of the image sensor 110 shown in FIG. The image sensor 110 includes a pixel array unit 21, a timing control unit 22, a row decoder 23, a column ADC array unit 24, a column decoder 25, a sense amplifier 26, an LVDS serializer 27, an output terminal 28, a ramp wave generation circuit 29, and an input terminal. 210 and 211 are provided.

  The pixel array unit 21 is arranged in a matrix with M (integer of 2 or more) rows × N (integer of 2 or more) columns, and includes a plurality of pixels including light receiving elements.

  Each pixel is driven by the image sensor control unit 122 by switching between the reverse bias mode and the zero bias mode in one frame period. Here, the reverse bias mode is a mode in which exposure is performed by resetting a light receiving element included in a pixel in a reverse bias state. The reverse bias state refers to a state in which the cathode of the light receiving element included in each pixel is set to a higher potential than the anode. Note that the reverse bias mode is a mode that has been widely used in the past as a method for driving a photodiode constituting the solid-state imaging device, and is also referred to as a photodiode mode.

  The zero bias mode is a mode in which exposure is performed by resetting a light receiving element included in a pixel to a zero bias state. The zero bias state refers to a state where the anode and the cathode are at the same potential. The zero bias mode is also called a solar cell mode because it is the same driving method as the driving method of the light receiving element in the solar cell.

  Each pixel is composed of R, G, and B pixels each having a primary color filter of any one of red (R), green (G), and blue (B), for example. The R, G, and B pixels are arranged according to a predetermined arrangement pattern such as a Bayer arrangement.

  In place of the primary color filter, for example, a complementary color filter of cyan (C), yellow (Y), and magenta (M) may be employed. In this case, the C, Y, and M pixels may be arranged according to an arrangement pattern such as a Bayer arrangement.

  Complementary color filters are generally more sensitive than primary color filters. Therefore, when priority is given to sensitivity, a complementary color filter may be employed. However, when a complementary color filter is employed, a color conversion process for converting C, Y, and M image signals into R, G, and B image signals may be required, so that the processing cost is reduced. Is preferably a primary color filter.

  The timing control unit 22 includes a PLL, a timing generator (TG), and a register, and controls the row decoder 23, the column ADC array unit 24, and the column decoder 25. The PLL multiplies (for example, doubles) SYSCLK as necessary and supplies it to the TG. The TG generates a timing signal such as a horizontal synchronizing signal and a vertical synchronizing signal in accordance with the signal supplied from the PLL, and supplies the timing signal to the row decoder 23, the column ADC array unit 24, and the column decoder 25 to synchronize their operations. .

  The register holds data for defining the waveforms of various pixel control signals output from the row decoder 23 to each pixel, for example. Here, data held by the register is written by a register control signal output from the image sensor control unit 122.

  The row decoder 23 includes, for example, a vertical scanning circuit and a driver circuit. The vertical scanning circuit is configured by, for example, a shift register, and cyclically selects each row of the pixel array unit 21 using a vertical synchronization signal output from the timing generator as a trigger, and vertically scans the pixel array unit 21. Here, the row decoder 23 may sequentially select the pixel array unit 21 row by row from the upper side to the lower side, or sequentially row by pixel from the lower side to the upper side of the pixel array unit 21. You may choose.

  The driver circuit generates a pixel control signal according to the data written in the register of the timing control unit 22, and drives each pixel by supplying it to each pixel.

  The column ADC array unit 24 includes N column ADCs 212 corresponding to the respective columns of the pixel array unit 21. The column ADC 212 is connected to the pixels of each column via the vertical signal line L_1 corresponding to each column of the pixel array unit 21, and reads the image signal from the pixel of the row selected by the vertical scanning circuit.

  In the present embodiment, the column ADC array unit 24 includes a column ADC array unit 241 provided on the lower side of the pixel array unit 21 and a column ADC array unit 242 provided on the upper side of the pixel array unit 21. Yes.

  The column ADC array unit 241 reads out image signals from the odd-numbered columns of pixels in the pixel array unit 21, and the column ADC array unit 242 reads out image signals from the even-numbered columns of pixels in the pixel array unit 21. The image signal output from the column ADC array unit 241 via the sense amplifier 261 and the LVDS serializer 271 is the first channel signal CH1, and is output from the column ADC array unit 242 via the sense amplifier 262 and the LVDS serializer 272. The image signal is the second channel signal CH2.

  Each pixel outputs an image signal composed of only a noise component and an image signal obtained by adding a signal component to the noise component in one horizontal period. Here, an image signal consisting only of a noise component is described as a noise component signal, and an image signal obtained by adding a signal component to the noise component is described as a noise signal component signal.

  The column ADC 212 includes a correlated double sampling circuit and an AD conversion circuit. The correlated double sampling circuit performs correlated double sampling processing on the noise component signal and the noise signal component signal output from the pixel. As a result, the difference between the noise signal component signal and the noise component signal is obtained, the noise component contained in the noise signal component signal is removed, and a signal component signal that is an image signal composed only of the signal component is generated. The

  The AD conversion circuit AD-converts (analog-digital conversion) and holds the signal component signal generated by the correlated double sampling circuit. Specifically, when the signal component signal is input from the correlated double sampling circuit, the AD conversion circuit determines the time until the level of the ramp signal output from the ramp wave generation circuit 29 exceeds the level of the signal component signal. The analog signal component signal is AD converted. In the present embodiment, the signal component signal is converted into, for example, 14-bit digital data.

  The column decoder 25 includes a column decoder 251 provided below the column ADC array unit 241 and a column decoder 252 provided above the column ADC array unit 242.

  The column decoder 251 is composed of, for example, a shift register, and outputs a column selection signal synchronized with the horizontal synchronization signal output from the timing control unit 22 to cyclically select the column ADC 212 of each column in one horizontal scanning period. Then, the column ADC array unit 241 is horizontally scanned, and the digital image signals held by the column ADC 212 of each column are sequentially output to the sense amplifier 261. Note that the column decoder 252 is the same as the column decoder 251, and thus the description thereof is omitted.

  The sense amplifier 26 includes a sense amplifier 261 provided at the subsequent stage of the column ADC array unit 241 and a sense amplifier 262 provided at the subsequent stage of the column ADC array unit 242.

  The sense amplifier 261 amplifies a digital image signal output from the column ADC array unit 241 via the horizontal signal line L_2 and outputs the amplified signal to the LVDS serializer 271. In this embodiment, the column ADC 212 generates a 14-bit digital image signal, shifts the phase of each bit signal by 180 degrees, and outputs a signal whose phase is shifted by 180 degrees and a signal whose phase is not shifted. 28 signals in total are output to the sense amplifier 261.

  Therefore, a total of 28 horizontal signal lines L_2 connecting the column ADC array unit 241 and the sense amplifier 261 are provided. The sense amplifier 261 amplifies the signals flowing through the 28 horizontal signal lines L_2, shapes the waveform of each signal, and outputs the waveform to the LVDS serializer 271. Since the sense amplifier 262 has the same configuration as that of the sense amplifier 261, description thereof is omitted.

  The LVDS serializer 271 is a serializer compliant with the LVDS (Low Voltage differential singalings) standard, and differentially amplifies a signal output in parallel via the 28 horizontal signal lines L_2 from the sense amplifier 261, thereby a 14-bit signal. And converted to serial and output to the output terminal 281. Since the LVDS serializer 272 has the same configuration as the LVDS serializer 271, description thereof is omitted.

  The output terminal 28 includes an output terminal 281 provided at the subsequent stage of the LVDS serializer 271 and an output terminal 282 provided at the subsequent stage of the LVDS serializer 272.

  The output terminal 281 outputs the image signal from the LVDS serializer 271 to the image signal processing unit 121 as the first channel signal CH1. The output terminal 282 outputs the image signal from the LVDS serializer 272 to the image signal processing unit 121 as the second channel signal CH2.

  The ramp wave generation circuit 29 generates a ramp signal that changes linearly with a certain slope and outputs the ramp signal to each column ADC 212. The input terminal 210 receives SYSCLK supplied from the image sensor control unit 122 and outputs it to the timing control unit 22. The input terminal 211 receives a register control signal supplied from the image sensor control unit 122 and outputs the register control signal to the timing control unit 22.

  FIG. 3 is a circuit diagram of pixels constituting the pixel array unit 21 according to the first embodiment of the present invention. The pixel circuit shown in FIG. 5 includes a light receiving element (hereinafter referred to as “PD”), a reset transistor RST (hereinafter referred to as “RST”), and an amplifier AMP (hereinafter referred to as “AMP”). , A row selection transistor SEL (hereinafter referred to as “SEL”).

  The PD is composed of, for example, a surface-type photodiode, and a PD bias signal (an example of a pixel control signal, hereinafter referred to as “φRSB”) is input to the cathode via the RST, and the negative drive voltage PVSS is input to the anode. (Hereinafter referred to as “PVSS”) is applied. Here, a low level voltage (hereinafter referred to as “Lo”) is adopted as PVSS, and 0 V is adopted as the Lo voltage, for example.

  Then, PD is set to φRST = Hi (hereinafter referred to as “Hi”), Hi φRSB is input to the cathode, PVSS having the Lo level is input to the anode, and is reset in a reverse bias state. . Thereby, the pixel is driven in the reverse bias mode.

  On the other hand, PD has φRST = Hi, Lo φRSB is input to the cathode, PVSS having the Lo level is input to the anode, and is reset in a zero bias state. Thereby, the pixel is driven in the zero bias mode.

  The RST is composed of, for example, an nMOS and resets the PD. A reset signal φRST (an example of a pixel control signal, hereinafter referred to as “φRST”) for turning on / off RST is input to the gate of RST, φRSB is input to the drain, and the source is the cathode of PD. It is connected to the. When the pixel is driven in the reverse bias mode, the RST is turned on with φRST = Hi, supplies the Hi φRSB to the PD cathode, and resets the PD in the reverse bias state. When the pixel is driven in the zero bias mode, the RST is turned on with φRST = Hi, supplies the Lo φRSB to the cathode of the PD, and resets the PD in the zero bias state.

  Note that φRST and φRSB are output from the row decoder 23, for example. The PVSS is grounded, for example.

  The AMP has an input terminal connected to a connection point between the PD and the RST, an output terminal connected to the vertical signal line L_1 via the SEL, and amplifies the voltage of the cathode of the PD to output to the SEL. In the AMP, a positive drive voltage PVDD (hereinafter referred to as “PVDD”) is supplied to a positive power supply terminal, and PVSS is supplied to a negative power supply terminal. PVDD is supplied from a voltage source (not shown).

  The SEL is composed of, for example, an nMOS, and a row selection signal φVSEN (an example of a pixel control signal, hereinafter referred to as “φVSEN”) is input to a gate, a drain is connected to an output terminal of the AMP, and a source is a vertical signal. It is connected to the column ADC 212 in the corresponding column via the line L_1. The SEL outputs the voltage amplified by the AMP as an image signal to the column ADC 212 of the corresponding column via the vertical signal line L_1. Here, φVSEN is output from the row decoder 23.

  FIG. 4 is a timing chart of the pixel circuit shown in FIG. The timing chart of FIG. 4 shows a timing chart of one pixel circuit in one frame period T1. Here, one frame period T1 is a period required for pixels for one row to obtain an image signal for one line. Then, this one frame period T1 is repeated to sequentially obtain image signals for one horizontal line. In the present embodiment, one frame period T1 is divided into a first period T11 in which pixels are driven in the reverse bias mode and a second period T12 in which pixels are driven in the zero bias mode.

  Here, in the first period T11, an image signal D1 having a linear characteristic is output from the pixel, and in the second period T12, an image signal D2 having a log characteristic is output from the pixel.

  Since an image signal having a linear characteristic has time integration, it is necessary to secure a certain exposure period. On the other hand, since the log characteristics do not have time integration, it is not necessary to secure the exposure time unlike an image signal with linear characteristics. In the present embodiment, in one frame period T1, the pixels are first driven in the reverse bias mode to obtain an image signal D1 having linear characteristics, and then driven in the zero bias mode to have image characteristics having log characteristics. D2 is obtained. Therefore, in one frame period T1, a sufficient time for driving the pixels in the reverse bias mode can be secured, and an accurate image signal D1 can be obtained.

  At time t0, the pixel is driven in the reverse bias mode, and the voltage of the cathode of the PD decreases to the signal level V_s1 according to the amount of incident light.

  At time t1, φVSEN = Hi is set, and the voltage of the signal level V_s1 that is current-amplified by the AMP is read to the column ADC 212 as a noise signal component signal.

  At time t2, φRST = Hi is set, and the PD is reset. Since φRSB = Hi at this time, Hi φRSB is input to the cathode of PD, PVSS having Lo level is input to the anode of PD, and PD is reset in a reverse bias state. As a result, the cathode voltage of the PD rises to the Hi level.

  At time t3, φRST = Lo and φVSEN = Hi are set, and the voltage of the noise level V_n1 is current-amplified by the AMP and read to the column ADC 212 as a noise component signal. Here, when φRST = Lo, the voltage at the cathode of the PD decreases from the Hi level to the noise level V_n1 because of the influence of the parasitic capacitance between the PD and the RST.

  When the column ADC 212 reads the noise component signal from the pixel, the column ADC 212 performs correlated double sampling processing, takes the difference between the noise signal component signal read at time t1 and the noise component signal read at time t3, and obtains the noise component. A noise component included in the signal is removed, and a signal component signal is generated. This signal component signal is AD-converted and then output to the image signal processing unit 121 as an image signal D1 having linear characteristics.

  Next, φRSB = Lo, and the second period T12 is started.

  At time t4, φRST = Hi is set, Lo φRSB is input to the PD cathode, PVSS having the Lo level is input to the PD anode, and the PD is reset in a zero bias state. Thereby, the voltage of the cathode of PD is set to PVSS (= Lo).

  At time t5, the pixel is driven in the zero bias mode, and the voltage of the cathode of the PD decreases from PVSS to the signal level V_s2 according to the amount of incident light.

  At time t6, φVSEN = Hi is set, and the voltage of the signal level V_s2 that is current-amplified by AMP is read to the column ADC 212 as a noise signal component signal. Here, the voltage of the cathode of the PD fluctuates in the negative direction with respect to PVSS because the PD was reset in a zero bias state at time t4.

  At time t7, φRST = Hi is set, the PD is reset in a zero bias state, and the voltage of the cathode of the PD rises from the signal level V_s2 to PVSS. At time t7, φVSEN = Hi is set, and the voltage of PVSS generated at the cathode of the PD is read to the column ADC 212 as a noise component signal.

  When the column ADC 212 reads the noise component signal from the pixel, the column ADC 212 performs correlated double sampling processing, takes the difference between the noise signal component signal read at time t6 and the noise component signal read at time t7, A noise component included in the signal component signal is removed, and a signal component signal is generated. This signal component signal is AD-converted and then output to the image signal processing unit 121 as an image signal D2 having log characteristics.

  At time t8, φRST = Hi, φRSB = Hi, and the PD is reset in the reverse bias state. Thereafter, the drive sequence shown at times t1 to t8 is performed in one frame period T1, and this drive sequence is repeated to sequentially obtain one row of image signals.

  FIG. 5 is a graph showing an example of photoelectric conversion characteristics of a pixel driven in the reverse bias mode, in which the vertical axis indicates a signal component signal and the horizontal axis indicates incident light intensity. In FIG. 5, the horizontal axis is a logarithmic axis. As shown in FIG. 5, when the pixel is driven in the reverse bias mode, it can be seen that the signal component signal has a linear photoelectric conversion characteristic that linearly increases as the incident light intensity increases. In FIG. 5, since the horizontal axis is a logarithmic axis, a curve as shown in FIG. 5 is an output linear with respect to the incident light intensity. In FIG. 5, it can be seen that the signal component signal maintains a constant level and is saturated in the region where the incident light intensity is L1 or more. Further, it can be seen that the slope of the linear characteristic is large as shown in FIG. Therefore, it can be seen that the linear characteristic has a characteristic that the dynamic range is small but the sensitivity is high.

  In the conventional solid-state imaging device, as shown in FIG. 9, a transfer transistor TX (hereinafter referred to as “TX”) is provided between PD and FD, and the intermediate level between Hi and Lo is provided at the gate of TX. The PD pixel was exposed in the state where an intermediate voltage having the above is applied to realize a linear log characteristic.

  When an intermediate voltage is applied to the TX gate and the TX gate is in a half-open state, the signal charge accumulated in the PD cannot exceed the TX energy barrier until it exceeds a certain amount, and is accumulated with linear characteristics. Is done.

  On the other hand, if the signal charge accumulated in the PD exceeds a certain amount, a part of the signal charge leaks over the TX energy barrier and leaks to the TX side. Therefore, the PD accumulates while leaking the signal charge, and has log characteristics. Accumulate signal charge. Thus, the pixel has a linear log characteristic in which the low luminance side has a linear characteristic and the high luminance side has a log characteristic.

  Here, when the signal charges are accumulated with the linear characteristics, the pixels accumulate the signal charges without depending on the energy barrier of TX, so that there is little variation among individuals of the linear characteristics. On the other hand, when the signal charge is accumulated in the log characteristic, the pixel greatly depends on the TX energy barrier, and thus the variation in the log characteristic among individuals increases. As described above, the fact that the variation in the log characteristics is large while the variation in the linear characteristics is small is a problem of the conventional solid-state imaging device having the linear log characteristics.

  Therefore, in the present embodiment, the pixel is driven in the reverse bias mode in the first period T11 to obtain the image signal D1 having the linear characteristic, and the pixel is driven in the zero bias mode in the second period T12, so that the log characteristic is increased. By acquiring the image signal D2 possessed, the above problems were solved.

  FIG. 6 is a graph showing the photoelectric conversion characteristics of a pixel driven in the zero bias mode, in which the vertical axis indicates the signal component signal and the horizontal axis indicates the incident light intensity. The horizontal axis is logarithm. As shown in FIG. 6, when the pixel is driven in the zero bias mode, it is understood that the signal component signal has a logarithmic photoelectric conversion characteristic in which the signal component signal increases logarithmically as the incident light intensity increases. In FIG. 6, since the horizontal axis is a logarithmic axis, the logarithmic change is represented by a straight line.

  Here, the log characteristic obtained when the pixel is driven in the zero bias mode is not realized by applying an intermediate voltage to TX unlike the conventional solid-state imaging device having the linear log characteristic. Compared to a solid-state imaging device having characteristics, log characteristics with less variation can be obtained. Therefore, in this embodiment, the log characteristic variation is reduced by adopting the image signal D2 obtained by driving the pixel in the zero bias mode as the log characteristic image signal.

  FIG. 7 is a circuit diagram showing a detailed configuration of the image signal processing unit 121 shown in FIG. The image signal processing unit 121 includes a comparator 111, a CPU 112, two adders 113 and 115, two multipliers 114 and 116, a switch 117, and a color interpolation unit 118.

  The color interpolation unit 118 performs color interpolation processing for interpolating missing pixels for each color component, generates one image data composed of M rows × N columns for each color component, and outputs an image signal of each pixel. Are output sequentially. In the present embodiment, the pixel array unit 21 has R, G, B pixels arranged in a Bayer array, for example. Therefore, there are three color components R, G, and B for the image signal D1, and three color components R, G, and B for the image signal D2.

  Therefore, the color interpolation unit 118 generates three pieces of image data of R, G, and B for the image signal D1 by interpolation processing, and performs interpolation processing of the three pieces of image data of R, G, and B for the image signal D2. Generate by. Here, as the interpolation process, a process of calculating an image signal of a pixel to be interpolated by linearly interpolating an image signal of a peripheral pixel of the pixel to be interpolated may be employed.

  Specifically, the color interpolation unit 118, for example, three frame buffers for developing the R, G, and B image signals D1, and three sheets for developing the R, G, and B image signals D2. Frame buffer. Each time an image signal is input, the color interpolation unit 118 writes the image signal to the corresponding address of the corresponding color frame buffer, and develops the image signals D1 and D2 separately for each color component.

  The color interpolation unit 118 linearly interpolates the image signal D1 developed in the R, G, B frame buffer for developing the image signal D1, and R, G, B for developing the image signal D2. The image signal D2 developed in the frame buffer is linearly interpolated to interpolate missing pixels.

  When the interpolation processing is completed, the color interpolation unit 118 sequentially outputs the interpolated image signal D1 and simultaneously outputs the image signal D2 having the same pixel and color as the image signal D1. For example, if the color interpolation unit 118 outputs the R image signal D1 of the pixel in the first row and the first column, the color interpolation unit 118 outputs the R image signal D2 of the pixel in the first row and the first column simultaneously with the output. Thus, R image signals D1 and D2 of each pixel are sequentially output so as to perform raster scanning.

  When the output of the image signals D1 and D2 for all the R pixels ends, the color interpolation unit 118 then outputs the G image signals D1 and D2, and the output of the image signals D1 and D2 for all the G pixels. When the processing is completed, the image signals D are sequentially output in such a manner that the B image signals D1 and D2 are output next.

  The comparator 111 sequentially receives the image signals D1 after color interpolation from the color interpolation unit 118. The comparator 111 compares the level of the input image signal D1 with a predetermined threshold TH, and switches the switch 117 to the image signal D1 side or the image signal D2 side based on the comparison result.

  Specifically, the comparator 111 switches the switch 117 to the image signal D2 side when the image signal D1> the threshold value TH. As a result, the image signal processing unit 121 finally outputs the image signal D2 as the output image signal D3.

  On the other hand, if the image signal D1 ≦ the threshold value TH, the comparator 111 switches the switch 117 to the image signal D1 side. As a result, the image signal processing unit 121 finally outputs the image signal D1 as the output image signal D3.

  Here, as the threshold value TH, the level of the signal component signal at the inflection point P1 of the photoelectric conversion characteristic shown in FIG. 8 is adopted. Therefore, when the image signal D1> the threshold value TH, the comparator 111 determines that the pixel that has output the image signal D1 has received high-luminance light in the log area, and outputs the image signal D2 having log characteristics as the output image signal D3. Select as.

  On the other hand, when the image signal D1 ≦ the threshold TH, the comparator 111 determines that the pixel that has output the image signal D1 has received low-luminance light in the linear region, and outputs the image signal D1 having linear characteristics as the output image signal D3. Select as. As a result, as shown in FIG. 8, it is possible to realize a photoelectric conversion characteristic of a linear log characteristic having a linear characteristic on the low luminance side and a log characteristic on the high luminance side.

  The switch 117 is configured by, for example, a switching element. When a signal indicating the image signal D1> threshold value TH (for example, a Hi signal) is input from the comparator 111, the switch 117 connects the terminal 117b and the terminal 117c, and the image signal D2 is output. Further, when a signal indicating the image signal D1 ≦ the threshold value TH (for example, a Lo signal) is input from the comparator 111, the switch 117 connects the terminal 117a and the terminal 117c and outputs the image signal D1.

  However, it is not possible to obtain a photoelectric conversion characteristic in which the linear characteristic and the log characteristic as shown in FIG. 8 are smoothly connected at the inflection point P1 by simply switching between the image signal D1 and the image signal D2. There is sex.

  Therefore, the image signal processing unit 121 shown in FIG. 7 includes adders 113 and 115 and multipliers 114 and 116. The adder 113 adds a predetermined addition value a1 to the image signal D1 and outputs it to the multiplier 114. The adder 115 adds a predetermined addition value a2 to the image signal D2 and outputs the result to the multiplier 116.

  Here, the level of the signal component signal at the corresponding point P1 'when the corresponding point P1' of the inflection point P1 shown in FIG. 8 is plotted on the linear characteristic graph shown in FIG. Further, the level of the signal component signal at the corresponding point P1 ″ when the corresponding point P1 ″ of the inflection point P1 shown in FIG. 12 is plotted on the log characteristics shown in FIG. The corresponding points P1 'and P1 "are points where the incident light intensity has the incident light intensity L2 at the inflection point P1.

  In this case, the added values a1 and a2 may be values such that V1 and V2 become the threshold value TH. That is, the addition values a1 and a2 may be determined so that TH = a1 + V1 = a2 + V2. Here, the addition values a1 and a2 are preset and supplied from the CPU 112 to the adders 113 and 115.

  In addition, the slope of the linear characteristic of the image signal D1 and the log characteristic of the image signal D2 may fluctuate according to changes in ambient temperature, for example. Therefore, the multiplier 114 multiplies the image signal D1 by a coefficient b1 in order to return the slope of the changed linear characteristic to the original slope of the linear characteristic. Further, the multiplier 116 multiplies the image signal D2 by a count b2 in order to return the slope of the changed log characteristics to the original slope of the log characteristics. Thereby, an output image signal D3 having a certain linear log characteristic is obtained.

  Here, the coefficients b1 and b2 are preset and supplied from the CPU 112 to the multipliers 114 and 116. Specifically, the CPU 112 determines the coefficients b1 and b2 by referring to a lookup table in which the relationship between the ambient temperature and the coefficients b1 and b2 corresponding to the ambient temperature is defined in advance, and the multiplier 114, 116 may be supplied.

  Further, the CPU 112 may determine the ambient temperature from measurement data detected by a temperature sensor (not shown), for example.

  In FIG. 7, the comparator 111 compares the image signal D1 with the threshold value TH. However, the present invention is not limited to this, and the image signal D2 may be compared with the threshold value TH.

  FIG. 8 is a graph showing the photoelectric conversion characteristics of the output image signal D3, where the vertical axis shows the signal component signal and the horizontal axis shows the incident light intensity. The horizontal axis is a logarithmic axis.

  Since the image signal processing unit 121 performs the above processing, the output image signal D3 has a linear characteristic on the low luminance side and a log characteristic on the high luminance side at the inflection point P1, as shown in FIG. It has a photoelectric conversion characteristic of a linear log characteristic.

  For example, when the threshold value TH is set to 50% of the maximum level of the signal component signal, when an image signal D1 less than 50% of the maximum level is output, an image signal D1 having a linear characteristic is output, and 50% or more of the maximum level. When the image signal D1 is output, the log characteristic image signal D2 is output. Therefore, it is possible to image a subject having a lower luminance than the inflection point P1 with a highly sensitive linear characteristic and to image a subject having a higher luminance than the inflection point with a log characteristic having a high dynamic range.

  Since the image signal D2 is output from a pixel driven in the zero bias mode, an image signal with very little variation can be obtained. In particular, there is very little noise near the threshold TH, and a high-quality image signal can be obtained.

  As described above, in the solid-state imaging device, one frame period T1 is divided into the first period T11 and the second period T12, and the pixels are driven in the reverse bias mode in the first period T11 to obtain the image signal D1. In the second period T12, the pixel is driven in the zero bias mode to acquire the image signal D2. Therefore, in one frame period, an image signal D1 having a high sensitivity linear characteristic and an image signal D2 having a log characteristic with little variation can be obtained simultaneously. Then, by switching both signals by the image signal processing unit 121 provided in the subsequent stage, it is possible to provide a solid-state imaging device having a linear log characteristic in which the linear characteristic and the log characteristic are combined, and a linear log with little variation in the log area. Characteristics can be realized. In addition, since the pixel is configured by a surface-type photodiode, the manufacturing process of the pixel array unit 21 can be simplified.

(Embodiment 2)
The solid-state imaging device according to the second embodiment is characterized in that the light receiving element of the pixel is configured by an embedded photodiode. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  FIG. 9 is a circuit diagram of pixels constituting the pixel array unit 21 according to the second embodiment of the present invention. The pixel circuit shown in FIG. 9 is further provided with TX and a floating diffusion layer (hereinafter referred to as “FD”; FD: floating diffusion) in addition to the pixel circuit shown in FIG.

  In the pixel circuit shown in FIG. 9, the PD is composed of an embedded photodiode, PVSS is input to the anode, and the source of TX is connected to the cathode.

  The TX is configured by, for example, an nMOS (negative channel metal oxide semiconductor), and transfers signal charges accumulated by the PD to the FD. A transfer control signal φTX (an example of a pixel control signal, hereinafter referred to as “φTX”) for turning on / off TX is input to the gate of TX. The drain of TX is connected to RST via FD. When φTX becomes Lo, the TX gate is closed and TX is turned off. When φTX becomes Hi, the TX gate is opened and TX is turned on. Note that φTX is output from the row decoder 23.

  The FD accumulates signal charges transferred from the PD. As a result, a voltage corresponding to the signal charge appears in the FD.

  The RST is composed of, for example, an nMOS, resets the FD, and discharges signal charges accumulated in the FD to the outside of the FD.

  ΦRST is input to the gate of RST, φRSB is input to the drain, and the source is connected to the input terminal of AMP via FD. The RST resets the PD by inputting a voltage of φRSB = Hi to the cathode of the PD in order to drive the pixel in the reverse bias mode. The RST resets the PD by inputting a voltage of φRSB = Lo to the cathode of the PD in order to drive the pixel in the zero bias mode.

  Note that φRST and φRSB are output from the row decoder 23. The PVSS is grounded, for example.

  The AMP has an input terminal connected to the FD and an output terminal connected to the vertical signal line L_1 via the SEL, and amplifies the voltage of the cathode of the FD and outputs it to the SEL. In the AMP, PVDD is supplied to the positive power supply terminal and PVSS is supplied to the negative power supply terminal.

  FIG. 10 is a timing chart of the pixel circuit shown in FIG. Note that the timing chart shown in FIG. 10 is also divided into the first period T11 and the second period T12 in the same manner as the timing chart shown in FIG. 4, and the pixels are driven in the reverse bias mode in the first period T11. In the second period T12, the pixel is driven in the zero bias mode.

  At time t0, φRST = Hi, Hi φRSB is applied to the FD, and the FD is reset. Thereby, the voltage of FD becomes Hi.

  At time t1, φVSEN = Hi is set, and the voltage of the noise level V_n1 appearing in the FD is read by the column ADC 212 as a noise component signal. At time t1, φRST = Lo, so that the voltage of FD decreases from Hi to noise level V_n1 because of the influence of parasitic capacitance between FD and RST, ktc noise of FD, and the like. Because.

  At time t2, φVSEN = Lo and φTX = Hi are set, and the signal charge accumulated in the PD is transferred to the FD. Thereby, the voltage of FD falls from noise level V_n1 to signal level V_s1.

  At time t3, φVSEN = Hi and φTX = Lo are set, and the voltage of the signal level V_s1 appearing in the FD is current-amplified by the AMP and read out by the column ADC 212 as a noise signal component signal.

  When the column ADC 212 reads the noise signal component signal, the column ADC 212 performs correlated double sampling, takes the difference between the noise component signal read at time t1 and the noise signal component signal read at time t3, and obtains the noise signal. A noise component included in the component signal is removed, and a signal component signal is generated. This signal component signal is AD-converted and then output to the image signal processing unit 121 as an image signal D1 having linear characteristics.

  Next, φRSB = Lo, and the second period T12 is started.

  At time t4, φRST = Hi and φTX = Hi are set, Lo φRSB is input to the cathode of the PD, and the PD is reset in a zero bias state. Thereby, the voltage of FD falls from signal level V_s1 to PVSS (= Lo).

  Next, φRST is changed from Hi to Lo, and exposure in the zero bias mode is started.

  At time t5, the pixel is driven in the zero bias mode, the voltage of the cathode of the PD decreases from PVSS to the signal level V_s2 according to the amount of incident light, and the voltage of the FD decreases from PVSS to the signal level V_s2.

  At time t6, φVSEN = Hi, the voltage of the signal level V_s2 appearing on the FD is amplified by the AMP, and read out to the column ADC 212 as a noise signal component signal.

  At time t7, φRST = Hi is set, Lo φRSB is input to the cathode of the PD, and the PD is reset in a zero bias state. As a result, the voltage of the FD increases from the signal level V_s2 to PVSS. At time t7, since φVSEN = Hi, the voltage of PVSS appearing on the FD is amplified by the AMP and read to the column ADC 212 as a noise component signal.

  When the column ADC 212 reads the noise component signal, it performs correlated double sampling, takes the difference between the noise signal signal component read at time t6 and the noise component signal read at time t7, and obtains the noise signal component signal. The noise component contained in is removed, and a signal component signal is generated. This signal component signal is AD-converted and then output to the image signal processing unit 121 as an image signal D2 having log characteristics.

  At time t8, φRST = Hi, φRSB = Hi, Hi φRSB is input to the FD, and the FD is reset. Thereby, the voltage of FD rises from PVSS to Hi. At time t8, Hi φRSB is input to the cathode of the PD, so that the PD is reset in a reverse bias state. As a result, in the subsequent first period T11, the pixel is driven in the reverse bias mode.

  As described above, in the solid-state imaging device according to the embodiment, an image signal having linear characteristics in one frame period T1 is the same as in the first embodiment, even when a pixel including an embedded photodiode is employed. D1 and an image signal D2 having log characteristics can be obtained. Therefore, linear log characteristics with little variation in the log area can be realized. Further, since the pixel is composed of an embedded photodiode, a high-quality image signal can be obtained.

  In Embodiments 1 and 2, the pixels are driven in the order of the reverse bias mode and the zero bias mode in one frame period. However, the present invention is not limited to this, and the order may be reversed. Good.

DESCRIPTION OF SYMBOLS 110 Image sensor 120 Image processing part 121 Image signal processing part 122 Image sensor control part 21 Pixel array part 22 Timing control part 23 Row decoder 24 Column ADC array part 25 Column decoder P1 Inflection point D1 Image signal D2 Image signal D3 Output image signal RST reset transistor TX transfer transistor SEL row selection transistor AMP amplifier

Claims (7)

A solid-state imaging device having a photoelectric conversion characteristic of a linear log characteristic in which a linear characteristic and a log characteristic are switched at an inflection point,
An image sensor composed of a plurality of pixels including a light receiving element;
A reverse bias mode in which the light receiving element is reset and exposed in a reverse bias state to output a first image signal having a linear characteristic from the pixel, and the light receiving element is reset and exposed in a zero bias state to expose the pixel. An image sensor control unit for driving the pixels so that a zero bias mode for outputting a second image signal having a log characteristic is switched in one frame period;
A solid-state imaging device comprising: an image signal processing unit that switches and outputs the first image signal and the second image signal based on a level of the first image signal or the second image signal.   The solid-state imaging device according to claim 1, wherein the imaging element control unit drives the pixel in the zero bias mode after driving the pixel in the reverse bias mode in the one frame period.   The image signal processing unit outputs the first image signal when the level of the first image signal is equal to or lower than a threshold value indicating the level of the image signal at the inflection point, and the level of the first image signal is the threshold value 3. The solid-state imaging device according to claim 1, wherein the second image signal is output when the value is larger.   The solid-state imaging device according to claim 1, wherein the pixel includes a primary color filter.   The solid-state imaging device according to claim 1, wherein the pixel includes a complementary color filter.   The solid-state imaging device according to claim 1, wherein the light receiving element is a surface type photodiode.   The solid-state imaging device according to claim 1, wherein the light receiving element is an embedded photodiode.

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