JP2012238745A - Semiconductor wafer - Google Patents

Abstract

A semiconductor wafer capable of highly accurately evaluating electrical characteristics of a semiconductor chip at a plurality of timings and capable of reducing the total amount of metal in a scribe region.
A semiconductor wafer includes a plurality of wiring layers, a plurality of semiconductor chip regions, and a scribe region that separates the plurality of semiconductor chip regions in a plan view, and is disposed in the scribe region. The electrical characteristic evaluation monitor element 10, the first electrode pad 20 disposed in the scribe region S, connected to the monitor element 10, and formed in any one of the plurality of wiring layers, and the semiconductor A second electrode pad 40 is provided in the chip region C, connected to the first electrode pad 20, and formed in an upper layer than the wiring layer in which the first electrode pad 20 is formed.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor wafer.

  In the manufacture of a semiconductor chip provided with at least one semiconductor element, a plurality of semiconductor chips are collectively formed on one semiconductor wafer and then divided into individual semiconductor chips in a subsequent dicing process.

In the process of manufacturing a semiconductor wafer, in order to monitor the electrical characteristics of the semiconductor chip such as the element characteristics of the semiconductor element and quickly detect a defect, the semiconductor wafer has at least one monitor element for evaluating the electrical characteristics of the semiconductor chip. (Monitor pattern) and monitor element electrode pads for conducting an operation test of the monitor element are formed. The probe is brought into contact with the monitor element electrode pad to inspect the electrical characteristics of the semiconductor chip.
Conventionally, as the chip size is reduced, monitor elements and monitor element electrode pads that are unnecessary for the final product are formed in a scribe area (dicing area) of a semiconductor wafer.
Patent Documents 1 and 3-5 disclose a technique for disposing at least one of a monitor element and a monitor element electrode pad in a scribe region.

  Patent Document 1 describes a semiconductor wafer in which monitor elements are arranged in a scribe region and electrode pads are arranged in a semiconductor chip region (FIG. 1 of Patent Document 1).

  Patent Document 3 describes a semiconductor wafer in which monitor elements are arranged in a scribe region and electrode pads are formed in a semiconductor chip (FIG. 1C of Patent Document 3).

In Patent Document 4,
An LSI chip formed by integrating an internal circuit composed of semiconductor elements and an inspection circuit used for inspecting the internal circuit, and a scribe TEG formed on a scribe region around the LSI chip and formed with an evaluation element and an electrode terminal Prepared,
At least one of the electrode terminals in the scribe TEG describes a semiconductor wafer electrically connected to an evaluation element in the scribe TEG and an inspection circuit in the LSI chip (FIG. 2 of Patent Document 4).

In Patent Document 5,
An LSI chip formed by integrating internal circuits made of semiconductor elements;
A scribe TEG formed on a scribe region around the LSI chip and provided with an evaluation element and an electrode terminal,
A semiconductor wafer is described in which at least one evaluation element of the scribe TEG and an electrode terminal of the scribe TEG are separately formed in different regions in the scribe region (FIGS. 1 and 2 of Patent Document 5).

  As a related technique, Patent Document 2 discloses a semiconductor wafer in which a monitor element for detecting whether a crack or the like has occurred in a semiconductor chip is provided in an area outside the guard ring in the semiconductor chip. (FIG. 1 of Patent Document 2).

JP 2010-087354 A JP 2010-056428 A JP2008-060094 Japanese Patent No. 4105180 Japanese Patent No. 4112573

As a result of intensive studies by the inventors, the following problems have been found. The following description is based on the results of investigation by the inventors.
FIG. 8 is a diagram for explaining the problem created by the inventor. In the drawing, symbol C indicates a semiconductor chip region, symbol S indicates a scribe region, symbol M indicates a metal (wiring or electrode pad), and symbol V indicates a via hole. In FIG. 8, a wiring structure including a plurality of metals in the semiconductor chip region C, an interlayer insulating film that insulates between the plurality of metals, and a via hole formed in the interlayer insulating film is not shown.

In the semiconductor wafer 101 in FIG. 8, the monitor element 110 is formed in the scribe region S, and the first electrode pad 120 that is electrically connected to the monitor element 110 is formed in the lowermost layer metal MB of the plurality of wiring layers. The first electrode pad 120 is for detecting electrical characteristics of the semiconductor chip region C such as element characteristics of the semiconductor element before forming a plurality of wiring layers in the semiconductor chip region C.
A plurality of via holes V and metals M are alternately connected on the first electrode pad 120, and the second electrode pad 140 is formed on the uppermost metal layer MT. When the lowermost wiring layer is formed, the first electrode pad 120 connected to the monitor element 110 is energized to determine whether the process is normal from the characteristics of the monitor element 110. When the formation of the plurality of wiring layers is completed, the second electrode pad 140 connected to the monitor element 110 is energized to determine whether the process is normal from the characteristics of the monitor element 110. Since it can be determined at this early stage whether the characteristics are normal, the process cost can be reduced.
Here, the inventors have revealed that the following problems occur. When a probe is brought into contact with the first electrode pad 120 to energize, a trace of probing is formed on the surface of the first electrode pad 120. At this time, there is a risk of affecting electrical contact between the first electrode pad 120 and the via hole V and the metal M formed on the first electrode pad 120. For this reason, the accuracy of the inspection using the second electrode pad 140 may be reduced.
Patent Documents 1-5 do not recognize such a problem, and do not disclose a solution to the problem.

The semiconductor wafer of the present invention is
A plurality of wiring layers are laminated, and a semiconductor wafer having a plurality of semiconductor chip regions in plan view and a scribe region that separates the plurality of semiconductor chip regions,
A monitor element for electrical property evaluation arranged in the scribe region;
A first electrode pad disposed in the scribe region, connected to the monitor element, and formed in any one of the plurality of wiring layers; and disposed in the semiconductor chip region, the first electrode A second electrode pad is provided which is connected to a pad and formed in an upper layer than the wiring layer on which the first electrode pad is formed.

  In the semiconductor wafer of the present invention, since the planar positions of the first electrode pad and the second electrode pad on the first electrode pad are different from each other, the first electrode pad is used after the initial inspection using the first electrode pad. Even if a probing mark remains on the electrode pad, the inspection can be performed with high accuracy without affecting the probing mark at the later stage of manufacturing using the second electrode pad.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor wafer which can evaluate the electrical property of a semiconductor chip with high precision at several timings in the manufacture process of a semiconductor wafer can be provided.

1 is an overall plan view of a semiconductor wafer according to an embodiment of the present invention. It is a partial enlarged plan view of a semiconductor wafer of one embodiment concerning the present invention. It is a principal part perspective view of the semiconductor wafer of one Embodiment concerning this invention. It is a principal part perspective view which shows the example of the formation pattern of the seal ring of the semiconductor wafer of one Embodiment which concerns on this invention. It is a principal part perspective view which shows the other example of a formation pattern of the seal ring of the semiconductor wafer of one Embodiment which concerns on this invention. It is an example of principal part sectional drawing of the structure shown in FIG. FIG. 6 is another example of a cross-sectional view of the main part of the structure shown in FIG. 5. It is a principal part perspective view for demonstrating a subject.

"One embodiment"
A configuration of a semiconductor wafer according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an overall plan view of the semiconductor wafer of this embodiment, and FIG. 2 is a partially enlarged plan view. 3 to 5 are perspective views of the main part of the semiconductor wafer according to the present embodiment, and FIGS. 6 and 7 are cross-sectional views of the main part.
In order to facilitate visual recognition on the drawings, the scales and positions of the respective members are appropriately simplified from the actual ones. In addition, illustration of some components is omitted.
In the figure, reference numeral C denotes a semiconductor chip area, reference numeral S denotes a scribe area, reference numeral M denotes a metal (wiring or electrode pad), reference numeral I denotes an interlayer insulating film, and reference numeral V denotes a via hole. In the above figure, the wiring structure is formed in the semiconductor chip region C and includes a plurality of metals M, an interlayer insulating film I that insulates between the plurality of metals M, and a via hole V formed in the interlayer insulating film I. The illustration is omitted.

  As shown in FIG. 1, a semiconductor wafer 1 according to the present embodiment has a plurality of rectangular semiconductor chip regions C formed in a matrix in a plan view. A scribe region S is formed between adjacent semiconductor chip regions C. The number and arrangement of the semiconductor chip regions C are appropriately designed.

A plurality of wiring layers are stacked on the semiconductor wafer 1. The wiring layer can be formed by a CMP (chemical mechanical polishing) process using a damascene process. The plurality of wiring layers are formed in the semiconductor chip region C and the scribe region S. In the scribe region S, some of the wiring layers may be removed.
In the semiconductor wafer 1, a plurality of wiring layers include a wiring layer composed of wiring (metal M) and an interlayer insulating film I, and a via layer composed of a via hole V embedded in the interlayer insulating film I and the interlayer insulating film V. Shall be included. In the semiconductor chip region C, wiring layers and via layers are usually stacked alternately.

The composition of the interlayer insulating film is not particularly limited, and examples thereof include Low-K materials such as silicon oxide, SiOC, SiOCH, MSQ, HSQ, MHSQ, porous Si, and SiLK. A barrier film such as SiN may be formed between adjacent metals. The composition of the metal M is not particularly limited, and a material containing Al and / or Cu is preferable.
In the semiconductor chip region C, semiconductor elements (not shown) such as transistors are formed.

  As shown in FIG. 3, the semiconductor wafer 1 is electrically connected to the monitor element 10 and at least one monitor element (monitor pattern) 10 for evaluating element characteristics and the like of the semiconductor element in the manufacturing process of the semiconductor wafer 1. The first electrode pads 20 are formed in any one of the plurality of wiring layers, and are connected to the first electrode pads 20 and the first electrode pads 20 for performing the characteristic inspection of the monitor element 10. A plurality of second electrode pads 40 formed above the wiring layer on which the electrode pads 20 are formed are formed.

The first electrode pad 20 is for evaluating the electrical characteristics of the semiconductor chip region C before forming a plurality of wiring layers in the semiconductor chip region C (in the initial stage of manufacturing the semiconductor wafer). It is preferable to form the first electrode pad 20 with the lowermost layer metal MB (first layer metal).
The second electrode pad 40 is for evaluating the electrical characteristics of the semiconductor chip region C after forming a plurality of wiring layers in the semiconductor chip region C (late stage of semiconductor wafer manufacture). It is preferable to form the first electrode pad 20 with the uppermost layer metal MT.
In the initial stage of manufacture, the probe is brought into contact with each of the plurality of first electrode pads 20 conducted to the monitor element 10, and the characteristics of the monitor element are evaluated. Further, in the later stage of manufacturing after the formation of the plurality of wiring layers, the probe is brought into contact with each of the plurality of second electrode pads 40 to evaluate the characteristics of the monitor element. If it is judged as abnormal as a result of the characteristic evaluation at the initial stage of production, whether the production of the lot is stopped as an abnormal wafer, or whether the same process is performed again after performing a reconstruction process to return to the previous process Then, it is determined whether or not to perform defect analysis. Wafers in which no abnormality is found in the characteristic evaluation at the initial stage of manufacture are advanced to the next process, and the characteristic evaluation is performed again in the latter stage of manufacturing.

The monitor element is not particularly limited, and examples thereof include a transistor, a resistor, a via chain, and an intermetal leak check pattern.
In the example shown in FIG. 3, the monitor element 10 is a transistor for evaluating the element characteristics of the semiconductor element in the semiconductor chip region C, and is formed on the surface layer of the semiconductor wafer. An interlayer insulating film is formed thereon so as to cover it. A lowermost wiring layer having the lowermost metal MB is formed thereon.
In the illustrated example, the first electrode pad 20 is formed on the lowermost metal MB. The wiring M and the via hole V are not formed immediately above the first electrode pad 20. Only the interlayer insulating film I is formed immediately above the first electrode pad 20. However, the interlayer insulating film immediately above the first electrode pad 20 may be partially or entirely removed.
On the periphery of the semiconductor chip region C, the second electrode pad 40 is formed on the uppermost metal layer MT. In FIG. 3, the second electrode pad 40 is formed on the uppermost layer metal MT, but may be any layer above the wiring layer on which the first electrode pad 20 is formed, and may not necessarily be the uppermost layer metal MB. .

In the present embodiment, the first electrode pad 20 and the monitor element 10 are the wiring 11 and the wiring 11 that are formed in the scribe region S and drawn from the first electrode pad 20 and the monitor element 10 below the wiring 11. Are connected through a contact 12 connecting the two.
Also, a wiring 21 extending from the first electrode pad 20 into the semiconductor chip region C is formed, and this wiring 21 is connected to a wiring 30 formed in the semiconductor chip region C by the lowermost metal MB. Yes.
The wiring 30 formed in the lowermost metal MB and the second electrode pad 40 formed in the uppermost metal MT are electrically connected through the plurality of metals M and the plurality of via holes V formed therebetween. Yes.

The monitor element 10 is for evaluating element characteristics of a semiconductor element, as well as an electric resistance between the via hole V and the metal M, an electric resistance between the active region of the semiconductor layer and the contact 12, and a resistance such as polysilicon. Any one of a body resistance value, a leak check between adjacent metals, and a leak check of a capacitor may be evaluated.
The semiconductor wafer 1 can include a plurality of types of monitor elements 10 to be inspected.
In the example shown in FIG. 3, the monitor element 10 is for evaluating the element characteristics of the semiconductor element and is formed on the surface layer of the semiconductor layer. The layer on which the monitor element 10 is formed depends on the inspection object.

In the example shown in FIG. 3, the first electrode pad 20 is formed on the lowermost layer metal MB, and the second electrode pad 40 is formed on the uppermost layer metal MT. If the electrode pad 40 is an upper layer, these may be formed in any layer. The second electrode pad 40 may be formed immediately above the uppermost metal layer MT (see examples shown in FIGS. 6 and 7 to be described later).
Regardless of which electrode pad 20, 40 is formed, when the first electrode pad 20 is formed, an inspection using the first electrode pad 20 is performed, and the second electrode pad 40 is formed. At the time, an inspection using the second electrode pad 40 can be performed.

As shown in FIG. 4, a seal ring 50 may be formed on the periphery of the semiconductor chip region C in order to prevent moisture and the like from entering the semiconductor chip region C.
As shown in FIGS. 6 and 7, the seal ring 50 has a structure in which a plurality of metals M and a plurality of via holes V are connected.

As shown in FIG. 4, the wiring structure X including the second electrode pad 40 can be formed outside the seal ring 50.
As shown in FIG. 5, the second electrode pad 40 is formed inside the seal ring 50 formed at the peripheral edge of the semiconductor chip region C, and the first electrode pad 20 and the second electrode pad 40 are connected to each other. It is good also as a structure which conducts through the diffused layer formed in the polysilicon layer or semiconductor layer of the lower layer of the seal ring 50. FIG.
In FIG. 5, the formation position of the seal ring 50 is indicated by a broken line.

6 and 7 show an example of a cross section of the main part of the structure shown in FIG. The number of wiring layers in these figures is different from that in FIGS.
In these examples, the second electrode pad 40 is formed directly above the uppermost metal MT, not the uppermost metal MT.

In the figure, numeral 61 is a semiconductor substrate, numeral 62 is an element isolation region, numeral 63 is a well region, numeral 64 is a diffusion layer (active layer), numeral 65 is a gate electrode made of polysilicon, numeral 66 is a passivation film, numeral I Is an interlayer insulating film.
For example, as shown in FIG. 6, the wiring structure X including the first electrode pad 20 and the second electrode pad 40 is connected via the diffusion layer (active layer) 64 of the semiconductor element 60 below the seal ring 50. Can be conducted. Alternatively, as shown in FIG. 7, the wiring structure X including the first electrode pad 20 and the second electrode pad 40 is connected via the gate electrode 65 made of polysilicon of the semiconductor element 60 below the seal ring 50. Can be conducted.

  In the configuration in which the first electrode pad 20 and the wiring structure X including the second electrode pad 40 are connected via a conductive layer below the seal ring 50, scattering of wiring pieces in the dicing process and the semiconductor chip region C This is preferable because it can reduce the influence on the environment.

In Patent Document 4 listed in the “Background Art” section, the uppermost layer of the seal ring is partially cut, so that the sealing performance of the seal ring is reduced, and moisture or the like enters the semiconductor chip region C. There is a fear.
In the example shown in FIGS. 5 to 7, since the seal ring 50 is not partially removed, there is no possibility of reducing the sealing performance of the seal ring.

  In the above example, the first electrode pad 20 and the wiring structure X including the second electrode pad 40 are electrically connected via the diffusion layer 64 which is a conductive layer below the seal ring 50 or the gate electrode 65 made of polysilicon. Although the structure to perform was demonstrated, these can be conduct | electrically_connected through the arbitrary conductive layers in the lower layer from the seal ring 50. FIG.

In the semiconductor wafer 1 of the present embodiment, the first electrode pad 20 and the second electrode pad 40 that is higher than the first electrode pad 20 are provided. Multiple inspections can be performed at the same time.
In the semiconductor wafer 1 of the present embodiment, since the positions of the first electrode pad 20 and the second electrode pad 40 in the upper layer are different from each other in plan view, the inspection using the first electrode pad 20 is performed. Even if a probing trace remains on the first electrode pad 20 later, the probing trace does not affect the inspection using the second electrode pad 40, and the inspection can be performed with high accuracy.

  In the present embodiment, since the planar positions of the first electrode pad 20 and the second electrode pad 40 in the upper layer are different from each other, it is not necessary to form a wiring structure immediately above the first electrode pad 20. . Therefore, the total amount of metal in the scribe region S can be reduced. As a result, it is possible to suppress the metal from adhering to the dicing blade and damaging the semiconductor wafer 1 in the dicing process after the wafer is manufactured.

In the semiconductor wafer 1 of the present embodiment, as shown in FIG. 2, the wiring structure of the semiconductor chip region C is the same as that in the region different from the formation region of the first electrode pad 20 in the scribe region S as necessary. A dummy wiring structure D having a wiring structure and having a total plane area smaller than the total plane area of the first electrode pads 20 can be provided.
In such a configuration, the dummy wiring structure D can ensure surface flatness at the time of CMP in the scribe region S, and the wiring structure in the semiconductor chip region C can be favorably formed. Here, the dummy wiring structure D may be a structure in which a plurality of dummy wirings are connected to each other by via holes, or may be a structure in which the plurality of dummy wirings are not connected by via holes. The dummy wiring is not connected to the wiring in the semiconductor chip region C.
The electrode pad 20 for the monitor element needs a certain area in order to contact the probe. Since the dummy wiring structure D does not include electrode pads, the total plane area of the dummy multilayer wiring structure D can be made smaller than the total plane area of the first electrode pad 20. Therefore, in the configuration of this embodiment, even if the dummy wiring structure D is provided in the scribe region S, the total metal amount in the scribe region S is reduced as compared with the conventional configuration in which the electrode pad and the wiring structure immediately above the scribe region S are provided. can do.

  As described above, according to the present embodiment, the electrical characteristics of the semiconductor chip region C can be evaluated with high accuracy at a plurality of timings in the manufacturing process of the semiconductor wafer 1, and the total metal amount of the scribe region S can be evaluated. The semiconductor wafer 1 capable of manufacturing the semiconductor chip region C with a high yield can be provided.

"Comparative example"
Differences between the comparative example shown in FIG. 8 and the embodiment according to the present invention will be described.
In the comparative example shown in FIG. 8, after confirming the characteristics of the monitor element 110 using the first electrode pad 120 used for inspection at the initial stage of manufacturing, after forming a plurality of wiring layers, the second electrode pad 140 is formed. When the characteristics of the monitor element 110 are confirmed using the first electrode pad 110 and the second electrode pad 140, a plurality of via holes V and a plurality of metals M are connected to electrically connect the two. . Therefore, when the first electrode pad 120 is arranged in the scribe region S, the total amount of metal in the scribe region S increases as shown in FIG.
The increase in the total amount of metal in the scribe region S causes chipping when the semiconductor chip region C is separated. The semiconductor chip region C is divided into each semiconductor chip region C by cutting the normal scribe region S with a dicing blade. At this time, if the total amount of metal in the scribe region S is large, clogging occurs in the dicing blade, stress is applied to the semiconductor wafer 101, and chipping occurs.
In the embodiment according to the present invention, the second electrode pad 140 is disposed not in the scribe region S but in the semiconductor chip region C. Therefore, chipping of the semiconductor chip region C can be suppressed.
In particular, when the wiring layer formation process is a damascene process using CMP (Chemical Mechanical Polishing), in order to ensure the flatness of the wiring layer in the CMP process, the first electrode pad 120 and the second electrode pad 140 in FIG. The metal M between the first electrode pad 120 and the first electrode pad 120 needs to have the same area. The metal M between the first electrode pad 120 and the second electrode pad 140 needs to be larger than a size that allows the first electrode pad 120 and the second electrode pad 140 to be electrically connected. is there. Therefore, in the configuration of FIG. 8, the total amount of metal in the scribe region S tends to increase. In the embodiment according to the present invention, when the wiring layer is formed by a damascene process, chipping can be suppressed more than in FIG. 8, which is preferable.

"Design changes"
The present invention is not limited to the above embodiment, and can be appropriately modified within a range not departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 10 Monitor element 20 1st electrode pad 40 2nd electrode pad 50 Seal ring 60 Semiconductor element 62 Element isolation area 64 Diffusion layer 65 Gate electrode C Semiconductor chip S Scribe area M Metal MB Bottom layer metal MT Top layer metal I Insulating film V Via hole X Wiring structure D Dummy wiring structure

Claims (7)

A plurality of wiring layers are laminated, and a semiconductor wafer having a plurality of semiconductor chip regions in plan view and a scribe region that separates the plurality of semiconductor chip regions,
A monitor element for electrical property evaluation arranged in the scribe region;
A first electrode pad disposed in the scribe region, connected to the monitor element, and formed in any one of the plurality of wiring layers;
A semiconductor wafer comprising a second electrode pad disposed in the semiconductor chip region, connected to the first electrode pad, and formed in an upper layer than the wiring layer on which the first electrode pad is formed.   The semiconductor wafer according to claim 1, wherein no metal is formed immediately above the first electrode pad.   The scribe region has a plurality of wiring layers in a region different from a region where the first electrode pad is formed, and has a dummy wiring structure having a total plane area smaller than a total plane area of the first electrode pad. Item 3. The semiconductor wafer according to Item 1 or 2.   The semiconductor wafer according to claim 1, wherein the first electrode pad is formed in a lowermost wiring layer of the plurality of wiring layers.   The semiconductor wafer according to claim 1, wherein the second electrode pad is formed on an uppermost wiring layer of the plurality of wiring layers.   The semiconductor wafer according to claim 1, wherein the second electrode pad is formed outside a seal ring formed at a peripheral portion of the semiconductor chip.   The second electrode pad is formed on the inner side of a seal ring formed at a peripheral portion of the semiconductor chip, and the first electrode pad and the second electrode pad form a conductive layer below the seal ring. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is conducted through the semiconductor wafer.

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