JP2012235069A - Method of manufacturing optical integrated element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing an optical integrated element which can suppress a drop from a design value of characteristics of a passive element.SOLUTION: An active region for forming an active element which is formed by a semiconductor laminate structure including an active core layer, and a passive region for forming a passive element which is formed by a semiconductor laminate structure including a passive core layer are formed on a substrate. A first etching mask having a coating part and an opening part is formed in each of the active region and the passive region. Dry etching is performed via the opening part in each of the active region and the passive region, thereby forming an active mesa structure of the active element in the active region, and a passive mesa structure of the passive element in the passive region. A second etching mask is formed in the passive region, and the active mesa structure is subjected to wet etching while protecting the passive mesa structure with the second etching mask.

Description

  The present invention relates to a method for manufacturing an optical integrated device in which an active device and a passive device are integrated.

  For example, as a functional optical integrated device for optical communication, an active device composed of an active waveguide having a semiconductor active layer as a core layer and a semiconductor passive waveguide having a substantially transparent passive semiconductor layer as a core layer. There is an optical integrated device that monolithically integrates a configured passive device. As an example of this type of optical integrated device, an integrated semiconductor laser device is disclosed as a wavelength variable light source for DWDM (Dense Wavelength Division Multiplexing) optical communication (see, for example, Patent Document 1).

  This type of integrated semiconductor laser device includes a plurality of distributed feedback (DFB) type semiconductor lasers having different oscillation wavelengths, a plurality of bent optical waveguides, an optical combiner, and a semiconductor optical amplifier (SOA: Semiconductor). Optical Amplifier) is integrated on a single substrate.

  The operation of this integrated semiconductor laser device will be described. First, one DFB laser selected from the DFB lasers is driven. The bent optical waveguide optically connected to the driving DFB laser guides the laser beam output from the driving DFB laser. For example, an optical combiner composed of a multimode interference (MMI) optical waveguide passes laser light guided by a bent optical waveguide and outputs it from an output port. The semiconductor optical amplifier amplifies the laser beam output from the output port and outputs it from its output end. This integrated semiconductor laser element operates as a wavelength tunable light source by changing the DFB laser to be driven.

  In the integrated semiconductor laser element as described above, a semiconductor optical modulator as an external modulator may be further provided on the output end side of the semiconductor optical amplifier. In this case, the integrated semiconductor laser device is used as an optical transmitter for long-distance optical transmission in, for example, a DWDM optical communication network system. In this integrated semiconductor laser element, the bending waveguide and the optical combiner correspond to a passive element. In addition, semiconductor lasers, semiconductor optical amplifiers, and semiconductor optical modulators, which are other elements, correspond to active elements.

  As another example of an optical integrated device, there is an integrated semiconductor optical amplifier device in which a semiconductor optical amplifier and a spot size converter (SSC) are integrated (see, for example, Patent Document 2). The spot size converter is for coupling a semiconductor optical amplifier and an optical fiber or a planar lightwave circuit (PLC) with low loss. In this type of integrated semiconductor optical amplifier, the spot size converter corresponds to a passive element, and the semiconductor optical amplifier corresponds to an active element.

JP 2003-258368 A JP 2001-135877 A

  By the way, in the case of forming a conventional buried type semiconductor waveguide, first, a mesa structure of the semiconductor waveguide is formed by dry etching, and then a damaged layer by dry etching is removed by wet etching, and then the semiconductor material is used. Mesa structure may be embedded. When the mesa structure is formed by dry etching, the side wall thereof is perpendicular to the semiconductor lamination surface, so that the bottom surface and the side wall subjected to dry etching form a corner. The wet etching after the dry etching also has an effect of smoothing the corners so that the portion can be filled without a gap when the portion is filled with the semiconductor material.

  However, when an optical integrated device including a buried semiconductor waveguide is formed by dry etching and subsequent wet etching as described above, the characteristics of the passive device may be lower than the design value. For example, in the case of a spot size converter, the coupling loss may be larger than the design value, in the case of an optical combiner, the coupling loss and wavelength characteristics of the design value may not be obtained, and in the case of a bent optical waveguide There was a problem that the bending loss might be larger than the design value.

  The present invention has been made in view of the above, and an object of the present invention is to provide a method of manufacturing an optical integrated device that can suppress a decrease in the characteristic of a passive device from a design value.

  In order to solve the above-described problems and achieve the object, an optical integrated device manufacturing method according to the present invention is an optical integrated device manufacturing method in which an active device and a passive device are integrated. An active region for forming the active element formed with a semiconductor multilayer structure including a core layer and a passive region for forming the passive element formed with a semiconductor multilayer structure including a passive core layer are formed. Forming a first etching mask having a covering portion and an opening in the active region and the passive region, performing dry etching from the opening in the active region and the passive region, and forming the active region in the active region; An active mesa structure of the element is formed, and a passive mesa structure of the passive element is formed in the passive region. Forming a said second etching mask is formed passive region, wet etching the active mesa structure while protecting the Passhibumesa structure in the second etching mask, characterized in that it comprises.

  In the method for manufacturing an optical integrated device according to the present invention, a difference is formed between the etching depth of the dry etching in the passive region and the etching depth of the dry etching in the active region. The dry etching is performed, and the wet etching is performed so that the etching depth of the wet etching becomes substantially the difference.

  The method for manufacturing an optical integrated device according to the present invention is the method for manufacturing an optical integrated device according to the above invention, wherein the second coverage of the first etching mask in the passive region is higher than the first coverage of the first etching mask in the active region. The etching depth difference is formed by increasing the etching depth.

  The method for manufacturing an optical integrated device according to the present invention is characterized in that, in the above invention, the first coverage is 0% to 20%, and the second coverage is 70% to 100%. To do.

  The method for manufacturing an optical integrated device according to the present invention is characterized in that, in the above invention, an etch stop layer is formed between the substrate, the active core layer, and the passive core layer.

  According to the present invention, in the wet etching process, the mesa structure of the passive element is protected, thereby preventing a change in the shape of the passive core layer due to the wet etching. Play.

FIG. 1 is a schematic plan view of an integrated semiconductor optical amplifying element that can be manufactured by the manufacturing method according to the first embodiment. FIG. 2 is a perspective view for explaining the waveguide structure of the integrated semiconductor optical amplifier shown in FIG. 3 is a cross-sectional view of the main part of the integrated semiconductor optical amplifying element shown in FIG. 4 is a cross-sectional view of the main part of the integrated semiconductor optical amplifying element shown in FIG. FIG. 5 is a cross-sectional view of the main part of the integrated semiconductor optical amplifier shown in FIG. FIG. 6 is a diagram for explaining the manufacturing method according to the first embodiment. FIG. 7 is a diagram for explaining the manufacturing method according to the first embodiment. FIG. 8 is a diagram for explaining the manufacturing method according to the first embodiment. FIG. 9 is a diagram for explaining the manufacturing method according to the first embodiment. FIG. 10 is a diagram for explaining the manufacturing method according to the first embodiment. FIG. 11 is a diagram for explaining the manufacturing method according to the first embodiment. FIG. 12 is a diagram for explaining the manufacturing method according to the first embodiment. FIG. 13 is a diagram illustrating an example of the relationship between the width of the light input / output end of the spot size converter and the coupling loss between the spot size converter and the PLC. FIG. 14 is a diagram illustrating an example of the relationship between the etching mask coverage and the etching rate when dry etching is performed on the semiconductor layer on which the etching mask is formed using ICP-RIE. FIG. 15 is a schematic cross-sectional view of a semiconductor optical amplifier of an integrated semiconductor optical amplifier device according to a modification of the first embodiment. FIG. 16 is a schematic cross-sectional view of a spot size converter of an integrated semiconductor optical amplifier device according to a modification of the first embodiment. FIG. 17 is a schematic plan view of an integrated semiconductor laser device that can be manufactured by the manufacturing method according to the first embodiment. FIG. 18 is a diagram showing the relationship between the bending radius and bending loss of the bent optical waveguide according to the first embodiment and the conventional manufacturing method.

  Embodiments of a method for manufacturing an optical integrated device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Moreover, in each drawing, the same code | symbol is attached | subjected suitably to the same or corresponding component. Furthermore, it should be noted that the drawings are schematic, and the relationship between the thickness and width of each layer, the ratio of each layer, and the like may differ from the actual ones. Even between the drawings, there are cases in which portions having different dimensional relationships and ratios are included.

(Embodiment 1)
First, an integrated semiconductor optical amplifying element that is an optical integrated element that can be manufactured by the manufacturing method according to the first embodiment of the present invention will be described. FIG. 1 is a schematic plan view of an integrated semiconductor optical amplifying element that can be manufactured by the manufacturing method according to the first embodiment. As shown in FIG. 1, the integrated semiconductor optical amplifying element 100 includes a spot size converter 10, a semiconductor optical amplifier 20, and a spot size converter 30 that are sequentially connected. The spot size converter 10 which is a passive element is formed in the passive region S1. Similarly, the semiconductor optical amplifier 20 which is an active element is formed in the active region S2. The spot size converter 30 which is a passive element is formed in the passive region S3. The integrated semiconductor optical amplifying element 100 receives a 1.55 μm band signal light from the light input / output end 11 side of the spot size converter 10 and amplifies the signal light by the semiconductor optical amplifier 20 to produce a spot. The size converter 30 is configured to output from the light input / output end 31 side. For the input / output of signal light, for example, an optical fiber or a PLC is connected to the spot size converters 10 and 30. The signal light may be input from the light input / output end 31 side of the spot size converter 30.

  FIG. 2 is a perspective view for explaining the waveguide structure of the integrated semiconductor optical amplifier device 100 shown in FIG. As shown in FIG. 2, the spot size converter 10 includes a so-called tapered passive core layer 114 in which both the width and the thickness decrease from the side connected to the semiconductor optical amplifier 20 toward the optical input / output end 11. It is out. Similarly, the spot size converter 30 includes a tapered passive core layer whose width and thickness decrease from the side connected to the semiconductor optical amplifier 20 toward the optical input / output end 31. Since the passive core layer is a taper type, the spot size converters 10 and 30 can be connected to an optical fiber or a PLC with low loss.

  The semiconductor optical amplifier 20 has, for example, a waveguide structure having a length of 2000 μm, a width of 2 μm and an equal width. Further, the spot size converters 10 and 30 have a length of, for example, 500 μm, and the width changes from 2 μm to 0.5 μm in the longitudinal direction.

  Next, a cross-sectional structure of the integrated semiconductor optical amplifier device 100 will be described. FIG. 3 is a cross-sectional view of the main part of the integrated semiconductor optical amplifier 100 taken along the line AA. FIG. 4 is a cross-sectional view of the main part of the integrated semiconductor optical amplifier 100 taken along the line BB. FIG. 5 is a cross-sectional view of the main part of the integrated semiconductor optical amplifier 100 taken along the line CC.

  First, the cross-sectional structure of the semiconductor optical amplifier 20 will be described with reference to FIG. The semiconductor optical amplifier 20 includes an n-type InP lower clad layer 103 that also serves as a buffer layer on an n-type InP substrate 102 having an n-side electrode 101 formed on the back surface, and an active core layer 104. And an upper clad layer 105 made of p-type InP are sequentially stacked. From the upper part of the substrate 102 to the upper clad layer 105 has a mesa structure M1. Both sides of the mesa structure M1 are buried with a buried semiconductor layer 106 made of a lower current blocking semiconductor layer 106a made of p-type InP and an upper current blocking semiconductor layer 106b made of n-type InP. Therefore, the semiconductor optical amplifier 20 has a buried mesa structure.

  On the upper cladding layer 105 and the buried semiconductor layer 106, an upper cladding layer 107 made of p-type InP and a contact layer 108 made of p-type InGaAsP are sequentially stacked. A p-side electrode 109 is formed on the contact layer 108 so as to cover the active core layer 104. Note that a protective film made of SiN, for example, may be formed in a region on the contact layer 108 where the p-side electrode 109 is not formed.

  The active core layer 104 is made of an InGaAsP material, and has a MQW layer 104a having a multi quantum well (MQW) structure and a three-stage separated confinement heterostructure (SCH) formed so as to sandwich the MQW 104a. Layers 104b and 104c. Thus, the active core layer 104 has an MQW-SCH structure. The MQW layer 104a has a so-called 6QW structure in which, for example, six well layers having a thickness of 6 nm and barrier layers having a thickness of 10 nm are alternately stacked. However, the structure of the active core layer 104 is not particularly limited, and may be a single quantum well structure or a bulk structure.

  The mesa structure M1 including the active core layer 104 of the semiconductor optical amplifier 20 has a substantially trapezoidal cross section due to side etching by wet etching described later. The thickness of the active core layer 104 is t1, and ½ of the difference between the lower base and the upper base of the trapezoid is d1. Hereinafter, d1 is referred to as a side etch depth.

  Next, the sectional structure of the spot size converter 10 will be described with reference to FIG. The spot size converter 10 has a semiconductor laminated structure in which a lower clad layer 103, a passive core layer 114, and an upper clad layer 115 made of undoped InP are laminated on a substrate 102 having an n-side electrode 101 formed on the back surface. Have. The upper part of the substrate 102 to the upper cladding layer 115 has a mesa structure M2. Both sides of the mesa structure M2 are buried with a buried semiconductor layer 106 including a lower current blocking semiconductor layer 106a and an upper current blocking semiconductor layer 106b. Therefore, the spot size converter 10 has an embedded mesa structure.

  An upper cladding layer 107 and a contact layer 108 are sequentially stacked on the upper cladding layer 115 and the buried semiconductor layer 106. For example, a protective film made of SiN may be formed on the contact layer 108.

  The passive core layer 114 is made of an InGaAsP material having a band gap wavelength of 1.3 μm. Therefore, the passive core layer 114 does not absorb the input signal light in the 1.55 μm band and mainly guides the signal light.

  Note that the mesa structure M2 including the passive core layer 114 of the spot size converter 10 is hardly side-etched by dry etching described later, and thus has a trapezoidal cross section. Similar to the active core layer 104, the passive core layer 114 has a thickness t2. The side etch depth is d2. d2 is almost a value close to 0 μm.

  The spot size converter 30 has the same cross-sectional structure as the spot size converter 10.

  Further, as shown in FIG. 5, in the spot size converters 10 and 30, the thickness of the passive core layer 114 decreases from the side connected to the semiconductor optical amplifier 20 toward the optical input / output end face. The spot size converter 10, the semiconductor optical amplifier 20, and the spot size converter 30 are monolithically integrated on a common substrate 102.

  Next, a manufacturing method of the integrated semiconductor optical amplifying element 100 will be described with reference to a plan view or a cross-sectional view corresponding to a cross section taken along line AA, BB, or CC in FIG. First, as shown in the cross-sectional view of FIG. 6, using a known crystal growth apparatus such as a MOCVD (Metal Organic Chemical Vapor Deposition) crystal growth apparatus, a lower clad layer 103, an active core layer 104, an upper part are formed on a substrate 102. The cladding layer 105 is crystallized sequentially.

  Next, as shown in the plan view of FIG. 7, a mask M10 made of, for example, SiN for forming the structure of the spot size converters 10 and 30 is formed on the upper cladding layer 105. In FIG. 7, only the region corresponding to the right half of the integrated semiconductor optical amplifier device 100 in FIG. 1 is shown for simplification. The mask M10 covers the both sides of the region S4 where the semiconductor optical amplifier 20 is formed, the region S5 where the spot size converter 30 is formed, and both sides of the region (not shown) where the spot size converter 10 is formed. Form.

  In order to grow a semiconductor layer whose thickness varies along the longitudinal direction in a region where the spot size converters 10 and 30 are formed, masks M10 on both sides of the region where the spot size converters 10 and 30 are formed are The mask width changes along the longitudinal direction.

  Next, dry etching and wet etching are sequentially performed using the mask M10 as an etching mask, and the upper cladding layer 105 and the active layer core 104 in a region other than the region where the mask M10 is formed are removed. The wet etching can be performed using, for example, an etching solution of hydrochloric acid: phosphoric acid = 1: 3. The dry etching is performed by using, for example, reactive ion etching (RIE) by inductively coupled plasma (IPC) using chlorine gas or electron cyclotron resonance (ECR). be able to. The sectional view of FIG. 8 shows a state after etching.

  Next, using the mask M10 as a growth mask, a passive core layer 114 and an upper cladding layer 115 are sequentially formed in a region where the upper cladding layer 105 and the active layer core 104 are removed by a selective growth (SAG) method. Butt joint grows. In the region where the spot size converters 10 and 30 are formed, more semiconductor material is supplied to the region where the width of the mask M10 on both sides thereof is wider, so that the thickness is increased along the longitudinal direction as shown in FIG. A decreasing passive core layer 114 and an upper cladding layer 115 are formed. Thereafter, the mask M10 is removed.

  Next, as shown in FIG. 10, masks M21, M22, and M23 as first etching masks made of, for example, SiN are formed in the active region S2 and the passive regions S1 and S3 (see FIG. 1). Each of the masks M21, M22, and M23 includes openings M21a, M22a, and M23a, and other covering portions M21b, M21c, M22b, M22c, M23b, and M23c. FIG. 10 shows a region where one integrated semiconductor optical amplifier is formed. Since a large number of integrated semiconductor optical amplifier elements are actually formed on the substrate 102, a similar integrated semiconductor optical amplifier element forming region exists adjacent to the region shown in FIG.

  The covering portions M21c, M22c, and M23c are masks corresponding to the mesa structures M1 and M2 in FIGS. The openings M21a, M22a, and M23a correspond to regions where the buried semiconductor layer 106 shown in FIGS. Here, the total area of the two openings M21a and the total area of the two openings M23a are set equal to A1, and the total area is set to A2 smaller than the total area of the two openings M22a. The reason will be explained later.

  Next, dry etching is performed from the openings M21a, M22a, and M23a of the masks M21, M22, and M23 in the active region S2 and the passive regions S1 and S3. The dry etching can be performed using, for example, RIE by IPC or ECR using a chlorine-based gas. As a result, a substantially rectangular mesa structure M2 in the passive region S1 as shown in FIG. 11A and a substantially rectangular mesa structure M3 in the active region S2 as shown in FIG. 11B are formed. Trench grooves T1 and T2 corresponding to the openings M21a (M23a) and M22a are formed on both sides of the mesa structures M1 and M3. Here, as described above, by setting the total areas A1 and A2 of the openings to be different from each other, even in the same dry etching process, the passive regions S1 and S3 are more trenches than the active region S2. The etching depth of the groove is increased by a predetermined difference d.

  Next, as shown in FIG. 12A, a mask M30 as a second etching mask is formed in the passive regions S1 and S3. Then, wet etching is performed while protecting the mesa structure M2 in the passive regions S1 and S3. The wet etching can be performed using, for example, a chlorine-based etching solution. Then, only the active region S2 is wet etched. At this time, the damage layer by dry etching of the mesa structure M3 is removed by side etching, and the trapezoidal mesa structure M1 shown in FIGS. 3 and 12B is formed. By removing the damaged layer, the reliability of the active core layer 104 is improved.

  Here, the etching depth of this wet etching is made substantially the same as the etching depth difference d described above. As a result, the total etching depth by dry etching and wet etching becomes substantially equal in the passive regions S1 and S3 and the active region S2.

  That is, in the manufacturing method according to the first embodiment, in the masks M21, M22, and M23, the passive regions S1 and S3 and the active region S2 are substantially equal in dry etching and wet etching. The total area A1, A2 of the opening (or the total area of the covering part in the masks M21, M22, M23) is set.

  Thereafter, the buried semiconductor layer 106 is crystal-grown in the trench grooves T1 and T2 on both sides of the mesa structures M1 and M2. In the mesa structure M1, the inner corner of the trench groove T2 is smoothed by wet etching, so that the buried semiconductor layer 106 can be filled without a gap. This improves the current blocking characteristics of the buried semiconductor layer 106 and suppresses the formation of a leakage current path. As a result, the reliability of the semiconductor optical amplifier 20 is increased. In order to form a good buried structure with good current blocking characteristics, it is preferable that the etching depth of wet etching (that is, the difference d in etching depth) is 0.5 μm or more.

  Further, as described above, the total etching depths by the dry etching and the wet etching are substantially equal in the passive regions S1 and S3 and the active region S2. As a result, since the height of the outermost surface of the formed embedded semiconductor layer 106 is substantially equal between the passive regions S1 and S3 and the active region S2, unevenness on the outermost surface is reduced. Accordingly, when a photolithography process is subsequently performed, the adhesion between the mask formed by photolithography and the outermost surface of the semiconductor layer is increased. As a result, the accuracy of photolithography is increased.

  Next, the upper cladding layer 107 and the contact layer 108 are crystal-grown. Next, a photolithography process and a vapor deposition / lift-off process are performed to form a p-side electrode 109 made of AuZn.

  Finally, the entire back surface of the substrate 102 is polished, an AuGeNi / Au film is deposited on the polished back surface to form the n-side electrode 101, and then sintered (sintered) at 430 ° C. for ohmic contact. Thereafter, element isolation is performed to complete the integrated semiconductor optical amplifying element 100.

  According to the above manufacturing method, the mesa structure M2 including the passive core layer 114 of the spot size converters 10 and 30 is integrated without performing wet etching while removing the damaged layer of the active core layer 104 by wet etching. Type semiconductor optical amplifying element 100 can be manufactured. Thereby, the shape of the spot size converters 10 and 30, particularly the width at the light input / output ends 11 and 31 can be formed with high accuracy. As a result, it is possible to suppress deterioration of the characteristics of the spot size converters 10 and 30, for example, characteristics such as connection loss with the PLC.

  This will be specifically described below. When wet etching is performed, the mesa structure is side-etched, so that it may be difficult to manufacture by adjusting the mesa width strictly as designed. In the case of active elements such as semiconductor lasers, semiconductor optical amplifiers, and semiconductor optical modulators, the mesa width dependency of the laser characteristics, optical amplification characteristics, or optical modulation characteristics is small. Its characteristics are almost unchanged.

  On the other hand, in the case of passive elements such as an MMI optical combiner, a bent waveguide, and a spot size converter, the characteristics are sensitive to changes in the mesa width of the optical waveguide. For example, FIG. 13 is a diagram illustrating an example of the relationship between the mesa width of the light input / output end of the spot size converter and the coupling loss between the spot size converter and the PLC. The spot size converter has a length of 500 μm and a mesa width that decreases from 2.0 μm to the value on the horizontal axis in FIG. On the other hand, the PLC connected to the light input / output terminal of the spot size converter has a relative refractive index difference of 1.2% relative to the cladding and a core size of 10 μm × 10 μm.

  In FIG. 13, when the mesa width is 0.5 μm, the connection loss becomes a substantially minimum value. However, when wet etching is performed on the mesa structure of the spot size converter, even if the mesa width at the light input / output end is set to 0.5 μm, the mesa width can be reduced to about 0.2 μm by wet etching. . As a result, the connection loss may increase by 6 dB to 7 dB. In addition, in the case of wet etching, the mesa structure becomes trapezoidal due to the effect of side etching, which may further increase the connection loss.

  On the other hand, when only dry etching is performed on the mesa structure of the spot size converter without performing wet etching as in the first embodiment, the mesa structure is substantially rectangular and the mesa width is The manufacturing error is suppressed to about ± 0.1 μm with respect to the designed value of 0.5 μm. As a result, the connection loss is suppressed to an increase of about 1 dB at most as shown in FIG.

  As described above, according to the manufacturing method according to the first embodiment, it is possible to manufacture the integrated semiconductor optical amplifying element 100 in which the deterioration of the characteristics of the spot size converters 10 and 30 is suppressed.

  Next, a method for making the total etching depth equal in the passive regions S1 and S3 and the active region S2 will be described more specifically.

  In the case of dry etching using RIE by ICP or ECR, the etching rate greatly depends on the coverage of the etching mask. Here, the coverage means the ratio of the area of the region (covering portion) where the mask is formed in the region to the total area of the predetermined region. The higher the coverage, that is, the smaller the area of the opening, the faster the etching rate because the etching gas supplied to the predetermined region concentrates in the opening. Therefore, the coverage of the masks M21 and M23 may be increased in the passive regions S1 and S3 where the etching depth of dry etching is desired to be deeper.

FIG. 14 is a diagram illustrating an example of the relationship between the etching mask coverage and the etching rate when dry etching is performed on the semiconductor layer on which the etching mask is formed using ICP-RIE. The semiconductor layer is made of InP, and the etching mask is made of SiN. The ICP-RIE conditions were ICP power of 200 W, bias power of 50 W, gas pressure of 0.45 Pa, Cl ₂ gas flow rate of 15 sccm, and Ar gas flow rate of 15 sccm.

As shown in FIG. 14, the coverage and the rate are approximately proportional, and the following equation (1) is substantially established.
Etch rate (μm / min) = 0.026 × coverage (%) + 0.4481 (1)

  Therefore, by adjusting the coverage from 0% to 100%, an etch rate difference of up to 1.58 times can be provided between the two regions.

  For example, in FIG. 11, by the same dry etching, the etching depth of the trench groove T1 in the passive region S1 is 2.4 μm, the etching depth of the trench groove T2 in the active region S2 is 1.9 μm, and the subsequent active region S2 Assume that wet etching with an etching depth of 0.5 μm is performed. In this case, the coverage of the active region S2 (first coating) so that (passive region S1 etch rate) / (active region S2 etch rate) is 1.263 (= 2.4 / 1.9). Rate) and the coverage of the passive region S1 (second coverage) may be set. For example, under the conditions shown in FIG. 14, the first coverage may be 20% and the second coverage may be 70%. As a result, the etching depth difference d (depth etched by wet etching) can be set to 0.5 μm. If the first coverage is 0% to 20% and the second coverage is 70% to 100%, the difference d can be 0.5 μm or more.

Further, in FIG. 10, the width of the two covering portions M22b located on both sides of the cover portion M22c in the active region S2 and W _{mask _ active,} two covering portions located on opposite sides of the cover portion M21c a passive region S1, S3 M21b, and both the width of the two covering portions M23b located on both sides of the cover portion M23c is W _{mask _ passive,} the chip interval (the width of one element forming region) and Wchip, the length of the passive region S1, S3 Is L _SSC , the length of the active region S 2 is L _SOA , the width of the covering portions M 21 c and M 23 c on the covering portion M 22 c side is W _{SSC 1} , and the width on the light input / output end face side is W _{SSC 2} . At this time, the second coverage (%) in the passive regions S1 and S3 can be expressed by the following equation (2).

100 × (1/2 × ( W SSC1 + W SSC2) × L SSC + 2 × W _{mask _ passive × L SSC) / (W chip} × L SSC) ··· (2)

  Further, the first coverage ratio (%) in the active region S2 can be expressed by the following formula (3).

100 × (W _SOA × L _SOA + 2 × W _{mask_active} × L _SOA ) / (W _chip × L _SOA ) (3)

Therefore, the parameters included in each equation, particularly W _{mask_active} and W _{mask_passive,} may be set using equations (2) and (3) so as to obtain a desired coverage.

As shown in FIG. 10, W _SOA is set _wider than W _SSC1 by the amount of side etching by wet etching (W _{WET depth} ).

Here, W _SOA is preferably a range in which single mode transmission is performed for light in a wavelength band to be used in an optical communication wavelength band (850 nm to 1630 nm). For example, in the case of the 1.55 _μm band, W _SSC1 may be 2.0 _μm to 6.0 μm. L _SOA is preferably 500 μm to 3000 μm. If L _SOA is 500 μm or more, a net gain can be obtained in the semiconductor optical amplifier 20. Moreover, if it is 3000 micrometers or less, it will be suppressed that the output and the noise figure of the semiconductor optical amplifier 20 fall by the influence of a waveguide loss. Further, (W _SSC1 −W _SSC2 ) / L _SSC <1.5 / 500 is preferable because the waveguide loss in the spot size converters 10 and 30 can be reduced.

Further, as described above, by adjusting the coverage from 0% to 100%, it is possible to provide a maximum etch rate difference of 1.58 times between the two regions. Therefore, it is preferable that the relationship of the following formula (4) is satisfied with respect to the depth of dry etching and the depth of wet etching in the active region S2.
{(Dry etching depth) + (Wet etching depth)} / (Dry etching depth) ≦ 1.58 (4)

  In the first embodiment, the total etching depth is made equal in the passive regions S1 and S3 and the active region S2 by adjusting the coverage ratio of the etching mask during dry etching. However, an etch stop layer may be provided as in the following modification of the first embodiment so that the passive regions S1, S3 and the active region S2 have the same etching depth after wet etching.

  FIG. 15 is a schematic cross-sectional view of the semiconductor optical amplifier 20A of the integrated semiconductor optical amplifying element 100A according to the modification of the first embodiment. FIG. 15 is a cross-sectional view of the active region S2 corresponding to FIG. FIG. 16 is a schematic cross-sectional view of a spot size converter 10A of the integrated semiconductor optical amplifier device 100A according to a modification of the first embodiment. FIG. 16 is a cross-sectional view of the passive region S1 corresponding to FIG.

  The integrated semiconductor optical amplifying device 100 according to the first embodiment and the integrated semiconductor optical amplifying device 100A according to the modified example have substantially the same configuration except for the presence or absence of an etch stop layer. Hereinafter, the etch stop layer will be described.

  As shown in FIGS. 15 and 16, the etch stop layer 120 is provided between the substrate 102 and the lower cladding layer 103. The etch stop layer 120 is made of a material that allows the wet etchant to be used to selectively etch the lower cladding layer 103 and hardly etch the etch stop layer 120. Therefore, the etch stop layer 120 is made of InGaAsP, for example.

  When manufacturing the integrated semiconductor optical amplifying element 100A, the etching is stopped immediately above the etch stop layer 120 in the dry etching for forming the mesa structure. Thereafter, when wet etching is performed, the wet etching proceeds only in the width direction because of the etch stop layer 120. As a result, the etching depths after the wet etching are equal in the passive regions S1 and S3 and the active region S2.

  The position where the etch stop layer 120 is formed is not limited to the position between the substrate 102 and the lower cladding layer 103, and may be between the active core layer 104 and the passive core layer 114 and the substrate 102.

  Next, an integrated semiconductor laser element that is another optical integrated element that can be manufactured by the manufacturing method according to the first embodiment will be described. FIG. 17 is a schematic plan view of an integrated semiconductor laser device that can be manufactured by the manufacturing method according to the first embodiment.

  As shown in FIG. 17, the integrated semiconductor laser device 200 includes a plurality of DFB semiconductor lasers 40-1 to 40-n (n is an integer of 2 or more) having different oscillation wavelengths, and a semiconductor laser 40-1. To 40-n, a plurality of bent optical waveguides 50-1 to 50-n, an MMI type optical combiner 60 connected to the bent optical waveguides 50-1 to 50-n, and an MMI type optical combiner 60. The semiconductor optical amplifier 70 connected to the semiconductor optical amplifier 80 and the semiconductor optical modulator 80 connected to the semiconductor optical amplifier 70 are monolithically integrated.

  The semiconductor lasers 40-1 to 40-n are active elements formed in the active region S6. The bent optical waveguides 50-1 to 50-n and the MMI type optical combiner 60 are passive elements formed in the passive region S7. The semiconductor optical amplifier 70 and the semiconductor optical modulator 80 are active elements formed in the active region S8.

  The semiconductor optical amplifier 70 and the semiconductor optical modulator 80 have the same cross-sectional structure as the semiconductor optical amplifier 20 shown in FIG. The semiconductor lasers 40-1 to 40-n have substantially the same cross-sectional structure as the semiconductor optical amplifier 20, except that a diffraction grating layer is formed on a part of the upper cladding layer 105. The bent optical waveguides 50-1 to 50-n and the MMI type optical combiner 60 have the same cross-sectional structure as the spot size converter 10 shown in FIG. The mesa width of the MMI type optical combiner 60 is set so as to generate multimode interference.

  This integrated semiconductor laser device 200 is also formed by performing dry etching and wet etching on the active regions S6 and S8 and performing only dry etching on the passive region S7 in accordance with the manufacturing method according to the first embodiment. The reliability of the active element is increased, and the deterioration of the characteristics of the bent optical waveguides 50-1 to 50-n, which are passive elements, and the MMI type optical combiner 60 is suppressed. For example, in the case of the bent optical waveguides 50-1 to 50-n, an increase in bending loss is suppressed. In the case of the MMI type optical combiner 60, the increase of the coupling loss and the deterioration of the wavelength characteristics are suppressed.

  Here, the relationship between the bending loss generated in the bent optical waveguide and the cross-sectional structure of the optical waveguide will be described. In a bent optical waveguide, bending loss increases when the cross-sectional structure of the waveguide becomes trapezoidal due to side etching such as wet etching. In particular, when the ratio of the side etch depth to the core layer thickness is greater than 167%, the bending loss increases rapidly.

  For example, a curved optical waveguide having a rectangular cross-section of the passive core layer manufactured according to the first embodiment, and a bent optical waveguide manufactured according to a conventional manufacturing method and having a trapezoidal cross-section of the passive core layer by side etching, Compare the bending loss. Here, the passive core layer is made of an InGaAsP material having a band gap wavelength of 1.3 μm, and the periphery of the passive core layer is surrounded by a cladding layer made of InP and a buried semiconductor layer. The rectangular passive core layer has a thickness of 0.3 μm and a width of 2.0 μm. The thickness of the trapezoidal passive core layer is 0.3 μm, the width of the lower base is 2.0 μm, and the width of the upper base is 1.5 μm.

  FIG. 18 is a diagram showing the relationship between the bending radius and bending loss of the bent optical waveguide according to the first embodiment and the conventional manufacturing method. The unit (dB / turn) of the bending loss means a bending loss per turn when a case where the waveguide is bent 360 ° with a predetermined bending radius is defined as one turn.

  As shown in FIG. 18, the bending waveguide manufactured according to the first embodiment has a bending loss smaller than that according to the conventional manufacturing method. The reason for this is considered that the bending loss is increased because the cross section of the passive core layer is trapezoidal in the case of the conventional manufacturing method.

  In the first embodiment, the active core layer of the active element has a trapezoidal mesa structure by wet etching. However, if the optical waveguide of the active element is linear and the ratio of the side etch depth to the thickness of the active core layer is 167% or more and 467% or less, the deterioration of the characteristics hardly causes a problem.

  In the optical amplifying device according to the above embodiment, the material, size, etc. of the compound semiconductor and electrodes are set for the 1.55 μm band. However, each material, size, and the like can be appropriately set according to the wavelength of light to be amplified within the optical communication wavelength band, and are not particularly limited.

  In the above embodiment, the optical waveguide has a buried mesa structure, but may have a high mesa structure. The high mesa structure means a structure in which the mesa structure is not embedded with a material having a refractive index close to that of the semiconductor layer or the core layer.

  Moreover, what comprised each component of said each embodiment suitably was also included in this invention. For example, an etch stop layer may be formed when the integrated semiconductor laser device shown in FIG. 17 is manufactured. In addition, other embodiments, examples, operational techniques, and the like made by those skilled in the art based on the above-described embodiments are all included in the present invention.

10, 10A, 30 Spot size converter 11, 31 Optical input / output terminals 20, 20A, 70 Semiconductor optical amplifier 40 Semiconductor laser 50 Curved optical waveguide 60 MMI optical combiner 80 Semiconductor optical modulator 100, 100A Integrated semiconductor optical amplification Element 101 N-side electrode 102 Substrate 103 Lower clad layer 104 Active core layer 104a MQW layer 104b, 104c SCH layers 105, 107, 115 Upper clad layer 106 Embedded semiconductor layer 106a Lower current blocking semiconductor layer 106b Upper current blocking semiconductor layer 108 Contact layer 109 p-side electrode 114 passive core layer 120 etch stop layer M1, M2, M3 mesa structure M10, M21, M22, M23, M30 mask M21a, M22a, M23a openings M21b, M22b, M23b, M21c, 22c, M23c covering portion S1, S3, S7 passive region S2, S6, S8 active region S4, S5 regions T1, T2 trench

Claims (5)

A method of manufacturing an optical integrated device in which an active device and a passive device are integrated,
An active region for forming the active element formed with a semiconductor multilayer structure including an active core layer and a passive element formed with a semiconductor multilayer structure including a passive core layer are formed on a substrate. Forming a passive region,
Forming a first etching mask having a covering portion and an opening in the active region and the passive region;
Performing dry etching from the opening in the active region and the passive region, forming an active mesa structure of the active element in the active region and forming a passive mesa structure of the passive device in the passive region;
Forming a second etching mask in the passive region;
Wet etching the active mesa structure while protecting the passive mesa structure with the second etching mask;
The manufacturing method of the optical integrated element characterized by the above-mentioned.   The dry etching is performed such that a difference is formed between the etching depth of the dry etching in the passive region and the etching depth of the dry etching in the active region, and the etching depth of the wet etching is substantially the difference. The method of manufacturing an optical integrated device according to claim 1, wherein the wet etching is performed as described above.   The etching depth difference is formed by making the second coverage of the first etching mask in the passive region larger than the first coverage of the first etching mask in the active region. Item 3. A method for manufacturing an optical integrated device according to Item 2.   4. The method of manufacturing an optical integrated device according to claim 3, wherein the first coverage is 0% to 20%, and the second coverage is 70% to 100%.   2. The method of manufacturing an optical integrated device according to claim 1, wherein an etch stop layer is formed between the substrate and the active core layer and the passive core layer.

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