JP2012231071A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

A dual metal gate structure capable of obtaining an appropriate threshold voltage Vt for further miniaturization is realized.
A gate electrode 120b includes a first metal-containing film 114b having a first work function, and a second metal having a second work function formed on the first metal-containing film 114b. Containing film 117b. The gate electrode 120a does not include the first metal-containing film 114 and includes the second metal-containing film 117a. A diffusion prevention layer 115b is formed between the first metal-containing film 114b and the second metal-containing film 117b in the gate electrode 120b.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate electrode including a metal-containing film and a manufacturing method thereof.

  In recent years, as semiconductor integrated circuit devices become highly integrated, highly functional, and speeded up, metal-insulator-semiconductor field-effect transistors (MISFETs) have been miniaturized. ing.

  On the other hand, if the gate insulating film is made thinner with the miniaturization of the MISFET, the influence of the increase in the gate leakage current due to the tunnel phenomenon or the depletion of the polysilicon gate electrode becomes remarkable, and the on-current is secured. As a result, it becomes difficult to maintain or improve the operation speed of the MISFET.

In order to solve this problem, instead of a conventional silicon oxide film, an insulating film having a higher dielectric constant such as a hafnium oxide film (HfO ₂ ) (high dielectric constant insulating film (high-k film)) is used as a gate insulating film. ) And at least a portion of the gate electrode in contact with the gate insulating film is considered to be replaced with a metal-containing material from polysilicon. This reduces the equivalent oxide thickness (EOT) while increasing the physical thickness of the gate insulating film, and reduces the inversion layer thickness (Tinv In other words, it is expected to reduce the electrical thickness of the gate insulating film, where the equivalent oxide thickness EOT is different from that of silicon oxide. The film thickness value obtained by converting the film thickness of the dielectric film having a relative dielectric constant of silicon oxide.

  One of the most important issues in realizing a transistor using the aforementioned high dielectric constant gate insulating film and metal-containing gate electrode is to obtain an appropriate threshold voltage Vt. For this purpose, a p-channel metal-containing film having a work function close to the valence band of Si (5.15 eV) is used in the gate electrode structure of the p-channel MISFET, and the Si conduction band is used in the gate electrode structure of the n-channel MISFET. It is necessary to realize a structure using an n-channel metal-containing film having a work function close to (4.05 eV), that is, a dual metal gate structure.

  Hereinafter, the structure disclosed in Patent Document 1 will be described as an example of a conventional dual metal gate structure. FIGS. 7A to 7E and FIGS. 8A to 8C are diagrams showing respective steps of the conventional method for manufacturing a semiconductor device disclosed in Patent Document 1. FIG.

  First, as shown in FIG. 7A, an element isolation region 2 made of shallow trench isolation (STI) is selectively formed on a semiconductor substrate 1 made of silicon (Si). Subsequently, by ion implantation, a p-type well region 3a is formed in an n-channel MISFET formation region (hereinafter referred to as an NMIS region), and an n-type well is formed in a p-channel MISFET formation region (hereinafter referred to as a PMIS region). Region 3b is formed. Subsequently, a high dielectric constant insulating film 5 is formed on the surface of the semiconductor substrate 1 via a base film 4, and then a p-channel metal-containing film 6 is formed on the high dielectric constant insulating film 5.

  Next, as shown in FIG. 7B, after forming a mask pattern 7 that covers the PMIS region, the mask pattern 7 is used to form a portion of the p located in the NMIS region as shown in FIG. 7C. The channel metal-containing film 6 is removed by etching back, and then the mask pattern 7 is removed. Next, as shown in FIG. 7D, the n-channel metal-containing film is formed on the high dielectric constant insulating film 5 in the portion of the NMIS region and on the p-channel metal-containing film 6 remaining in the PMIS region. 8 is formed.

  Next, as shown in FIG. 7E, after a conductive film 9 is formed on the n-channel metal-containing film 8, a mask pattern 10 is formed to cover the gate electrode formation regions of the NMIS region and the PMIS region. Next, the conductive film 9, the n-channel metal-containing film 8 and the p-channel metal-containing film 6 are sequentially patterned by dry etching using the mask pattern 10 as shown in FIG. 10 is removed. As a result, an n-channel gate electrode 12a composed of an n-channel metal-containing film 8a and a conductive film 9a is formed in the NMIS region, and a p-channel metal-containing film 6b and an n-channel metal are formed in the PMIS region. A p-channel gate electrode 12b made of the containing film 8b and the conductive film 9b is formed. At this time, the base film 4 and the high dielectric constant insulating film 5 located outside the n-channel gate electrode 12a and the p-channel gate electrode 12b are removed, and the semiconductor substrate 1 and the n-channel gate electrode 12a are removed. A gate insulating film 11a composed of the base film 4a and the high dielectric constant insulating film 5a is formed between the base film 4b and the high dielectric constant insulating film between the semiconductor substrate 1 and the p-channel gate electrode 12b. A gate insulating film 11b made of the film 5b is formed.

  Next, as shown in FIG. 8B, n-type extension regions 13a are formed on both sides of the n-channel gate electrode 12a in the semiconductor substrate 1 by ion implantation, and the p-channel gate electrode 12b in the semiconductor substrate 1 is formed. A p-type extension region 13b is formed on both sides of the substrate. Next, as shown in FIG. 8C, after forming the insulating sidewall spacers 14a and 14b on the side surfaces of the n-channel gate electrode 12a and the p-channel gate electrode 12b, an ion implantation method is used. The n-type source / drain regions 15a are formed on both sides of the n-channel gate electrode 12a and the insulating sidewall spacer 14a in the semiconductor substrate 1, and the p-channel gate electrode 12b and the insulating sidewall spacer 14b in the semiconductor substrate 1 are formed. P-type source / drain regions 15b are formed on both sides.

  As described above, according to the conventional semiconductor device having the dual metal gate structure, the gate electrode having the n-channel metal-containing film is formed on the high dielectric constant gate insulating film in the NMIS region, and the PMIS region. In FIG. 1, a gate electrode having a p-channel metal-containing film is formed on a high dielectric constant gate insulating film.

US Pat. No. 7,657,791 US Pat. No. 6,794,234

K. Mistry et al., A 45nm Logic Technology with High-k + Metal gate Transitors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging, IEDM2007, p.247-250

  However, the conventional semiconductor device having a dual metal gate structure has a problem that an appropriate threshold voltage Vt cannot be obtained with miniaturization.

  In view of the above, an object of the present invention is to realize a dual metal gate structure capable of obtaining an appropriate threshold voltage Vt for further miniaturization.

  In order to achieve the above-mentioned object, the inventors of the present application have examined the cause of the failure to obtain an appropriate threshold voltage Vt with miniaturization in the conventional dual metal gate structure, and obtained the following knowledge.

  According to the prior art shown in FIGS. 7A to 7E and FIGS. 8A to 8C, the PMISFET gate electrode metal-containing film (p-channel metal-containing film 6) is subjected to gate patterning. The portion formed in the NMIS region is removed by etch back. On the other hand, the NMISFET gate electrode metal-containing film (n-channel metal-containing film 8) is formed in the PMIS region until gate patterning for the purpose of reducing process damage and simplifying the process. Is left. Therefore, the gate electrode (p-channel gate electrode 12b) of the PMISFET has a laminated structure of the p-channel metal-containing film 6b and the n-channel metal-containing film 8b. Here, in the above-described prior art, the effective work function of the p-channel gate electrode 12b is substantially determined by the p-channel metal-containing film 6b positioned closer to the gate insulating film 11b. In other words, it is assumed that the n-channel metal-containing film 8b located away from the gate insulating film 11b does not substantially affect the effective work function of the p-channel gate electrode 12b. The “effective work function” is a work function obtained from the electrical characteristics of the MISFET, and is a physical work function indicating a difference between a vacuum level and a metal energy level, a level in an insulating film, and the like. This means that taking into account the effects of.

  However, in practice, the gate electrode structure is exposed to a high-temperature process at 1000 ° C. or higher in a process such as activation heat treatment of impurities (impurities contained in the source / drain regions) after gate patterning. As a result, as shown in FIG. 9, in the p-channel gate electrode 12b, an interface reaction occurs in the laminated structure of the p-channel metal-containing film 6b and the n-channel metal-containing film 8b, and an alloyed layer (alloyed) is formed. Layer 20) may be formed. Depending on the degree of generation of the alloyed layer, the effective work function of the gate electrode metal-containing film (p-channel metal-containing film 6 b) located in the lower layer deviates from a desired value. As a result, an appropriate threshold voltage Vt cannot be obtained in a conventional semiconductor device having a dual metal gate structure.

  In the prior art shown in FIGS. 7A to 7E and FIGS. 8A to 8C, if the thickness of the p-channel metal-containing film 6b is sufficiently increased, the alloyed layer described above is used. Although the influence of (alloyed layer 20) can be suppressed, in this case, another problem arises in that the process load in selective etch-back and gate patterning of p-channel metal-containing film 6b increases.

  Further, Patent Document 2 proposes a configuration that uses a work function after an alloying reaction using an interfacial alloying reaction in a laminated structure of different types of gate electrode metal-containing films similar to Patent Document 1. Yes. However, in the technique disclosed in Patent Document 2, there are practical problems that there are few options for metal materials that can use the work function after the alloying reaction, and it is difficult to control the alloying reaction itself. For this reason, there is a possibility of causing the same problem as in Patent Document 1.

  Non-Patent Document 1 discloses the formation of a dual metal gate structure using a gate last method instead of the gate-first method as in Patent Documents 1 and 2. When the gate last method is used, since the source / drain regions can be formed before the gate electrode is formed, the main thermal load in the process after the gate electrode is formed is about 420 to 430 ° C. As compared with the case where the gate first method is used as in Patent Documents 1 and 2, there is a possibility that an undesirable alloying reaction in a laminated structure of different metal-containing films for gate electrodes can be suppressed. However, for example, when a metal material such as aluminum is used, metal diffusion and alloying occur even if the sintering heat load. In the gate last method, a laminated structure of different kinds of metal-containing films is embedded in a recess formed by removing a dummy gate electrode made of polysilicon or the like. Therefore, it is necessary to reduce the thickness of each gate electrode metal-containing film that determines the work function to about 10 nm or less, for example. As a result, if the interfacial alloying reaction in the laminated structure of different types of gate electrode metal-containing films cannot be sufficiently suppressed, the thickness of the lower gate electrode metal-containing film is, for example, about 5 nm due to the formation of the alloyed layer. As a result, the desired work function cannot be obtained.

  As described above, in order to achieve the object of the present invention, that is, to realize a dual metal gate structure capable of obtaining an appropriate threshold voltage Vt even for further miniaturization, the gate first method and Regardless of which gate last method is used, an interfacial alloy in a stacked structure of different types of gate electrode metal-containing films (a stacked structure of a p-channel metal-containing film and an n-channel metal-containing film) that determines the work function. It is extremely important to suppress the chemical reaction as much as possible.

  The present invention has been made on the basis of the above knowledge, and the gist of the present invention is a laminated structure of metal-containing films for different types of gate electrodes for determining a work function (a metal-containing film for p-channel and a metal-containing film for n-channel). A diffusion preventing layer for preventing metal diffusion between the metal-containing films in the laminated structure. As a result, even for further miniaturization, a desired work function can be obtained by suppressing the interfacial alloying reaction in the laminated structure of the different metal-containing films for gate electrodes, so that an appropriate threshold voltage Vt can be obtained. A dual metal gate structure can be realized. When forming the diffusion prevention layer, in particular, in order to avoid complication of the process, an increase in the thickness of the gate electrode caused by newly forming the diffusion prevention layer itself, an influence on the work function, etc. In order to suppress as much as possible, it is preferable to modify the surface of the lower-layer metal-containing film for a gate electrode or to modify the interface between different types of metal-containing films for a gate electrode. In addition to film deposition, for example, heat treatment, plasma treatment, ion implantation, or the like can be used as the modification means. Moreover, as an effective diffusion preventing layer material, for example, a metal oxide, a metal nitride, or a metal oxynitride can be used.

  Specifically, a semiconductor device according to the present invention is a semiconductor device including a first conductivity type MISFET having a first gate electrode and a second conductivity type MISFET having a second gate electrode on a semiconductor substrate. The first gate electrode includes a first metal-containing film having a first work function, and a second metal layer formed on the first metal-containing film and having a second work function. And the second gate electrode does not include the first metal-containing film and includes the second metal-containing film, and the first metal-containing film in the first gate electrode. And a diffusion preventing layer is formed between the second metal-containing film.

  The diffusion prevention layer is preferably a conductive layer from the viewpoint of reducing the resistance of the gate electrode, but may be an extremely thin (for example, about 2 nm or less) insulating layer that generates a tunnel effect. Even if the diffusion preventing layer is a conductive layer, from the viewpoint of miniaturization (especially when the gate last method is used), the thickness of the diffusion preventing layer is preferably about 5 nm or less. From the viewpoint of resistance reduction, the thickness of the diffusion preventing layer is more preferably about 2 nm or less.

  In the semiconductor device according to the present invention, the diffusion prevention layer may be made of an oxide, nitride or oxynitride of a material constituting the first metal-containing film.

  In the semiconductor device according to the present invention, the first conductivity type MISFET is a p-channel MISFET, the second conductivity type MISFET is an n-channel MISFET, and the first metal-containing film includes Ti, Ta, W, or Ni. And the second metal-containing film is one metal selected from the group of metals including Hf, Zr, Ti, Ta, and Al, and the group of metals. May be composed of an alloy of two or more metals selected from among the above, or a nitride or carbide of the one metal or the alloy. Here, the diffusion preventing layer may be made of an oxide containing Ti or Ta. The first metal-containing film may be made of a metal nitride containing W or Ni, or a noble metal, and the diffusion prevention layer may be made of a metal nitride containing Ti or Ta. The first metal-containing film may be composed of a noble metal, and the diffusion prevention layer may be composed of a noble metal oxide, nitride, or oxynitride. The first metal-containing film is made of a metal nitride containing Ti, Ta, W or Ni, and the diffusion prevention layer is made of a metal oxynitride containing Ti, Ta, W or Ni. May be.

  In the semiconductor device according to the present invention, the first conductivity type MISFET is an n-channel MISFET, the second conductivity type MISFET is a p-channel MISFET, and the first metal-containing film includes Hf, Zr, Ti, Ta And one metal selected from a metal group including Al, an alloy of two or more metals selected from the metal group, or a nitride or carbide of the one metal or the alloy. The second metal-containing film may be made of a metal nitride containing Ti, Ta, W or Ni, or a noble metal. Here, the diffusion preventing layer may be made of an oxide containing Ti or Ta. Further, the first metal-containing film is formed of one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, and two or more metals selected from the metal group. It is made of an alloy, or a nitride of the one metal or the alloy (excluding nitrides of Ti or Ta) or carbide, and the diffusion prevention layer is made of a metal nitride containing Ti or Ta. May be. Further, the first metal-containing film is formed of one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, and two or more metals selected from the metal group. The diffusion prevention layer is made of an oxide, a nitride, or an oxynitride of a material constituting the first metal-containing film, the alloy, or the one metal or the carbide of the alloy. Also good. The first metal-containing film may be one metal nitride selected from a metal group including Hf, Zr, Ti, Ta, and Al, or two selected from the metal group. It is comprised from the nitride of the above metal alloy, The said diffusion prevention layer may be comprised from the oxide of the material which comprises a said 1st metal containing film | membrane.

  In the semiconductor device according to the present invention, a gate insulating film including a high dielectric constant insulating film may be formed under each of the first gate electrode and the second gate electrode. Here, the gate insulating film may be formed under the high dielectric constant insulating film and may include a base film made of a silicon oxide film.

  In the semiconductor device according to the present invention, each of the first gate electrode and the second gate electrode may include a conductive film formed on the second metal-containing film.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: a first conductive MISFET having a first gate electrode; and a second conductive MISFET having a second gate electrode on a semiconductor substrate. In the manufacturing method, the step (a) of forming a first metal-containing film having a first work function on the formation region of the first conductivity type MISFET in the semiconductor substrate; and the step (a) Later, a step of forming a second metal-containing film having a second work function on the first metal-containing film and on the formation region of the second conductivity type MISFET in the semiconductor substrate ( b) and after the step (b), the first metal-containing film and the second metal-containing film are patterned to include the first metal-containing film and the second metal-containing film. The first gate electrode; And (c) forming the second gate electrode not including the first metal-containing film and including the second metal-containing film, and the steps (a) and (c) (D) further forming a diffusion prevention layer interposed between the first metal-containing film and the second metal-containing film in the first gate electrode.

  In the method for manufacturing a semiconductor device according to the present invention, in the step (d), the diffusion prevention layer may be formed by modifying a surface portion of the first metal-containing film. Here, the step (d) is performed before the step (b), and in the step (d), the first step is performed by heat treatment or plasma treatment in an atmosphere containing at least one of oxygen and nitrogen. The surface portion of the metal-containing film may be modified. The step (a) includes the step (a1) of forming the first metal-containing film on the respective formation regions of the first conductivity type MISFET and the second conductivity type MISFET in the semiconductor substrate. And after the step (a1), a step (a2) of selectively removing the portion of the first metal-containing film formed on the formation region of the second conductivity type MISFET. (D) is carried out between the step (a1) and the step (a2), and in the step (d), on the respective formation regions of the first conductivity type MISFET and the second conductivity type MISFET. The diffusion preventing layer is formed by modifying the surface portion of the first metal-containing film formed in the step (a2), and is formed on the formation region of the second conductivity type MISFET in the step (a2). Partial The serial diffusion preventing layer may be selectively removed. Alternatively, the step (d) is performed after the step (b), and the surface portion of the first metal-containing film is modified by ion implantation of at least one of oxygen and nitrogen in the step (d). You may quality.

  In the method for manufacturing a semiconductor device according to the present invention, the step (d) is performed before the step (b), and the diffusion prevention is performed on the first metal-containing film in the step (d). A layer may be deposited. Here, the step (a) is a step (a1) of forming the first metal-containing film on the respective formation regions of the first conductivity type MISFET and the second conductivity type MISFET in the semiconductor substrate. And after the step (a1), a step (a2) of selectively removing a portion of the first metal-containing film formed on the formation region of the second conductivity type MISFET, The step (d) is performed between the step (a1) and the step (a2). In the step (d), each of the formation regions of the first conductivity type MISFET and the second conductivity type MISFET is formed. The diffusion preventing layer is formed on the first metal-containing film formed thereon, and in the step (a2), the portion of the diffusion formed on the formation region of the second conductivity type MISFET Select prevention layer It may be removed. In the case where the diffusion prevention layer is formed by film formation, the thickness of the diffusion prevention layer is preferably about 1 nm or more from the viewpoint of preventing the occurrence of pinholes.

  In the method of manufacturing a semiconductor device according to the present invention, the first gate electrode and the second gate electrode may be formed using a gate last method.

  According to the present invention, it is possible to realize a dual metal gate structure capable of obtaining an appropriate threshold voltage Vt for further miniaturization.

FIGS. 1A to 1F are cross-sectional views illustrating respective steps of the method for manufacturing a semiconductor device according to the first embodiment. 2A to 2E are cross-sectional views illustrating the respective steps of the semiconductor device manufacturing method according to the first embodiment. FIGS. 3A to 3C are cross-sectional views illustrating respective steps of the method for manufacturing the semiconductor device according to the modification of the first embodiment. 4A to 4E are cross-sectional views illustrating the respective steps of the semiconductor device manufacturing method according to the second embodiment. FIG. 5A to FIG. 5D are cross-sectional views illustrating respective steps of the method for manufacturing a semiconductor device according to the second embodiment. 6A to 6D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a modification of the second embodiment. 7A to 7E are diagrams for explaining each process of the conventional method for manufacturing a semiconductor device. 8A to 8C are diagrams for explaining each process of the conventional method for manufacturing a semiconductor device. FIG. 9 is a diagram for explaining a problem of a conventional semiconductor device.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. FIGS. 1A to 1F and FIGS. 2A to 2E are cross-sectional views illustrating respective steps of the method of manufacturing a semiconductor device according to the first embodiment.

First, as shown in FIG. 1A, an n-channel is formed by selectively forming an element isolation region 102 having, for example, a shallow trench isolation (STI) structure on a substrate 100 made of, for example, silicon (Si). A MISFET formation region (hereinafter referred to as an NMIS region) and a p-channel MISFET formation region (hereinafter referred to as a PMIS region) are partitioned. Subsequently, the p-type well region 103a is formed in the substrate 100 in the NMIS region, and the n-type well region 103b is formed in the substrate 100 in the PMIS region, for example, by ion implantation. Subsequently, for example, a known standard RCA cleaning and diluted hydrofluoric acid (HF) cleaning are sequentially performed on the surface of the substrate 100, and then the temperature of the substrate 100 on which the surface is cleaned is, for example, 600 ° C. to 600 ° C. Heat treatment is performed in an oxygen atmosphere at about 1000 ° C. Thereby, an insulating film having a thickness of about 1 to 3 nm made of, for example, a silicon oxide film (SiO ₂ film) is formed on the substrate 100 in the NMIS region and the PMIS region (that is, a complementary metal-insulator-semiconductor (CMIS) device forming region). 104 is formed. Here, the insulating film 104 made of, for example, a chemical silicon oxide film or an ISSG (In Situ Steam Generation) film may be formed by using, for example, a wet process. Next, a dummy gate electrode film 105 made of, for example, amorphous silicon having a thickness of, for example, about 60 to 80 nm corresponding to a desired gate electrode height is deposited on the insulating film 104. Subsequently, a mask pattern 106 made of, for example, a hard mask material or a resist material and covering the gate electrode formation regions of the NMIS region and the PMIS region is formed on the dummy gate electrode film 105 using a lithography technique.

Next, the dummy gate electrode film 105 is patterned as shown in FIG. 1B by performing dry etching or wet etching using, for example, chlorine (Cl ₂ ) gas or the like using the mask pattern 106, and then the mask pattern 106 is masked. The pattern 106 is removed. As a result, an n-channel dummy gate electrode 105a is formed in the NMIS region, and a p-channel dummy gate electrode 105b is formed in the PMIS region. At this time, portions of the insulating film 104 located outside the n-channel dummy gate electrode 105a and the p-channel dummy gate electrode 105b are removed, and a dummy is formed between the substrate 100 and the n-channel dummy gate electrode 105a. A gate insulating film 104a is formed, and a dummy gate insulating film 104b is formed between the substrate 100 and the p-channel dummy gate electrode 105b.

  Next, after forming offset spacers (not shown) on the side surfaces of the n-channel dummy gate electrode 105a and the p-channel dummy gate electrode 105b, as shown in FIG. The n-type extension regions 107a are formed on both sides of the n-channel dummy gate electrode 105a in the upper portion of the substrate 100, and the p-type extension regions 107b are formed on both sides of the p-channel dummy gate electrode 105b in the upper portion of the substrate 100.

  Next, as shown in FIG. 1 (d), an insulating property made of, for example, silicon nitride is provided on the side surfaces of the n-channel dummy gate electrode 105a and the p-channel dummy gate electrode 105b via the above-described offset spacers. Sidewall spacers 108a and 108b are formed. Thereafter, n-type source / drain regions 109a are formed on both sides of the n-channel dummy gate electrode 105a and the insulating sidewall spacer 108a in the upper portion of the substrate 100 by, for example, ion implantation, and the p-channel dummy in the upper portion of the substrate 100 is formed. P-type source / drain regions 109b are formed on both sides of the gate electrode 105b and the insulating sidewall spacer 108b. After that, for example, activation annealing is performed on the impurities implanted into the n-type extension region 107a and the p-type extension region 107b, and the n-type source / drain region 109a and the p-type source / drain region 109b at a temperature of 1000 ° C. or higher. I do. Thereby, the dummy gate transistor structure is completed.

  Thereafter, although not shown, after siliciding the surface portions of the n-type source / drain region 109a and the p-type source / drain region 109b, as shown in FIG. An interlayer insulating film 110 containing, for example, silicon oxide as a main component is deposited over the entire surface of the substrate 100 by the Chemical Vapor Deposition method. Subsequently, the deposited interlayer insulating film 110 is flattened or etched back by, for example, a CMP (Chemical Mechanical Polishing) method or a dry etching method, so that the n-channel dummy gate electrode 105a and the p-channel dummy gate electrode 105b. Expose the top surface of each.

Next, as shown in FIG. 1F, the n channel is formed by dry etching using an etching gas containing, for example, chlorine (Cl ₂ ) gas as a main component, or wet etching using, for example, tetraethyl ammonium hydroxide (TMAH). The dummy gate electrode 105a and the p-channel dummy gate electrode 105b are removed. Subsequently, the dummy gate insulating films 104a and 104b made of the silicon oxide film (SiO ₂ ) are removed by wet etching using, for example, hydrofluoric acid (HF). As a result, the dummy gate structure is removed to form a recess 111a having the insulating sidewall spacer 108a as the sidewall surface and the substrate 100 as the bottom surface, and the insulating sidewall spacer 108b as the sidewall surface and the substrate 100 as the bottom surface. A recess 111b is formed.

Next, as shown in FIG. 2A, a wet process using, for example, ozone oxidation is performed to form, for example, a silicon oxide film (SiO ₂ ) on the substrate 100 serving as the bottom surface of each of the recesses 111a and 111b. Base films 112a and 112b having a thickness of about 1 nm are formed. Here, for example, heat treatment may be used to form the base films 112a and 112b made of, for example, a silicon thermal oxide film or an ISSG film, but the base film 112a and 112b are formed after the silicidation process described above. The heat treatment temperature should not exceed 600 ° C. at the maximum. Next, on the entire surface of the substrate 100 including the base films 112a and 112b formed on the bottom surfaces of the recesses 111a and 111b, for example, using an ALD (Atomic Layer Deposition) method, for example, an insulating property is used. A high dielectric constant insulating film 113 made of metal oxide and having a thickness of about 3 nm is formed. Specifically, when a HfO ₂ film is formed as the high dielectric constant insulating film 113, for example, HfCl ₄ is used as the Hf raw material, H ₂ O is used as the oxidizing material, and the film forming temperature is set to 200 to 400 ° C. , HfCl ₄ supply, purge, H ₂ O supply and purge cycles are repeated to grow HfO ₂ at the atomic layer level, and a high dielectric constant insulating film made of an HfO ₂ film having a desired thickness 113 can be obtained.

  In order to configure a CMIS transistor, different gate electrodes having suitable work functions in the vicinity of band edges (valence band and conduction band) in each of the PMIS region and the NMIS region after the formation of the high dielectric constant insulating film 113 are formed. It is necessary to form metal-containing films for metal (p-channel metal-containing film and n-channel metal-containing film). Here, which of the p-channel metal-containing film and the n-channel metal-containing film is to be formed first should be determined in consideration of the selectivity during processing of each gate electrode material. In this embodiment, the case where the p-channel metal-containing film is formed first will be described as an example.

  After the formation of the high dielectric constant insulating film 113, as shown in FIG. 2A, a material having a work function suitable for the PMISFET, for example, a noble metal such as Pt, Pd, or Ru is formed on the high dielectric constant insulating film 113. Alternatively, a p-channel metal-containing film 114 made of a metal nitride containing Ti, Ta, W, or Ni and having a thickness of about several nanometers to several tens of nanometers is formed. When the recesses 111a and 111b have a high aspect ratio, the method for forming the p-channel metal-containing film 114 is, for example, an ALD method or a CVD method capable of conformal deposition, or good bottom coverage (that is, high coverage). A directional PVD (Physical Vapor Deposition) method or the like may be used.

  Subsequently, as shown in FIG. 2A, an alloying reaction between the p-channel metal-containing film 114 and an n-channel metal-containing film 117 described later (see FIG. 2C) is suppressed. Further, for example, the surface of the p-channel metal-containing film 114 is subjected to a modification process to form the diffusion prevention layer 115. The diffusion prevention layer 115 will be described in detail later. Thereafter, a mask pattern 116 covering the PMIS region is formed on the diffusion prevention layer 115.

  Next, as shown in FIG. 2B, the p-channel metal-containing film 114 and the diffusion prevention layer 115 located in the NMIS region are etched back and removed using the mask pattern 116, and then the mask is removed. The pattern 116 is removed. Next, as shown in FIG. 2C, the work function suitable for the NMISFET was provided on the portion of the high dielectric constant insulating film 113 located in the NMIS region and on the diffusion prevention layer 115 remaining in the PMIS region. One metal selected from a group of materials including, for example, Hf, Zr, Ti, Ta, and Al, an alloy of two or more metals selected from the group of metals, or the one metal Alternatively, an n-channel metal-containing film 117 made of nitride or carbide of the alloy and having a thickness of about several nm to several tens of nm is formed. When the recesses 111a and 111b have a high aspect ratio, the n-channel metal-containing film 117 can be formed by, for example, an ALD method or a CVD method capable of conformal deposition, or good bottom coverage (that is, high coverage). A directional PVD method or the like may be used.

  Next, as shown in FIG. 2D, a low-resistance material such as Al, Ti, W, or Cu is formed on the n-channel metal-containing film 117 so that the gaps of the recesses 111a and 111b are completely filled. A conductive film 118 made of metal is formed.

  Finally, as shown in FIG. 2 (e), portions of the conductive film 118, the n-channel metal-containing film 117, the diffusion prevention layer 115, the p-channel metal-containing film 114, and the high dielectric constant that protrude from the recesses 111a and 111b. The insulating film 113 is removed by, for example, planarization by a CMP method or etch back by a dry etching method. As a result, in the NMIS region, the n-channel is formed of the n-channel metal-containing film 117a and the conductive film 118a which is embedded in the recess 111a with the gate insulating film 119a formed of the base film 112a and the high dielectric constant insulating film 113a interposed therebetween. A gate electrode 120a is formed. In the PMIS region, the gate insulating film 119b composed of the base film 112b and the high dielectric constant insulating film 113b is sandwiched between the recesses 111b, and the p-channel metal-containing film 114b, the diffusion prevention layer 115b, and the n-channel use. A p-channel gate electrode 120b made of the metal-containing film 117b and the conductive film 118b is formed. That is, the basic structure of the gate last transistor is completed.

  As described above, according to the present embodiment, the diffusion prevention layer 115b is formed between the p-channel metal-containing film 114b and the n-channel metal-containing film 117b in the p-channel gate electrode 120b. For this reason, even when a thermal load is applied in a process such as sintering after the formation of the gate electrode, the alloying reaction between the p-channel metal-containing film 114b and the n-channel metal-containing film 117b is suppressed, and the desired reaction is achieved. Since a work function can be obtained, a dual metal gate structure capable of obtaining an appropriate threshold voltage Vt can be realized. In addition, since the gate last method is used in this embodiment, the impurity activation heat treatment accompanying the formation of the source / drain regions can be performed before the gate electrode is formed, thereby reducing the thermal load in the process after the gate electrode is formed. Thus, the alloying reaction described above can be further suppressed.

  In the present embodiment, the diffusion prevention layer 115 is preferably a conductive layer from the viewpoint of reducing the gate electrode resistance, but is an extremely thin (for example, about 2 nm or less) insulating layer that generates a tunnel effect. Also good. Even if the diffusion preventing layer 115 is a conductive layer, the thickness of the diffusion preventing layer 115 is about 5 nm or less from the viewpoint of miniaturization (particularly when the gate last method is used as in the present embodiment). From the viewpoint of reducing the gate electrode resistance, the thickness of the diffusion preventing layer 115 is more preferably about 2 nm or less. In particular, assuming the 20 nm generation and beyond, not only the thickness of the diffusion prevention layer 115 but also the thicknesses of the p-channel metal-containing film 114 and the n-channel metal-containing film 117 that determine the effective work function are several nm. It is desirable to suppress to the following extent.

  Further, as in this embodiment, the p-channel metal-containing film 114 is made of a noble metal such as Pt, Pd, or Ru, or a metal nitride containing Ti, Ta, W, or Ni, and the n-channel metal-containing film 117 is formed. One metal selected from a metal group including Hf, Zr, Ti, Ta and Al, an alloy of two or more metals selected from the metal group, or the one metal or the alloy When made of nitride or carbide, the diffusion prevention layer 115 may be made of an oxide containing Ti or Ta, for example. Alternatively, when the p-channel metal-containing film 114 is made of a noble metal such as Pt, Pd, or Ru, or a metal nitride containing W or Ni, the diffusion prevention layer 115 is made of a metal nitride containing Ti or Ta, for example. It may be. Alternatively, when the p-channel metal-containing film 114 is made of a noble metal such as Pt, Pd, or Ru, the diffusion prevention layer 115 is made of an oxide, nitride, or oxynitride of a noble metal such as Pt, Pd, or Ru. May be. Alternatively, when the p-channel metal-containing film 114 is made of a metal nitride containing Ti, Ta, W, or Ni, the diffusion prevention layer 115 is made of a metal oxynitride containing Ti, Ta, W, or Ni. Also good.

  In this embodiment, in order to form the diffusion preventing layer 115, for example, the surface modification of the p-channel metal-containing film 114 may be performed. As a specific method of surface modification, there is a method of performing heat treatment in an atmosphere containing at least one of elements having a diffusion preventing effect, for example, nitrogen and oxygen. When such a method is used, the diffusion prevention layer 115 made of an oxide, nitride or oxynitride of the material constituting the p-channel metal-containing film 114 is formed. Instead of the heat treatment in an atmosphere containing at least one of nitrogen and oxygen, the surface of the p-channel metal-containing film 114 may be exposed to plasma made of a gas containing at least one of nitrogen and oxygen, for example. When such a plasma treatment is performed, it is effective to perform the plasma treatment before forming the n-channel metal-containing film 117 shown in FIG.

  In this embodiment, the diffusion prevention layer 115 may be formed on the p-channel metal-containing film 114 without using the surface modification of the p-channel metal-containing film 114. For example, the diffusion prevention layer 115 may be formed by performing reactive sputtering in an atmosphere containing at least one of nitrogen and oxygen using a refractory metal target made of Ti or Ta. When forming the diffusion prevention layer 115, it is preferable that the thickness of the diffusion prevention layer 115 is about 1 nm or more from the viewpoint of preventing the generation of pinholes.

  In this embodiment, the diffusion prevention layer 115 is formed before the formation of the n-channel metal-containing film 117 shown in FIG. 2C. Instead, after the formation of the n-channel metal-containing film 117, For example, the diffusion prevention layer 115 may be formed by modifying the vicinity of the stacked interface between the p-channel metal-containing film 114 and the n-channel metal-containing film 117 by implanting at least one of nitrogen and oxygen. Good. In this case, since the diffusion prevention layer 115 can be formed not only near the upper surface (that is, the surface portion) of the p-channel metal-containing film 114 but also near the lower surface of the n-channel metal-containing film 117, the diffusion prevention effect can be obtained. It is effective to raise.

  Further, in this embodiment, as shown in FIGS. 2A to 2C, after the p-channel metal-containing film 114 is formed in the entire CMIS device formation region, the diffusion is performed on the p-channel metal-containing film 114. The prevention layer 115 was formed, and then the p-channel metal-containing film 114 and the diffusion prevention layer 115 located in the NMIS region were etched back and selectively removed. However, instead of this, as shown in FIGS. 3A to 3C, after forming the p-channel metal-containing film 114 over the entire CMIS device formation region, a mask pattern 116 covering the PMIS region is used. The portion of the p-channel metal-containing film 114 located in the NMIS region may be selectively removed by etching back, and then the diffusion prevention layer 115 may be formed on the remaining p-channel metal-containing film 114. Note that an optimal sequence may be selected according to the selectivity determined by the combination of the gate electrode materials, etc., for the context of the selective removal of the p-channel metal-containing film 114 and the formation of the diffusion prevention layer 115. Specifically, in the sequence shown in FIGS. 2A to 2C, the etching of the p-channel metal-containing film 114 and the diffusion prevention layer 115 is complicated, but the high dielectric constant of the portion located in the NMIS region is complicated. Damage to the insulating film 113 occurs only once due to the etching of the p-channel metal-containing film 114 and the diffusion prevention layer 115. On the other hand, in the sequence shown in FIGS. 3A to 3C, although the etching of the p-channel metal-containing film 114 is simplified, the damage to the high dielectric constant insulating film 113 in the portion located in the NMIS region is p. It occurs twice by etching the metal-containing film 114 for the channel and forming the diffusion prevention layer 115.

  In this embodiment, since the p-channel metal-containing film 114 is formed first, the p-channel gate electrode 120b has a stacked structure of the p-channel metal-containing film 114b and the n-channel metal-containing film 117b. Therefore, the diffusion prevention layer 115b is formed between the p-channel metal-containing film 114b and the n-channel metal-containing film 117b in the p-channel gate electrode 120b. However, instead of this, by forming the n-channel metal-containing film first, the n-channel gate electrode has a laminated structure of the n-channel metal-containing film and the p-channel metal-containing film. A diffusion prevention layer may be formed between the n-channel metal-containing film and the p-channel metal-containing film in the n-channel gate electrode. In this case, the n-channel metal-containing film is one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, and an alloy of two or more metals selected from the metal group Or when the p-channel metal-containing film is made of a noble metal such as Pt, Pd, or Ru, or a metal nitride containing Ti, Ta, W, or Ni. The diffusion prevention layer may be made of an oxide containing, for example, Ti or Ta. Alternatively, the n-channel metal-containing film is one metal selected from a metal group including Hf, Zr, Ti, Ta and Al, an alloy of two or more metals selected from the metal group, Alternatively, in the case of a nitride of the one metal or the alloy (except for a nitride of Ti or Ta) or a carbide, the diffusion prevention layer may be made of a metal nitride containing Ti or Ta, for example. Alternatively, the n-channel metal-containing film is one metal selected from a metal group including Hf, Zr, Ti, Ta and Al, an alloy of two or more metals selected from the metal group, Or when it consists of carbide | carbonized_material of said one metal or said alloy, the diffusion prevention layer may be comprised from the oxide, nitride, or oxynitride of the material which comprises the metal content film | membrane for n channels. Alternatively, the n-channel metal-containing film is a nitride of one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, or two or more selected from the metal group When made of a metal alloy nitride, the diffusion prevention layer may be made of an oxide of the material constituting the n-channel metal-containing film.

  In this embodiment, the p-channel metal-containing film 114 and the n-channel metal-containing film 117 may each include a work function adjusting layer. In this embodiment, the n-channel gate electrode 120a is composed of an n-channel metal-containing film 117a and a conductive film 118a, and the p-channel gate electrode 120b is composed of a p-channel metal-containing film 114b, a diffusion prevention layer 115b, n The channel metal-containing film 117b and the conductive film 118b are used. However, depending on the dimensions of the recesses 111a and 111b, at least the p-channel gate electrode 120b may not include the conductive film 118.

  In the present embodiment, in order to prevent an alloying reaction between the p-channel metal-containing film 114b and the n-channel metal-containing film 117b in the p-channel gate electrode 120b, A diffusion prevention layer 115b was formed between the n-channel metal-containing film 117b. However, when an alloying reaction may occur between the n-channel metal-containing film 117a and the conductive film 118a in the n-channel gate electrode 120a, the n-channel metal-containing film 117a and the conductive film 118a Needless to say, a diffusion preventing layer may be formed.

(Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment, MISFET formation is performed using the gate last method, whereas in this embodiment, MISFET formation is performed using the gate first method.

  FIGS. 4A to 4E and FIGS. 5A to 5D are cross-sectional views illustrating the respective steps of the semiconductor device manufacturing method according to the second embodiment.

First, as shown in FIG. 4A, an element isolation region 201 having, for example, a shallow trench isolation (STI) structure is selectively formed on an upper portion of a substrate 200 made of, for example, silicon (Si), thereby forming an n channel. A MISFET formation region (hereinafter referred to as an NMIS region) and a p-channel MISFET formation region (hereinafter referred to as a PMIS region) are partitioned. Subsequently, the p-type well region 202a is formed in the substrate 200 in the NMIS region, and the n-type well region 202b is formed in the substrate 200 in the PMIS region, for example, by ion implantation. Subsequently, for example, a known standard RCA cleaning and diluted hydrofluoric acid (HF) cleaning are sequentially performed on the surface of the substrate 200, and then the temperature of the substrate 200 on which the surface is cleaned is, for example, 600 ° C. Heat treatment is performed in an oxygen atmosphere at about 1000 ° C. Thereby, a base film 203 having a thickness of about 1 nm made of, for example, a silicon oxide film (SiO ₂ film) is formed on the substrate 200 in the NMIS region and the PMIS region (that is, the CMIS device forming region). Here, the base film 203 made of, for example, a chemical silicon oxide film or an ISSG film may be formed by using, for example, a wet process. Next, a high dielectric constant insulating film 204 made of, for example, an insulating metal oxide and having a thickness of about 3 nm is formed on the base film 203 using, for example, an ALD method. Specifically, for example, when an HfO ₂ film is formed as the high dielectric constant insulating film 204, HfCl ₄ is used as the Hf raw material, H ₂ O is used as the oxidizing material, and the film forming temperature is set to 200 to 400 ° C. , HfCl ₄ supply, purge, H ₂ O supply and purge cycles are repeated to grow HfO ₂ at the atomic layer level, and a high dielectric constant insulating film made of an HfO ₂ film having a desired thickness 204 can be obtained.

  To form a CMIS transistor, different gate electrodes having suitable work functions in the vicinity of band edges (valence band and conduction band) in each of the PMIS region and the NMIS region after the formation of the high dielectric constant insulating film 204 It is necessary to form metal-containing films for metal (p-channel metal-containing film and n-channel metal-containing film). Here, which of the p-channel metal-containing film and the n-channel metal-containing film is to be formed first should be determined in consideration of the selectivity during processing of each gate electrode material. In this embodiment, the case where the p-channel metal-containing film is formed first will be described as an example.

  After the formation of the high dielectric constant insulating film 204, as shown in FIG. 4A, on the high dielectric constant insulating film 204, a material having a work function suitable for PMISFET, for example, a noble metal such as Pt, Pd or Ru. Alternatively, a p-channel metal-containing film 205 made of metal nitride containing Ti, Ta, W, or Ni and having a thickness of about several nanometers to several tens of nanometers is formed.

  Next, as shown in FIG. 4B, a mask pattern 206 covering the PMIS region is formed on the p-channel metal-containing film 205, and then the mask pattern 206 is used to show the pattern shown in FIG. As described above, the portion of the p-channel metal-containing film 205 located in the NMIS region is removed by etching back, and then the mask pattern 206 is removed.

  Subsequently, as shown in FIG. 4D, an alloying reaction between the p-channel metal-containing film 205 and an n-channel metal-containing film 208 described later (see FIG. 4E) (particularly described later). In order to suppress an alloying reaction due to a high-temperature process such as impurity activation heat treatment accompanying the source / drain region formation, for example, the surface portion of the p-channel metal-containing film 205 is subjected to a modification process and diffused. The prevention layer 207 is formed. The diffusion prevention layer 207 will be described later in detail.

  Next, as shown in FIG. 4E, the work function suitable for the NMISFET was provided on the portion of the high dielectric constant insulating film 204 located in the NMIS region and on the diffusion prevention layer 207 located in the PMIS region. One metal selected from a group of materials including, for example, Hf, Zr, Ti, Ta, and Al, an alloy of two or more metals selected from the group of metals, or the one metal Alternatively, an n-channel metal-containing film 208 having a thickness of several nanometers to several tens of nanometers made of the nitride or carbide of the alloy is formed.

  Next, in order to lower the gate electrode resistance value to a desired value, as shown in FIG. 5A, on the n-channel metal-containing film 208, for example, conductive polysilicon, Ti, Ta, W, or A conductive film 209 having a thickness of about several tens of nanometers made of a metal such as Ni or a nitride of the metal is formed. Subsequently, a mask pattern 210 that covers the gate electrode formation regions of the NMIS region and the PMIS region is formed on the conductive film 209 by lithography, for example.

Next, by using the mask pattern 210, for example, dry etching or wet etching using an etching gas or the like mainly containing chlorine (Cl ₂ ) gas is performed, as shown in FIG. After the n-channel metal-containing film 208, the diffusion prevention layer 207, and the p-channel metal-containing film 205 are sequentially patterned, the mask pattern 210 is removed. Thereby, in the NMIS region, the n-channel gate electrode 212a composed of the n-channel metal-containing film 208a and the conductive film 209a is formed, and in the PMIS region, the p-channel metal-containing film 205b and the diffusion preventing layer 207b. Then, a p-channel gate electrode 212b composed of the n-channel metal-containing film 208b and the conductive film 209b is formed. At this time, portions of the base film 203 and the high dielectric constant insulating film 204 located outside the n-channel gate electrode 212a and the p-channel gate electrode 212b are removed, and the substrate 200 and the n-channel gate electrode 212a A gate insulating film 211a composed of a base film 203a and a high dielectric constant insulating film 204a is formed between the base film 203b and the high dielectric constant insulating film 204b between the substrate 200 and the p-channel gate electrode 212b. A gate insulating film 211b made of is formed.

  In order to maintain good processability and selectivity in the gate patterning step shown in FIG. 5B, the thickness of each of the p-channel metal-containing film 205, the diffusion prevention layer 207, and the n-channel metal-containing film 208 is determined. It is desirable to suppress the thickness to a minimum thickness that can realize a desired effective work function. In particular, assuming the 20 nm generation and beyond, the thicknesses of the p-channel metal-containing film 205, the diffusion prevention layer 207, and the n-channel metal-containing film 208 that determine the effective work function are suppressed to about several nm or less. Is desirable.

  Next, after forming offset spacers (not shown) on the side surfaces of the n-channel gate electrode 212a and the p-channel gate electrode 212b, as shown in FIG. An n-type extension region 213a is formed on both sides of the n-channel gate electrode 212a in the upper portion of the substrate 200, and a p-type extension region 213b is formed on both sides of the p-channel gate electrode 212b in the upper portion of the substrate 200.

  Next, as shown in FIG. 5D, an insulating sidewall made of, for example, silicon nitride is provided on each side surface of the n-channel gate electrode 212a and the p-channel gate electrode 212b via the above-described offset spacer. Spacers 214a and 214b are formed. Thereafter, n-type source / drain regions 215a are formed on both sides of the n-channel gate electrode 212a and the insulating sidewall spacer 214a in the upper portion of the substrate 200 by, for example, ion implantation, and the p-channel gate electrode in the upper portion of the substrate 200 is formed. A p-type source / drain region 215b is formed on both sides of 212b and the insulating sidewall spacer 214b. Thereafter, for example, activation annealing is performed on the impurities implanted into the n-type extension region 213a and the p-type extension region 213b, and the n-type source / drain region 215a and the p-type source / drain region 215b at a temperature of 1000 ° C. or higher. I do.

  Thereafter, although not shown in the drawings, the basic structure of the gate-first transistor is completed by silicidizing the surface portions of the n-type source / drain region 215a and the p-type source / drain region 215b.

  As described above, according to the present embodiment, the diffusion prevention layer 207b is formed between the p-channel metal-containing film 205b and the n-channel metal-containing film 208b in the p-channel gate electrode 212b. For this reason, even if a thermal load of, for example, 1000 ° C. or higher is applied in a process such as impurity activation heat treatment accompanying the formation of the source / drain regions after forming the gate electrode, the p-channel metal-containing film 205b and the n-channel metal-containing film are contained. Since a desired work function can be obtained by suppressing the alloying reaction with the film 208b, a dual metal gate structure capable of obtaining an appropriate threshold voltage Vt can be realized.

  In the present embodiment, the diffusion prevention layer 207 is preferably a conductive layer from the viewpoint of reducing the gate electrode resistance, but is an extremely thin (for example, about 2 nm or less) insulating layer that causes a tunnel effect. Also good. Even if the diffusion prevention layer 207 is a conductive layer, the thickness of the diffusion prevention layer 207 is preferably about 5 nm or less from the viewpoint of miniaturization, and from the viewpoint of reducing the gate electrode resistance, the diffusion prevention layer 207 is prevented. The thickness of the layer 207 is more preferably about 2 nm or less. In particular, assuming the 20 nm generation and beyond, not only the thickness of the diffusion prevention layer 207 but also the thicknesses of the p-channel metal-containing film 205 and the n-channel metal-containing film 208 that determine the effective work function are several nm. It is desirable to suppress to the following extent.

  Further, as in this embodiment, the p-channel metal-containing film 205 is made of a noble metal such as Pt, Pd, or Ru, or a metal nitride containing Ti, Ta, W, or Ni, and the n-channel metal-containing film 208 is formed. One metal selected from a metal group including Hf, Zr, Ti, Ta and Al, an alloy of two or more metals selected from the metal group, or the one metal or the alloy In the case of being made of nitride or carbide, the diffusion prevention layer 207 may be made of an oxide containing Ti or Ta, for example. Alternatively, when the p-channel metal-containing film 205 is made of a noble metal such as Pt, Pd, or Ru, or a metal nitride containing W or Ni, the diffusion prevention layer 207 is made of, for example, a metal nitride containing Ti or Ta. It may be. Alternatively, when the p-channel metal-containing film 205 is made of a noble metal such as Pt, Pd, or Ru, the diffusion prevention layer 207 is made of an oxide, nitride, or oxynitride of a noble metal such as Pt, Pd, or Ru. May be. Alternatively, when the p-channel metal-containing film 205 is made of a metal nitride containing Ti, Ta, W or Ni, the diffusion prevention layer 207 is made of a metal oxynitride containing Ti, Ta, W or Ni. Also good.

  In this embodiment, in order to form the diffusion prevention layer 207, for example, surface modification of the p-channel metal-containing film 205 may be performed. As a specific method of surface modification, there is a method of performing heat treatment in an atmosphere containing at least one of elements having a diffusion preventing effect, for example, nitrogen and oxygen. When such a method is used, the diffusion prevention layer 207 made of an oxide, nitride or oxynitride of the material constituting the p-channel metal-containing film 205 is formed. Instead of the heat treatment in an atmosphere containing at least one of nitrogen and oxygen, the surface of the p-channel metal-containing film 205 may be exposed to plasma made of a gas containing at least one of nitrogen and oxygen, for example. When such a plasma treatment is performed, it is effective to perform the plasma treatment before forming the n-channel metal-containing film 208 shown in FIG.

  In this embodiment, the diffusion prevention layer 207 may be formed on the p-channel metal-containing film 205 without using the surface modification of the p-channel metal-containing film 205. For example, the diffusion prevention layer 207 may be formed by performing reactive sputtering in an atmosphere containing at least one of nitrogen and oxygen using a refractory metal target made of Ti or Ta. When the diffusion prevention layer 207 is formed, the thickness of the diffusion prevention layer 207 is preferably about 1 nm or more from the viewpoint of preventing the occurrence of pinholes.

  In the present embodiment, the diffusion prevention layer 207 is formed before the formation of the n-channel metal-containing film 208 shown in FIG. 4E. Instead, after the formation of the n-channel metal-containing film 208, For example, the diffusion prevention layer 207 may be formed by modifying the vicinity of the stacked interface between the p-channel metal-containing film 205 and the n-channel metal-containing film 208 by implanting at least one of nitrogen and oxygen, for example. Good. In this case, the diffusion prevention layer 207 can be formed not only near the upper surface (that is, the surface portion) of the p-channel metal-containing film 205 but also near the lower surface of the n-channel metal-containing film 208. It is effective to raise.

  Further, in the present embodiment, as shown in FIGS. 4A to 4D, a p-channel metal-containing film 205 is formed over the entire CMIS device formation region, and then a mask pattern 206 that covers the PMIS region is used. The portion of the p-channel metal-containing film 205 located in the NMIS region was etched back and selectively removed, and then the diffusion prevention layer 207 was formed on the remaining p-channel metal-containing film 205. However, instead of this, as shown in FIGS. 6A to 6D, after the p-channel metal-containing film 205 is formed over the entire CMIS device formation region, diffusion prevention is performed on the p-channel metal-containing film 205. The layer 207 may be formed, and then the p-channel metal-containing film 205 and the diffusion prevention layer 207 located in the NMIS region may be selectively removed by etching back. Note that an optimal sequence may be selected according to the selectivity determined by the combination of the gate electrode materials, etc., as to the relationship between the selective removal of the p-channel metal-containing film 205 and the formation of the diffusion prevention layer 207. Specifically, in the sequence shown in FIGS. 4A to 4D, although the etching of the p-channel metal-containing film 205 is simplified, damage to the high dielectric constant insulating film 204 in the portion located in the NMIS region is simplified. Is generated twice by etching the p-channel metal-containing film 205 and forming the diffusion prevention layer 207. On the other hand, in the sequence shown in FIGS. 6A to 6D, although the etching of the p-channel metal-containing film 205 and the diffusion prevention layer 207 is complicated, the portion of the high-dielectric-constant insulating film 204 located in the NMIS region is complicated. Is caused only once by etching of the p-channel metal-containing film 205 and the diffusion prevention layer 207.

  In this embodiment, since the p-channel metal-containing film 205 is formed first, the p-channel gate electrode 212b has a stacked structure of the p-channel metal-containing film 205b and the n-channel metal-containing film 208b. Therefore, the diffusion prevention layer 207b is formed between the p-channel metal-containing film 205b and the n-channel metal-containing film 208b in the p-channel gate electrode 212b. However, instead of this, by forming the n-channel metal-containing film first, the n-channel gate electrode has a laminated structure of the n-channel metal-containing film and the p-channel metal-containing film. A diffusion prevention layer may be formed between the n-channel metal-containing film and the p-channel metal-containing film in the n-channel gate electrode. In this case, the n-channel metal-containing film is one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, and an alloy of two or more metals selected from the metal group Or when the p-channel metal-containing film is made of a noble metal such as Pt, Pd, or Ru, or a metal nitride containing Ti, Ta, W, or Ni. The diffusion prevention layer may be made of an oxide containing, for example, Ti or Ta. Alternatively, the n-channel metal-containing film is one metal selected from a metal group including Hf, Zr, Ti, Ta and Al, an alloy of two or more metals selected from the metal group, Alternatively, in the case of a nitride of the one metal or the alloy (except for a nitride of Ti or Ta) or a carbide, the diffusion prevention layer may be made of a metal nitride containing Ti or Ta, for example. Alternatively, the n-channel metal-containing film is one metal selected from a metal group including Hf, Zr, Ti, Ta and Al, an alloy of two or more metals selected from the metal group, Or when it consists of carbide | carbonized_material of said one metal or said alloy, the diffusion prevention layer may be comprised from the oxide, nitride, or oxynitride of the material which comprises the metal content film | membrane for n channels. Alternatively, the n-channel metal-containing film is a nitride of one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, or two or more selected from the metal group When made of a metal alloy nitride, the diffusion prevention layer may be made of an oxide of the material constituting the n-channel metal-containing film.

  In this embodiment, the p-channel metal-containing film 205 and the n-channel metal-containing film 208 may each include a work function adjusting layer. In the present embodiment, the n-channel gate electrode 212a is composed of the n-channel metal-containing film 208a and the conductive film 209a, and the p-channel gate electrode 212b is composed of the p-channel metal-containing film 205b, the diffusion prevention layer 207b, n Although the channel metal-containing film 208b and the conductive film 209b are included, at least the p-channel gate electrode 212b may not include the conductive film 209.

  In this embodiment, in order to prevent an alloying reaction between the p-channel metal-containing film 205b and the n-channel metal-containing film 208b in the p-channel gate electrode 212b, the p-channel metal-containing film 205b A diffusion prevention layer 207b was formed between the n-channel metal-containing film 207b. However, when an alloying reaction may occur between the n-channel metal-containing film 208a and the conductive film 209a in the n-channel gate electrode 212a, the n-channel metal-containing film 208a and the conductive film 209a Needless to say, a diffusion preventing layer may be formed.

  The present invention provides a semiconductor device having a gate electrode including a metal-containing film that determines a work function, and obtains a desired work function by suppressing an interface alloying reaction in a laminated structure of metal-containing films for different types of gate electrodes. It is possible to realize a CMIS type semiconductor device having an appropriate threshold voltage.

100 substrate 102 element isolation region 103a p-type well region 103b n-type well region 104 insulating film 104a, 104b dummy gate insulating film 105 dummy gate electrode film 105a n-channel dummy gate electrode 105b p-channel dummy gate electrode 106 mask pattern 107a n Type extension region 107b p type extension region 108a, 108b insulating sidewall spacer 109a n type source / drain region 109b p type source / drain region 110 interlayer insulating film 111a, 111b recess 112a, 112b base film 113, 113a, 113b high dielectric Insulating rate 114, 114b Metal film for p channel 115, 115b Diffusion prevention layer 116 Mask pattern 117, 117a, 117b For n channel Metal-containing film 118, 118a, 118b Conductive film 119a, 119b Gate insulating film 120a N-channel gate electrode 120b P-channel gate electrode 200 Substrate 201 Element isolation region 202a P-type well region 202b N-type well region 203, 203a, 203b Base film 204, 204a, 204b High dielectric constant insulating film 205, 205b Metal-containing film for p-channel 206 Mask pattern 207, 207b Diffusion prevention layer 208, 208a, 208b Metal-containing film for n-channel 209, 209a, 209b Conductive film 210 Mask pattern 211a, 211b Gate insulating film 212a n-channel gate electrode 212b p-channel gate electrode 213a n-type extension region 213b p-type extension region 214a, 214b Insulation Side wall spacer 215a n-type source / drain region 215b p-type source / drain region

Claims (23)

A semiconductor device comprising a first conductivity type MISFET having a first gate electrode and a second conductivity type MISFET having a second gate electrode on a semiconductor substrate,
The first gate electrode includes a first metal-containing film having a first work function, and a second metal-containing film formed on the first metal-containing film and having a second work function. Including
The second gate electrode does not include the first metal-containing film and includes the second metal-containing film,
A semiconductor device, wherein a diffusion prevention layer is formed between the first metal-containing film and the second metal-containing film in the first gate electrode. The semiconductor device according to claim 1,
The diffusion prevention layer is made of an oxide, nitride or oxynitride of a material constituting the first metal-containing film. The semiconductor device according to claim 1 or 2,
The first conductivity type MISFET is a p-channel MISFET,
The second conductivity type MISFET is an n-channel MISFET,
The first metal-containing film is made of a metal nitride containing Ti, Ta, W or Ni, or a noble metal,
The second metal-containing film includes one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, an alloy of two or more metals selected from the metal group, Alternatively, the semiconductor device is made of a nitride or carbide of the one metal or the alloy. The semiconductor device according to claim 3.
The diffusion preventing layer is made of an oxide containing Ti or Ta. The semiconductor device according to claim 3.
The first metal-containing film is made of a metal nitride containing W or Ni, or a noble metal,
The diffusion preventing layer is made of a metal nitride containing Ti or Ta. The semiconductor device according to claim 3.
The first metal-containing film is made of a noble metal,
The diffusion prevention layer is made of a noble metal oxide, nitride, or oxynitride. The semiconductor device according to claim 3.
The first metal-containing film is made of a metal nitride containing Ti, Ta, W or Ni,
The diffusion preventing layer is made of a metal oxynitride containing Ti, Ta, W, or Ni. The semiconductor device according to claim 1 or 2,
The first conductivity type MISFET is an n-channel MISFET,
The second conductivity type MISFET is a p-channel MISFET,
The first metal-containing film includes one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, an alloy of two or more metals selected from the metal group, Or consisting of a nitride or carbide of the one metal or the alloy,
The semiconductor device, wherein the second metal-containing film is made of a metal nitride containing Ti, Ta, W, or Ni, or a noble metal. The semiconductor device according to claim 8,
The diffusion preventing layer is made of an oxide containing Ti or Ta. The semiconductor device according to claim 8,
The first metal-containing film includes one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, an alloy of two or more metals selected from the metal group, Or a nitride (except for Ti or Ta nitride) or a carbide of the one metal or the alloy,
The diffusion preventing layer is made of a metal nitride containing Ti or Ta. The semiconductor device according to claim 8,
The first metal-containing film includes one metal selected from a metal group including Hf, Zr, Ti, Ta, and Al, an alloy of two or more metals selected from the metal group, Or a carbide of the one metal or the alloy,
The diffusion prevention layer is made of an oxide, nitride or oxynitride of a material constituting the first metal-containing film. The semiconductor device according to claim 8,
The first metal-containing film may be one metal nitride selected from a metal group including Hf, Zr, Ti, Ta, and Al, or two or more selected from the metal group. Made of metal alloy nitride,
The said diffusion prevention layer consists of an oxide of the material which comprises said 1st metal containing film | membrane, The semiconductor device characterized by the above-mentioned. The semiconductor device according to any one of claims 1 to 12,
A semiconductor device, wherein a gate insulating film including a high dielectric constant insulating film is formed under each of the first gate electrode and the second gate electrode. The semiconductor device according to claim 13,
The semiconductor device according to claim 1, wherein the gate insulating film is formed under the high dielectric constant insulating film and includes a base film made of a silicon oxide film. The semiconductor device according to claim 1,
Each of the first gate electrode and the second gate electrode includes a conductive film formed on the second metal-containing film. A method for manufacturing a semiconductor device comprising a first conductivity type MISFET having a first gate electrode and a second conductivity type MISFET having a second gate electrode on a semiconductor substrate,
Forming a first metal-containing film having a first work function on the formation region of the first conductivity type MISFET in the semiconductor substrate;
After the step (a), a second metal-containing film having a second work function on the first metal-containing film and on the formation region of the second conductivity type MISFET in the semiconductor substrate. Forming step (b);
After the step (b), the first metal-containing film and the second metal-containing film are patterned to include the first metal-containing film and the second metal-containing film. And (c) forming a gate electrode and the second gate electrode not including the first metal-containing film and including the second metal-containing film,
A diffusion prevention layer interposed between the first metal-containing film and the second metal-containing film in the first gate electrode is formed between the step (a) and the step (c). A method of manufacturing a semiconductor device, further comprising a step (d). In the manufacturing method of the semiconductor device according to claim 16,
In the step (d), the diffusion preventing layer is formed by modifying a surface portion of the first metal-containing film. In the manufacturing method of the semiconductor device according to claim 17,
The step (d) is performed before the step (b),
In the step (d), the surface portion of the first metal-containing film is modified by heat treatment or plasma treatment in an atmosphere containing at least one of oxygen and nitrogen. In the manufacturing method of the semiconductor device according to claim 18,
The step (a) includes the step (a1) of forming the first metal-containing film on the respective formation regions of the first conductivity type MISFET and the second conductivity type MISFET in the semiconductor substrate; A step (a2) of selectively removing a portion of the first metal-containing film formed on the formation region of the second conductivity type MISFET after the step (a1);
The step (d) is performed between the step (a1) and the step (a2),
In the step (d), the diffusion prevention is achieved by modifying the surface portion of the first metal-containing film formed on the respective formation regions of the first conductivity type MISFET and the second conductivity type MISFET. Forming a layer,
In the step (a2), a method of manufacturing a semiconductor device, wherein a portion of the diffusion prevention layer formed on a formation region of the second conductivity type MISFET is selectively removed. In the manufacturing method of the semiconductor device according to claim 17,
The step (d) is performed after the step (b),
In the step (d), a surface portion of the first metal-containing film is modified by ion implantation of at least one of oxygen and nitrogen. In the manufacturing method of the semiconductor device according to claim 16,
The step (d) is performed before the step (b),
In the step (d), the diffusion preventing layer is formed on the first metal-containing film. In the manufacturing method of the semiconductor device according to claim 21,
The step (a) includes the step (a1) of forming the first metal-containing film on the respective formation regions of the first conductivity type MISFET and the second conductivity type MISFET in the semiconductor substrate; A step (a2) of selectively removing a portion of the first metal-containing film formed on the formation region of the second conductivity type MISFET after the step (a1);
The step (d) is performed between the step (a1) and the step (a2),
In the step (d), the diffusion prevention layer is formed on the first metal-containing film formed on the respective formation regions of the first conductivity type MISFET and the second conductivity type MISFET,
In the step (a2), a method of manufacturing a semiconductor device, wherein a portion of the diffusion prevention layer formed on a formation region of the second conductivity type MISFET is selectively removed. In the manufacturing method of the semiconductor device of any one of Claims 16-22,
A method of manufacturing a semiconductor device, wherein the first gate electrode and the second gate electrode are formed by a gate last method.

Images