JP2012230559A - Clock supply circuit and semiconductor integrated circuit - Google Patents

Abstract

In order to supply a high-speed clock to an internal circuit, a clock buffer with high power consumption is required. Therefore, a clock supply circuit and a semiconductor integrated circuit that supply a high-speed clock with low power consumption are desired.
A clock supply circuit includes a PLL circuit including a voltage controlled oscillator and a clock having a frequency substantially the same as the oscillation frequency of the voltage controlled oscillator based on an oscillation control voltage for controlling the oscillation frequency of the voltage controlled oscillator. And a self-oscillation buffer circuit that outputs in synchronization with the reference clock of the PLL circuit.
[Selection] Figure 1

Description

  The present invention relates to a clock supply circuit and a semiconductor integrated circuit. In particular, the present invention relates to a clock supply circuit and a semiconductor integrated circuit that can supply a high-speed clock.

  The amount of data handled by semiconductor integrated circuits including CPUs (Central Processing Units) is increasing year by year. In order to cope with an increase in the amount of data, the semiconductor integrated circuit needs to operate at a high speed, and a rise in clock frequency is remarkable.

  Here, Patent Document 1 discloses a clock driver circuit that realizes a high-speed operation by reducing the input capacitance of the two-phase clock driver circuit and suppresses the occurrence of a phase shift between the two-phase clocks.

Japanese Patent Laid-Open No. 6-59770

  Each disclosure of the above prior art document is incorporated herein by reference. The following analysis has been made from the viewpoint of the present invention.

  As described above, the operation clock of the semiconductor integrated circuit is increasing year by year. Furthermore, system LSIs that integrate a plurality of operation modules in the same semiconductor integrated circuit are widely used. As a result, there are a plurality of operation modules (internal circuits) that require a high-speed clock in the same semiconductor integrated circuit. These internal circuits are supplied with a clock from a clock supply circuit.

  Also, a clock buffer is often required when supplying a clock to a plurality of internal circuits. FIG. 2 is a diagram illustrating an example of an internal configuration of a semiconductor integrated circuit that supplies a clock to a plurality of internal circuits. The internal circuits 50 to 53 are circuits that use the differential clock output from the clock supply source 60 as an operation clock. If the internal circuit and the clock supply source 60 are close to each other, the clock output from the clock supply source 60 can be directly supplied to the internal circuit. However, if a plurality of internal circuits exist in the same semiconductor integrated circuit, it is impossible to arrange all the internal circuits in the vicinity of the clock supply source 60. Therefore, clock buffers CB01 to CB06 are inserted between the internal circuit and the clock supply source 60.

  Here, when the clock supplied from the clock supply source 60 is high speed, it is necessary to use the clock buffers CB01 to CB06 with high power consumption in order to supply the high speed clock to the internal circuit without dullness. In addition, the wiring between clock buffers must be able to transmit a high-speed clock (it is necessary to secure the frequency band of the transmission path), the wiring between clock buffers cannot be lengthened, and the number of clock buffers required increases. End up. As a result, power consumption further increases.

  As described above, there are problems to be solved in order to supply a high-speed clock to the internal circuit. Therefore, a clock supply circuit and a semiconductor integrated circuit that supply a high-speed clock with low power consumption are desired.

  According to the first aspect of the present invention, based on a PLL circuit including a voltage controlled oscillator and an oscillation control voltage for controlling the oscillation frequency of the voltage controlled oscillator, a frequency substantially equal to the oscillation frequency of the voltage controlled oscillator is set. There is provided a clock supply circuit including a self-oscillation type buffer circuit that outputs a clock having the same clock in synchronization with a reference clock of the PLL circuit.

  According to a second aspect of the present invention, a semiconductor integrated circuit including the above-described clock supply circuit is provided.

  According to each aspect of the present invention, a clock supply circuit and a semiconductor integrated circuit that supply a high-speed clock with low power consumption are provided.

It is a figure for demonstrating the outline | summary of embodiment of this invention. It is a figure which shows an example of the internal structure of the semiconductor integrated circuit which supplies a clock to several internal circuits. 1 is a diagram illustrating an example of a semiconductor integrated circuit including a clock supply circuit according to a first embodiment of the present invention. It is a figure which shows an example of an internal structure of the self-oscillation type voltage control oscillator shown in FIG. FIG. 4 is a diagram illustrating an example of an internal configuration of a self-oscillation buffer illustrated in FIG. 3. It is a figure which shows an example of the semiconductor integrated circuit containing the clock supply circuit of the 2nd Embodiment of this invention.

  First, the outline of the embodiment will be described with reference to FIG. Note that the reference numerals of the drawings attached to this summary are attached to the respective elements for convenience as an example for facilitating understanding, and are not intended to limit the present invention to the illustrated embodiment.

  As described above, in order to supply a high-speed clock to the internal circuit, there is a problem that a clock buffer with high power consumption is required. Therefore, a clock supply circuit and a semiconductor integrated circuit that supply a high-speed clock with low power consumption are desired.

  Therefore, the clock supply circuit shown in FIG. 1 is provided as an example. The clock supply circuit shown in FIG. 1 is based on a PLL circuit including a voltage controlled oscillator, and an oscillation control voltage that controls the oscillation frequency of the voltage controlled oscillator. And a self-oscillation buffer circuit that outputs in synchronization with the reference clock of the PLL circuit.

  The self-oscillating buffer circuit is a replica circuit that simulates a voltage controlled oscillator included in the PLL circuit. Then, by making the oscillation control voltage applied to the self-oscillation type buffer circuit and the voltage controlled oscillator in common, the oscillation frequencies of both circuits can be made substantially the same. Furthermore, if the internal circuit that receives the clock supplied from the self-oscillation buffer circuit and the self-oscillation buffer circuit are brought close to each other, a high-speed clock is generated in the vicinity of the internal circuit. The clock buffer between internal circuits can be reduced. As a result, clock buffers with high power consumption can be reduced, and high-speed clocks can be supplied with low power consumption.

[First Embodiment]
Next, the first embodiment of the present invention will be described in more detail with reference to the drawings. FIG. 3 is a diagram illustrating an example of a semiconductor integrated circuit including the clock supply circuit 1 according to the present embodiment.

  The semiconductor integrated circuit shown in FIG. 3 includes a clock supply circuit 1 and internal circuits 2 to 5. The internal circuits 2 to 5 are circuits that operate with the differential clocks HCLKP and HCLKN supplied from the clock supply circuit 1. The clock supply circuit 1 is a circuit that receives a single-phase clock LCLK and supplies differential clocks HCLKP and HCLKN that are faster than the single-phase clock LCLK.

  The clock supply circuit 1 includes a PLL circuit 10, a single differential conversion buffer 20, differential clock buffers 30 to 33, and self-oscillation buffers 40 to 43. The single phase clock LCLK is input to the PLL circuit 10 and the single differential conversion buffer 20.

  The single differential conversion buffer 20 converts the single phase clock LCLK into a normal phase clock LCLKP and a reverse phase clock LCLKN, and outputs the converted clock to the differential clock buffer 30. Since the cycle of the normal phase clock LCLKP and the reverse phase clock LCLKN is the same as that of the single phase clock LCLK, it is longer than the cycle of the differential clocks HCLKP and HCLKN.

  The differential clock buffer 30 outputs the received differential clocks LCLKP and LCLKN to the self-oscillation buffer 40 and the differential clock buffer 31. Similarly, the differential clock buffers 31 to 33 output the differential clocks LCLKP and LCLKN output from the previous-stage differential clock buffer to the self-oscillation type buffer and the next-stage differential clock buffer. Since there is no differential clock buffer ahead of the differential clock buffer 33, the differential clock buffer 33 outputs differential clocks LCLKP and LCLKN only to the self-oscillation buffer 43.

  The self-oscillation buffers 40 to 43 receive the differential clocks LCLKP and LCLKN output from the differential clock buffers 30 to 33 and the voltage control signal VCNT of the PLL circuit 10. The self-oscillation buffers 40 to 43 output differential clocks HCLKP and HCLKN to the corresponding internal circuits 2 to 5, respectively.

  The PLL circuit 10 receives the single-phase clock LCLK and outputs a voltage control signal VCNT. The PLL circuit 10 includes a self-oscillating voltage controlled oscillator (VCO) 101, a frequency divider (DIV) 102, a frequency comparator (PHD) 103, and a low-pass filter (LFP) 104.

  The self-oscillating voltage controlled oscillator 101 is a circuit that changes the clock frequency based on the voltage control signal VCNT output from the low-pass filter 104. The frequency divider 102 is a circuit that divides the frequency of the clock output from the self-oscillation type voltage controlled oscillator 101.

  The frequency comparator 103 detects synchronization between the single-phase clock LCLK and the clock output from the frequency divider 102. The single phase clock LCLK corresponds to a reference clock in the PLL circuit 10. If these signals are not synchronized, a signal for increasing or decreasing the voltage control signal VCNT output from the low-pass filter 104 is output to the low-pass filter 104.

  The low-pass filter 104 removes noise from the output of the frequency comparator 103 and outputs it as a voltage control signal VCNT to the self-oscillation type voltage control oscillator 101 and the self oscillation type buffers 40 to 43.

  Next, the self-oscillation type voltage controlled oscillator 101 will be described. FIG. 4 is a diagram illustrating an example of an internal configuration of the self-oscillation type voltage controlled oscillator 101.

  A self-oscillation type voltage controlled oscillator 101 shown in FIG. 4 includes a self oscillation type voltage controlled oscillation circuit 1011 and an output buffer circuit 1012.

  The self-oscillation type voltage control oscillation circuit 1011 receives the voltage control signal VCNT from the voltage control signal input terminal Vin. The self-oscillation type voltage control oscillation circuit 1011 self-oscillates based on the voltage control signal VCNT and outputs a differential clock to the output buffer circuit 1012.

  In the output buffer circuit 1012, the self-oscillation type voltage controlled oscillation circuit 1011 inverts and amplifies the differential clock and outputs it. As output terminals at that time, a normal phase clock output terminal VoutP and a reverse phase clock output terminal VoutN are used.

  The self-oscillation type voltage controlled oscillation circuit 1011 includes N channel type MOS transistors NM01 to NM04, P channel type MOS transistors PM01 and PM02, a resistor R01, and an inductor L01.

  The source terminals of the N-channel MOS transistors NM01 and NM02 are commonly connected to each other and connected to the ground terminal GND. The gate terminal of the N channel type MOS transistor NM01 is connected to the drain terminal of the N channel type MOS transistor NM02. The gate terminal of the N channel type MOS transistor NM02 is connected to the drain terminal of the N channel type MOS transistor NM01. The drain terminal of the N-channel MOS transistor NM01 is connected to the drain terminal of the P-channel MOS transistor PM01, one end of the inductor L01, and the gate terminal of the N-channel MOS transistor NM03. This connection point is defined as node S1. Similarly, the drain terminal of the N-channel MOS transistor NM02 is connected to the drain terminal of the P-channel MOS transistor PM02, the other end of the inductor L01, and the gate terminal of the N-channel MOS transistor NM04. This connection point is defined as node S2. The drain terminal, source terminal, and back gate terminal of the N channel type MOS transistor NM03 are connected in common. Similarly, the drain terminal, the source terminal, and the back gate terminal of the N channel type MOS transistor NM04 are connected in common. The commonly connected terminals of the N-channel MOS transistors NM03 and NM04 are connected to each other and connected to the voltage control signal input terminal Vin via the resistor R01.

  The source terminals of the P-channel MOS transistors PM01 and PM02 are commonly connected to each other and connected to the power supply voltage terminal VDD. The gate terminal of the P-channel MOS transistor PM01 is connected to the drain terminal of the P-channel MOS transistor PM02. The gate terminal of the P-channel MOS transistor PM02 is connected to the drain terminal of the P-channel MOS transistor PM01.

  The self-oscillation type voltage controlled oscillation circuit 1011 outputs a differential clock to the output buffer circuit 1012 with the nodes S1 and S2 as output terminals.

  The N-channel MOS transistors NM03 and NM04 behave as variable capacitance elements having a capacitance between the gate terminal and the back gate terminal, and generate a differential clock by configuring an inductor L01 and an oscillation circuit. Furthermore, the oscillation is continued by receiving the supply of the power supply voltage from the power supply voltage terminal VDD and the ground terminal GND. Further, by changing the voltage control signal VCNT, the gate-back gate voltages of the N-channel MOS transistors NM03 and NM04 change, and the capacitance values of the N-channel MOS transistors NM03 and NM04 change. As a result, the oscillation frequency can be changed by the voltage control signal VCNT.

  The output buffer circuit 1012 includes N-channel MOS transistors NM05 and NM06 and P-channel MOS transistors PM03 and PM04.

  The source terminals of the N-channel MOS transistors NM05 and NM06 are commonly connected to each other and connected to the ground terminal GND. The gate terminal of the N-channel MOS transistor NM05 is connected to the node S1 and the gate terminal of the P-channel MOS transistor PM03. The drain terminal of the N-channel MOS transistor NM05 is connected to the drain terminal of PM03. Similarly, the gate terminal of the N-channel MOS transistor NM06 is connected to the node S2 and the gate terminal of the P-channel MOS transistor PM04, and the drain terminal is connected to the drain terminal of PM04.

  The source terminals of the P-channel MOS transistors PM03 and PM04 are commonly connected to each other and connected to the power supply voltage terminal VDD. The gate terminal of the P-channel MOS transistor PM03 is connected to the node S1 and the gate terminal of the N-channel MOS transistor NM05. Similarly, the gate terminal of the P-channel MOS transistor PM04 is connected to the node S2 and the gate terminal of the N-channel MOS transistor NM06.

  A connection point of the drain terminals of the N-channel MOS transistor NM06 and the P-channel MOS transistor PM04 is a positive phase clock output terminal VoutP. A connection point of the drain terminals of the N channel type MOS transistor NM05 and the P channel type MOS transistor PM03 is defined as a reverse phase clock output terminal VoutN. The output buffer circuit 1012 inverts the voltage of the node S2 and outputs it from the normal phase clock output terminal VoutP, and inverts the voltage of the node S1 and outputs it from the negative phase clock output terminal VoutN.

  Next, the self oscillation type buffers 40 to 43 will be described. Since the configurations of the self-oscillation buffers 40 to 43 are the same, only the self-oscillation buffer 40 will be described, and description of the self-oscillation buffers 42 and 43 will be omitted.

  FIG. 5 is a diagram illustrating an example of the internal configuration of the self-oscillation buffer 40. The self-oscillation buffer 40 includes a self-oscillation voltage control buffer circuit 401 and an output buffer circuit 402.

  The self-oscillation type voltage control buffer circuit 401 receives the voltage control signal VCNT from the voltage control signal input terminal Vin. Further, the normal phase clock LCLKP output from the differential clock buffer 30 is received by the clock input terminal ICLKP, and the reverse phase clock LCLKN is received by the clock input terminal ICLKN. The output buffer circuit 402 outputs the high-speed differential clock output from the self-oscillation type voltage control buffer circuit 401 from the normal phase clock output terminal VoutP and the negative phase clock output terminal VoutN.

  The self-oscillating voltage control buffer circuit 401 self-oscillates based on the voltage control signal VCNT and outputs a differential clock synchronized with the differential clocks LCLKP and LCLKN received at the clock input terminals ICLKP and ICLKN. That is, by turning on / off the N-channel MOS transistors NM07 and NM08 and the P-channel MOS transistors PM05 and PM06 by the differential clocks LCLKP and LCLKN received at the clock input terminals ICLKP and ICLKN, the inductors L02 and NCLK are controlled. The state of the oscillation circuit constituted by the channel type MOS transistors NM07 and NM08 is determined.

  The self-oscillating voltage control buffer circuit 401 includes N-channel MOS transistors NM07 to NM10, P-channel MOS transistors PM05 and PM06, a resistor R02, and an inductor L02. The self-oscillation type voltage control buffer circuit 401 is a replica circuit of the self-oscillation type voltage control oscillation circuit 1011. The difference between the self-oscillation type voltage control oscillation circuit 1011 and the self-oscillation type voltage control buffer circuit 401 is that the gate terminals of the N-channel MOS transistors NM07 to NM08 and the P-channel MOS transistors PM05 and PM06 are differently connected.

  In the self-oscillation type voltage control buffer circuit 401, the gate terminal of the N-channel MOS transistor NM08 and the gate terminal of the P-channel MOS transistor PM06 are connected, and this connection point is connected to the clock input terminal ICLKP. Similarly, the gate terminal of the N-channel MOS transistor NM07 and the gate terminal of the P-channel MOS transistor PM05 are connected, and this connection point is connected to the clock input terminal ICLKN. As described above, the difference between the self-oscillation voltage control oscillation circuit 1011 and the self-oscillation voltage control buffer circuit 401 is that the connection between the gate terminals of the N-channel MOS transistors NM07 and NM08 and the P-channel MOS transistors PM05 and PM06 is different. They are only different, and other explanations are omitted.

  Similarly to the self-oscillation type voltage control oscillation circuit 1011, the self-oscillation type voltage control buffer circuit 401 also changes the capacitance value by changing the gate-back gate voltages of the N-channel type MOS transistors NM09 and NM10, thereby controlling the voltage. The oscillation frequency can be changed by the signal VCNT. As described above, the self-oscillation voltage control oscillation circuit 1011 and the self-oscillation voltage control buffer circuit 401 are common in that they self-oscillate based on the voltage control signal VCNT. Further, by making the sizes of the transistors in both circuits, the inductance of the inductor, and the like the same, if the voltage control signal VCNT is input, a differential clock having the same period can be output.

  The output buffer circuit 402 includes N channel type MOS transistors NM11 and NM12 and P channel type MOS transistors PM07 and PM08. Since the output buffer circuit 402 and the output buffer circuit 1012 have the same configuration, description thereof is omitted.

  Next, the operation of the clock supply circuit 1 shown in FIG. 3 will be described. The frequency division ratio of the frequency divider 102 of the PLL circuit 10 shown in FIG. 3 is N, and the frequency of the single-phase clock LCLK (reference clock) input to the PLL circuit 10 is Fr. Then, the self-oscillation type voltage controlled oscillator 101 inside the PLL circuit 10 oscillates at a frequency of Fr × N.

  The self-oscillation buffers 40 to 43 are replica circuits of the self-oscillation voltage control oscillator 101, and the voltage control signal VCNT input to the self-oscillation voltage control oscillator 101 and the self-oscillation buffers 40 to 43 is common. Therefore, the natural frequencies of the self-oscillation type voltage controlled oscillator 101 and the self-oscillation type buffers 40 to 43 match. Accordingly, the self-oscillation buffers 40 to 43 can also output differential clocks HCLKP and HCLKN having a frequency of Fr × N. The differential clocks HCLKP and HCLKN output from the self-oscillation buffers 40 to 43 are output in synchronization with the differential clocks LCLKP and LCLKN.

  In the present embodiment, the case where a high-speed clock is supplied to four internal circuits has been described, but the present invention is not limited to this. An arbitrary number of internal circuits can be easily accommodated by preparing a self-oscillation type buffer in accordance with an internal circuit that requires high-speed clock supply.

  As described above, by using the self-oscillation type buffers 40 to 43 which are replica circuits of the self-oscillation type voltage controlled oscillator 101 of the PLL circuit 10, high-speed clock transmission is possible with low power consumption. By arranging the self-oscillation buffers 40 to 43 in the vicinity of the internal circuits 2 to 5, the high-speed clock wiring in the semiconductor integrated circuit is shortened. For this reason, the ratio of wiring that needs to transmit a high-speed clock in the clock wiring in the semiconductor integrated circuit decreases. Therefore, when a high-speed clock is wired over a long distance, a large number of clock buffers are required, but these buffers are not necessary.

  On the other hand, in response to the shortening of the wiring for transmitting the high-speed clock, the wiring for transmitting the low-speed clock becomes long. However, since the low-speed clock is transmitted, a clock buffer with high power consumption is unnecessary. Furthermore, since a low-speed clock is transmitted, the distance between clock buffers can be increased (clock buffers can be reduced). As a result, by using the clock supply circuit 1, a high-speed clock can be supplied to the internal circuit with low power consumption.

[Second Embodiment]
Next, a second embodiment will be described in detail with reference to the drawings. FIG. 6 is a diagram showing an example of a semiconductor integrated circuit including the clock supply circuit 1a according to the present embodiment. 6, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof is omitted.

  The difference between the clock supply circuit 1 and the clock supply circuit 1a is the connection between the differential clock buffers 30 to 33 and the self-oscillating buffers 40 to 41.

  In the clock supply circuit 1, differential clock buffers 30 to 33 are connected in series to the differential clocks LCLKP and LCLKN output from the single differential conversion buffer 20. In the clock supply circuit 1a, differential clock buffers 30 to 33 are connected in parallel to the differential clocks LCLKP and LCLKN.

  In the connection like the clock supply circuit 1, the timings of the differential clocks HCLKP and HCLKN supplied to the internal circuits 2 to 5 are shifted by the differential clock buffers 30 to 33. However, in the clock supply circuit 1a, the timings of the differential clocks HCLKP and HCLKN supplied to the internal circuits 2 to 5 can be matched.

  Each disclosure of the cited patent documents and the like cited above is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiment can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea. For example, even if the N channel type MOS transistor and the P channel type MOS transistor are exchanged, it can be dealt with by appropriately changing the connection of the power source or the like. That is, the N channel type MOS transistor can be regarded as a first conductivity type transistor, and the P channel type MOS transistor can be regarded as a second conductivity type transistor.

1, 1a Clock supply circuit 2 to 5, 50 to 53 Internal circuit 10 PLL circuit 20 Single differential conversion buffer 30 to 33 Differential clock buffer 40 to 43 Self oscillation type buffer 60 Clock supply source 101 Self oscillation type voltage controlled oscillator 102 Frequency divider 103 Frequency comparator 104 Low-pass filter 401 Self-oscillation type voltage control buffer circuit 402, 1012 Output buffer circuit 1011 Self-oscillation type voltage control oscillation circuit CB01-CB06 Clock buffer L01, L02 Inductors NM01-NM12 N-channel type MOS Transistors PM01 to PM08 P-channel MOS transistors R01 and R02 Resistors

Claims (11)

A PLL circuit including a voltage controlled oscillator;
A self-oscillation buffer that outputs a clock having substantially the same frequency as the oscillation frequency of the voltage-controlled oscillator based on an oscillation control voltage that controls the oscillation frequency of the voltage-controlled oscillator in synchronization with a reference clock of the PLL circuit Circuit,
A clock supply circuit comprising:   2. The clock supply circuit according to claim 1, comprising a plurality of the self-oscillation type buffer circuits, each of which outputs a clock based on the oscillation control voltage.   3. The clock supply circuit according to claim 1, further comprising a clock buffer circuit that receives the reference clock, buffers the received reference clock, and outputs the buffered reference clock to the self-oscillation buffer circuit.   4. The clock supply circuit according to claim 3, comprising a plurality of said clock buffer circuits, wherein said plurality of clock buffer circuits and said self-oscillation type buffer circuit are respectively connected correspondingly.   The clock supply circuit according to claim 4, wherein the plurality of clock buffer circuits are connected in parallel to the reference clock.   The clock supply circuit according to claim 1, further comprising a single differential conversion buffer that converts the reference clock into a differential clock, wherein the self-oscillation buffer circuit outputs a differential clock.   The clock supply circuit according to claim 1, wherein a frequency of a clock output from the self-oscillation buffer circuit is higher than a frequency of the reference clock.   The clock supply circuit according to claim 1, wherein an output voltage of a low-pass filter included in the PLL circuit is the oscillation control voltage.   9. The clock supply circuit according to claim 1, wherein the self-oscillation buffer circuit is a replica circuit of the voltage controlled oscillator.   A semiconductor integrated circuit comprising the clock supply circuit according to claim 1.   The semiconductor integrated circuit according to claim 10, further comprising an internal circuit that operates according to a clock output from the self-oscillation buffer circuit, wherein the self-oscillation buffer circuit and the internal circuit are connected without a buffer.

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