JP2012222038A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method in which a semiconductor chip is exposed to a high temperature the least number of times.SOLUTION: A semiconductor device manufacturing method comprises the steps of: preparing a plurality of semiconductor chips 10 each having bump electrodes 12 connected via a through electrode 13; laminating a second semiconductor chip 10b on a first semiconductor chip 10a such that the bump electrodes 12 confront each other; temporarily pressure bonding the bump electrodes 12 on the semiconductor chip 10a with the bump electrodes on the semiconductor chip 10b; laminating a third semiconductor chip 10c on the semiconductor chip 10b such that the bump electrodes 12 confront each other; temporarily pressure bonding the bump electrodes 12 on the semiconductor chip 10b with the bump electrodes 12 on the semiconductor chip 10c to form a chip laminate 11; and actually pressure bonding the plurality of bump electrodes 12 collectively that are temporarily pressure bonded in the chip laminate 11.

Description

  The present invention relates to a CoC (Chip on Chip) type semiconductor device.

  Patent Document 1 describes an example of a method for manufacturing a CoC type semiconductor device in which a plurality of semiconductor chips each having a through electrode are stacked. The manufacturing method described in Patent Document 1 includes a step of stacking a plurality of semiconductor chips each having bump electrodes connected to each other through through electrodes to form a chip stack, and a chip stack. Mounting on a wiring board.

  Here, in the manufacturing method described in Patent Document 1, the stack of semiconductor chips and the connection and fixing of the stacked semiconductor chips are repeated a plurality of times to form a chip stack. Specifically, the second-stage semiconductor chip is formed such that the bump electrode on the first-stage semiconductor chip and the bump electrode on the second-stage semiconductor chip are abutted on the first-stage semiconductor chip. Stack the chips. Next, heat and a load at a predetermined temperature (about 300 ° C.) are applied to the two stacked semiconductor chips to bond the bump electrodes on the first-stage semiconductor chip and the bump electrodes on the second-stage semiconductor chip. That is, the bump electrodes are thermocompression bonded. Thereafter, the bump electrode on the second-stage semiconductor chip and the bump electrode on the third-stage semiconductor chip are abutted on the second-stage semiconductor chip, so that the third-stage semiconductor chip Are stacked. Thereafter, heat and a load at a predetermined temperature (around 300 ° C.) are applied to the three stacked semiconductor chips to join the bump electrodes on the second-stage semiconductor chip and the bump electrodes on the third-stage semiconductor chip. . Thereafter, similar steps are repeated to stack the required number of semiconductor chips.

JP 2010-251347 A

  The manufacturing method described in Patent Document 1 has the following problems. That is, in the manufacturing method described above, the chip stack is formed by repeating the stacking of the semiconductor chips and the connection and fixing of the stacked semiconductor chips a plurality of times. Therefore, the number of times the semiconductor chip is heated increases as the number of stacked semiconductor chips increases. For example, when forming a chip stack in which five semiconductor chips are stacked, the first-stage semiconductor chip is heated four times around 300 ° C., and the second-stage semiconductor chip is heated three times. As described above, when the semiconductor chip is exposed to a high temperature many times, the performance of the semiconductor chip may be deteriorated.

  In the method for manufacturing a semiconductor device according to the present invention, a plurality of semiconductor chips are stacked while a bump electrode is temporarily press-bonded to form a chip stack, and then a plurality of bump electrodes in the chip stack are collectively pressed. Specifically, a plurality of semiconductor chips having bump electrodes connected via through electrodes are prepared, and the second semiconductor chip is placed on the first semiconductor chip so that the bump electrodes are brought into contact with each other. The bump electrodes on the first semiconductor chip and the bump electrodes on the second semiconductor chip that are in contact with the bump electrodes are temporarily pressed together so that the bump electrodes are in contact with each other. Further, a third semiconductor chip is stacked on the second semiconductor chip, a bump electrode on the second semiconductor chip, and a bump electrode on the third semiconductor chip that is abutted against the bump electrode Are temporarily bonded to each other to form a chip laminated body, and a plurality of bump electrodes temporarily bonded in the chip laminated body are collectively bonded together. Therefore, even if the number of stacked semiconductor chips is increased, the high-temperature heat required for the final pressure bonding of the bump electrodes can be applied only once.

  According to the present invention, the number of times that the semiconductor chip is exposed to a high temperature is reduced, so that the possibility of the performance degradation of the semiconductor chip is reduced.

It is sectional drawing which shows the structure of the semiconductor device manufactured by the manufacturing method of this invention. It is sectional drawing which shows an example of the temporary crimping | compression-bonding process in the manufacturing method of this invention. It is a schematic diagram which shows an example of the apparatus which performs the temporary crimping | compression-bonding process in the manufacturing method of this invention. It is sectional drawing which shows an example of this crimping | compression-bonding process in the manufacturing method of this invention. It is sectional drawing which shows an example of the sealing process in the manufacturing method of this invention. It is sectional drawing which shows an example of the mounting process in the manufacturing method of this invention. It is sectional drawing which shows an example of the mounting process in the manufacturing method of this invention. It is sectional drawing which shows another example of this crimping | compression-bonding process in the manufacturing method of this invention. It is a schematic diagram which shows another example of the apparatus which performs the temporary crimping | compression-bonding process in the manufacturing method of this invention. It is sectional drawing which shows another example of this crimping | compression-bonding process in the manufacturing method of this invention.

(First embodiment)
A semiconductor device manufacturing method according to a first embodiment of the present invention will be described below. FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 1 manufactured by the manufacturing method according to the present embodiment. The illustrated semiconductor device 1 includes a chip stack 11 on which a plurality of semiconductor chips 10 are stacked, and an interface chip (hereinafter referred to as “IF chip 20”) is disposed under the chip stack 11. Has been. The lowermost semiconductor chip 10 of the chip stack 11 is connected and fixed to the wiring substrate 30 via the IF chip 20.

  Each semiconductor chip 10 and IF chip 20 have one surface on which a circuit is formed and the other surface on which no circuit is formed. In the following description, the surface of the semiconductor chip 10 and the IF chip 20 on which the circuit is formed is referred to as “front surface”, and the surface on which the circuit is not formed is referred to as “back surface”. However, such a distinction is merely a distinction for convenience of explanation.

  For example, a memory circuit is formed on the surface of the semiconductor chip 10, and a circuit for controlling the semiconductor chip 10 is provided on the surface of the IF chip 20. Further, bump electrodes 12 are provided on the front and back surfaces of the semiconductor chip 10 and the IF chip 20, respectively. Further, the bump electrodes 12 on the chips 10 and 20 are connected to each other through the through electrodes 13.

  The IF chip 20 also serves as a support member that receives stress applied to the semiconductor chip 10 in the manufacturing process of the semiconductor device 1. Specifically, the IF chip 20 receives stress generated by thermal expansion and contraction of the through electrode 13 in the semiconductor chip 10. The bump electrodes 12 on the surface of the IF chip 20 are arranged corresponding to the positions of the connection pads 31 on the wiring board 30.

  In the following description, the laminated body including the chip laminated body 11 and the IF chip 20 is referred to as a “composite chip laminated body 40” to be distinguished from the chip laminated body 11. However, such a distinction is merely a distinction for convenience of explanation, and the composite chip laminate 40 is also a chip laminate in which a plurality of semiconductor chips are laminated.

  A gap between the semiconductor chip 10 and the IF chip 20 in the composite chip stack 40 is filled with the first sealing resin layer 14. Further, gaps between the semiconductor chips 10 are also filled with the first sealing resin layer 14. Further, a part of the side surface of the composite chip stack 40 is also covered with the first sealing resin layer 14. As shown in FIG. 1, the cross section of the first sealing resin layer 14 is substantially trapezoidal when the semiconductor device 1 is viewed from the side. The first sealing resin layer 14 is formed using, for example, a known underfill material.

  A wiring substrate 30 on which predetermined wiring is formed is connected and fixed to the IF chip 20 disposed on the short side (corresponding to the upper base of the trapezoid) of the substantially trapezoidal first sealing resin layer 14. . As the wiring board 30, for example, a glass epoxy board having predetermined wirings formed on both sides is used.

  A plurality of connection pads 31 are formed on one surface of the wiring board 30, and a plurality of lands 33 are formed on the other surface. Each connection pad 31 is connected to the bump electrode 12 on the IF chip 20 via a wire bump 35, and a metal ball 32 serving as an external electrode of the semiconductor device 1 is provided on each land 33. . The connection pad 31 is connected to a predetermined land 33 via a wiring provided in the wiring board 30. The wiring board 30 is covered with an insulating film 34 such as a solder resist film except for the connection pads 31 and the lands 33. The lands 33 are arranged on the wiring board 30 in a grid pattern at predetermined intervals. However, the arrangement of the lands 33 is not limited to the lattice shape.

  The composite chip stack 40 and the wiring board 30 are bonded and fixed by an adhesive 15 such as NCP (Non Conductive Paste), and the bonding pad 15 on the wiring board 30 and the bump electrode 12 on the IF chip 20 are bonded by the adhesive 15. The junction site is protected. The composite chip stack 40 on the wiring substrate 30 is sealed with the second sealing resin layer 16.

  Next, a method for manufacturing the semiconductor device 1 shown in FIG. 1 will be described with reference to the drawings.

  2 and 3 are cross-sectional views showing a part of the manufacturing process of the composite chip laminate 40 shown in FIG. More specifically, FIG. 2 is a cross-sectional view showing the temporary press-bonding step, and FIG. 3 is a cross-sectional view showing the main press-bonding step.

(Temporary crimping process)
When the semiconductor device 1 shown in FIG. 1 is manufactured, first, a plurality of semiconductor chips 10 are prepared. The structure of each semiconductor chip 10 is as described above.

  As shown in FIG. 2A, the first-stage semiconductor chip 10 a is placed on the stage 100. The semiconductor chip 10a is placed on the stage 100 with its surface facing up. The mounted semiconductor chip 10 a is vacuum sucked by a vacuum device (not shown) through a suction hole 101 provided in the stage 100.

  As illustrated in FIG. 2B, the second-stage semiconductor chip 10 b is mounted on the first-stage semiconductor chip 10 a using the bonding tool 110. The second-stage semiconductor chip 10b is mounted on the first-stage semiconductor chip 10a with its surface facing up. That is, the two semiconductor chips 10a and 10b are overlapped so that the front surface of the first-stage semiconductor chip 10a and the back surface of the second-stage semiconductor chip 10b face each other. The second-stage semiconductor chip 10b is held by the bonding tool 110 and mounted on the first-stage semiconductor chip 10a until a vacuum device (not shown) is inserted through the suction hole 111 of the bonding tool 110. Vacuum suction. Therefore, the second-stage semiconductor chip 10b is not dropped from the bonding tool 110.

  Next, the bump electrode 12 on the front surface of the semiconductor chip 10a and the bump electrode 12 on the back surface of the semiconductor chip 10b are temporarily bonded. Specifically, heat and a load at a predetermined temperature (around 200 ° C.) are applied to the bump electrode 12 on the semiconductor chip 10a and the bump electrode 12 on the semiconductor chip 10b that are abutted with each other. For example, the bonding tool 110 shown in FIG. 2B is heated to around 200 ° C., and the second-stage semiconductor chip 10 b is pressed against the first-stage semiconductor chip 10 a by the heated bonding tool 110.

  Next, by the same procedure as described above, the third-stage semiconductor chip 10c (FIG. 2C) is mounted on the second-stage semiconductor chip 10b, and the bump electrode and the semiconductor chip on the surface of the semiconductor chip 10b are mounted. A bump electrode on the back surface of 10c is temporarily pressed. Next, by the same procedure as described above, the fourth-stage semiconductor chip 10d (FIG. 2C) is mounted on the third-stage semiconductor chip 10c, and the bump electrodes and the semiconductor chip 10d on the surface of the semiconductor chip 10c are mounted. The bump electrode on the back surface of the substrate is temporarily pressed.

  Thereafter, as shown in FIG. 2C, the IF chip 20 is mounted on the fourth-stage semiconductor chip 10d by using the bonding tool 110. The IF chip 20 is mounted on the fourth-stage semiconductor chip 10d with its surface facing up. Next, the bump electrode on the front surface of the semiconductor chip 10d and the bump electrode on the back surface of the IF chip 20 are temporarily bonded. Specifically, heat and a load at a predetermined temperature (around 200 ° C.) are applied to the bump electrodes on the fourth-stage semiconductor chip 10d and the bump electrodes on the IF chip 20 that are in contact with each other. For example, the bonding tool 110 shown in FIG. 2C is heated to around 200 ° C., and the IF chip 20 is pressed against the fourth-stage semiconductor chip 10 d by the heated bonding tool 110.

  As described above, the composite chip stack 40 including the chip stack 11 and the IF chip 20 is obtained. The composite chip stack 40 and the composite chip stack 40 shown in FIG. 1 are turned upside down.

(Main crimping process)
FIG. 3 is a schematic diagram showing an example of an apparatus used in the main crimping process. The illustrated apparatus includes a stage 201 and a load tool 202 that face each other, and a pair of reels 204 and 205 that supply a sheet 203 between the stage 201 and the load tool 202.

  The stage 201 and the load tool 202 have heating means (for example, an electric heater) 206 built therein. A belt-like sheet 203 is wound around the first reel 204, and the second reel 205 winds up the sheet 203 wound around the first reel 204.

  Next, the main crimping process will be described. First, as shown in FIG. 4A, a plurality of composite chip stacks 40 are arranged on the stage 201. Thereafter, heat and a load at a predetermined temperature (around 300 ° C.) are applied to the bump electrodes in each of the chip stacks 40 that are temporarily press-bonded. For example, as shown in FIG. 4B, after the stage 201 and the load tool 202 are heated to around 300 ° C. by the heating means 206 (FIG. 3), the load tool 202 is bundled into a plurality of composite chip stacks 40. Press. At this time, the sheet 203 is interposed between the load tool 202 and each composite chip stack 40. Through this process, the bump electrodes that have been temporarily crimped are completely crimped together.

  In some cases, the heights of the composite chip stacks 40 may be different due to manufacturing variations, bump electrode height variations, and the like. However, in the present embodiment, the variation in height between the composite chip stacks is absorbed by the sheet 203 interposed between the load tool 202 and the composite chip stack 40. Therefore, predetermined heat and load can be uniformly applied to the plurality of composite chip stacks 40. As the sheet 203, a sheet made of fluororesin or a sheet coated with fluororesin is preferably used. However, as the sheet 203, any sheet having resistance to heat applied in the main crimping process and elasticity capable of absorbing the variation in height between the composite chip stacks can be used. It is not limited.

  After the above series of steps is completed, the second reel 205 shown in FIG. 3 is rotated to wind up the used sheet 203, and a new sheet 203 is supplied between the stage 201 and the load tool 202.

  As described above, the manufacturing method according to the present embodiment includes the temporary press-bonding step and the main press-bonding step with different heating conditions. Further, in the temporary press-bonding step, each time the semiconductor chips are stacked, a first temperature (T1) is applied to the stacked semiconductor chips to temporarily press-bond the bump electrodes. On the other hand, in the final press-bonding step, the second temperature (T2) higher than the first temperature (T1) is applied only once to the chip stack formed by the temporary press-bonding step, thereby completely bonding the bump electrodes together. Therefore, even if the number of stacked semiconductor chips increases, the number of times the temperature (T2) is applied to the semiconductor chips does not increase. That is, the semiconductor chip is not exposed to a high temperature multiple times.

(Sealing process)
Next, the sealing process of the composite chip stack 40 will be described. As shown in FIG. 5A, the composite chip stack 40 is placed on a coating sheet 302 disposed on a stage 301. The coating sheet 302 is a sheet made of a material having poor wettability with respect to the resin forming the first sealing resin layer 14 (FIG. 1), such as a sheet coated with a fluorine-based sheet or a silicone-based adhesive. Is used. Note that the coating sheet 302 need not be directly attached to the stage 301. For example, the coating sheet 302 may be disposed on a jig or the like placed on the stage 301.

  Next, as illustrated in FIG. 5B, the underfill material 304 is supplied to the composite chip stack 40 placed on the coating sheet 302 using the dispenser 303. The supplied underfill material 304 enters a gap between adjacent semiconductor chips 10 by capillary action while forming a fillet around the composite chip stack 40. Further, the underfill material 304 also enters the gap between the IF chip 20 and the semiconductor chip 10.

  In the present embodiment, since a sheet made of a material having poor wettability with respect to the underfill material 304 is used as the coating sheet 302, the spread of the underfill material 304 is suppressed and the fillet width does not increase.

  Next, as shown in FIG. 5C, the composite chip stack 40 covered with the underfill material 304 is cured (heat treated) at a predetermined temperature (for example, around 150 ° C.), whereby the underfill material 304 is changed. Heat cure.

  After the underfill material 304 is thermally cured, the composite chip stack 40 is picked up from the coating sheet 302. In the present embodiment, since the sheet made of a material having poor wettability with respect to the underfill material 304 is used as the coating sheet 302, the composite chip stack 40 can be easily picked up from the coating sheet 302.

  As described above, the composite chip stack 40 sealed with the first sealing resin layer 14 is obtained (FIG. 5D).

  When supplying the underfill material 304 to the composite chip stack 40, if the composite chip stack 40 may be displaced, the composite chip stack 40 is temporarily fixed to the coating sheet 302 using a resin adhesive. May be.

(Mounting process)
Next, a process of assembling the semiconductor device 1 shown in FIG. 1 using the composite chip stack 40 shown in FIG. 5D will be described with reference to FIGS.

  6 and 7 are cross-sectional views showing an example of a process for assembling the semiconductor device 1 shown in FIG. 6 and 7 show an example of a process of assembling a plurality of semiconductor devices 1 at once.

  First, a substrate 400 shown in FIG. 6A is prepared. On the substrate 400, a plurality of product forming portions 401 are arranged in a lattice pattern. Each product forming portion 401 on the substrate 400 finally becomes the wiring substrate 30 shown in FIG. Each product forming portion 401 is formed with a predetermined pattern of wiring. Further, a plurality of connection pads 31 are formed on one surface of each product forming portion 401, and a plurality of lands 33 are formed on the other surface. Furthermore, wire bumps 35 made of Au, Cu or the like are provided on the connection pads 31. The roles of the connection pad 31, the land 33, and the wire bump 35 are as described above. In addition, by forming the wire bumps 35 on the wiring board 30, the size of the through electrodes 13 of the chips 10 and 20 can be reduced and the pitch can be reduced.

  In the present embodiment, wire bumps 35 are formed on the connection pads 31 in order to facilitate the connection between the composite chip stack 40 and the connection pads 31. However, the bump electrodes 12 on the chips 10 and 20 and the connection pads 31 may be directly connected.

  When the preparation of the substrate 400 is completed, as shown in FIG. 6A, the insulating adhesive material 15 is applied onto each product forming portion 401 using the dispenser 500.

  Next, as shown in FIG. 6B, the composite chip stack 40 is sucked and held by the bonding tool 501 and mounted on each product forming unit 401.

  Next, each bump electrode 12 on the IF chip 20 and each wire bump 35 on the product forming portion 401 are joined using, for example, a thermocompression bonding method. At this time, the adhesive 15 is filled between the composite chip stack 40 and each product forming portion 401 on which the composite chip stack 40 is mounted, and the substrate 400 and the composite chip stack 40 are bonded and fixed (FIG. 6C). )). Here, since the first sealing resin layer 14 is formed in a tapered shape around the composite chip stack 40, the adhesive 15 is prevented from creeping up. Therefore, damage to the composite chip stack 40 due to the adhesive 15 adhering to the bonding tool 501, bonding failure, and the like are reduced.

  Next, the board | substrate 400 with which the some composite chip laminated body 40 was mounted is set to the shaping die of a transfer mold apparatus not shown. The molding die includes an upper die and a lower die, and a cavity that collectively covers the plurality of composite chip stacks 40 is formed in the upper die. The plurality of composite chip laminates 40 set in the molding die are accommodated in the upper mold cavity.

  Next, the sealing resin heated and melted is filled in the upper mold cavity, and the entire composite chip stack 40 in the cavity is covered with the sealing resin. As the sealing resin, for example, a thermosetting resin such as an epoxy resin is used.

  Subsequently, the sealing resin in the cavity is thermally cured by curing at a predetermined temperature, for example, around 180 ° C., thereby forming the second sealing resin layer 16 that collectively covers the plurality of composite chip stacks 40. (FIG. 7A). Furthermore, the second sealing resin layer 16 is completely cured by baking at a predetermined temperature. In the present embodiment, since the chips of the composite chip stack 40 are sealed in advance by the first sealing resin layer 14, voids are formed between the chips when the second sealing resin layer 16 is formed. Generation | occurrence | production can be suppressed.

  After the second sealing resin layer 16 is formed, the structure shown in FIG. 7A is turned upside down. Thereafter, as shown in FIG. 7B, metal balls (for example, solder balls) 32 are mounted on the lands 33 formed on the substrate 400. Specifically, a plurality of metal balls 32 are sucked and held using a mounting tool 600 having a plurality of suction holes corresponding to the respective lands 33 on the substrate 400, and the flux is transferred to each metal ball 32 and then held. The plurality of metal balls 32 are mounted on the lands 33 of the substrate 400 at once.

  After the mounting of the metal balls 32 on all the lands 33 is completed, the metal balls 32 and the lands 33 are connected by reflowing the substrate 400.

After the connection between the lands 33 and the metal balls 32 is completed, the substrate 400 is cut using a dicing blade 601 as shown in FIG. The substrate 400 is cut along a predetermined dicing line. When the substrate 400 is cut, the product forming portion 401 is supported by sticking the dicing tape 602 to the second sealing resin layer 16. The dicing tape 602 is peeled off from each product forming portion 401 after the substrate 400 is cut. Thus, the semiconductor device 1 shown in FIG. 1 is obtained.
(Second Embodiment)
A second embodiment of the method for manufacturing a semiconductor device of the present invention will be described. The manufacturing method according to the present embodiment is different from the manufacturing method according to the first embodiment with respect to the provisional pressure bonding process.

  FIG. 8 is a cross-sectional view showing a temporary pressure bonding step in the manufacturing method according to the present embodiment. In the final press-bonding step in the manufacturing method according to the first embodiment, the sheet 203 is disposed between the composite chip stack 40 and the load tool 202 (FIG. 4). On the other hand, in the final press-bonding step in the manufacturing method according to the present embodiment, the coating sheet 302 is disposed between the stage 201 and the composite chip stack 40 as shown in FIG. The coating sheet 302 shown in FIG. 8A is the same sheet as the coating sheet 302 shown in FIG. That is, the sheet is made of a material having heat resistance and poor wettability with respect to the underfill material 304.

  Hereinafter, the main press-bonding step in the manufacturing method according to the present embodiment will be specifically described. As shown in FIG. 8A, a plurality of composite chip stacks 40 are arranged at predetermined intervals on a coating sheet 302 disposed on a stage 201. Each composite chip laminated body 40 has undergone a temporary pressure bonding process, and the bump electrodes are temporarily pressure bonded.

  Next, heat and a load at a predetermined temperature (around 300 ° C.) are collectively applied to the plurality of composite chip laminates 40. For example, as illustrated in FIG. 8B, the stage 201 and the load tool 202 are heated to around 300 ° C., and then the load tool 202 is collectively pressed against the plurality of composite chip stacks 40. At this time, the variation in height between the composite chip stacks is absorbed by the coating sheet 302. Therefore, the predetermined heat and load can be uniformly applied to the plurality of composite chip stacks 40 as in the manufacturing method according to the first embodiment.

  Thereafter, the underfill material 304 is supplied to each composite chip laminate 40 placed on the coating sheet 302 using the dispenser 303, and each laminate 40 is sealed with the first sealing resin layer 14. Stop (FIGS. 8C and 8D). Note that when the composite chip stack 40 is arranged on the coating sheet 302, the interval between the adjacent composite chip stacks is adjusted in consideration of the spread of the underfill material 304.

  In the manufacturing method according to the present embodiment, the main crimping step is executed on the stage on which the coating sheet is laid. In other words, the coating sheet is used as a sheet for absorbing the variation in height between the composite chip stacks. For this reason, a main press-bonding process and a sealing process can be performed continuously. Specifically, the sealing step can be performed without transferring the composite chip laminate that has undergone the main pressure bonding step onto the coating sheet. Furthermore, a sealing process can be performed after the completion | finish of this press-fit process, maintaining a heating state. Therefore, breakage of the bump joint due to warpage that occurs when the composite chip laminated body heated in the main pressure bonding step returns to room temperature is prevented.

  FIG. 9 is a schematic diagram illustrating an example of an apparatus used in the main crimping step in the manufacturing method according to the present embodiment. The illustrated apparatus includes a first stage 201a, a second stage 201b, a load tool 202 facing the first stage 201a, and a pair of reels 204 for supplying and conveying the coating sheet 302 onto the stages 201a and 201b. , 205. The first stage 201a, the second stage 201b, and the load tool 202 incorporate heating means (for example, an electric heater).

The main crimping step is performed on the first stage 201a shown in FIG. 9, and the sealing step is performed on the second stage 201b. The second reel 205 winds up the coating sheet 302 when the main press-bonding step on the first stage 201a is completed. As a result, the composite chip stack 40 is conveyed from the first stage 201a to the second stage 201b, and a new coating sheet 302 is supplied onto the first stage 201a. In order to reliably convey the composite chip stack 40, it is preferable to apply viscosity to the coating sheet 302 and temporarily fix the composite chip stack 40 to the coating sheet 302.
(Third embodiment)
In the manufacturing method according to the first embodiment, the composite chip laminated body 40 that has undergone the main crimping process is placed on the substrate 400 (FIG. 6). However, as shown in FIG. 10, the composite chip stack 40 that has undergone the provisional pressure bonding process may be placed on the substrate 400, and the main pressure bonding process may be performed on the substrate 400.

  In the present specification, a method of manufacturing a semiconductor device in which four semiconductor chips and one IF chip are stacked has been described. However, the present invention is applicable to the manufacture of all semiconductor devices having three or more chips connected through through electrodes. The present invention is also applicable to the manufacture of a semiconductor device in which a device chip and a Si interposer are stacked.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Semiconductor chip 11 Chip laminated body 12 Bump electrode 13 Through electrode 20 Interface chip (IF chip)
201 stage 202 load tool 203 sheet 400 substrate

Claims (11)

Prepare a plurality of semiconductor chips having bump electrodes connected via through electrodes,
A second semiconductor chip is stacked on the first semiconductor chip so that the bump electrodes of each other face each other;
Temporarily pressing the bump electrode on the first semiconductor chip and the bump electrode on the second semiconductor chip that is abutted against the bump electrode;
A third semiconductor chip is stacked on the second semiconductor chip so that the bump electrodes of each other face each other;
Forming a chip stack by temporarily pressing the bump electrodes on the second semiconductor chip and the bump electrodes on the third semiconductor chip that are in contact with the bump electrodes;
A method of manufacturing a semiconductor device, wherein a plurality of bump electrodes that are temporarily press-bonded in the chip stack are collectively pressed. By applying heat and load at a first temperature to the bump electrodes that are butted against each other, the bump electrodes are temporarily crimped,
By applying heat and a load at a second temperature higher than the first temperature to the plurality of bump electrodes that are temporarily press-bonded in the chip stack, the plurality of bump electrodes are collectively bonded together. A method for manufacturing a semiconductor device according to claim 1. Forming a plurality of chip laminates on which bump electrodes are temporarily bonded;
The method of manufacturing a semiconductor device according to claim 2, wherein a plurality of bump electrodes temporarily bonded in each of the chip stacks are collectively bonded together.   The method of manufacturing a semiconductor device according to claim 3, wherein the load is applied to the plurality of chip stacks via a sheet capable of absorbing a variation in height between the plurality of chip stacks. Cover the plurality of chip stacks arranged on the stage with the sheet,
The method of manufacturing a semiconductor device according to claim 4, wherein a load tool is pressed against the plurality of chip stacks from above the sheet to apply the load.   The method of manufacturing a semiconductor device according to claim 4, wherein the sheet is disposed between a stage and the plurality of chip stacks, and a load tool is pressed against the plurality of chip stacks to apply the load.   The method for manufacturing a semiconductor device according to claim 6, wherein the plurality of chip stacks on the sheet are transported to another stage where another process is performed by moving the sheet after the load is applied.   The method of manufacturing a semiconductor device according to claim 5, wherein the heat is applied by heating at least one of the stage and the load tool to a predetermined temperature. Arranging the plurality of chip stacks on a substrate,
A plurality of bump electrodes that are temporarily crimped in each of the chip stacks arranged on the substrate are collectively crimped together,
Each of the chip stacks is sealed with resin,
The method of manufacturing a semiconductor device according to claim 3, wherein the substrate is cut and divided for each of the chip stacks sealed with resin. Preparing a plurality of semiconductor chips and interface chips having bump electrodes connected through through electrodes,
A second semiconductor chip is stacked on the first semiconductor chip so that the bump electrodes of each other face each other;
The bump electrodes on the first semiconductor chip and the bump electrodes on the second semiconductor chip that are in contact with the bump electrodes are applied with heat and load at a first temperature to temporarily press the bump electrodes. ,
A third semiconductor chip is stacked on the second semiconductor chip so that the bump electrodes of each other face each other;
The bump electrodes on the second semiconductor chip and the bump electrodes on the third semiconductor chip that are abutted against the bump electrodes are subjected to heat and load at the first temperature to temporarily press the bump electrodes. Let
A fourth semiconductor chip is stacked on the third semiconductor chip so that the bump electrodes of each other face each other;
The bump electrodes on the third semiconductor chip and the bump electrodes on the fourth semiconductor chip that are in contact with the bump electrodes are applied with heat and load at the first temperature to temporarily press the bump electrodes. Let
Stacking the interface chip on the fourth semiconductor chip so that the bump electrodes of each other face each other;
The bump electrode on the fourth semiconductor chip and the bump electrode on the interface chip that is abutted against the bump electrode are subjected to heat and load at the first temperature to temporarily press-bond these bump electrodes to the chip. Forming a laminate,
By applying heat and a load at a second temperature higher than the first temperature to the plurality of bump electrodes that are temporarily press-bonded in the chip stack, the plurality of bump electrodes are collectively bonded together. A method for manufacturing a semiconductor device.   11. The method of manufacturing a semiconductor device according to claim 2, wherein the first temperature is around 200 ° C. and the second temperature is around 300 ° C. 11.

Images