JP2012222034A - Semiconductor device, manufacturing method of the same and semiconductor substrate - Google Patents

Abstract

A semiconductor device manufacturing method capable of suppressing the influence of foreign matter on a semiconductor element caused by foreign matter or the like formed on an inner surface of an alignment mark.
A first thin film GI1 and a second thin film GI2, GE, and PE are formed in this order on a main surface of a semiconductor substrate SUB. Among the main surfaces, the second thin films GI2, GE, GE, GE2, GE, PE in the element formation region are used for alignment while using the mark MK in which the second thin films GI2, GE, PE in the peripheral region of the element formation region are patterned. PE is patterned to form a component part of the element. In the step of forming the component, the second thin films GI2, GE, and PE are patterned in a state where the inner surface of the mark MK is covered with the protective film RS2.
[Selection] Figure 15

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and a semiconductor substrate, and more particularly, to a manufacturing method of a semiconductor device using an alignment mark, and a semiconductor device and a semiconductor substrate formed by the manufacturing method.

  With the miniaturization of semiconductor integrated circuits, the size of each part of a semiconductor element constituting the semiconductor integrated circuit is being reduced. Therefore, for example, as described in Non-Patent Document 1 below, when the gate electrode is processed using a normal photolithography, so-called twice processing may be performed.

C.Auth, 33 others, “45 nm High-k + Metal Gate Strain-Enhanced Transistors”, 2008 Symposium on VLSI Technology Digest of Technical Papers, USA, IEEE, 2008, p. 128-129

  Specifically, in the two-time processing of Non-Patent Document 1, only a pattern in which a plurality of gate electrodes are continuous in a plan view is formed in the first processing. Thereafter, in the second processing, in order to form the gate electrode of each semiconductor element, the pattern formed in the first processing is cut so as to be a gate electrode for each adjacent semiconductor element. In this way, even when the distance between a pair of adjacent gate electrodes is reduced due to miniaturization, each gate electrode has a sharp end with a square shape without rounding the end in plan view. It is formed to become.

  However, in the above method, during the first processing (etching) of the conductive film constituting the gate electrode, the dielectric film constituting the inner surface of the mark used for alignment during the processing of the gate electrode is etched. Or foreign matter as a residue may adhere to the inner surface of the mark. In this situation, if the conductive film is processed a second time to form the final shape of the gate electrode, the substrate underlying the dielectric film is etched or reacted with the etching material. The foreign matter may be altered. If the foreign matter is altered, it may be difficult to remove it. Even if such etching of the base substrate or foreign matter occurs in the mark forming portion, if it goes around the region where the element is formed, the characteristics of the element may be deteriorated.

  The present invention has been made in view of the above problems. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing etching in an unintended region and generation of foreign matters even when a miniaturized semiconductor element is formed by the above-described two-time processing. . Another object is to provide a semiconductor device or a semiconductor substrate using the manufacturing method.

A manufacturing method of a semiconductor device according to an embodiment of the present invention includes the following steps.
First, the first thin film and the second thin film are formed in this order on the main surface of the semiconductor substrate. Of the main surface, the second thin film in the peripheral region of the element formation region where the element is formed is patterned. While using the mark formed in the patterning step for alignment, the second thin film in the element formation region is patterned to form a component part of the element. In the patterning step, at least a part of the second thin film in a region sandwiched between a pair of adjacent elements in the element formation region is removed. In the step of forming the component, the second thin film is patterned in a state where the inner surface of the mark is covered with a protective film.

  According to the first embodiment, the second thin film forming the component part of the element is patterned in a state where the inner surface of the mark is covered with the protective film. For this reason, when the 2nd thin film which forms the structure part of an element is patterned, it is suppressed that the inner surface of a mark receives the etching material of a 2nd thin film. For this reason, generation | occurrence | production of malfunctions, such as a base substrate being etched or a foreign material of an inner surface changing, can be suppressed, and the characteristic deterioration of the area | region in which an element is formed is suppressed.

1 is a schematic plan view showing a state of a wafer in a semiconductor device according to the present embodiment. FIG. 2 is a schematic enlarged plan view of a region surrounded by a round dotted line “II” in FIG. 1 in the first embodiment. It is a schematic sectional drawing in the part which follows the III-III line of FIG. FIG. 5 is a schematic plan view showing a more specific first example of marks formed in the first embodiment. It is a schematic sectional drawing in the part which follows the VV line of FIG. 6 is a schematic plan view showing a second more specific example of the mark formed in the first embodiment. FIG. It is a schematic sectional drawing in the part which follows the VII-VII line of FIG. FIG. 5 is a schematic plan view showing a first step of the method for manufacturing the semiconductor device in the first embodiment shown in FIG. It is a schematic sectional drawing in the part which follows the IX-IX line of FIG. 7 is a schematic plan view showing a second step of the method for manufacturing the semiconductor device in the first embodiment. FIG. It is a schematic sectional drawing in the part which follows the XI-XI line of FIG. 7 is a schematic plan view showing a third step of the method for manufacturing the semiconductor device in the first embodiment. FIG. It is a schematic sectional drawing in the part which follows the XIII-XIII line | wire of FIG. FIG. 10 is a schematic plan view showing a fourth step of the method for manufacturing the semiconductor device in the first embodiment. It is a schematic sectional drawing in the part which follows the XV-XV line | wire of FIG. FIG. 10 is a schematic plan view showing a fifth step of the method for manufacturing the semiconductor device in the first embodiment. It is a schematic sectional drawing in the part which follows the XVII-XVII line of FIG. It is a 1st top view explaining the processing method of a gate electrode common to Embodiment 1 and a comparative example. It is a 2nd top view explaining the processing method of a gate electrode common to Embodiment 1 and a comparative example. It is a 3rd top view explaining the processing method of a gate electrode common to Embodiment 1 and a comparative example. FIG. 14 is a schematic plan view showing a fourth step following the step of FIGS. 12 and 13 in the method for manufacturing a semiconductor device in the comparative example of the present invention. It is a schematic sectional drawing in the part which follows the XXII-XXII line | wire of FIG. It is a schematic plan view which shows the 5th process of the manufacturing method of the semiconductor device in the comparative example of this invention. It is a schematic sectional drawing in the part which follows the XXIV-XXIV line | wire of FIG. It is a schematic plan view which shows the 6th process of the manufacturing method of the semiconductor device in the comparative example of this invention. It is a schematic sectional drawing in the part which follows the XXVI-XXVI line of FIG. FIG. 3 is a schematic enlarged plan view showing a modified example different from FIG. 2 in the region surrounded by a round dotted line “II” in FIG. 1. It is a schematic sectional drawing in the part which follows the XXVIII-XXVIII line | wire of FIG. FIG. 30 is a schematic plan view showing a fourth step following the step of FIGS. 8 and 9 in the method for manufacturing the semiconductor device in the modification example of the present embodiment shown in FIG. 27; It is a schematic sectional drawing in the part which follows the XXX-XXX line of FIG. It is a schematic plan view which shows the 5th process of the manufacturing method of the semiconductor device in the modification of this invention. It is a schematic sectional drawing in the part which follows the XXXII-XXXII line | wire of FIG. FIG. 8 is a schematic enlarged plan view of a region surrounded by a round dotted line “II” in FIG. 1 in the second embodiment. It is a schematic sectional drawing in the part which follows the XXXIV-XXXIV line | wire of FIG. FIG. 10 is a schematic plan view showing a more specific example of marks formed in the second embodiment. It is a schematic sectional drawing in the part which follows the XXXVI-XXXVI line of FIG. FIG. 34 is a schematic plan view showing a first step of the method for manufacturing the semiconductor device in the second embodiment shown in FIG. 33. It is a schematic sectional drawing in the part which follows the XXXVIII-XXXVIII line | wire of FIG. FIG. 11 is a schematic plan view showing a second step of the method for manufacturing a semiconductor device in the second embodiment. It is a schematic sectional drawing in the part which follows the XL-XL line | wire of FIG. FIG. 10 is a schematic plan view showing a third step in the method for manufacturing a semiconductor device in the second embodiment. It is a schematic sectional drawing in the part which follows the XLII-XLII line | wire of FIG. 12 is a schematic plan view showing a fourth step of the method for manufacturing the semiconductor device in the second embodiment. FIG. It is a schematic sectional drawing in the part which follows the XLIV-XLIV line | wire of FIG. FIG. 10 is a schematic plan view showing a fifth step of the method for manufacturing the semiconductor device in the second embodiment. It is a schematic sectional drawing in the part which follows the XLVI-XLVI line | wire of FIG. FIG. 10 is a schematic plan view showing a sixth step of the method for manufacturing the semiconductor device in the second embodiment. It is a schematic sectional drawing in the part which follows the XLVIII-XLVIII line | wire of FIG. FIG. 6 is a schematic enlarged plan view of a region surrounded by a round dotted line “II” in FIG. 1 in the third embodiment. It is a schematic sectional drawing in the part which follows the LL line of FIG. FIG. 11 is a schematic plan view showing a more specific example of marks formed in the third embodiment. It is a schematic sectional drawing in the part which follows the LII-LII line | wire of FIG. FIG. 50 is a schematic plan view showing a first step of the method for manufacturing the semiconductor device in the third embodiment shown in FIG. 49. It is a schematic sectional drawing in the part which follows the LIV-LIV line | wire of FIG. FIG. 11 is a schematic plan view showing a second step of the method for manufacturing a semiconductor device in the third embodiment. It is a schematic sectional drawing in the part which follows the LVI-LVI line of FIG. 12 is a schematic plan view showing a third step of the method for manufacturing the semiconductor device in the third embodiment. FIG. It is a schematic sectional drawing in the part which follows the LVIII-LVIII line of FIG. FIG. 10 is a schematic plan view showing a fourth step of the method for manufacturing the semiconductor device in the third embodiment. It is a schematic sectional drawing in the part which follows the LX-LX line | wire of FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
First, a semiconductor device in a wafer state will be described as this embodiment.

  Referring to FIG. 1, a plurality of chip regions IMC and dicing line regions DLR are formed on a semiconductor wafer SW formed in the present embodiment. The semiconductor wafer SW includes a semiconductor substrate made of a semiconductor crystal such as silicon. The conductivity type of the impurity in the semiconductor substrate may be so-called n-type or p-type. Each of the plurality of chip regions IMC here has a rectangular planar shape and is arranged in a matrix.

  Referring to FIGS. 1 and 2, each of a plurality of chip regions IMC is an element formation region, and a semiconductor element TM such as a MIS (Metal Insulator Semiconductor) transistor or a diode is formed in the element formation region. Each of the plurality of dicing line regions DLR is a region used to divide the semiconductor wafer SW into semiconductor chips composed of a plurality of chip regions IMC. The dicing line region DLR is a region including a mark formation region (peripheral region of the element formation region), and is used for determining (positioning) a patterning position when a semiconductor element such as a MIS transistor is formed by photolithography. Marks are formed.

  2 and 3, semiconductor substrate SUB is a base substrate of semiconductor wafer SW in FIG. On one main surface (upper side in FIG. 3) of the semiconductor substrate SUB, an isolation insulating film SIF made of, for example, a silicon oxide film is formed. The element formation region IMC and the mark formation region DLR of the semiconductor substrate SUB are separated from each other in plan view by the isolation insulating film SIF. In the element formation region IMC, a plurality of semiconductor elements TM formed at intervals from each other in plan view are separated from each other in plan view by the isolation insulating film SIF.

  When the semiconductor element TM is a MIS transistor, the MIS transistor TM includes a channel region, a source region SO as a pair of impurity regions, a drain region DR, a gate insulating film GI1, a dielectric film GI2, and a metal film GE. A polycrystalline silicon film PE.

  The source region SO and the drain region DR are formed on one main surface of the semiconductor substrate SUB at a distance from each other. For example, when the semiconductor substrate SUB is made of an n-type silicon single crystal and the transistor TM is a so-called n-channel transistor, the source region SO and the drain region DR are arranged on one main surface of the semiconductor substrate SUB. It is preferably formed in the mold well region WL.

  On the well region WL, a gate insulating film GI1 (first thin film), a dielectric film GI2, a metal film GE, and a polycrystalline silicon film PE are stacked in this order. The gate insulating film GI1 is formed so as to cover almost the entire region where the isolation insulating film SIF is not formed. The laminated structure (second thin film) of the dielectric film GI2, the metal film GE, and the polycrystalline silicon film PE has a smaller area in plan view than the gate insulating film GI1. The laminated structure of the dielectric film GI2, the metal film GE, and the polycrystalline silicon film PE constitutes a gate electrode (component) of the semiconductor element TM.

  A plurality of gate electrodes arranged in the element formation region IMC have, for example, a long rectangular shape in plan view. If attention is paid to a pair of adjacent elements TM, the end portions in the longitudinal direction of the gate electrodes are arranged to face each other. Accordingly, the longitudinal directions (extending directions) of the gate electrodes of the plurality of elements TM adjacent in the vertical direction in FIG. 2 are substantially parallel to each other. In addition, the gate electrodes of the plurality of elements TM adjacent in the vertical direction in FIG. 2 are all arranged on a substantially straight line. In other words, the gate electrodes of a plurality of elements TM adjacent in the vertical direction in FIG. 2 have substantially the same position (coordinates) in the horizontal direction in FIG.

  Also in the mark formation region DLR, there is a region covered with the dielectric film GI1 without being formed with the isolation insulating film SIF in a part in plan view. Also in the mark formation region, a stacked structure (consisting of the dielectric film GI2, the metal film GE, and the polycrystalline silicon film PE) similar to the gate electrode of the semiconductor element TM is formed. A groove MK is formed in a part of the mark formation region in plan view. The groove part MK is an area for forming a groove shape lacking the laminated structure of the mark formation area. Here, as an example, a cross-shaped groove MK (mark) is shown in which two straight lines are substantially orthogonal to each other in plan view. The groove MK is used as an alignment mark for patterning when the semiconductor element TM is formed.

  4 to 7, mark MK shown in FIGS. 2 and 3 has a stacked structure of dielectric film GI2, metal film GE, and polycrystalline silicon film PE, which is the same as the gate electrode of MIS transistor TM. It is formed by the wall surface. 4 to 7 show a mode in which a resist RS used in an element formation region patterning step (so-called second processing) to be described later is applied so as to cover the inner surface of the previously formed mark MK. Yes. Further, the resist RS covers a region having an area larger than the area of the mark MK in plan view (the resist RS also covers a part of the region outside the mark MK).

  4 and 5, mark MK is formed on isolation insulating film SIF on the main surface of semiconductor substrate SUB. On the other hand, in FIGS. 6 and 7, the mark MK is formed on the dielectric film GI1 on the main surface of the semiconductor substrate SUB. Thus, the bottom surface of the mark MK may be the isolation insulating film SIF or the dielectric film GI1. In the present embodiment, in order to explain this, for example, FIG. 2 and FIG. 3 show a mode in which the mark MK is formed so as to straddle both the silicon oxide film GI1 and the isolation insulating film SIF. Yes.

  The semiconductor element SW and the mark MK coexist before the semiconductor wafer SW is divided into individual semiconductor chips IMC (semiconductor devices) by the dicing process. Next, with reference to FIGS. 8 to 17, the manufacturing method of the semiconductor chip IMC (semiconductor wafer SW) of the present embodiment having the above-described configuration is focused on a single chip region IMC and a dicing line region DLR. While explaining.

  Referring to FIGS. 8 and 9, first, a semiconductor substrate SUB made of a single crystal such as silicon or germanium is prepared. This semiconductor substrate SUB is a substrate used as a base of the semiconductor wafer SW of FIG.

  Next, in both the element formation region and the mark formation region, an isolation insulating film SIF is formed on one main surface of the semiconductor substrate SUB. Specifically, first, a silicon oxide film or a silicon nitride film formed on one main surface of the semiconductor substrate SUB is patterned by ordinary photolithography. Using the pattern to be formed as a mask, the substrate SUB is partially removed by, for example, a dry etching technique to form a groove. Next, after thermally oxidizing the inner wall surface of the groove, an isolation insulating film SIF made of a silicon oxide film is formed by, for example, a CVD (Chemical Vapor Deposition) method so as to fill the inside of the groove.

  The isolation insulating film SIF electrically isolates a plurality of semiconductor elements TM to be formed later, or electrically isolates the element formation region IMC and the mark formation region DLR from each other. Isolation insulating film SIF is patterned by, for example, ordinary photolithography so as to be disposed only in a necessary region on the main surface of semiconductor substrate SUB. Specifically, for example, the isolation insulating film SIF is preferably formed in a region other than a region where the semiconductor element TM is formed later. In the mark formation region DLR, for example, the isolation insulating film SIF can be formed in an arbitrary region such as a region where a mark is to be formed later and its periphery.

  After the isolation insulating film SIF is formed, a well region WL is formed in a region where the semiconductor element TM is formed. The well region WL is formed using ordinary photolithography and ion implantation techniques. For example, when the semiconductor substrate SUB is made of an n-type semiconductor crystal, a well region WL as a p-type impurity region is formed.

  Referring to FIGS. 10 and 11, on the main surface of semiconductor substrate SUB on which isolation insulating film SIF and well region WL are formed, dielectric film GI1 (first thin film), dielectric film GI2, and metal film GE, polycrystalline silicon film PE (second thin film) are laminated in this order. Dielectric film GI1 is preferably an insulating film made of, for example, a silicon oxide film, and dielectric film GI2 is preferably made of an insulating film made of, for example, a silicon nitride film. The metal film GE is preferably a thin film made of, for example, aluminum or tungsten.

  In FIG. 11, the dielectric film GI1 is formed only in a region where the isolation insulating film SIF is not formed, for example, by normal photolithography and etching. The dielectric film GI2 and the thin films on the dielectric film GI2 are formed including a region overlapping the isolation insulating film SIF in plan view. However, the dielectric film GI1 may also be formed including a region overlapping the isolation insulating film SIF in plan view, like the dielectric film GI2. In FIG. 11, the uppermost surface (uppermost surface in FIG. 11) of isolation insulating film SIF extends, for example, above the uppermost surface of gate insulating film GI1 on well region WL. However, if the isolation insulating film SIF can secure the function of electrically isolating the regions, the uppermost surface of the isolation insulating film SIF and the uppermost surface of the well region WL have substantially the same height in the vertical direction in FIG. Also good.

  Referring to FIGS. 12 and 13, for example, a photosensitizer such as photoresist RS1 is applied onto polycrystalline silicon film PE, and normal photolithography and etching (patterning) are performed. By this process, the dielectric film GI2, the metal film GE, and the polycrystalline silicon film PE in a part of the mark formation region DLR are removed, and a groove-shaped mark MK is formed. Here, the bottom surface of the mark MK (the lowermost surface of the mark MK in FIG. 13) is the same material as the active region corresponding to the channel region of the semiconductor element TM, that is, the dielectric film GI1 made of a silicon oxide film. Good. Alternatively, the bottom surface of the mark MK may be an isolation insulating film SIF made of a silicon oxide film. In order to show this in FIGS. 12 and 13, the left half of the bottom surface of the mark MK is the dielectric film GI1, and the right half is the isolation insulating film SIF.

  During patterning for forming the mark MK, the dielectric film GI2, the metal film GE, and the polycrystalline silicon film PE are removed in a part of the element formation region IMC at the same time, leaving the dielectric film GI1 at the bottom. Thus, the trench part TR is formed. The trench part TR is preferably formed in a region sandwiched between regions where a pair of semiconductor elements TM will be formed later. More specifically, for example, when the semiconductor element TM is a MIS transistor, the trench part TR may be formed so as to include a region sandwiched between the end portions of the gate electrode of the MIS transistor extending in plan view. preferable. In the MIS transistor to be formed, the left-right direction in FIG. 12 is the longitudinal direction, and a gate electrode is formed at the center in the longitudinal direction. Therefore, the trench part TR is formed so as to extend in the left-right direction in FIG. 12 in a region sandwiched between regions where a pair of MIS transistors adjacent in the vertical direction in FIG. 12 are formed.

  Referring to FIGS. 14 and 15, a photoresist RS2 for forming a constituent portion as a gate electrode is applied, and normal photolithography and etching are performed. By this treatment, it is preferable that the resist RS2 pattern (protective film) is formed so as to cover the region where the gate electrode of the MIS transistor TM is to be formed and the inner surface of the mark MK. . More specifically, the pattern of the resist RS2 is preferably arranged so as to fill, for example, the mark MK in the mark formation region DLR in addition to the region where the gate electrode is to be formed. In this way, the resist RS2 can cover the inner surface of the mark MK, that is, the side surface inside the mark MK (the side surface extending in the vertical direction from the polycrystalline film PE to the dielectric film GI2 in FIG. 15) and the bottom surface. . The protective film (resist RS2) protects the inner surface of the mark MK from being exposed.

  In order for the resist RS2 to cover almost the entire inner surface of the mark MK, it is preferable to form the resist RS2 so as to have an area larger than the area of the mark MK in plan view. The resist RS2 that protects the inner surface of the mark MK may be formed in a region having an area larger than the area of the mark MK in plan view, as shown in FIG. In this case, the pattern of the resist RS2 is formed so as to cover at least part of the outer periphery of the mark MK in plan view while filling the inside of the mark MK so as to cover the inner surface of the mark MK. In this way, the resist RS2 pattern can be formed so as to reliably cover the inside of the mark MK. However, as will be described later, for example, it may be formed only in a region overlapping the mark MK in plan view.

Referring to FIG. 16 and FIG. 17, the mark MK is covered with the resist pattern RS2,
Etching is performed using the resist pattern RS2 formed in the element formation region IMC as a mask. By this process, the dielectric film GI2 and the like in the element formation region IMC are patterned, and a gate electrode is formed. This gate electrode has a laminated structure of a dielectric film GI2, a metal film GE, and a polycrystalline silicon film PE. The mode of the mark formation region shown in FIGS. 16 and 17 corresponds to the mark formation region shown in FIGS. 4 and 5.

  Here, patterning for forming a gate electrode is performed in a state where the resist pattern RS2 in the mark formation region covers the inner surface of the mark MK. Thereafter, the source region SO and the drain region DR are formed inside the well region WL by an ion implantation technique using a new mask.

  By removing the resist pattern RS2, the semiconductor element TM and the mark MK shown in FIGS. 2 and 3 are formed. In addition, although illustration is omitted, actually, a semiconductor having a plurality of semiconductor elements having a configuration in which wirings, insulating films, and the like are further formed in the semiconductor element TM of the embodiment shown in FIGS. A substrate (semiconductor wafer SW: see FIG. 1) is formed. Further, the semiconductor wafer SW is diced in the dicing line region DLR, thereby forming semiconductor chips as individual chip regions IMC.

  Next, the effect of this Embodiment is demonstrated, referring the comparative example of FIGS. First, a gate electrode processing method common to the present embodiment and the comparative example will be described with reference to FIGS.

  18 to 20, only the top view of the element formation region is shown. Referring to FIG. 18, semiconductor element TM is a MIS transistor having the same configuration (laminated structure including polycrystalline silicon film PE) as semiconductor element TM of the present embodiment shown in FIGS. In FIG. 18, as in the present embodiment, the gate electrodes of the plurality of semiconductor elements TM are arranged so as to be substantially parallel to each other and on a substantially straight line. An isolation insulating film SIF that electrically isolates the elements TM is formed around the semiconductor element TM.

  In particular, if the semiconductor integrated circuit is further miniaturized and the distance between the end portions in the longitudinal direction of a pair of adjacent gate electrodes in FIG. 18 is reduced, the region sandwiched between the end portions is accurately processed by ordinary photoengraving. It becomes difficult to perform the etching process. As a countermeasure, referring to FIG. 19, first, a thin film having a stacked structure that forms a gate electrode is etched so as to form a trench TR including a region sandwiched between regions where a gate electrode is formed. Thereafter, referring to FIG. 20, the stacked structure in the other region is etched away so that only the region for forming the gate electrode remains. The gate electrode (polycrystalline silicon film PE) shown in FIG. 20 is formed by performing so-called twice processing of the process shown in FIG. 19 and the process shown in FIG. Also in the present embodiment, as shown in FIGS. 12, 14, and 16, the same processing method (so-called two-time processing) as in FIGS. 18 to 20 is used.

  Next, a manufacturing method including a mark formation region in a comparative example of the present embodiment will be described with reference to FIGS. In the comparative example, after the same processing as that of the present embodiment shown in FIGS. 8 to 13 is performed, the processing shown in FIGS. 21 to 26 is performed. Accordingly, also in the comparative example, the formation of the groove portions TR and MK (see FIGS. 12 and 13) as the first machining out of the two machinings shown in FIGS. 12 and 13 and the gate as the second machining. An electrode is formed (FIGS. 21 to 26).

  The steps of FIGS. 21 and 22 differ from the steps of FIGS. 14 and 15 in that the resist RS2 is not filled in the groove of the mark MK. That is, in this comparative example, the resist RS2 used for patterning using a conductive film such as the polycrystalline silicon film PE as a gate electrode is entirely removed by etching in the mark formation region. For this reason, when patterning the gate electrode, the inner surface of the mark MK is exposed. Similarly, in the process of FIGS. 23 and 24, the resist RS2 pattern is not formed on the inner surface of the mark MK as compared with FIGS. 16 and 17, so that the laminated structure such as the thin film PE in the mark formation region DLR is etched. Are different in that they are all removed. 25 and FIG. 26 differ from FIGS. 2 and 3 in that a laminated structure is not formed in the mark formation region DLR.

  Here, the mark MK formed in the step (see FIGS. 12 and 13) performed before the step shown in FIGS. 21 and 22 is normally (planar view) in order to ensure good visibility (semiconductor substrate). The width (in the direction along the main surface of the SUB) is relatively large at 0.1 μm or more. When the groove portion MK having a relatively large width is formed as described above, an over-etched portion OE and a foreign matter FRN may be formed on the inner surface of the groove portion MK. The over-etched portion OE means a region where a part of the dielectric film GI1 constituting the bottom surface of the mark MK (which should not be etched originally) is etched together with the dielectric film GI2 when the mark MK is formed. The foreign substance FRN is a residue such as an etching product or a photoresist that adheres on the isolation insulating film SIF constituting the bottom surface of the mark MK when the mark MK is formed in FIGS. .

  In the comparative example of FIGS. 21 to 26, etching for forming the gate electrode is performed in a state where the inner surface of the mark MK is not protected by the resist (protective film). For this reason, the etching is performed in a state where the over-etched portion OE and the foreign matter FRN generated during the formation of the mark MK are exposed.

  If the gate electrode shown in FIGS. 23 and 24 is patterned with the overetched portion OE exposed, the semiconductor existing under the overetched dielectric film GI1 by the etching gas or etchant used at that time. The substrate SUB may also be etched. If the gate electrode shown in FIGS. 23 and 24 is patterned in a state where the foreign matter FRN formed on the inner surface of the mark MK is exposed, the foreign matter FRN reacts with the etching gas or etchant used at that time. May be altered. The altered foreign substance FRN is difficult to remove together with the resist RS2 even in the step shown in FIGS. 25 and 26 (removing the pattern of the resist RS2).

  Further, when the foreign matter FRN remaining in the steps shown in FIGS. 25 and 26 is peeled off in the subsequent steps, the foreign matter FRN may enter the element formation region, thereby possibly affecting the performance of the element TM. is there. Even when a part of the semiconductor substrate SUB underneath is etched by the over-etching portion OE, the foreign matter formed due to the over-etching portion may adhere to the element formation region. .

  Therefore, as in the present embodiment shown in FIGS. 14 to 17, in the second processing among the above two processings, the inner surface of the mark MK is covered with the same resist RS2 as the resist RS2 used for etching the gate electrode. . If the gate electrode is etched in this state, the over-etched portion OE and the foreign matter FRN on the inner surface of the mark MK are not exposed to the etching gas or the etchant used for the etching. This is because the over-etched portion OE and the foreign matter FRN are protected by the resist RS2. Therefore, for example, it is possible to reduce the possibility that the semiconductor substrate SUB under the overetched portion OE that has etched the dielectric film GI1 is etched. Therefore, the generation of foreign matter due to the etching of the semiconductor substrate SUB can be suppressed.

  Further, the foreign substance FRN formed in the groove MK at the time of the first processing (when the groove MK is formed) of the two times processing is changed by the etching gas or the etching liquid forming the gate electrode, and is difficult to remove. The possibility of becoming can be reduced. Therefore, when removing the resist RS2 shown in FIGS. 16 to 17, it becomes easy to remove the foreign substance FRN at the same time.

  As described above, if the mark MK is protected by the resist RS2 as in the present embodiment, it is possible to suppress the occurrence of a defect that foreign matter adheres to the element formation region and improve the performance of the formed semiconductor element (semiconductor device). Can be made.

  In particular, if the semiconductor element TM is miniaturized, for example, the distance between a pair of elements TM adjacent in the vertical direction in FIG. 2 (the distance between the end portions of the gate electrode) is also reduced. In this case, the width of the trench TR formed in the first processing shown in FIG. 12 (the vertical width in the figure) is also reduced to less than 0.1 μm. In this case, the possibility of occurrence of overetching OE and foreign matter FRN like the inner surface of the mark MK on the inner surface of the trench part TR is reduced. Therefore, it is not necessary to protect the inner surface of the trench part TR with the resist RS2 during the second processing. However, when the width is 0.1 μm or more, it is preferable to protect the trench part TR in the element formation region using the resist RS2 as in the case of the mark MK. In each drawing explaining the manufacturing process of FIGS. 8 to 17, it is exaggerated that the width of the mark MK is larger than the groove part TR between the elements TM.

  Next, although partially overlapping with the above description, a modified example of the resist RS2 that covers the inner surface of the mark MK in the present embodiment will be described with reference to FIGS.

  Referring to FIGS. 27 and 28, these figures are different from FIGS. 2 and 3 in the region other than the region overlapping with the mark MK in the mark forming region such as the polycrystalline silicon film PE. The difference is that a conductor film is not formed. That is, FIGS. 27 and 28 have the same configuration as that of FIGS. 2 and 3 except for the points described above.

  The structure of the element formation region and the mark formation region shown in FIGS. 27 and 28 is basically formed by the same processes as those in FIGS. Referring to FIGS. 29 and 30, the steps shown in these drawings are basically the same as the steps shown in FIGS. 14 and 15 described above. However, in FIG. 29 and FIG. 30, the pattern of the resist RS2 used for the second processing for forming the gate electrode of the element TM is formed only in the region overlapping the mark MK in plan view in the mark formation region. . In this respect, the steps of FIGS. 29 and 30 are different from the steps of FIGS.

  Therefore, referring to FIGS. 31 and 32, if etching is performed using the resist pattern RS2, the laminated structure of the conductive film such as the polycrystalline silicon film PE remains only in the region where the gate electrode is formed, and the mark formation region All are removed. Along with this, the mark MK disappears from the main surface of the semiconductor substrate SUB. In this respect, the steps of FIGS. 31 and 32 are different from the steps of FIGS.

  The mark MK is used for patterning when the element TM is formed. Therefore, if the patterning is completed, there is no problem even if the mark MK disappears from the mark formation region. Even in the case where the steps shown in FIGS. 29 to 32 are used, it is possible to suppress the occurrence of defects caused by foreign matters attached to the inner surface of the mark MK.

(Embodiment 2)
This embodiment differs from the first embodiment in the type of thin film that is processed twice and the manufacturing method. Hereinafter, the configuration of the present embodiment will be described.

  Referring to FIGS. 33 and 34, in the present embodiment, so-called twice processing is performed to form a pattern of isolation insulating film SIF in the element formation region. More specifically, as a result of forming a plurality of patterns of the dielectric film GI1 arranged in the element formation region of FIGS. 33 and 34 by the two-time processing, an isolation insulating film is formed in a region sandwiched between the patterns of the dielectric film GI1. A SIF is formed.

  The pattern of the plurality of dielectric films GI1 in the element formation region of FIGS. 33 and 34 constitutes the semiconductor element TM (see FIG. 2), similar to the dielectric film GI1 in the element formation region of the first embodiment. There may be. Therefore, as shown in FIG. 34, a well region WL may be formed below the dielectric film GI1.

  After the desired isolation insulating film SIF pattern is formed in the element formation region, the mark disappears in the mark formation region as a result of filling the isolation insulating film SIF in the groove for forming the cross-shaped mark. That is, the uppermost surfaces of both the element formation region and the mark formation region are substantially flat surfaces due to the isolation insulating film SIF and the dielectric film GI1. However, this is merely an example, and a step may be formed on the surface of the isolation insulating film SIF and the dielectric film GI1, as will be described later.

  Referring to FIGS. 35 and 36, in the present embodiment, mark MK formed for performing processing twice is formed of silicon nitride film NF (disappearing in FIGS. 33 and 34). The The mark MK is formed on the dielectric film GI1 on the main surface of the semiconductor substrate SUB. The silicon nitride film NF is processed twice in the element formation region, whereby the pattern of the dielectric film GI1 arranged in the element formation region of FIGS. 33 and 34 is processed twice.

  Since the configuration of the present embodiment is substantially the same as the configuration of the first embodiment except for the above, the same elements as those in the first embodiment are denoted by the same reference numerals in FIGS. Do not repeat the explanation.

  Next, a method for manufacturing the semiconductor chip IMC (semiconductor wafer SW) of the present embodiment having the above-described configuration will be described with reference to FIGS.

  Referring to FIGS. 37 and 38, first, a semiconductor substrate SUB made of a single crystal such as silicon or germanium is prepared. This semiconductor substrate SUB is the same as the semiconductor substrate SUB shown in FIGS. A dielectric film GI1 (first thin film) and a silicon nitride film NF (second thin film) are stacked in this order on the main surface of the semiconductor substrate SUB. Dielectric film GI1 is preferably an insulating film made of, for example, a silicon oxide film.

  Referring to FIGS. 39 and 40, for example, a photosensitizer such as photoresist RS1 is applied onto silicon nitride film NF, and normal photolithography and etching (patterning) are performed. By this process, the silicon nitride film NF in a part of the mark formation region DLR is removed, and a groove-shaped mark MK is formed. This corresponds to the first processing of the two processing of the silicon nitride film NF.

  At the time of patterning for forming the mark MK, the silicon nitride film NF is also removed in a part of the element formation region IMC, and the trench TR is formed leaving the dielectric film GI1 at the bottom. However, when forming the trench part TR, the dielectric film GI1 at the bottom of the trench part TR and a part of the semiconductor substrate SUB may be etched. This trench part TR is preferably formed in a region sandwiched between a plurality of semiconductor elements TM to be formed later, for example, as shown in FIGS. 2 and 3 of the first embodiment.

  Referring to FIGS. 41 and 42, a photoresist RS2 for forming a region for forming the pattern of the isolation insulating film is applied, and normal photolithography and etching are performed. By this treatment, it is preferable that the resist RS2 pattern (protective film) is formed so as to cover the region other than the region where the pattern of the isolation insulating film is to be formed and the inner surface of the mark MK. More specifically, the pattern of the resist RS2 is arranged so as to fill, for example, the mark MK in the mark formation region DLR in addition to the region other than the region where the isolation insulating film pattern is to be formed later in the element formation region. It is preferred that In this way, the resist RS2 can cover the inner surface of the mark MK, that is, the side surface inside the mark MK (the side surface extending in the vertical direction of the silicon nitride film NF in FIG. 42) and the bottom surface. The protective film (resist RS2) protects the inner surface of the mark MK from being exposed.

  Referring to FIGS. 43 and 44, etching is performed using resist pattern RS2 formed in element formation region IMC as a mask while covering mark MK with resist pattern RS2. By this process, the silicon nitride film NF in the element formation region IMC is patterned. The steps of FIGS. 41 to 44 correspond to the second process of the two processes of the silicon nitride film NF. The mode of the mark formation region shown in FIGS. 43 and 44 corresponds to the mark formation region shown in FIGS.

  Referring to FIGS. 45 and 46, after resist pattern RS2 is removed, dielectric film GI1 in the region where silicon nitride film NF is removed in FIGS. 43 and 44 and a part of semiconductor substrate SUB therebelow are formed. It is removed by etching. This etching is performed using the pattern of the silicon nitride film NF as a mask to form a groove-shaped etching region ET.

  47 and 48, isolation insulating film SIF is formed to fill etching region ET. The isolation insulating film SIF is preferably formed by a CVD method after forming a thin silicon oxide film by a thermal oxidation method. Next, the formed silicon oxide film is planarized by, for example, CMP (Chemical Mechanical Polishing). At this time, since the silicon nitride film NF is harder than the silicon oxide film and difficult to be polished by CMP, the silicon oxide film GI1 under the silicon nitride film NF can be prevented from being polished.

  After the isolation insulating film SIF is polished, the silicon nitride film used as the mask (protective film for the dielectric film GI1) as described above is removed, and the modes shown in FIGS. 47 and 48 are obtained. These correspond to the embodiment shown in FIGS. 8 and 9 in which the isolation insulating film SIF is formed on the semiconductor substrate SUB. 8, 9, 47, and 48, the surface of the isolation insulating film SIF is raised upward with respect to the surface of the semiconductor substrate SUB because the silicon nitride film is not polished during the above CMP, and the silicon nitride film This is because the isolation insulating film SIF remains on the upper side by the thickness of. However, by adjusting the thickness of the silicon nitride film NF, etc., the step on the surface of the isolation insulating film SIF and the dielectric film GI1 can be made as small as possible as shown in FIGS. Thereafter, similarly to FIGS. 8 and 9, if necessary, well region WL is formed in a region where semiconductor element TM is to be formed later.

Next, the effect of this Embodiment is demonstrated.
Also in the present embodiment, the mark MK is filled with the resist pattern RS2 when the silicon nitride film NF is processed twice in order to form the isolation insulating film SIF in the element formation region, as in the first embodiment. The second processing of the silicon nitride film NF is performed as it is. Therefore, as in the first embodiment, when the silicon nitride film NF is processed for the second time, the over-etched portion OE on the inner surface of the groove MK formed during the first processing over-etches the semiconductor substrate SUB. Generation of foreign matter can be suppressed. Further, it is possible to suppress the deterioration of the foreign matter on the inner surface of the groove MK formed during the first processing of the silicon nitride NF during the first processing. As described above, since the deterioration of the foreign matter is suppressed, the foreign matter can be easily removed.

  The second embodiment of the present invention is different from the first embodiment of the present invention only in each point described above. That is, the configuration, conditions, procedures, effects, and the like that have not been described above for the second embodiment of the present invention are all in accordance with the first embodiment of the present invention.

(Embodiment 3)
This embodiment differs from the first embodiment in the type of thin film that is processed twice. Hereinafter, the configuration of the present embodiment will be described.

  Referring to FIGS. 49 and 50, in the present embodiment, a wiring pattern (configuration part) that electrically connects a plurality of semiconductor elements TM (see FIGS. 2 and 3) formed in the element formation region. ) Is formed so-called twice. More specifically, a wiring pattern made of a laminated structure of metal films (laminated metal film) or the like arranged in a plurality of element formation regions in FIGS. 49 and 50 is formed by twice processing. At this time, the mark MK made of the wall surface of the laminated structure is formed in the mark formation region DLR. Here, the metal film constituting the wiring and the mark MK may be a single metal film or a laminated structure of metal films (laminated metal film). 49 and 50, the laminated metal film has a structure in which, for example, a laminated film MF1 in which a thin film of titanium and a thin film of titanium nitride are laminated, a thin film MF2 made of aluminum, and a laminated film MF1 are laminated in this order. It has become. The laminated metal film as the wiring is formed on the interlayer insulating film II made of, for example, a silicon oxide film. The interlayer insulating film II is a part of a stack that is stacked in a direction (vertical direction in FIGS. 49 to 50) that intersects the main surface of the semiconductor substrate SUB.

  Referring to FIGS. 51 and 52, in the present embodiment, mark MK formed for performing the two-time machining is formed by the wall surface of the laminated structure (laminated metal film) of the metal film. The mark MK is formed on the interlayer insulating film II on the main surface of the semiconductor substrate SUB similarly to the wiring pattern.

  Since the configuration of the present embodiment is substantially the same as the configuration of the first embodiment except for the above, the same elements as those in the first embodiment are denoted by the same reference numerals in FIGS. Do not repeat the explanation.

  Next, a method for manufacturing the semiconductor chip IMC (semiconductor wafer SW) of the present embodiment having the above-described configuration will be described with reference to FIGS.

  Referring to FIGS. 53 and 54, for example, a titanium / titanium nitride multilayer film MF1 and an aluminum film MF2 are formed on the main surface of interlayer insulating film II (first thin film) on semiconductor substrate SUB similar to that of the first embodiment. And a titanium / titanium nitride laminated film MF1 (second thin film) are laminated in this order. A laminate of these films is a laminated metal film that becomes a wiring pattern in the element formation region.

  Referring to FIGS. 55 and 56, for example, a photosensitive agent such as photoresist RS1 is applied on the uppermost titanium / titanium nitride laminated film MF1, and normal photolithography and etching (patterning) are performed. By this process, the laminated metal film in a part of the mark formation region DLR is removed, and a groove-shaped mark MK is formed. This corresponds to the first processing of the two processings of the laminated metal film.

  During the patterning for forming the mark MK, at the same time, also in the element formation region IMC, the laminated metal film is removed in a part of the region, and the trench TR is formed leaving the interlayer insulating film II at the bottom. The trench part TR is preferably formed in a region sandwiched between a plurality of laminated metal film patterns to be formed later.

  Referring to FIGS. 57 and 58, a photoresist RS2 for forming a wiring pattern is applied, and normal photolithography and etching are performed. By this processing, it is preferable that the pattern (protective film) of the resist RS2 is formed so as to cover the area overlapping the area where the wiring pattern is to be formed in plan view and the inner surface of the mark MK. More specifically, the pattern of the resist RS2 may be arranged so as to fill, for example, the mark MK in the mark formation region DLR in addition to the region where the wiring pattern connecting the semiconductor elements is to be formed. preferable. In this way, the resist RS2 can cover the inner surface of the mark MK, that is, the side surface inside the mark MK (the side surface extending in the vertical direction of the laminated metal film in FIG. 58) and the bottom surface. The protective film (resist RS2) protects the inner surface of the mark MK from being exposed.

  Referring to FIGS. 59 and 60, etching is performed using resist pattern RS2 formed in element formation region IMC as a mask while mark MK is covered with resist pattern RS2. By this process, the laminated metal film in the element formation region IMC is patterned. The process of FIGS. 57 to 60 corresponds to the second processing of the two processings of the laminated metal film. The form of the mark formation region shown in FIGS. 59 and 60 corresponds to the mark formation region shown in FIGS.

  Then, by removing the resist pattern RS2, the semiconductor element TM and the mark MK shown in FIGS. 49 and 50 are formed. Thereafter, through various post-processes, a semiconductor substrate (semiconductor wafer SW: see FIG. 1) having a plurality of semiconductor elements having a structure in which wirings, insulating films and the like are further formed is formed. Further, the semiconductor wafer SW is diced in the dicing line region DLR, thereby forming semiconductor chips as individual chip regions IMC.

  The third embodiment of the present invention is different from the first embodiment of the present invention only in each point described above. That is, the configuration, conditions, procedures, effects, and the like that have not been described above for the third embodiment of the present invention are all in accordance with the first embodiment of the present invention.

Next, the effect of this Embodiment is demonstrated.
Also in the present embodiment, as in the first embodiment, when the wiring pattern of the laminated metal film, for example, formed in the element formation region is processed twice, the mark MK remains filled with the resist pattern RS2. The second processing of the metal film is performed. For this reason, as in the first embodiment, the alteration of the foreign matter on the inner surface of the groove MK formed during the first processing can be suppressed during the second processing of the metal film. As described above, since the deterioration of the foreign matter is suppressed, the foreign matter can be easily removed.

  The third embodiment of the present invention is different from the first embodiment of the present invention only in each point described above. That is, the configuration, conditions, procedures, effects, and the like that have not been described above for the third embodiment of the present invention are all in accordance with the first embodiment of the present invention.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be used particularly advantageously in a method for manufacturing a semiconductor device using alignment marks.

  DLR dicing line region, DR drain region, ET etching region, FRN foreign matter, GE metal film, GI1 gate insulating film, GI2 dielectric film, II interlayer insulating layer, IMC chip region, MK mark, NF silicon nitride film, OE overetching Part, PE polycrystalline silicon film, RS, RS1, RS2 photoresist, SIF isolation insulating film, SO source region, SW semiconductor wafer, TM semiconductor element, TR trench, WL well region.

Claims (10)

Forming a first thin film and a second thin film in this order on the main surface of the semiconductor substrate;
Patterning the second thin film in a peripheral region of an element formation region where an element is formed on the main surface;
Using the mark formed in the patterning step for alignment, patterning the second thin film in the element formation region to form a component part of the element, and
In the patterning step, at least a part of the second thin film in a region sandwiched between a pair of adjacent elements in the element formation region is removed;
The method of manufacturing a semiconductor device, wherein in the step of forming the constituent part, the second thin film is patterned in a state where an inner surface of the mark is covered with a protective film.   The method of manufacturing a semiconductor device according to claim 1, wherein the mark has a width in the direction along the main surface of 0.1 μm or more. In the step of forming the component, the protective film is a resist material used for patterning to form the component.
3. The method of manufacturing a semiconductor device according to claim 1, wherein the component part is formed in a state where the resist material covers a region having an area equal to or larger than the area of the mark in plan view.   The method of manufacturing a semiconductor device according to claim 1, wherein the component is a gate electrode of the element.   The method for manufacturing a semiconductor device according to claim 1, wherein an isolation insulating film is formed in a region sandwiched between the elements.   The method for manufacturing a semiconductor device according to claim 1, wherein the first thin film is a silicon oxide film.   The method of manufacturing a semiconductor device according to claim 1, wherein the component is a wiring that electrically connects the elements, and the wiring is a stacked metal film in which a plurality of metal thin films are stacked.   The method of manufacturing a semiconductor device according to claim 7, wherein the first thin film is an interlayer insulating film that forms a stacked structure in which the first thin film is stacked in a direction intersecting the main surface of the semiconductor substrate.   A semiconductor device formed by the manufacturing method according to claim 1.   A semiconductor substrate on which a plurality of semiconductor devices formed by the manufacturing method according to claim 1 are formed.

Images