JP2012209339A - Fin type field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in which: a bulk region during operation requires complete depletion to reduce power consumption according to an operation principle of a fin type field effect transistor; and, as a result, variations in processes produce variations in bulk region to lead to variations in power consumption.SOLUTION: A fin type field effect transistor having a gate electrode for applying an electrical field to a channel region via a gate insulating film, includes a bulk electrode for applying predetermined electrical potential to a bulk region, separately from the gate electrode. This structure eliminates the need for keeping a width of a fin around a level of a width of a depletion layer, and allows power consumption to be reduced by using a substrate bias effect in which substrate electric potential is changed to change characteristics of a device.

Description

  The present invention relates to a MOS field effect transistor (hereinafter referred to as a MOSFET), and relates to a fin field effect transistor having an upright channel.

  Since electronic devices in recent years have been reduced in size and power consumption, there is a demand for miniaturization and lower power consumption in LSIs used therefor. In many cases, this has been dealt with by miniaturizing the size of a semiconductor element to be mounted according to a scaling rule.

The scaling law in the semiconductor industry means that if the MOSFET size and power supply voltage are multiplied by 1 / κ, the operation of the MOSFET is guaranteed, the switching speed is 1 / κ times, and the power consumption is 1 / κ ^2. This is a known law of doubling.

However, in order to maintain a constant performance under a lower power supply voltage, it is necessary to set the threshold voltage of the MOSFET low. For this purpose, it is necessary to reduce the thickness of the gate insulating film. However, the reduction in the thickness of the gate insulating film causes an increase in standby leakage current, resulting in an increase in power consumption of the LSI.
In recent LSIs, low power consumption is indispensable due to the trend toward miniaturization and low power consumption of electronic devices, and new semiconductor elements that enable low power consumption have been proposed. .

As one of representative examples of such a new semiconductor element, a fin-type field effect transistor has been proposed.
A fin-type field effect transistor is a MOSFET having an upright channel region. The standing channel region is provided with an insulating film over the semiconductor substrate, and a semiconductor layer (single crystal silicon material) formed thereover includes a source region, a drain region, and a bulk region (in which the channel region is formed). . Since the shape of this semiconductor layer resembles a fish fin, it is called a fin-type field effect transistor.

  Fin-type field effect transistors often have a structure in which a channel region is provided on a vertical end face of a semiconductor layer. For this reason, the vertical height of the semiconductor layer becomes the channel width of the MOSFET. A gate electrode is provided on the vertical end face of the semiconductor layer serving as the channel region.

  Since the fin-type field effect transistor has a semiconductor layer standing above the semiconductor substrate in this way, a normal MOSFET having a channel region in the semiconductor substrate (referred to as a bulk MOSFET for convenience). ) And can be downsized.

  In addition, since a plurality of gate electrodes can be provided for the semiconductor layer, variation in threshold value can be suppressed as compared with the case where there is one gate electrode, and a MOSFET having a low threshold value can be configured ( For example, see Patent Document 1.)

  In the prior art disclosed in Patent Document 1, the upper surface of a semiconductor layer constituting a fin-type field effect transistor is covered with a thick insulating film, and two gate electrodes separated on left and right side walls (vertical end surfaces) are provided, and this is formed by wiring. It is a connected structure.

The conventional fin-type field effect transistor disclosed in Patent Document 1 has a plurality of gate electrodes, and an electric field can be applied from the left and right vertical end faces of an upstanding semiconductor layer. The transistor operation can be started before pinching off.
In the case of a MOSFET having only one gate electrode, the potential change from the channel region toward the depletion layer is abrupt. On the other hand, the conventional fin-type field effect transistor disclosed in Patent Document 1 also has a potential change. Relatively stable. In addition, the structure in which a plurality of gate electrodes are separated is more suitable for controlling the threshold value than a normal fin-type field effect transistor.

JP-T-2007-504679 (8th page, FIG. 9)

  By the way, there are two types of structures of semiconductor elements that are not bulk MOSFETs, such as fin-type field effect transistors, partially depleted and fully depleted. The partially depleted type does not completely deplete the bulk region but has a partial neutral region, and the fully depleted type depletes all the bulk region.

In general, the partial depletion type is characterized in that the breakdown voltage of the source region and the drain region can be increased. However, since the neutral region exists in the bulk region, it is necessary to take measures against the substrate floating effect.
Compared with the partial depletion type, the fully depleted type has the characteristics that the junction capacitance between the source region and the drain region and the bulk region is small, and the subthreshold characteristic as an index of the current driving capability is good. In addition, the substrate floating effect is very small. Since the off-leakage current can be reduced, in other words, if the off-leakage current is made the same, the operating voltage can be lowered.

  The partial depletion type and the full depletion type each have advantages and are selectively used depending on the application. From the viewpoint of reducing the power consumption of the semiconductor element, the full depletion type is advantageous. The reason for operating at a low operating voltage is that the threshold value can also be lowered.

  In a fin-type field effect transistor, in order to drive at a low voltage and reduce power consumption, at least a bulk region must be completely depleted when a transistor is operated by applying a voltage from a gate electrode.

  As in the fin-type field effect transistor according to the prior art disclosed in Patent Document 1, when a channel region is provided on the vertical end surface of an upstanding semiconductor layer and two gate electrodes are provided opposite to the channel region, the thickness of the semiconductor layer is increased. If is thick, the channel region cannot be completely depleted. Forcing full depletion requires that the electric field from the gate electrode be further increased, which goes against the trend of lower power consumption.

  In addition, in order to avoid such a situation, if an attempt is made to reduce the planar thickness of an upstanding semiconductor layer serving as a channel region, it is affected by processing variations (dimensional variations) in the manufacturing process, resulting in electrical characteristics. However, a stable semiconductor element cannot be constructed.

Although the prior art disclosed in Patent Document 1 has the advantage that the threshold value can be controlled by the electric fields from the two gate electrodes, it is difficult to operate stably in a state where the bulk region is completely depleted. Therefore, it is difficult to reduce power consumption. It is also difficult to stabilize the electrical characteristics of the semiconductor element.

  The present invention has been made to solve such problems. It is possible to provide a fin-type field effect transistor that achieves both low power consumption and stable electrical characteristics of the fin-type field effect transistor.

  In order to achieve the above object, the fin-type field effect transistor of the present invention employs the following structure.

  The fin-type field effect transistor of the present invention includes an insulating film provided on a semiconductor substrate and a semiconductor layer provided on the insulating film, and a bulk region, a source region, a channel region, and a drain region are provided in predetermined portions of the semiconductor layer. A fin-type field effect transistor comprising a gate insulating film on a surface of the semiconductor layer in a channel region and a gate electrode for applying an electric field to the channel region through the gate insulating film. A bulk electrode for application is provided separately from the gate electrode.

  With such a structure, since a potential can be directly applied to the bulk region, a low threshold value can be realized, threshold value variation and leakage current can be suppressed, and power consumption can be reduced.

  A channel region may be provided on the first vertical end surface of the semiconductor layer, and the bulk region may be provided on a second vertical end surface opposite to the first vertical end surface of the semiconductor layer.

  With such a configuration, the width of the semiconductor layer can be arbitrarily defined, and thus the planar area of the fin-type field effect transistor can be reduced. Further, by providing the bulk region in a portion facing the channel region, the bulk region having the same area as the channel region is opposed, so that there is no uneven potential for the substrate bias.

  The gate insulating film may be provided on the first vertical end face.

  With such a configuration, the vertical height of the semiconductor layer can be the channel width, and if there is no limitation in the vertical direction, the drain current can be arbitrarily defined by the thickness of the semiconductor layer.

  The gate electrode may be provided to face the first vertical end face, and the bulk electrode may be provided to face the second vertical end face and be directly connected to the bulk region.

  With such a configuration, a gate electric field can be applied from the first vertical end face, a bulk potential can be applied from the second vertical end face, and the electrical characteristics of the MOSFET can be stabilized.

  Since the fin-type field effect transistor of the present invention can directly apply an arbitrary potential to the bulk region, the threshold voltage can be set to an arbitrary value, and is set to a low threshold during operation and to a high threshold during non-operation. By maintaining the value, an ideal subthreshold wing can be performed, so that a low leakage current can be realized.

Further, because of this structure, the substrate bias effect can be used, and it becomes possible to prevent the variation of the threshold due to the dimensional variation of the semiconductor layer, which is a problem in the fin field effect transistor. Therefore, low power consumption can be realized, and it is not necessary to suppress the thickness of the semiconductor layer to about the depth of the fully depleted layer, which facilitates its manufacture.

It is the top view and sectional drawing explaining the structure of the fin type field effect transistor in the 1st Embodiment of this invention. It is the top view and sectional drawing explaining the structure of the application example of the fin type field effect transistor in the 1st Embodiment of this invention. It is the top view and sectional drawing explaining the structure of the fin type field effect transistor in the 2nd Embodiment of this invention. It is a top view explaining the structure of the fin type field effect transistor in the 3rd Embodiment of this invention. It is sectional drawing explaining the structure of the fin type field effect transistor in the 3rd Embodiment of this invention. It is sectional drawing explaining the example which integrated two fin type field effect transistors of this invention from which a conductivity type differs.

  The fin type field effect transistor of the present invention has a low threshold by providing a bulk electrode separately from the gate electrode for directly applying a predetermined potential to the bulk region of the fin type field effect transistor provided on the insulating film. In addition, the variation in threshold value is suppressed.

  Hereinafter, the fin-type field effect transistor will be described with reference to the drawings. In the embodiment described below, the fin-type field effect transistor will be described using an example in which an SOI (Silicon-On-Insulator) substrate is used. An example in which the conductivity type of the fin-type field effect transistor is an N-channel MOSFET (hereinafter referred to as an N-type MOSFET) will be described. In addition, configurations that are not necessary for the description (for example, a final protective film, a source electrode, a drain electrode, and the like) are omitted for easy understanding of the drawing.

[Description of Configuration of First Embodiment of the Present Invention: FIG. 1]
The overall configuration of the fin-type field effect transistor according to the first embodiment will be described with reference to FIG. 1A and 1B are a plan view and a cross-sectional view schematically showing the structure of a fin-type field effect transistor. FIG. 1A is a plan view, and FIG. 1B is cut along a cutting line AA ′. A cross-sectional view is shown.

  In FIG. 1, 1 is a semiconductor substrate and 2 is an insulating film. Reference numeral 3 denotes a semiconductor layer, 3A denotes a first vertical end face of the semiconductor layer 3, 3B denotes a second vertical end face of the semiconductor layer 3, and 3C denotes an upper end face of the semiconductor layer 3. 4 is a gate insulating film, 5 is a channel region, and 6 is a gate electrode. 7A is a source region, 7B is a drain region, 8 is a bulk region, 9 is a bulk electrode, 10 is an interlayer insulating film, 11 is a contact hole, and 12 is a metal wiring.

  The fin-type field effect transistor of the first embodiment is manufactured using an SOI substrate. The semiconductor substrate 1 is a support substrate made of single crystal silicon. The insulating film 2 is a silicon oxide film that is a buried oxide film. The semiconductor layer 3 is single crystal silicon and is provided via the insulating film 2. The semiconductor layer 3 stands with respect to the semiconductor substrate 1.

By the way, a fin-type field effect transistor can be formed without using an SOI substrate. For example, an insulating film 2 made of a silicon oxide film is formed on the semiconductor substrate 1 by oxidation or the like, and an amorphous silicon film is formed on the insulating film 2 by a chemical vapor deposition method (hereinafter referred to as a CVD method). Form. Thereafter, the semiconductor layer 3 can be formed by single-crystallizing by heat treatment. In this case, the semiconductor layer 3 is processed into a predetermined shape by etching after forming a single crystal film on the insulating film 2.

  The semiconductor layer 3 has a shape in which the first vertical end surface 3A and the second vertical end surface 3B face each other and are positioned in parallel. In the case of an N-type MOSFET, the conductivity type of the semiconductor layer 3 is P-type.

In the semiconductor layer 3, a bulk region 8 is provided between the source region 7A and the drain region 7B. A channel region 5 is provided in the bulk region 8. This configuration is the same as that of the bulk type MOSFET.
The gate insulating film 4 is provided on the surface of the semiconductor layer 3. Specifically, the semiconductor layer 3 is provided on the surface of the first vertical end face 3A of the channel region 5 sandwiched between the source region 7A and the drain region 7B.
This gate insulating film 4 is formed by thermally oxidizing the semiconductor layer 3 made of single crystal silicon by a known method, and has a film thickness of, for example, 8 nm.

  The gate electrode 6 is provided on the channel region 5 so as to cover the gate insulating film 4. The gate electrode 6 is made of, for example, polycrystalline silicon formed by a CVD method. The film thickness is, for example, 350 nm.

As described above, the source region 7A and the drain region 7B are provided so as to sandwich the bulk region 8 in a plane, and the channel region 5 is provided on the first vertical end face 3A of the bulk region 8.
The source region 7A and the drain region 7B are composed of high-concentration impurity layers. The impurity is, for example, arsenic (As) or phosphorus (P) in the case of an N-type MOSFET, and has a dose of about 10E- ¹⁵ atoms / cm ^2. It is formed by ion implantation in an amount (impurity amount).

  The bulk electrode 9 is an electrode that directly applies a potential to the bulk region 8 provided separately from the gate electrode 6, and is provided so as to be in direct contact with the surface of the upper end surface 3 </ b> C of the semiconductor layer 3. In a plan view, the gate electrode 6 is provided on the surface of the bulk region 8 sandwiched between the source region 7A and the drain region 7B.

  The bulk electrode 9 is preferably, for example, a laminated film of titanium and aluminum. Although a natural oxide film is generated on the silicon surface as the semiconductor layer 3, it is electrically good between the semiconductor layer 3 and the bulk electrode 9 by siliciding titanium and silicon as the semiconductor layer 3. This is because a simple connection can be obtained and it is suitable for voltage control.

Further, the interlayer insulating film 10 is provided on the entire surface, the contact hole 11 is provided in the interlayer insulating film 10, the metal wiring 12 is connected to the gate electrode 6, and the bulk electrode 9 is connected to the bulk region 8.
The metal wiring 12 and the bulk electrode 9 are formed by the same material and the same process in this embodiment, respectively, and are connected to predetermined circuit elements and terminals not shown.
The interlayer insulating film 10 is, for example, a silicon oxide film formed by a CVD method. The metal wiring 12 is made of, for example, a laminated film of titanium and aluminum.

  It is also necessary to make electrical connection to the source region 7A and the drain region 7B to exchange electric signals. A contact hole 11 is provided in a portion of the interlayer insulating film 10 that overlaps with these regions in a planar manner, and electrical connection is made by metal wiring. Note that illustration of these structures is omitted as already described.

By the way, generally, the width of the fin is the first vertical end face 3 which is opposed to each other and is indicated by a symbol W in FIG.
This corresponds to the distance of the semiconductor layer 3 sandwiched between A and the second vertical end face 3B.
If this distance W is narrow, it will be affected by the processing accuracy as described above, the electrical characteristics will not be stable, and if it is thick, it will be difficult to completely deplete for low power consumption.
However, since the fin-type field effect transistor of the present invention is provided with the bulk electrode 9 and can directly apply a voltage to the bulk region 8, the potential of the bulk region 8 can be freely controlled. For this reason, even if the distance W is thick, it can be completely depleted.

[Description of Operation of First Embodiment]
Next, the structure of the fin-type field effect transistor according to the first embodiment will be summarized and the state of driving will be described.
The fin-type field effect transistor has a semiconductor layer 3 standing on an insulating film 2 provided on an upper portion of a semiconductor substrate 1. The semiconductor layer 3 constitutes a fin.
A channel region 5 is provided on the surface of the first vertical end face 3 </ b> A of the bulk region 8 of the semiconductor layer 3, a gate insulating film 5 is provided so as to cover the channel region 5, and a gate electrode is interposed through the gate insulating film 5. 6 is provided.
A bulk electrode 9 is provided so as to be directly connected to the upper end surface 3 </ b> C of the semiconductor layer 3.

  When driving the fin field effect transistor, a gate voltage is applied to the gate electrode 6. A bulk voltage for directly applying a potential to the bulk region 8 is applied from a bulk electrode 9 provided separately from the gate electrode 6.

  The channel region 5 is inverted in conductivity type by the electric field due to the gate voltage, and the source region 7A and the drain region 7B are electrically connected through the inverted region. That is, a current flows along the surface portion of the first vertical end face 3 </ b> A of the semiconductor layer 3.

As already described, the fin-type field effect transistor of the present invention applies a gate voltage as an electric field from the gate electrode 6 to the channel region 5 through the gate insulating film 4 and applies a bulk potential from the bulk electrode 9 instead of an electric field. It can be applied directly to the bulk region 8. Since the electric field is not applied, the potential of the bulk region 8 can be accurately controlled.
A conventionally known example of a semiconductor element using an SOI substrate has been proposed in which an electric field is applied to the semiconductor layer through an insulating film from the semiconductor substrate side. However, the configuration is completely different from such a configuration. It is.

  The relationship between the electric field applied from the gate electrode 6 to the channel region 5 and the potential applied from the bulk electrode 9 to the bulk region 8 can be freely changed according to the electrical characteristics desired for the fin-type field effect transistor.

For example, the gate voltage applied from the gate electrode 6 and the bulk voltage applied from the bulk electrode 9 can be made the same.
In this way, the fin field effect transistor can be operated as a known DTMOSFET.

Of course, this is only an example, and both voltage values may be changed.
For example, if the potential of the bulk region 8 is lowered by applying a predetermined potential from the bulk electrode 9 to the bulk region 8, the potential difference between the bulk region 8 and the gate voltage increases. The threshold voltage can be increased. Then, leakage current can be reduced and power consumption can be reduced.
On the other hand, if the potential of the bulk region 8 is increased, the potential difference between the bulk region 8 and the gate voltage is reduced, so that the threshold voltage can be lowered. Then, high speed operation can be realized.

As described above, the fin-type field effect transistor of the present invention can freely change the potential applied to the bulk region 8 by the bulk electrode 9, so that a fin-type field effect transistor corresponding to the desired electrical characteristics can be obtained. .
Further, by applying a voltage to the bulk region 8, variation in threshold voltage can be suppressed, so that a highly reliable fin field effect transistor can be configured.

[Description of Configuration of Application Example of First Embodiment: FIG. 2]
Next, an application example of the fin-type field effect transistor according to the first embodiment will be described with reference to FIG. 2A and 2B are a plan view and a cross-sectional view schematically showing the structure of an application example of the fin-type field effect transistor. FIG. 2A is a plan view, and FIG. 2B is a section line BB ′. Sectional drawing cut | disconnected by is shown.

The feature of this application example is that it has two gate electrodes.
As shown in FIG. 2, the gate insulating film 4a and the gate electrode 6a are provided on the first side end face 3A, and the gate insulating film 4b and the gate electrode are provided on the second side end face 3 opposite to the first side end face 3A. 6b is provided.
Note that the material and film thickness of the gate insulating films 4a and 4b and the gate electrodes 6a and 6b are the same as those in the second embodiment, and thus the description thereof is omitted.

  It is also necessary to make electrical connection to the source region 7A and the drain region 7B to exchange electric signals. A contact hole 11 is provided in a portion of the interlayer insulating film 10 that overlaps with these regions in a planar manner, and electrical connection is made by metal wiring. Note that, as already described, these structures are omitted for easy understanding of the drawings. Therefore, in FIG. 2A, the bulk electrode 9 is wired on the source region 7A. However, in the actual configuration, the source electrode and the bulk electrode 9 are arranged so as not to contact each other.

[Description of Effects of Application Example of First Embodiment]
This application example has two gate electrodes 6 and can independently apply a gate voltage. Such a structure is already known as a so-called double gate type MOSFET. The application example of the first embodiment shown in FIG. 2 is that a potential can be directly applied to the bulk region 8 by the bulk electrode 9 in addition to the characteristics of the known double-gate MOSFET.

  With such a configuration, variation in threshold voltage when the bulk potential is brought close to 0 V can be suppressed, and in addition to reducing power consumption, switching characteristics are improved and short channels are used. It becomes possible to make it easier to suppress the leakage current.

  The reason is that since the number of gate electrodes increases, the voltage of the channel region can be easily controlled by the gate electrode as compared with a MOSFET having only one gate electrode.

  For example, when a potential is applied from the bulk electrode and the bulk region is kept at 0V, the potential approaches the potential 0V of the semiconductor layer (bulk region) as the distance from the gate electrode increases in the channel portion where current flows. It becomes difficult to smooth the gradient of the voltage change in the channel region with the gate voltage due to.

  On the other hand, if this example has a double gate structure in which gate electrodes are provided on the left and right sides of the channel region, the opposing gate electrodes extend each other's channels, so the potentials of both channel regions are As it goes to the bulk region, the voltage gradually changes to 0V.

  As a result, the variation in the voltage in the channel region can be reduced, and the voltage in the channel region can be more easily controlled by the gate electrode.

  When variation in voltage in the channel region is reduced, switching characteristics can be improved, and leakage current can be easily suppressed even when the gate length is short.

  In addition, when the number of gate electrodes increases, when driving with the same potential, the amount of current during driving increases (ideally increases the number of gates), so that a large current driving capability is obtained even with a small MOSFET. You can also do that.

[Description of Configuration of Second Embodiment of the Present Invention: FIG. 3]
Next, a second embodiment of the fin field effect transistor will be described with reference to FIG. 3A and 3B are a plan view and a cross-sectional view schematically showing the structure of the fin-type field effect transistor. FIG. 3A is a plan view, and FIG. 3B is cut along the cutting line CC ′. A cross-sectional view is shown.

  A feature of the second embodiment is that the gate electrode 6 and the bulk electrode 9 are provided to face each other with the semiconductor layer 3 interposed therebetween.

As shown in FIG. 3, a channel region 5 is provided on the first vertical end face 3A of the semiconductor layer 3, and a gate insulating film 4 is provided so as to cover this. Similarly to the example already described, the gate electrode 6 is provided so as to cover the gate insulating film 4, and many portions are provided so as to face the first vertical end face 3A.
The bulk electrode 9 is provided in direct contact with the bulk region 8 of the second vertical end surface 3B of the semiconductor layer 3.

[Description of Effects of Third Embodiment]
The third embodiment has an effect that the bulk region 8 and the bulk electrode 9 can be connected with a lower resistance in addition to the same effects as those of the embodiments described above.
That is, instead of connecting the bulk region 8 and the bulk electrode 9 in a narrow region of the upper end surface of the semiconductor layer 3 (upper end surface 3c in FIG. 1), the bulk electrode is not connected to the vertical end surface 3B of the wider semiconductor layer 3. Can be connected to the bulk region.

  Specifically, since the distance between the semiconductor layer 3 raised from the semiconductor substrate 1 side and the wiring width of the bulk electrode 9 on the second vertical end surface 3B of the semiconductor layer 3 can be in contact with each other, more With the contact area, the bulk region 8 and the bulk electrode 9 can be brought into contact with each other. Thereby, it has the effect that both can be electrically connected with lower resistance.

  In addition, since the processing may be performed more easily than processing so that the bulk electrode 9 and the bulk region 8 are brought into contact with the upper end surface of the semiconductor layer 3, the process cost may be reduced.

[Description of Configuration and Effect of Third Embodiment of the Present Invention: FIGS. 4 and 5]
Next, a third embodiment of the fin-type field effect transistor will be described with reference to FIGS. FIG. 4 is a plan view schematically showing the structure of the fin-type field effect transistor. FIG. 5 shows a cross-sectional view of the configuration shown in FIG. 4. FIG. 5A shows a state cut along the cutting line DD ′ shown in FIG. 4, and FIG. Sectional drawing cut | disconnected by the cutting line EE 'shown is each shown.

  A feature of the second embodiment is that the gate electrode 6 and the bulk electrode 9 are provided to face each other with the semiconductor layer 3 interposed therebetween.

As shown in FIG. 4, unlike the example already described, the bulk region 8 is bent in the direction of the source region 7A in a plane.
The configuration in which the channel region 5, the gate insulating film 4, and the gate electrode 6 are provided on the first vertical end face 3A of the semiconductor layer 3 is the same as the example already described, but the bulk electrode 9 and the bulk region are formed by the bent bulk region 8. The contact portion with 8 is not on the extension line of the gate electrode 6 but shifted in the direction of the source region 7A. This will be apparent from FIG. 5 showing the state of cutting along two cutting lines.

  With such a configuration, the degree of freedom in the planar arrangement of the gate electrode 6 and the bulk electrode 9 can be improved. As already described, a source electrode and a drain electrode are connected to the source region 7A and the drain region 7B, although not shown. When there are a large number of wirings in this way, the degree of freedom of wiring routing increases if the bulk electrode 9 is shifted as in the third embodiment.

  In the third embodiment as well, as in the second embodiment, the bulk region 8 and the bulk electrode 9 are in contact with each other at the second vertical end surface 3B of the semiconductor layer 3, so that both the contacts are made. The resistance is low, and even the configuration in which the bulk region 8 is bent has no influence at all.

[Description of configuration of application example: FIG. 6]
Next, with reference to FIG. 6, an application example of the already described embodiment will be described by taking the second embodiment as an example.
In this application example, a fin-type field effect transistor N-type MOSFET and a P-channel MOSFET (hereinafter referred to as P-type MOSFET) are arranged in parallel (complementary MOS, so-called CMOS structure). is there. In the embodiment described above, for example, an example of configuring an N-type MOSFET has been described, but an example of a CMOS structure combined with a P-type MOSFET will be described.

  In FIG. 6, 13A is an N-type MOSFET, 13B is a P-type MOSFET, and 14 is an inter-element insulating film. The inter-element insulating film 14 is a silicon oxide film formed by a known CVD method. 4a and 4b are gate insulating films, 5a and 5b are channel regions, 6a and 6b are gate electrodes, 8a and 8b are bulk regions, 12a and 12b are metal wirings, 3Aa and 3Ab are first vertical end faces, 3Ba and 3Bb are The second vertical end surfaces correspond to the gate insulating film 3, the channel region 5, the gate electrode 6, the bulk electrode 8, the metal electrode 12, the first vertical end surface 3A, and the second vertical end surface 3B, which have already been described. .

As shown in FIG. 6, the N-type MOSFET 13A and the P-type MOSFET 13B are arranged next to each other so that the second vertical end face 3Ba and the second vertical end face 3Bb face each other.
A channel region 5a is provided on the first vertical end surface 3Aa of the bulk region 8a of the N-type MOSFET 13A, a gate insulating film 4a is provided so as to cover the channel region 5a, and a gate electrode 6a is further provided.
A channel region 5b is provided on the first vertical end surface 3Ab of the bulk region 8b of the P-type MOSFET 13B, a gate insulating film 4b is provided so as to cover the channel region 5b, and a gate electrode 6b is further provided.

A common bulk electrode 9 is provided which is directly connected to the second vertical end face 3Ba and the second vertical end face 3Bb. The bulk electrode 9 and the metal wirings 12a and 12b connected to the gate electrodes 6a and 6b are formed in the same material and in the same process in this embodiment as in the other embodiments, and are not shown in the figure. Or connected to a terminal.

  The inter-element insulating film 14 serves to insulate the N-type MOSFET 13A and the P-type MOSFET 13B, to prevent the electric field from the bulk electrode 9 from excessively reaching the semiconductor substrate 1, and to form the bulk electrode. There is a role to improve the coverage. For this reason, a certain amount of film thickness is required, and depending on the applied bulk potential, it is, for example, about 0.5 μm.

[Explanation of effects of application example]
Appropriate gate voltages for driving the respective MOSFETs are applied to the gate electrodes of the N-type MOSFET 13A and the P-type MOSFET 13B. A predetermined voltage is applied to the bulk electrode 9.
For example, 0.5V is applied to the bulk electrode 9, and + 0.8V is applied to the gate electrode 6a at the timing of driving the N-type MOSFET 13A. Next, -0.5V is applied to the bulk electrode 9, and -0.8V is applied to the gate electrode 6b at the timing of driving the P-type MOSFET 13B.

Then, due to the applied bulk potential, when the N-type MOSFET 13A is turned on, the P-type MOSFET 13B is hardly turned on. Conversely, when the P-type MOSFET 13B is turned on, the N-type MOSFET 13A is hardly turned on.
This is because the voltage applied to the semiconductor layer increases and decreases the threshold voltage.

Since the fin-type field effect transistor of the present invention described above is provided with a bulk electrode that directly applies a potential to the bulk region in addition to the gate electrode, the threshold voltage can be set to an arbitrary value during operation. It can be kept at a low threshold and at a high threshold when not in operation.
If it has such a feature, it can be modified without departing from the gist of the present invention. For example, the shape of the semiconductor layer, the positional relationship between the gate electrode and the bulk electrode, the type of electrode, and the like can be arbitrarily determined.

  The present invention can implement a low threshold voltage, threshold voltage variation and leakage current suppression, and a low area. For this reason, it can be applied to an LSI driven at a low voltage. It is particularly suitable for LSIs that require low power consumption.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Embedded insulating film 3 Semiconductor layer 3A 1st vertical end surface 3B 2nd vertical end surface 3C Upper end surface 4 Gate insulating film 5 Channel region 6 Gate electrode 7A Source region 7B Drain region 8 Bulk region 9 Bulk electrode 10 Interlayer insulation Film 11 Contact hole 12 Metal wiring 13A N-type MOSFET
13B P-type MOSFET
14 Inter-element insulating film Figure 1

Claims (5)

An insulating film provided on the semiconductor substrate;
A semiconductor layer provided on the insulating film,
A bulk region, a source region, a channel region, and a drain region are provided in a predetermined portion of the semiconductor layer,
A gate insulating film is provided on the surface of the semiconductor layer in the channel region,
In a fin-type field effect transistor comprising a gate electrode for applying an electric field to the channel region through the gate insulating film,
A fin-type field effect transistor comprising a bulk electrode for applying a predetermined potential to the bulk region separately from the gate electrode. Providing the channel region on a first vertical end face of the semiconductor layer;
2. The fin field effect transistor according to claim 1, wherein the bulk region is provided on a second vertical end face opposite to the first vertical end face of the semiconductor layer.   The fin-type field effect transistor according to claim 2, wherein the gate insulating film is provided on the first vertical end face. The gate electrode is provided to face the first vertical end surface;
4. The fin-type field effect transistor according to claim 2, wherein the bulk electrode is provided to face the second vertical end face and is directly connected to the bulk region. 5. The fin-type field effect transistor according to claim 1, further comprising a connection wiring that electrically connects the gate electrode and the bulk electrode.

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