JP2012208790A - Data transfer device - Google Patents

Abstract

A data transfer device capable of efficiently outputting the operation state of a common bus to the outside with a small number of terminals is provided.
A plurality of peripheral circuits A and B exchange data through a common bus. The transfer waiting determination unit 12 outputs a first signal W indicating whether or not a selected peripheral circuit among the plurality of peripheral circuits A and B is waiting for data transfer to the outside through the first terminal C. The data transfer right notifying unit 14 outputs the second signal K representing the peripheral circuit in the plurality of peripheral circuits A and B that is transferring data to the outside through the second terminal D. The error notification unit 16 outputs a third signal E indicating whether or not a buffer error has occurred in any one of the plurality of peripheral circuits to the outside through the third terminal E.
[Selection] Figure 1

Description

  The present invention relates to a data transfer apparatus.

  In a system that employs a common bus system, methods for detecting a failure content are disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 60-183657) and Patent Document 2 (Japanese Patent Laid-Open No. 60-69754).

  In Patent Document 1, in a microcomputer application system in which a bus master and a bus slave are connected to a common bus, the time from reception of a transfer request signal to reception of a transfer response signal is monitored for each bus master. A timer circuit is provided, and at least one of the bus masters includes a memory for storing a fault diagnosis program and a microcomputer that uses the memory for an interrupt processing operation, and the timer circuit exceeds a monitoring time. Thus, it is disclosed that the microcomputer is caused to execute an interrupt processing operation.

  Patent Document 2 discloses a common bus control method for a computer system that is connected to a common bus and that includes a plurality of CPUs. A bus use request signal is issued to each of the plurality of CPUs, and then a bus use right is given. It is disclosed that a waiting time until the waiting time is measured and a bus load abnormality signal is issued when the waiting time becomes longer than a set time determined for each CPU.

JP 60-183657 A JP 60-69754 A

  By the way, in a high-function SoC (System-on-a-chip) or the like, the number of external terminals necessary for operation is large, and a large number of signals cannot be extracted in order to notify the operation state of the data transfer bus.

  As a result, the operation state of the data transfer bus inside the chip cannot be accurately grasped from the outside, and the designer can determine the operation state of the data transfer bus of each peripheral circuit exclusively based on highly integrated circuit specification information. I had to guess. Therefore, it is difficult to confirm the validity of the estimated value of the bus performance calculation and to identify the cause of the abnormality.

  However, Patent Documents 1 and 2 do not disclose a configuration for efficiently outputting the operation state of the data transfer bus to the outside with a small number of terminals.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data transfer device that can efficiently output the operation state of a common bus to the outside with a small number of terminals.

  A data transfer device according to an embodiment of the present invention includes a common bus, a plurality of bus use circuits that exchange data through the common bus, first, second, and third terminals connected to the outside, A transfer wait determination unit for outputting a first signal indicating whether or not a selected bus use circuit in the bus use circuit is waiting for data transfer to the outside through the first terminal; and data in the plurality of bus use circuits Whether a buffer error has occurred in the data transfer right notification unit that outputs the second signal representing the bus use circuit being transferred to the outside through the second terminal, and any of the bus use circuits among the plurality of bus use circuits And an error notification unit for outputting a third signal indicating whether or not to the outside through a third terminal.

  According to the data transfer device of one embodiment of the present invention, the operation state of the common bus can be efficiently output to the outside with a small number of terminals.

It is a figure showing the structure of the data transfer apparatus in 1st Embodiment. It is a figure for demonstrating the operation | movement of the notification of the data transfer right in 1st Embodiment, and the notification of an error. It is a figure showing the timing of the signal transmitted with the data transfer apparatus of 1st Embodiment. It is a figure showing the structure of the data transfer apparatus of 2nd Embodiment. It is a figure for demonstrating the measurement operation | movement of the data transfer waiting time of 2nd Embodiment. It is a figure showing the structure of the data transfer apparatus of 3rd Embodiment. 4 is a diagram illustrating an example of changing priority by a priority changing circuit 40. FIG. It is a figure showing the structure of the data transfer apparatus of 4th Embodiment. It is a figure showing the transfer waiting and data transfer in a sampling area. It is a figure for demonstrating the clock control in the state of the transfer waiting of FIG. 9, and a data transfer. It is a figure showing the structure of the data transfer apparatus of 5th Embodiment. It is a figure showing the example of the priority of a peripheral circuit. (A) is a figure showing the initial value of the data transfer amount per time of each peripheral circuit. (B) is a diagram showing the data transfer amount per time of each peripheral circuit after the transfer amount adjustment. (A) is a figure for demonstrating the data transfer of the peripheral circuit B under the setting value of the transfer amount of Fig.13 (a). FIG. 13B is a diagram for explaining data transfer of the peripheral circuit B under the transfer amount setting value of FIG.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram illustrating a configuration of a data transfer apparatus according to the first embodiment.

  Referring to FIG. 1, this data transfer apparatus 2 includes a data transfer bus 4, a plurality of peripheral circuits A and B, a data transfer control circuit 10, a transfer waiting determination unit 12, a data transfer right notification unit 14, and the like. The error notification unit 16 and external terminals C, D, and E are provided.

The external terminals C, D, and E are connected to the outside of the data transfer device and output signals to the outside.
The data transfer bus 4 is a common bus used in common by a plurality of peripheral circuits A and B.

  Each peripheral circuit A, B is connected to the data transfer bus 4. Each peripheral circuit A, B exchanges data with other peripheral circuits through the data transfer bus 4.

  Peripheral circuits A and B include a read buffer and a write buffer. The peripheral circuits A and B assert the buffer error signal to the “H” level when an error occurs in the read buffer or the write buffer. Errors include underflow and overflow. Underflow refers to a case where data is extracted while data is not stored in the buffer. Overflow refers to a state where the amount of data in the buffer exceeds a predetermined threshold.

  When the peripheral circuits A and B need to transfer data to other peripheral circuits A and B, or when they need to receive data transfer from other data transfers, the peripheral circuits A and B send data transfer request signals to the data transfer bus 4. Is output to the data transfer control circuit 10. The peripheral circuits A and B receive the data transfer permission signal from the data transfer control circuit 10 via the data transfer bus 4 and then write data to the other peripheral circuits A and B (that is, other peripheral circuits A and B). To the data transfer bus 4 or read data from the other peripheral circuits A and B (that is, data sent from the other peripheral circuits A and B) is received from the data transfer bus 4.

  The data transfer control circuit 10 controls data transfer of the peripheral circuits A and B. The data transfer control circuit 10 receives a data transfer request signal from the peripheral circuits A and B via the data transfer bus 4 and, when permitting data transfer, sends a data transfer permission signal via the data transfer bus 4 to the peripheral circuit. Output to A and B. When the data transfer control circuit 10 receives data transfer request signals from the plurality of peripheral circuits A and B, the data transfer control circuit 10 outputs a permission signal for permitting data transfer to the peripheral circuits A and B having the highest priority. A rejection signal for rejecting data transfer is output to the peripheral circuits A and B. Further, when the data transfer control circuit 10 receives the data transfer request signal from the peripheral circuits A and B, and the data transfer is being executed in the other peripheral circuits A and B, the other peripheral circuits A and B After the data transfer in B is completed, a data transfer permission signal is output to the peripheral circuits A and B that issued the data transfer request signal.

  The transfer waiting determination unit 12 measures the data transfer waiting time for the selected peripheral circuits A and B among the plurality of peripheral circuits A and B. The transfer wait determination unit 12 outputs a transfer wait signal to the external terminal C. The transfer wait determination unit 12 asserts the transfer wait signal W to the “H” level when data transfer wait occurs for the selected peripheral circuits A and B among the plurality of peripheral circuits A and B.

  The data transfer right notification unit 14 includes a mode register 18, a selector 20, and an encoder circuit 22.

  A CPU (not shown) sets an identifier representing a peripheral circuit for notifying the presence / absence of data transfer right in the mode register 18.

  The selector 20 receives read data or write data from all the peripheral circuits A and B connected to the data transfer bus 4, and among them, read data output from the peripheral circuit of the identifier set in the mode register 18, Alternatively, write data is output to the encoder circuit 22.

  The encoder circuit 22 receives the read data or write data output from the selector 20, and specifies the peripheral circuit having the data transfer right when the read data or write data indicates that data is being transferred. The encoder circuit 22 outputs, to the external terminal D, a 3-bit bus right display signal K that encodes an identifier of a peripheral circuit having a data transfer right.

  For example, when the identifiers of the peripheral circuit A and the peripheral circuit B are set in the mode register 18, the selector 20 outputs read data and write data from the peripheral circuit A and the peripheral circuit B to the encoder circuit 22. The encoder circuit 22 encodes an identifier representing the peripheral circuit A when the read data of the peripheral circuit A indicates a state in which the data is being read (for example, when the read data or the write data can be identified by the header). A 3-bit bus right indication signal K is output. For example, when representing peripheral circuits A, B, C, D, E, F, and G, the 3-bit bus right indication signal K is 001, 010, 011, 100, 101, 110, and 111 in binary numbers, respectively.

The error notification unit 16 includes an OR circuit 24 and an error status register 26.
The OR circuit 24 receives buffer error signals from all the peripheral circuits A and B connected to the data transfer bus 4. The OR circuit 24 calculates the logical sum of the buffer error signals from all the peripheral circuits A and B and outputs the logical sum to the external terminal E as the error signal E. Therefore, the OR circuit 24 asserts the error signal E to the “H” level when a buffer error occurs in any of the peripheral circuits connected to the data transfer bus 4. The OR circuit 24 sets the error signal E to the “L” level when no buffer error occurs in all the peripheral circuits A and B connected to the data transfer bus 4.

  The error status register 26 stores an identifier of a peripheral circuit in which a buffer error has occurred and an identifier indicating the type of buffer error. The identifier indicating the type of buffer error is “00” for the overflow of the read buffer, “01” for the underflow of the read buffer, “10” for the overflow of the write buffer, and “11” for the underflow of the write buffer. To do.

(Operation)
FIG. 2 is a diagram for explaining the data transfer right notification and error notification operations in the first embodiment.

  First, it is assumed that an identifier for identifying the peripheral circuit A and the peripheral circuit B is set in the mode register 18 in the data transfer right notification by the CPU.

  Referring to FIG. 2, data transfer control circuit 10 waits for a data transfer request signal to be generated (step S101).

  Peripheral circuit A outputs a data transfer request signal to data transfer control circuit 10. The peripheral circuit A receives the data transfer permission signal from the data transfer control circuit 10 and starts outputting write data, that is, starts data transfer (step S102).

  The selector 20 outputs the write data from the peripheral circuit A to the encoder circuit 22. The encoder circuit 22 receives the write data output from the selector 20 and specifies the peripheral circuit A having the data transfer right when the write data indicates that data is being transferred. The encoder circuit 22 outputs, to the external terminal D, a 3-bit bus right display signal K “001” that encodes the identifier of the peripheral circuit A having the data transfer right (step S103).

  Thereafter, an overflow occurs in the write buffer of the peripheral circuit A (step S104), the peripheral circuit A outputs a buffer error signal, and the OR circuit 24 of the error notification unit 16 asserts the error signal E to “H” level. (Step S105).

  The error status register 26 of the error notification unit 16 stores an identifier “001” of the peripheral circuit in which the buffer error has occurred and an identifier “10” indicating the type of buffer error (here, overflow of the write buffer). (Step S106).

  Thereafter, the peripheral circuit B outputs a data transfer request signal to the data transfer control circuit 10. The peripheral circuit B receives the data transfer permission signal from the data transfer control circuit 10 and starts outputting write data, that is, starts data transfer (step S107).

  The encoder circuit 22 receives the write data output from the selector 20, and specifies the peripheral circuit B having the data transfer right when the write data indicates that data is being transferred. The encoder circuit 22 once clears the 3-bit bus right display signal K output to the external terminal D to “000” (step S108), and then sets the identifier “010” of the peripheral circuit B having the data transfer right (step S108). Step S109).

(Signal change timing)
FIG. 3 is a diagram illustrating the timing of signals transmitted by the data transfer apparatus according to the first embodiment.

  First, it is assumed that the peripheral circuit B performs data transfer, and then the peripheral circuit A performs data transfer.

  Each of the peripheral circuits A and B has a transfer waiting state from when the data transfer request signal is transmitted until the data is actually transferred after receiving the permission signal. In the example of FIG. 3, when the peripheral circuit A transmits the data transfer request signal, the peripheral circuit B is in the data transfer state, so that the peripheral circuit A receives the permission signal after the peripheral circuit B finishes the data transfer. Data transfer.

  The transfer waiting signal W is activated to “H” level when transfer waiting occurs in any of the peripheral circuits.

  The bus right indication signal K represents the identifier of the peripheral circuit B when the data transfer is performed in the peripheral circuit B, and represents the identifier of the peripheral circuit A when the data transfer is performed in the peripheral circuit A. .

  As described above, according to the present embodiment, a signal indicating whether or not the selected peripheral circuit is waiting for data transfer, a signal indicating whether or not a buffer error has occurred in any of the peripheral circuits, and data Since a signal indicating which peripheral circuit has the transfer right can be efficiently output to the outside with three terminals, a load on the mounting environment is also given to a high-functional SoC having many important terminals in the system. It can be implemented without

  Further, debugging by the designer is facilitated by a signal output from the terminal. That is, the validity of the data transfer method and the transfer priority can be confirmed by the signal output from the terminal. In addition, the designer can consider an optimal hardware configuration (such as a built-in FIFO (First In First Out) amount) when designing the next device.

  In addition, the point in time when the buffer error occurs is clarified, and by referring to the contents of the error status register 26 and the output of the encoder circuit 22 before and after the point of occurrence, it is possible to determine at what transfer the error has occurred. Can be clarified and measures can be easily taken.

[Second Embodiment]
FIG. 4 is a diagram illustrating the configuration of the data transfer apparatus according to the second embodiment.

  Referring to FIG. 4, data transfer device 2 includes peripheral circuits A and B, a data transfer bus 4, a data transfer control circuit 10, a transfer wait determination unit 12, and an external terminal C. This data transfer apparatus may further include the error notification unit 16, the data transfer right notification unit 14, and the external terminals D and E described in FIG.

  The peripheral circuits A and B, the data transfer bus 4 and the data transfer control circuit 10 are the same as those described in the first embodiment.

  The transfer waiting determination unit 12 includes a mode register 28, a selector circuit 30, a counter control circuit 32, a 16-bit counter 38, a transfer waiting time holding register 34, and a maximum transfer waiting time holding register 36.

  A CPU (not shown) sets an identifier representing a peripheral circuit for measuring the transfer waiting time in the mode register 28.

  The selector circuit 30 receives data transfer request signals, read data, and write data from all the peripheral circuits A and B connected to the data transfer bus 4, and outputs them from the peripheral circuit of the identifier set in the mode register 28. The data transfer request signal, read data, and write data thus output are output to the counter control circuit 32.

  When the counter control circuit 32 receives a data transfer request signal from the selector, it outputs a start signal for starting the count operation of the 16-bit counter 38 and activates the transfer wait signal W described in the first embodiment. Output to external terminal C.

  Further, the counter control circuit 32 outputs a stop signal for stopping the count operation of the 16-bit counter 38 when receiving the head of read data or write data from the selector.

  The 16-bit counter 38 increases the count value based on the rising edge of the data transfer bus clock. The 16-bit counter 38 starts updating the count value when receiving the start signal, and stops updating the count value when receiving the end signal. The count value of the 16-bit counter 38 is output to the transfer wait time holding register 34 after stopping.

  The transfer waiting time holding register 34 is a transfer waiting time represented by the count value after the stop of the 16-bit counter 38, that is, the number of times the rising edge of the data transfer bus clock is received for the peripheral circuit of the identifier set in the mode register 28. Hold.

  The maximum transfer wait time holding register 36 holds the maximum value of the history of count values held in the transfer wait time holding register 34.

(Operation)
FIG. 5 is a diagram for explaining the data transfer waiting time measurement operation of the second embodiment.

  Referring to FIG. 5, it is assumed that an identifier for specifying peripheral circuit A is set in mode register 28 in transfer waiting determination unit 12 by the CPU.

  Referring to FIG. 5, data transfer control circuit 10 waits for a data transfer request signal to be generated (step S201).

  The peripheral circuit A outputs a data transfer request signal to the data transfer control circuit 10 (step S202).

  Thereafter, the selector circuit 30 outputs the data transfer request signal output from the peripheral circuit A to the counter control circuit 32. The counter control circuit 32 receives the data transfer request signal from the selector circuit 30 and outputs a start signal for starting the counting operation of the 16-bit counter 38 (step S203).

  Next, the peripheral circuit A receives the data transfer permission signal and starts outputting write data, that is, starts data transfer (step S204).

  Thereafter, when receiving the head of the write data from the selector circuit 30, the counter control circuit 32 outputs a stop signal for stopping the counting operation of the 16-bit counter 38 (step S205).

  When the counting operation of the 16-bit counter 38 stops, the count value is sent to the transfer wait time holding register 34, and the count value held in the transfer wait time holding register 34 is updated. For example, the counter value “b” is stored (step S206).

  The maximum transfer waiting time holding register 36, when the updated count value of the transfer waiting time holding register 34 is larger than the held count value (for example, “a”), holds the held count value “a”. The count value “b” in the transfer waiting time holding register 34 is updated (step S207).

  The 16-bit counter 38 clears the count value to 0 after stopping the counting operation (step S208).

  Thereafter, the peripheral circuit A stops outputting the write data, that is, ends the data transfer (step S209).

  As described above, according to the present embodiment, when a data transfer request signal is received, the counter starts a count operation based on the data transfer bus clock, and when the head of read data or write data is received, the counter By stopping the counting operation, it is possible to measure the time from when the data transfer request signal is issued until the data is actually transferred.

[Third Embodiment]
FIG. 6 is a diagram illustrating the configuration of the data transfer apparatus according to the third embodiment.

  Referring to FIG. 6, data transfer device 72 includes data transfer bus 4, peripheral circuits A and B, error notification unit 16, data transfer control circuit 10, and priority change circuit 40. This data transfer apparatus may further include the data transfer right notification unit 14, the transfer wait determination unit 12, and the external terminals C to E described in FIG.

  Peripheral circuits A and B include write buffers 46 and 50 and read buffers 44 and 48. The write buffers 46 and 50 hold the write data for outputting to the data transfer bus 4 at the time of write access. The read buffers 44 and 48 hold the read data received from the data transfer bus 4 at the time of read access.

  When the read buffers 44 and 48 of the peripheral circuits A and B underflow, the identifiers of the peripheral circuits A and B are used as the identifiers of the peripheral circuits A and B underflowed by the read buffers 44 and 48. Set to

  When the read buffers 44 and 48 of the peripheral circuits A and B overflow, the identifiers of the peripheral circuits A and B are set in the error status register 26 as the identifiers of the peripheral circuits A and B where the read buffers 44 and 48 overflow. Is done.

  When the write buffers 46 and 50 of the peripheral circuits A and B are underflowed, the identifiers of the peripheral circuits A and B are used as the identifiers of the peripheral circuits A and B whose write buffers 46 and 50 are underflowed. Set to

  When the write buffers 46 and 50 of the peripheral circuits A and B overflow, the identifiers of the peripheral circuits A and B become the identifiers A and B of the peripheral circuits A and B that have overflowed the write buffers 46 and 50, respectively. 26.

  The data transfer control circuit 10 includes a priority setting register 42. The priority setting register 42 holds priority setting values of a plurality of peripheral circuits connected to the data transfer bus 4. The priority takes a value from 0 to 15. Priority 0 is the lowest priority and priority 15 is the highest priority.

  The data transfer control circuit 10 permits or rejects a request for data transfer by the peripheral circuit based on the priority set for the plurality of peripheral circuits A and B.

FIG. 7 is a diagram illustrating a priority change example by the priority change circuit 40.
When the error status register 26 of the error notification unit 16 holds the identifier of the peripheral circuit that has overflowed the read buffer, the priority changing circuit 40 lowers the priority of the peripheral circuit specified by the identifier by one level. .

  When the error status register 26 of the error notification unit 16 holds the identifier of the peripheral circuit in which the read buffer underflows, the priority changing circuit 40 sets the priority of the peripheral circuit specified by the identifier to one level. increase.

  When the error status register 26 of the error notification unit 16 holds the identifier of the peripheral circuit that has overflowed the write buffer, the priority changing circuit 40 increases the priority of the peripheral circuit specified by the identifier by one level. .

  When the error status register 26 of the error notification unit 16 holds the identifier of the peripheral circuit in which the write buffer underflows, the priority changing circuit 40 sets the priority of the peripheral circuit specified by the identifier to one level. Lower.

  As described above, according to the present embodiment, it is possible to suppress the occurrence of errors by changing the priority of peripheral circuits in which errors have occurred.

[Fourth Embodiment]
FIG. 8 is a diagram illustrating the configuration of the data transfer apparatus according to the fourth embodiment.

  Referring to FIG. 8, data transfer device 2 includes data transfer bus 4, peripheral circuits A and B, data transfer control circuit 10, total transfer wait time calculation circuit 53, adder circuit 55, and total transfer. A time calculation circuit 52 and a clock control circuit 57 are provided. The data transfer apparatus may further include the error notification unit 16, the data transfer right notification unit 14, and the external terminals C to E described in FIG.

  The data transfer control circuit 10 includes a transfer amount setting register 59. The transfer amount setting register 59 holds a set value for the amount of data transferred per transfer for each peripheral circuit connected to the data transfer bus 4.

  The total transfer waiting time calculation circuit 53 calculates the number A of data transfer bus clocks corresponding to the total data transfer time in the sampling period.

  Specifically, the total transfer wait time calculation circuit 53 includes the transfer wait determination unit 12, the adder circuit 150, and the total transfer wait time holding register 51 described in the second embodiment.

  When the adder circuit 150 receives a stop signal from the counter control circuit 32 in the transfer wait determination unit 12 in the sampling period, it reads the count value R0 from the transfer wait time holding register 34 of the transfer wait determination unit 12 and waits for all transfers. The count value in the time holding register 51 is added, and the count value in the total transfer waiting time holding register 51 is updated with the addition result. After the end of the sampling period, the total transfer waiting time holding register 51 holds the number A of data transfer bus clocks corresponding to the total transfer waiting time.

  The total transfer time calculation circuit 52 calculates the number B of data transfer bus clocks corresponding to the total transfer time in the sampling period based on the data transfer amount per time set for each peripheral circuit set in the transfer amount setting register 59. To do.

  For example, it is assumed that the data transfer amount per one time of the peripheral circuit A is 64 bytes, and the data transfer amount per one time of the peripheral circuit B is 32 bytes. The transfer rate of the data transfer bus 4 is assumed to be X bytes / second. In the sampling period, when 10 data transfers occur in the peripheral circuit A and 5 data transfers occur in the peripheral circuit B, the data transfer of the peripheral circuit A requires (64 × 10) / X (seconds). However, the data transfer of the peripheral circuit B requires (32 × 5) / X (seconds). Therefore, the total transfer time in a certain period is 800 / X (seconds), and the number B of data transfer bus clocks corresponding to the total transfer time is 800 / (X × T). T is the period of the data transfer bus clock.

  The adder circuit 55 adds the number A of data transfer bus clocks corresponding to all data transfer times in the sampling interval and the number B of data transfer bus clocks corresponding to all data transfer times, and adds all the data transfer bus clocks in the sampling interval. The number C of data transfer bus clocks corresponding to the total time of the transfer waiting time and the total transfer time is calculated.

  The clock control circuit 57 changes the frequency of the data transfer bus clock based on the ratio of the total time to the time of the sampling period.

  The clock control circuit 57 includes a division circuit 54, a multiplication circuit 56, and a clock multiplication circuit 58.

  The division circuit 54 divides the number S of data transfer bus clocks corresponding to the time of the sampling interval by the number C of data transfer bus clocks corresponding to the total time of all transfer waiting times and all transfer times in the sampling interval, The division value D is output.

The multiplication circuit 56 multiplies the multiplication set value h and the division value D and outputs a multiplication value M.
The clock multiplication circuit 58 increases the frequency of the data transfer bus clock by the division value D.

  That is, the clock multiplication circuit 58 outputs a clock having a frequency h times the frequency of the reference clock as the data transfer bus clock before the adjustment, but is M times the frequency of the reference clock after the adjustment. The frequency clock is output as the data transfer bus clock.

(Example)
FIG. 9 is a diagram illustrating transfer waiting and data transfer in the sampling period.

  As shown in FIG. 9, in the sampling period, in the peripheral circuit A, the transfer waiting time is 100 data transfer bus clocks long, the transfer time is 250 data transfer bus clocks long, transfer waiting time Is the length of 150 data transfer bus clocks, and the transfer time is 250 data transfer bus clocks long.

  In peripheral circuit B, the transfer waiting time is 100 data transfer bus clocks long, the transfer time is 250 data transfer bus clocks long, and the transfer waiting time is 150 data transfer bus clocks. , And the transfer time is 250 data transfer bus clocks.

  FIG. 10 is a diagram for explaining clock control in the transfer waiting and data transfer states of FIG.

  As shown in FIG. 10, the total transfer waiting time A calculated by the total transfer waiting time calculation unit is the length of 500 data transfer bus clocks. The total transfer time B calculated by the total transfer time calculation unit is the length of 1000 data transfer bus clocks. The total time C of the total transfer waiting time and the total transfer time calculated by the adder circuit 55 is the length of 1500 data transfer bus clocks. The sampling period S has a length corresponding to 4500 data transfer bus clocks.

  The division value D calculated by the division circuit 54 is 3. When the multiplication set value h is 2, the multiplication value M is 6. Therefore, the clock multiplication circuit 58 outputs a clock having a frequency that is six times the frequency of the reference clock as the data transfer bus clock.

  As described above, according to the present embodiment, it is possible to determine and set the optimum operating frequency of the data transfer bus clock from the actual operation, and thus it is possible to suppress wasteful power consumption.

[Fifth Embodiment]
FIG. 11 is a diagram illustrating the configuration of the data transfer apparatus according to the fifth embodiment.

  Referring to FIG. 11, data transfer device 90 includes peripheral circuits A and B, data transfer bus 4, data transfer right notification unit 14, error notification unit 16, transfer amount change circuit 60, data transfer. And a control circuit 10. The data transfer apparatus may further include the transfer wait determination unit 12 and the external terminals C to E described with reference to FIG.

  The data transfer control circuit 10 includes a priority setting register 42 and a transfer amount setting register 59.

  The priority setting register 42 holds the setting values of the priorities of the peripheral circuits A and B connected to the data transfer bus 4.

  The transfer amount setting register 59 holds a set value of the data transfer amount per time for each peripheral circuit connected to the data transfer bus 4. Here, the amount of data transferred per time refers to the amount of data that can be transferred when a single data transfer request signal is issued and a permission signal is received.

  The data transfer control circuit 10 refers to the priority setting register 42 and, based on the priority set for the plurality of peripheral circuits A and B, permits or rejects the data transfer request signal from the peripheral circuits A and B. Or dismiss. When the data transfer control circuit 10 permits data transfer, the data transfer control circuit 10 refers to the transfer amount setting register 59, and determines the data transfer amount per one time set in the peripheral circuit that permits data transfer. Controls the amount of data transferred per time.

  As described in the first embodiment, the data transfer right notification unit 14 outputs a 3-bit bus right display signal K that encodes the identifier of the peripheral circuit having the data transfer right.

  As described in the first embodiment, when a buffer error occurs in any of the peripheral circuits connected to the data transfer bus 4, the error notification unit 16 outputs the error signal E asserted to the “H” level. “H” is output.

  The transfer amount changing circuit 60 refers to the bus right display signal K output from the data transfer right notification unit 14 when the error signal E output from the error notification unit 16 is asserted to the “H” level. Identify the peripheral circuit where the error has occurred. The transfer amount changing circuit 60 refers to the priority setting register 42 and identifies a peripheral circuit having a higher priority than the peripheral circuit in which the identified error has occurred. When there are a plurality of peripheral circuits with high priority, the transfer amount changing circuit 60 specifies only one peripheral circuit with the highest priority among them. The transfer amount changing circuit 60 reduces the data transfer amount per time of the specified peripheral circuit having a high priority.

FIG. 12 is a diagram illustrating an example of priorities of peripheral circuits.
Referring to FIG. 12, in this example, the priorities of peripheral circuits A, B, and C are “9”, “6”, and “4”, respectively.

FIG. 13A shows an initial value of the data transfer amount per time of each peripheral circuit.
As shown in FIG. 13A, in this example, the data transfer amount per time of all the peripheral circuits is “64” bytes.

  In this state, when an error occurs in the peripheral circuit B, one time of the peripheral circuit C having a higher priority than the peripheral circuit B is specified. Then, the data transfer amount per transfer of the peripheral circuit C is reduced to ½ of the current transfer amount.

  FIG. 13B is a diagram showing the data transfer amount per time of each peripheral circuit after the transfer amount adjustment.

  As shown in FIG. 13B, in this example, the data transfer amount per time of the peripheral circuit C is reduced to 32 bytes.

  FIG. 14A is a diagram for explaining data transfer of the peripheral circuit B under the transfer amount set value of FIG.

  As shown in FIG. 14A, the data transferred from the peripheral circuit B is divided into 64 bytes and transferred. In this case, the peripheral circuit B issues a data transfer request signal every time before transferring the divided 64-byte data.

  FIG. 14B is a diagram for explaining data transfer of the peripheral circuit B under the transfer amount setting value of FIG. 13B.

  As shown in FIG. 14B, the data transferred from the peripheral circuit B is divided into 32 bytes and transferred. In this case, the peripheral circuit B issues a data transfer request signal every time before transferring the divided 32-byte data.

  As described above, according to the present embodiment, since the amount of data transferred per time of a peripheral circuit having a higher priority than the peripheral circuit in which the error has occurred is reduced, the occurrence of an error can be suppressed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  2, 72, 90 Data transfer device, 4 Data transfer bus, 10 Data transfer control circuit, 12 Transfer wait determination unit, 14 Data transfer right notification unit, 16 Error notification unit, 18, 28 Mode register, 20 Selector, 22 Encoder circuit , 24 OR circuit, 26 error status register, 30 selector circuit, 32 counter control circuit, 34 transfer waiting time holding register, 36 maximum transfer waiting time holding register, 38 16 bit counter, 40 priority changing circuit, 42 priority setting register 44, 48 Read buffer, 46, 50 Write buffer, 51 Total transfer latency holding register, 52 Total transfer time calculation circuit, 53 Total transfer latency calculation circuit, 54 Division circuit, 55, 150 Addition circuit, 56 Multiplication circuit, 57 Clock control circuit, 58 clock Multiplier circuit, 59 transfer amount setting register, 60 transfer volume deflection circuit, A, B peripheral circuit, C, D, E external terminal.

Claims (10)

A common bus,
A plurality of bus use circuits for transferring data through the common bus;
First, second and third terminals connected to the outside;
A transfer wait determination unit for outputting a first signal indicating whether or not a selected bus use circuit of the plurality of bus use circuits is waiting for data transfer to the outside through the first terminal;
A data transfer right notifying unit for outputting a second signal representing the bus use circuit that is transferring data among the plurality of bus use circuits to the outside through the second terminal;
An error notification unit that outputs a third signal indicating whether or not a buffer error has occurred in any one of the plurality of bus use circuits to the outside through the third terminal; Transfer device.   The data transfer device according to claim 1, wherein the transfer wait determination unit further measures the data transfer wait time of the selected bus use circuit. The transfer waiting determination unit
A counter that counts up according to the clock of the common bus;
When the transfer request signal output from the selected bus use circuit is received, the counter starts counting up. When the read data or write data output from the selected bus use circuit is received, the counter counts up. A counter control circuit for stopping
The data transfer device according to claim 2, further comprising: a first register that holds a count value after the counter is stopped. The transfer waiting determination unit further includes:
The data transfer device according to claim 3, further comprising a second register that holds a maximum value of the history of the count values held in the first register. The error notification unit further includes an error status register that holds an identifier representing a bus use circuit in which the buffer error has occurred,
The data transfer device
A data transfer control circuit for permitting or rejecting a request for data transfer by the bus using circuit based on the priority set for the plurality of bus using circuits;
The data transfer device according to claim 1, further comprising: a priority changing circuit that changes the priority of the bus use circuit in which the buffer error has occurred in the error status register. The bus use circuit includes a read buffer,
The priority changing circuit decreases the priority of the bus use circuit in which an overflow of the read buffer has occurred as the buffer error, and increases the priority of the bus use circuit in which an underflow of the read buffer has occurred as the buffer error. The data transfer device according to claim 5. The bus use circuit includes a write buffer,
The priority changing circuit increases the priority of the bus use circuit in which the write buffer overflow has occurred as the buffer error, and decreases the priority of the bus use circuit in which the write buffer underflow has occurred as the buffer error. The data transfer device according to claim 5. The data transfer device further includes:
A first calculation unit for calculating a total time for waiting for data transfer by the plurality of bus use circuits in the sampling period;
A second calculation unit for calculating a total time of data transfer by the plurality of bus using circuits in the sampling period;
An adder that calculates a sum of the total time of the data transfer and the total time of the data transfer waiting in the sampling period;
The data transfer device according to claim 1, further comprising: a clock control circuit that changes a clock frequency of the common bus based on a ratio of the sum of the total times to the time of the sampling period.   9. The data transfer device according to claim 8, wherein the clock control circuit increases the clock frequency of the common bus by a multiple of a value obtained by dividing the time of the sampling period by the sum of the total time. The data transfer device further includes:
Based on the priority set for the plurality of bus use circuits, when the data transfer request by the bus use circuit is permitted or rejected and the data transfer is permitted, the data transfer is permitted. A data transfer control unit for controlling the transfer amount per time by the bus using circuit based on the transfer amount per time set in
Based on the second signal and the third signal, the bus use circuit in which the buffer error has occurred is specified, and each bus use circuit having a higher priority than the priority of the specified bus use circuit The data transfer apparatus according to claim 1, further comprising: a transfer amount changing circuit that decreases a transfer amount of the data.

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