JP2012204640A - Method for forming alignment mark and method for manufacturing optical semiconductor element - Google Patents

Abstract

An alignment mark forming method and an optical semiconductor device manufacturing method capable of suppressing the collapse of the shape of a plurality of recesses in an alignment mark when an regrowth semiconductor layer is etched to dig out an alignment mark.
In this method, a part of a semiconductor layer is removed from a semiconductor laminate having a semiconductor layer containing Al in the composition and a semiconductor layer grown on the semiconductor layer. Formed on the alignment mark 24; a step of forming an alignment mark 24 including a plurality of recesses 22 with the layer 16 as a bottom surface; a step of growing an embedded semiconductor layer 26 on the semiconductor layer 18 and the plurality of recesses 22; Removing the embedded semiconductor layer 26 and exposing the plurality of recesses 22. The width of the concave portion 22 is formed to be larger than 1 μm and smaller than 6 μm, and the ratio (S / D) between the depth D of the concave portion 22 and the interval S between the concave portions 22 is set to 3 or more.
[Selection] Figure 2

Description

  The present invention relates to an alignment mark forming method and an optical semiconductor device manufacturing method.

  Patent Document 1 discloses a semiconductor laser element having a diffraction grating. In the semiconductor laser device described in this document, cladding layers are provided above and below the active layer. A current blocking layer having a stripe-shaped opening is embedded in at least one of these cladding layers. A diffraction grating for controlling the oscillation wavelength is formed at the interface of the current blocking layer, or between the interface and the active layer and excluding the stripe-shaped opening.

Japanese Patent Laid-Open No. 11-168261

  In a semiconductor process, alignment marks for alignment on a wafer are formed in a region other than a region where a semiconductor element is formed. The alignment mark is preferably configured by a plurality of recesses formed in the semiconductor layer by etching or the like and arranged in a predetermined direction. However, depending on the structure of the manufactured semiconductor element, the alignment mark once formed in the semiconductor process may be filled with the regrown semiconductor layer. In such a case, a step of removing the semiconductor layer covering the alignment mark by etching or the like and exposing the alignment mark again is necessary.

  As a semiconductor element that requires such a process, for example, there is a distribution feedback (DFB) laser element. In fabricating the DFB laser element, a diffraction grating semiconductor layer is first grown on the active layer, and then the diffraction grating semiconductor layer is etched to form a diffraction grating having a predetermined periodic structure. At this time, a plurality of concave portions serving as alignment marks for grasping the formation position of the diffraction grating are formed in a predetermined region on the wafer. Next, a semiconductor layer for embedding the diffraction grating is grown on the diffraction grating layer. Then, after removing a portion of the semiconductor layer on a predetermined region to expose the alignment mark, an etching mask having a stripe pattern is formed at a predetermined position on the semiconductor layer with reference to the alignment mark. Thereafter, the semiconductor layer is etched using the etching mask to obtain a structure for narrowing current and forming an optical waveguide (eg, mesa stripe structure).

  However, the present inventors have clarified that the following problems exist in the manufacturing process of the DFB laser element described above. That is, some DFB laser elements have an active layer made of a compound semiconductor crystal containing Al (for example, AlGaInAs). Further, since the plurality of recesses of the alignment mark are formed by etching the semiconductor layer for the diffraction grating, their bottom surfaces may reach the active layer. In such a case, Al exposed at the bottom surface of the recess is oxidized and an Al oxide layer is formed. When a semiconductor layer is regrown on such an Al oxide layer, abnormal growth occurs in the semiconductor layer, and the etching characteristics of the abnormally grown portion with respect to a predetermined etchant become different from other regions. As a result, when the semiconductor layer is etched to expose the alignment mark, the etching rate of the semiconductor layer is increased only on the plurality of recesses, and the shape of the plurality of recesses is broken by the etching.

  The present invention has been made in view of such problems, and alignment mark formation that can suppress the collapse of the shape of the plurality of recesses of the alignment mark when the regrowth semiconductor layer is etched to dig out the alignment mark. It is an object to provide a method and a method for manufacturing an optical semiconductor device.

  In order to solve the above-described problems, an alignment mark forming method according to the present invention is a method of forming an alignment mark used for alignment in manufacturing a semiconductor element, and includes (1) a first element containing Al in the composition. By removing a part of the second semiconductor layer in the semiconductor stack including the first semiconductor layer and the second semiconductor layer grown on the first semiconductor layer, the first semiconductor layer and the second semiconductor layer are arranged in a predetermined direction. An alignment mark forming step of forming an alignment mark including a plurality of recesses with the semiconductor layer as a bottom surface; (2) a growth step of growing a third semiconductor layer on the second semiconductor layer and the plurality of recesses; 3) An alignment mark digging step for exposing a plurality of recesses by removing the third semiconductor layer formed on the alignment mark. Then, in the alignment mark forming step, the width of each concave portion in a predetermined direction is larger than 1 μm and smaller than 6 μm, and the ratio between the depth D of each concave portion and the interval S between the concave portions adjacent to each other in the predetermined direction (S / D) is 3 or more.

  In this alignment mark forming method, the width of each recess constituting the alignment mark is formed to be larger than 1 μm and smaller than 6 μm, and the ratio between the depth D of each recess and the interval S between the recesses adjacent to each other in a predetermined direction ( S / D) is set to 3 or more. The inventor has found that the degree to which the plurality of recesses collapse when the alignment mark is dug depends on the dimensions of the plurality of recesses. That is, when the width of the concave portion is increased, the bottom area of the concave portion is increased, and the influence of the Al oxide layer generated on the bottom surface becomes remarkable. Moreover, when the ratio (S / D) of the depth D of a recessed part and the space | interval S between recessed parts is small, the side wall which partitions a recessed part will become thin, and the shape of a recessed part will fall easily. As a result of research by the present inventors, the width of each recess is formed to be larger than 1 μm and smaller than 6 μm, and the ratio (S / D) between the depth D of each recess and the interval S between the recesses is 3 or more. By doing this, it became clear that collapse of the shape of the plurality of recesses can be effectively suppressed. That is, according to the above-described alignment mark forming method, when the regrown third semiconductor layer is etched to dig out the alignment mark, it is possible to suppress the collapse of the shape of the plurality of recesses of the alignment mark.

  In the above-described alignment mark forming method, the third semiconductor layer may include at least one element of Al, Ga, and In and at least one element of P and As in the composition.

  The method of manufacturing an optical semiconductor device according to the present invention includes (1) a semiconductor having a first semiconductor layer containing Al in the composition and a second semiconductor layer grown on the first semiconductor layer on a substrate. Removing a part of the second semiconductor layer in the stacked body to form an alignment mark including a plurality of recesses arranged in a predetermined direction and having the first semiconductor layer as a bottom surface; ) A second step of forming a diffraction grating having periodic irregularities in the second semiconductor layer on a predetermined region of the substrate using the alignment mark; and (3) so as to cover the plurality of recesses and the diffraction grating. A third step of growing a third semiconductor layer; (4) a fourth step of exposing a plurality of recesses by removing the third semiconductor layer formed on the alignment mark; and (5). Including a pattern extending in a predetermined optical waveguide direction Comprising a fifth step of forming a Tchingumasuku the third semiconductor layer, and a sixth step of etching with respect to (6) using an etching mask, at least a third semiconductor layer. In the first step, the width of each concave portion in a predetermined direction is formed to be larger than 1 μm and smaller than 6 μm, and the ratio of the depth D of each concave portion to the interval S between the concave portions adjacent to each other in the predetermined direction (S / D) is 3 or more.

  In this optical semiconductor device manufacturing method, as in the alignment mark forming method described above, the width of each recess is formed to be greater than 1 μm and less than 6 μm, and the ratio between the depth D of each recess and the spacing S between the recesses ( S / D) is set to 3 or more. Therefore, when the regrowth third semiconductor layer is etched to dig out the alignment mark, it is possible to suppress the collapse of the shape of the plurality of recesses of the alignment mark.

  According to the method for forming an alignment mark and the method for manufacturing an optical semiconductor element according to the present invention, it is possible to suppress the collapse of the shape of the plurality of recesses of the alignment mark when the regrowth semiconductor layer is etched to dig out the alignment mark. .

FIG. 1 is a diagram showing each step of the alignment mark forming method according to the first embodiment. FIG. 2 is a diagram showing each step of the alignment mark forming method according to the first embodiment. FIG. 3 is a diagram for explaining the difference in visibility due to the dimensions of the plurality of recesses of the alignment mark. FIG. 4A is a photograph showing the state of the alignment marks dug when the width of the plurality of recesses is 4 μm. FIG. 4B is a photograph showing the state of the alignment mark dug when the width of the plurality of recesses is 2 μm. FIG. 5 is a diagram illustrating one process of the method of manufacturing an optical semiconductor device according to the second embodiment. (A) is a top view, (b) is a figure which shows the VV cross section of (a). FIG. 6 is a diagram illustrating one step of the method of manufacturing an optical semiconductor device according to the second embodiment. (A) is a top view, (b) is a figure which shows the VI-VI cross section of (a). FIG. 7 is a diagram illustrating one process of the method of manufacturing an optical semiconductor device according to the second embodiment. (A) is a top view, (b) is a figure which shows the VII-VII cross section of (a). FIG. 8 is a diagram illustrating one step of the method of manufacturing an optical semiconductor device according to the second embodiment. (A) is a top view, (b) is a figure which shows the VIII-VIII cross section of (a). FIG. 9 is a diagram illustrating a step of the method of manufacturing the optical semiconductor device according to the second embodiment. (A) is a top view, (b) is a figure which shows the IX-IX cross section of (a). FIG. 10 is a diagram illustrating a step of the method of manufacturing the optical semiconductor device according to the second embodiment. (A) is a top view, (b) is a figure which shows the XX cross section of (a). FIG. 11 is a diagram illustrating a step of the method of manufacturing an optical semiconductor device according to the second embodiment. (A) is a top view, (b) is a figure which shows the XI-XI cross section of (a). FIG. 12 is a diagram illustrating one process of the method of manufacturing an optical semiconductor device according to the second embodiment. (A) is a top view, (b) is a figure which shows the XII-XII cross section of (a). FIG. 13A and FIG. 13B are diagrams showing each step of the method for manufacturing the optical semiconductor device according to the second embodiment. FIG. 14A and FIG. 14B are diagrams showing respective steps of the method for manufacturing the optical semiconductor element according to the second embodiment.

  Embodiments of an alignment mark forming method and an optical semiconductor device manufacturing method according to the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
1 and 2 are diagrams showing each step of the alignment mark forming method according to the first embodiment of the present invention. In the present embodiment, alignment marks used for various alignments are formed in a general optical semiconductor element manufacturing process.

  First, as shown in FIG. 1A, semiconductor layers 10, 16, and 18 are grown on the wafer 12 in this order to produce the semiconductor stacked body 10. Here, the wafer 12 is a semiconductor substrate made of, for example, n-type InP. The semiconductor layers 14, 16, and 18 contain at least one element of Al, Ga, and In and at least one element of P and As in the composition. The semiconductor layer 14 is made of, for example, n-type InP. The semiconductor layer 16 contains Al in the composition, and is an active layer having, for example, an AlGaInAs multiple quantum well structure. The semiconductor layer 18 is made of, for example, p-type InGaAsP and is, for example, a semiconductor layer for a diffraction grating. In the present embodiment, the semiconductor layer 16 is a first semiconductor layer, and the semiconductor layer 18 is a second semiconductor layer. For the growth of the semiconductor layers 14, 16 and 18, for example, an organometallic vapor phase epitaxy (OMVPE) apparatus is used.

Next, as shown in FIG. 1B, an etching mask 20 is formed on the semiconductor layer 18 (etching mask forming step). This etching mask 20 is made of, for example, a silicon compound such as SiO ₂ or SiN, and has a plurality of openings 20a corresponding to the planar shape of a plurality of recesses that serve as alignment marks. The plurality of openings 20a are arranged in a predetermined direction (arrow A in the drawing). Such an etching mask 20 is formed by forming a silicon compound film on the entire surface of the semiconductor layer 18 by, for example, chemical vapor deposition (CVD), and then forming a plurality of silicon masks on the silicon compound film using a normal photolithography technique. It is suitably manufactured by forming the opening 20a.

  Subsequently, as shown in FIG. 1C, the semiconductor layer 18 is etched using the etching mask 20 to remove a part of the semiconductor layer 18 and expose the semiconductor layer 16. As an etching method in this step, for example, dry etching is suitable. By this step, an alignment mark 24 including a plurality of recesses 22 is formed (alignment mark forming step). In addition, the some recessed part 22 is located in a line along the predetermined direction A mentioned above. The bottom surface of each recess 22 is constituted by the semiconductor layer 16, and the side surface of each recess 22 is mainly constituted by the semiconductor layer 18.

  Here, in the above-described etching mask formation step and alignment mark formation step, the width W of each concave portion 22 in the predetermined direction A is formed to be larger than 1 μm and smaller than 6 μm. In addition, the ratio (S / D) between the depth D of each recess 22 and the interval S between the recesses 22 adjacent to each other in the predetermined direction A is set to 3 or more.

  Subsequently, as shown in FIG. 2A, the embedded semiconductor layer 26 is regrown on the semiconductor layer 18 and the plurality of recesses 22 (growth step). In the present embodiment, the buried semiconductor layer 26 is a third semiconductor layer, and contains at least one element of Al, Ga, and In and at least one element of P and As in the composition. It is out. The buried semiconductor layer 26 is made of, for example, p-type InP. For example, an OMVPE apparatus is used for the growth of the buried semiconductor layer 26.

  Subsequently, as shown in FIG. 2B, the embedded semiconductor layer 26 formed on the alignment mark 24 is removed to expose the plurality of recesses 22 of the alignment mark 24 (alignment mark digging step). . Specifically, after forming an etching mask having an opening on the alignment mark 24 on the embedded semiconductor layer 26, the portion of the embedded semiconductor layer 26 not covered with the etching mask is removed by wet etching or the like. As the etchant for wet etching, for example, a hydrochloric acid-based etchant is suitable.

  The effects obtained by the alignment mark forming method according to the present embodiment described above will be described. FIG. 3 is a diagram for explaining a difference in visibility due to the dimensions of the plurality of recesses 22 of the alignment mark 24. As described above, when the semiconductor layer 16 is composed of a compound semiconductor crystal containing Al (for example, AlGaInAs), Al on the surface of the semiconductor layer 16 exposed at the bottom surface of the recess 22 is oxidized to produce an Al oxide layer. . When the buried semiconductor layer 26 is regrown on such an Al oxide layer, an abnormally grown portion 26a is generated as shown in FIG. When etching the buried semiconductor layer 26, the etching rate of the abnormally grown portion 26a is higher than that of other portions. When the width W of the plurality of recesses 22 shown in FIG. 1C is wide and the interval S between the recesses 22 is short, the semiconductor layer 16 is eroded by the etchant as shown in FIG. As a result, the base portions of the plurality of recesses 22 are scraped off and the shape thereof is destroyed. As a result, the visibility of the alignment mark 24 is significantly reduced. On the other hand, in this embodiment, the width W of the plurality of recesses 22 is smaller than 6 μm, and the interval S between the recesses 22 is short (the ratio (S / D) of the depth D to the interval S of the recesses 22 is 3). As described above, as shown in FIG. 3C, the degree to which the semiconductor layer 16 is eroded can be kept low, and the shapes of the plurality of recesses 22 can be suitably maintained.

  Here, FIG. 4A shows the digging when the width W of the plurality of recesses 22 is 4 μm and the ratio (S / D) between the depth D of the recesses 22 and the interval S between the recesses 22 is 2. It is a photograph which shows the mode of the alignment mark taken out. Further, FIG. 4B is a photograph showing the state of the excavated alignment mark when the width W of the plurality of recesses 22 is 2 μm and the ratio (S / D) is 4. Referring to FIG. 4A, when the width W is 4 μm and the ratio (S / D) is 2, the shape of the plurality of recesses 22 is broken to the extent that it cannot be recognized by the stepper. On the other hand, referring to FIG. 4B, when the width W is 2 μm and the ratio (S / D) is 4, the shape of the plurality of recesses 22 is clear enough to be recognized by the stepper. Is maintained. As described above, according to the alignment mark forming method of the present embodiment, when the regrowth embedded semiconductor layer 26 is etched to dig out the alignment mark 24, the shape of the plurality of recesses 22 is significantly prevented from being deformed. be able to.

  The width W of the plurality of recesses 22 is preferably larger than 1 μm. Thereby, the alignment mark 24 can be suitably recognized in the stepper.

  Further, as in this embodiment, the embedded semiconductor layer 26 may include at least one element of Al, Ga, and In and at least one element of P and As in the composition. In such a case, an abnormally grown portion 26a (see FIG. 3A) tends to occur in the embedded semiconductor layer 26, so that the effect of the alignment mark forming method of the present embodiment becomes more remarkable.

(Second Embodiment)
5 to 14 are views showing each step of the method of manufacturing the optical semiconductor element according to the second embodiment of the present invention. 5 to 12, (a) is a plan view of a wafer being manufactured, and (b) is a cross-sectional view taken along the cutting line shown in (a). In this embodiment, an alignment mark is used for alignment between the diffraction grating and the mesa stripe structure in the process of manufacturing the DFB laser element as the optical semiconductor element.

  First, as shown in FIG. 5, a wafer 32 is prepared. The wafer 32 is made of, for example, n-type InP. The wafer 32 has an element formation region 32b and an alignment mark formation region 32c on the main surface 32a. Next, as illustrated in FIG. 6, the semiconductor layer 30 is manufactured by growing the cladding layer 34, the active layer 36, and the diffraction grating layer 38 in this order on the main surface 32 a of the wafer 32. The cladding layer 34, the active layer 36, and the diffraction grating layer 38 contain at least one element of Al, Ga, and In and at least one element of P and As in the composition. The clad layer 34 is made of, for example, n-type InP. The active layer 36 contains Al in the composition and has, for example, an AlGaInAs multiple quantum well structure. The diffraction grating layer 38 is made of, for example, p-type InGaAsP. In the present embodiment, the active layer 36 is a first semiconductor layer, and the diffraction grating layer 38 is a second semiconductor layer. For the growth of the cladding layer 34, the active layer 36, and the diffraction grating layer 38, for example, an OMVPE apparatus is used.

Subsequently, as shown in FIG. 7, an etching mask 40 is formed on the diffraction grating layer 38 (etching mask forming step). The etching mask 40 is made of, for example, a silicon compound such as SiO ₂ , and includes a plurality of openings 40a corresponding to the planar shape of a plurality of recesses serving as alignment marks, and a plurality of periodic openings 40b for forming a diffraction grating. And have. The plurality of openings 40 a are arranged along the predetermined direction A. The etching mask 40 is preferably manufactured by forming a silicon compound film on the entire surface of the diffraction grating layer 38 by CVD, for example, and then forming openings 40a and 40b in the silicon compound film using a normal photolithography technique. The

Subsequently, the diffraction grating layer 38 is etched using the etching mask 40 to remove a part of the diffraction grating layer 38 and expose the active layer 36 as shown in FIG. As an etching method in this step, for example, dry etching is suitable. By this step, an alignment mark 44 including a plurality of recesses 42 is formed (alignment mark forming step). Subsequently, a silicon compound film such as SiO ₂ is formed on the entire surface of the diffraction grating layer 38 on which the alignment mark 44 is formed by, for example, CVD. Thereafter, a resist is applied on the silicon compound film, and a diffraction grating pattern is formed on the resist by using an interference exposure method or an EB exposure method. Next, the silicon compound film is etched using the resist on which the diffraction grating pattern is formed, whereby the diffraction grating pattern is transferred to the silicon compound film, and a diffraction grating forming mask is created (not shown). When forming the diffraction grating forming mask, the alignment mark formed in the alignment mark forming step is used for alignment for forming the diffraction grating in the region where the diffraction grating pattern of the wafer 32 is to be formed. . As a result of alignment using the alignment mark, a diffraction grating pattern can be formed in a predetermined region of the wafer 32. This alignment mark is also used in a step of forming an etching mask for forming a semiconductor mesa described later and a step of forming an electrode in a predetermined region of the semiconductor mesa. In order to align the region where the diffraction grating is formed, the region where the semiconductor mesa is formed, and the region where the electrode is formed on the semiconductor mesa, an accuracy of submicrometer unit is required. By using the alignment mark 44 as a reference, it is possible to accurately and accurately control the positional relationship between the regions where the diffraction grating is formed, the region where the semiconductor mesa is formed, and the region where the electrode is formed on the semiconductor mesa. it can. The plurality of recesses 42 are arranged along the predetermined direction A described above. The bottom surface of each recess 42 is formed by an active layer 36, and the side surface of each recess 42 is mainly formed by a diffraction grating layer 38.

  Here, as shown in the partially enlarged view of FIG. 8B, in the above-described etching mask formation step and alignment mark formation step, the width W in the predetermined direction A of each recess 42 is set as in the first embodiment. It is larger than 1 μm and smaller than 6 μm. In addition, the ratio (S / D) between the depth D of each recess 42 and the interval S between the recesses 42 adjacent to each other in the predetermined direction A is 3 or more.

  Subsequently, as shown in FIG. 9, the buried semiconductor layer 48 is regrown on the entire surface of the semiconductor stack 30 to cover the diffraction grating 50 and the plurality of recesses 42 with the buried semiconductor layer 48 (growth step). ). In the present embodiment, the buried semiconductor layer 48 is a third semiconductor layer, and contains at least one element of Al, Ga, and In and at least one element of P and As in the composition. It is out. The buried semiconductor layer 48 is made of, for example, p-type InP. For example, an OMVPE apparatus is used for the growth of the buried semiconductor layer 48.

  Subsequently, the embedded semiconductor layer 48 formed on the alignment mark 44 is removed to expose the plurality of recesses 42 of the alignment mark 44 (alignment mark digging step). Specifically, as shown in FIG. 10, an etching mask 52 having an opening 52a on the alignment mark 44 is formed on the embedded semiconductor layer 48, and then covered with the etching mask 52 as shown in FIG. The portion of the buried semiconductor layer 48 that has not been removed is removed by wet etching or the like. As the etchant for wet etching, for example, a hydrochloric acid-based etchant is suitable.

  Subsequently, as shown in FIG. 12, an etching mask 54 is formed on the embedded semiconductor layer 48 (etching mask forming step). The etching mask 54 includes a pattern extending in a predetermined optical waveguide direction. In the present embodiment, the etching mask 54 is formed only on a region to be an optical waveguide of the semiconductor laser element. The etching mask 54 has a planar shape such as a stripe shape extending in the parallel direction of the diffraction grating 50. In this step, the relative positional relationship between the diffraction grating 50 and the etching mask 54 is determined based on the alignment mark 44. The etching mask 54 is preferably formed by the same method as the etching mask 40 described above.

  Subsequently, as shown in FIG. 13A, dry etching is performed using the etching mask 54 to remove a part of the active layer 36, the diffraction grating layer 38 and the embedded semiconductor layer 48. Thereby, a mesa structure 56 as an optical waveguide structure is formed. In FIG. 13A, the etching depth reaches the cladding layer 34, and the mesa structure 56 includes a part of the cladding layer 34, the active layer 36, the diffraction grating layer 38, and the buried semiconductor layer. 48.

  Subsequently, as shown in FIG. 13B, a current blocking region 58 is formed by selectively growing an n-type InP region 58a and a p-type InP region 58b in order while leaving the etching mask 54. For the growth of the n-type InP region 58a and the p-type InP region 58b, for example, an OMVPE apparatus is used.

  Subsequently, after removing the etching mask 54, as shown in FIG. 14A, the cladding layer 60 and the contact layer 62 are grown in order from the mesa structure 56 to the current blocking region 58. The clad layer 60 is made of, for example, p-type InP. The contact layer 62 is made of, for example, p-type InGaAs. For the growth of the cladding layer 60 and the contact layer 62, for example, an OMVPE apparatus is used. Then, after polishing the back surface 32d of the wafer 32 to reduce the thickness of the wafer 32 to, for example, about 100 μm, an anode electrode 64 is formed on the contact layer 62 as shown in FIG. A cathode electrode 66 is formed on the back surface 32 d of the wafer 32. Finally, the wafer product is divided into chips to complete a DFB laser device.

  In the optical semiconductor device manufacturing method according to the present embodiment, as in the first embodiment, the width W of each recess 42 constituting the alignment mark 44 is formed to be greater than 1 μm and less than 6 μm, and the depth D of each recess 42. And the ratio (S / D) between the recesses 42 adjacent to each other along the predetermined direction A is 3 or more. Therefore, when the regrowth embedded semiconductor layer 48 is etched to dig out the alignment mark 44, the shape of the plurality of recesses 42 of the alignment mark 44 can be prevented from being deformed.

In the case where an embedded semiconductor layer is grown on an Al oxide layer, a method of preventing abnormal growth by increasing the wafer temperature before growing the embedded semiconductor layer and etching the Al oxide layer with AsH ₃ or PH ₃ . Is also possible. However, when the diffraction grating 50 is exposed in the state before the buried semiconductor layer 48 is grown as in this embodiment, the shape of the diffraction grating 50 is destroyed at a high temperature, which affects the characteristics of the DFB laser element. Therefore, it is difficult to raise the wafer temperature. According to the method for manufacturing an optical semiconductor element according to the present embodiment, even in such a case, the collapse of the shapes of the plurality of recesses 42 of the alignment mark 44 can be effectively suppressed.

  The alignment mark forming method and the optical semiconductor device manufacturing method according to the present invention are not limited to the above-described embodiments, and various other modifications are possible. For example, in the second embodiment, the DFB laser element is exemplified as the optical semiconductor element. However, the optical semiconductor element to which the present invention is applied is not limited to this, and the semiconductor layer formed by regrowth is not regrown. Any device may be used as long as it is necessary to align the structure formed after and the structure formed after regrowth. In the second embodiment, the embedded mesa structure is exemplified as the optical waveguide structure. However, the present invention can be applied to other optical waveguide structures such as a ridge structure.

  DESCRIPTION OF SYMBOLS 10,30 ... Semiconductor laminated body, 12, 32 ... Wafer, 14, 16, 18 ... Semiconductor layer, 20, 40, 52, 54 ... Etching mask, 20a, 40a, 40b, 52a ... Opening, 22, 42 ... Recess 24, 44 ... alignment mark, 26, 48 ... buried semiconductor layer, 26a ... abnormally grown portion, 32b ... element forming region, 32c ... alignment mark forming region, 34, 60 ... clad layer, 36 ... active layer, 38 ... Diffraction grating layer, 50 ... Diffraction grating, 56 ... Mesa structure, 58 ... Current blocking region, 58a ... n-type InP region, 58b ... p-type InP region, 62 ... contact layer, 64 ... anode electrode, 66 ... cathode electrode, A ... predetermined direction, S ... interval, W ... width, D ... depth.

Claims (3)

A method of forming an alignment mark used for alignment in manufacturing a semiconductor element,
Removing a part of the second semiconductor layer in a semiconductor laminate having a first semiconductor layer containing Al in the composition and a second semiconductor layer grown on the first semiconductor layer; An alignment mark forming step for forming an alignment mark that includes a plurality of recesses arranged in a predetermined direction and having the first semiconductor layer as a bottom surface;
A growth step of growing a third semiconductor layer on the second semiconductor layer and on the plurality of recesses;
An alignment mark digging step for exposing the plurality of recesses by removing the third semiconductor layer formed on the alignment mark,
In the alignment mark formation step, the width of each recess in the predetermined direction is formed to be larger than 1 μm and smaller than 6 μm,
A method for forming an alignment mark, wherein a ratio (S / D) between a depth D of each recess and an interval S between the recesses adjacent to each other in the predetermined direction is 3 or more.   2. The alignment mark according to claim 1, wherein the third semiconductor layer includes at least one element of Al, Ga, and In and at least one element of P and As in the composition. Forming method. A part of the second semiconductor layer is removed from a semiconductor stack having a first semiconductor layer containing Al in the composition and a second semiconductor layer grown on the first semiconductor layer on a substrate. A first step of forming an alignment mark including a plurality of recesses arranged in a predetermined direction and having the first semiconductor layer as a bottom surface;
A second step of forming a diffraction grating having periodic irregularities in the second semiconductor layer on a predetermined region of the substrate using the alignment mark;
A third step of growing a third semiconductor layer so as to cover the plurality of recesses and the diffraction grating;
A fourth step of exposing the plurality of recesses by removing the third semiconductor layer formed on the alignment mark;
A fifth step of forming an etching mask including a pattern extending in a predetermined optical waveguide direction on the third semiconductor layer;
A sixth step of etching at least the third semiconductor layer using the etching mask,
In the first step, the width of each recess in the predetermined direction is formed to be larger than 1 μm and smaller than 6 μm,
A method of manufacturing an optical semiconductor element, wherein a ratio (S / D) between a depth D of each recess and an interval S between the recesses adjacent to each other in the predetermined direction is 3 or more.