JP2012248651A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

Distortion is introduced into a channel region to improve characteristics of a semiconductor device, and a gate wiring covered with a stress application film is prevented from being disconnected.
A semiconductor device includes a first active region 104 formed in a first element formation region 101, a second active region 105 formed in a second element formation region 102, and a first active region. A gate wiring 103 extending from the region 104 to the second active region 105; a first channel region 80 formed in a region immediately below the gate wiring 103 in the first active region 104; And a second channel region 90 formed in a region immediately below the gate wiring in the active region. The gate wiring 103 is formed on the first active region 104 and has a first region 164 having a first stress that is a tensile stress or a compressive stress, and a first stress that is more relaxed than the first region 164. And a second region 162 having.
[Selection] Figure 7

Description

  The technology described in this specification relates to a semiconductor device including a MIS transistor in which a hole or an electron is used as a carrier and stress is applied to a channel region, and a manufacturing method thereof.

  In recent years, strained silicon technology for realizing a semiconductor device that operates at high speed and with low power consumption by introducing strain into the channel region of the MIS transistor and improving carrier mobility has been studied.

  Various methods have been proposed as strained silicon technology. For example, the technology that introduces strain into the channel region indirectly by the stress application film formed on the upper surface of the semiconductor substrate after MISFET formation is relatively difficult in terms of process. It is widely used due to its low degree. As the strain introduction technology, Dual Stress Liner (DSL) technology that uses two types of stress application films, tensile stress film and compression stress film, and high-temperature heat treatment with stress applied by stress application film, the stress is applied to the substrate. Stress Memorization Technique (SMT) and the like to be memorized are introduced (Patent Documents 1 and 2, Non-Patent Documents 1 to 4).

  With respect to the strained silicon technology using this stress application film, for example, miniaturization is strongly demanded, and a static random access memory (SRAM) in which N-channel transistors and P-channel transistors are regularly arranged adjacent to each other. An application example is disclosed (Patent Document 3). Hereinafter, the conventional technique disclosed in Patent Document 3 will be described with reference to the drawings.

  FIG. 16A is a plan view showing a pattern of the SRAM bit cell 1300 according to the first conventional example. As shown in the figure, it has two pass gate transistors 1302 (N-channel FET), two pull-down transistors 1304 (N-channel FET), and two pull-up transistors 1306 (P-channel FET). An SRAM bit cell 1300 is formed on a semiconductor substrate.

  Here, the silicon nitride film 1308 is first deposited on the entire surface of the semiconductor substrate, and then the lithography and etching processes are performed, so that the silicon nitride film 1308 remains only on the pull-down transistor 1304. Patterned. The silicon nitride film 1308 has a tensile stress, and is then subjected to a high-temperature annealing treatment, whereby the region covered with the silicon nitride film 1308 is recrystallized and tensile strain is introduced into the channel region of the pull-down transistor 1304. Is done. Thereafter, the silicon nitride film 1308 is removed, but the tensile strain introduced into the channel region of the pull-down transistor 1304 is stored as it is. In the present specification, “the film has a tensile stress” means that the film is subjected to a tensile stress or a state in which a state subjected to a tensile stress is stored, “The film has a compressive stress” means that the film is subjected to a compressive stress or a state in which a state subjected to the compressive stress is stored.

  As described above, in the first conventional example shown in FIG. 16A, SMT is applied to an N-channel transistor in order to enhance uniaxial tensile stress.

  Further, FIG. 16B is a plan view showing a pattern of the SRAM bit cell 1600 according to the second conventional example. In the second conventional example, a Dual Stress Liner (DSL) technique using two types of stress application films, a tensile stress film and a compressive stress film, is used.

  An SRAM bit cell 1600 according to the second conventional example is formed on a semiconductor substrate, and includes two pass gate transistors 1602 (N-channel FET), two pull-down transistors 1604 (N-channel FET), and two A pull-up transistor 1606 (P-channel FET) is included. A stress liner 1608 for applying compressive stress is provided in a region where the pull-up transistor 1606 is formed and a region where the pass gate transistor 1602 is formed. A stress liner 1610 that applies tensile stress is provided in a region where the pull-down transistor 1604 is formed. It is well known that compressive stress decreases electron mobility and increases hole mobility. Therefore, by properly using the stress liner 1608 that applies compressive stress and the stress liner 1610 that applies tensile stress, a high PD / PG beta ratio can be obtained, and the stability of the SRAM can be increased.

  As described above, when the strained silicon technique using the stress application film is used, carrier mobility can be improved without changing the size of the transistor. Further, even with a small-sized transistor, carrier mobility equivalent to that of a larger-sized transistor can be obtained, which has a great effect on miniaturization of a semiconductor device such as an SRAM.

JP 2007-134718 A US Pat. No. 6,573,172 JP 2009-177151 A

"Stress memorization in High-Performance FDSOI devices with Ultra Thin Silicon and 25nm Gate lenghts" D.V.Singh, et al., (20.5), IEDM 2005 "Dual Stress Liner Enhancement in Hybrid Orientation Technology" C.D.Sheraw, et al., (2-1) VLSI 2005 E. Leobandung et al. “High Performance 65nm SOI Technology with Dual Stress Liner and low capacitance SRAM cell” 2005 Symposium on VLSI Technology Digest of Technical Papers 8A-1 2005 C. Ortolland et al., “Stress Memorization Technique (SMT) Optimization for 45nm CMOS”, VLSI Tech. Digest, 2006, p.96-97.

  However, when a method such as DSL technology or SMT that introduces strain into the channel region through the stress application film is used, stress is also generated inside the gate wiring covered with the stress application film. The stress inside the gate wiring is not necessarily constant, especially for gate wirings that are placed across the transistor formation regions of different conductivity types, there are multiple stress regions with different sizes and positive / negative directions inside. Will be. For this reason, the stress locally changes suddenly at the boundary of each stress region, and there is a problem that the gate wiring is cracked at the boundary portion of the stress region or the gate wiring itself is cut in the worst case.

  For example, in the first conventional example shown in FIG. 16A, in the gate wiring common to the pull-down transistor 1304 and the pull-up transistor 1306, in the region covered with the silicon nitride film 1308, which is a stress application film, Since tensile stress also acts on the wiring and no stress is generated in the region not covered with the silicon nitride film 1308, the stress in the gate wiring is locally changed from the tensile stress to the stress-free state at the boundary portion. It will change suddenly.

  Further, in the second conventional example shown in FIG. 16B, in the gate wiring common to the pull-down transistor 1604 and the pull-up transistor 1606, the region covered by the stress liner 1610 that applies tensile stress is also within the gate wiring. Tensile stress is generated, and compressive stress is generated in the gate wiring covered with the stress liner 1608 that applies compressive stress. Therefore, inside the gate wiring located below the boundary between the stress liner 1610 and the stress liner 1608, the internal stress suddenly changes locally from tensile stress to compressive stress.

  Normally, a MOSFET uses a polysilicon film as a gate wiring. However, when the stress locally changes suddenly inside the polysilicon film as described above, a crack occurs at that location, and in the worst case, the gate wiring is disconnected. End up. Furthermore, in recent years, some or all of the polysilicon gate wiring may be silicided for the purpose of reducing the electrical resistance of the polysilicon gate wiring. However, since silicide has low resistance to mechanical stress, only polysilicon is used. Compared with the case where the gate wiring is configured, the possibility that the silicide is cracked or disconnected at a location where the stress is suddenly changed is further increased.

  In view of the above, an object of the present invention is to improve the characteristics of a semiconductor device by introducing strain into a channel region and to prevent disconnection of a gate wiring covered with a stress application film.

  In order to achieve the above object, a semiconductor device according to an example of the present invention is formed on a semiconductor substrate having a first element formation region and a second element formation region, and on the first element formation region. A first active region, a second active region formed on the second element formation region and adjacent to the first active region, and at least the second active region from above the first active region. A gate line extending over the active region; a first channel region of a first conductivity type formed in a region of the first active region located immediately below the gate line; and the second active region And a second channel region of a second conductivity type formed in a region located immediately below the gate wiring in the region. The gate wiring is formed on at least the first active region, has a first region having a first stress which is a tensile stress or a compressive stress, and the second active region more than the first region. A first region that is close to the region, is adjacent to the first region, and has a second region having the first stress that is more relaxed than the first region. Has a strain corresponding to the first stress.

  According to this configuration, since the first stress is relieved in the second region of the gate wiring, it is possible to reduce the stress change that occurs at the boundary of each region of the gate wiring. For this reason, disconnection of the gate wiring can be effectively prevented, and the reliability can be improved. In addition, since the stress in the second region different from the first region is relaxed, the first channel is distorted and does not affect the effect of improving the element characteristics. .

  In addition, when the DLS technique is used and the SMT technique is used, the above-described effects can be obtained.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a first active region is formed in a first element formation region of a semiconductor substrate having a first element formation region and a second element formation region. And (a) forming a second active region adjacent to the first active region in the second element formation region, and at least the second active region from above the first active region. A first region extending over and located on the first active region; a second region closer to the second active region than the first region and adjacent to the first region; A step (b) of forming a gate wiring having a region on the first element formation region; and the first region and the second region on the first element formation region including the first active region. A first stress which is a tensile stress or a compressive stress is applied so as to cover the region of By forming the first stress application film, distortion is generated in the first channel region of the first conductivity type located immediately below the gate wiring in the first active region, and the first region and A step (c) of generating the first stress in the second region, and a portion of the first stress application film formed on the second region is processed to provide the second stress. And (d) reducing the first stress applied to the region.

  According to this method, since the stress applied from the first stress application film is relieved in the second region of the gate wiring, the occurrence of disconnection at the location can be effectively suppressed.

  According to another embodiment of the present invention, there is provided a method for manufacturing a semiconductor device, wherein a first active region is formed in the first element formation region of a semiconductor substrate having a first element formation region and a second element formation region. And (a) forming a second active region adjacent to the first active region in the second element formation region, and at least the second active region from above the first active region. A first region extending over the active region, located on the first active region, and closer to the second active region than the first region and adjacent to the first region; A step (b) of forming a silicon film having two regions on the first element formation region, and the first region and the first region on the first element formation region including the first active region. A first stress that is a tensile stress or a compressive stress is applied so as to cover the second region. By forming the stress applying film to be distorted, the first channel region of the first conductivity type located immediately below the silicon film in the first active region is distorted, and the first region and the first region The step (c) of generating the first stress in the region 2 and the portion of the stress application film formed on the second region are processed and applied to the second region. After the step (d) of reducing the first stress and the step (d), the semiconductor substrate is thermally annealed to store the first stress in the first region and to store the first stress. A step (e) of storing a strain generated according to the stress of 1 in the first channel region, and a step (f) of removing the stress application film.

  As described above, even when using the SMT technique in which the stress of the stress applying film is applied to the channel region and the strain generated at that time is stored by thermal annealing, the gate wiring (silicon film) generated at the end of the stress applying film is used. Since the internal stress can be reduced, the risk of disconnection of the gate wiring can be reduced.

  According to the semiconductor device and the manufacturing method thereof according to an example of the present invention, the stress generated in the gate wiring can be reduced while introducing strain in the channel region. Can be prevented.

FIG. 1A is a plan view showing the semiconductor device according to the first embodiment before the stress application film is formed, and FIG. 1B is a semiconductor taken along line Ib-Ib in FIG. It is sectional drawing of an apparatus. 1C is a cross-sectional view of the semiconductor device taken along line Ic-Ic in FIG. 1A, and FIG. 1D is a cross-sectional view of the semiconductor device taken along line Id-Id in FIG. is there. 2A to 2C are cross-sectional views illustrating steps after forming the stress applying film in the method for manufacturing the semiconductor device according to the first embodiment. 3A to 3C are cross-sectional views illustrating a process after the stress application film is formed in the method for manufacturing the semiconductor device according to the first embodiment. 4A and 4B are cross-sectional views illustrating a process after the stress application film is formed in the method for manufacturing the semiconductor device according to the first embodiment. FIGS. 5A and 5B are cross-sectional views showing the steps after forming the stress applying film in the method for manufacturing the semiconductor device according to the first embodiment. 6A and 6B are cross-sectional views showing a semiconductor device according to a reference example. FIG. 7 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 8 is a plan view showing the semiconductor device according to the first embodiment. FIG. 9 is a diagram illustrating an example of the relationship between the thickness of the stress application film and the stress generated in the gate wiring. FIGS. 10A to 10C are cross-sectional views illustrating steps after the stress application film is formed in the method for manufacturing a semiconductor device according to the second embodiment. FIGS. 11A to 11C are cross-sectional views illustrating steps after the stress application film is formed in the method for manufacturing a semiconductor device according to the second embodiment. 12A to 12C are cross-sectional views illustrating steps after the stress application film is formed in the method for manufacturing a semiconductor device according to the third embodiment. FIGS. 13A and 13B are cross-sectional views showing the steps after forming the stress applying film in the method of manufacturing a semiconductor device according to the third embodiment, and FIG. It is a top view which shows the semiconductor device in the process shown to (b). 14A to 14C are cross-sectional views illustrating a process after the stress application film is formed in the method of manufacturing a semiconductor device according to the fourth embodiment. FIG. 15 is a cross-sectional view illustrating a process after the stress applying film is formed in the method for manufacturing a semiconductor device according to the fourth embodiment. FIG. 16A is a plan view showing a pattern of the SRAM bit cell 1300 according to the first conventional example, and FIG. 16B is a plan view showing a pattern of the SRAM bit cell 1600 according to the second conventional example. is there.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A is a plan view showing the semiconductor device according to the first embodiment before the stress application film is formed. FIG. 1B is a cross-sectional view of the semiconductor device taken along line Ib-Ib in FIG. 1C is a cross-sectional view of the semiconductor device taken along line Ic-Ic in FIG. 1A, and FIG. 1D is a cross-sectional view of the semiconductor device taken along line Id-Id in FIG. is there. 2A to 2C, FIGS. 3A to 4C, FIGS. 4A and 4B, and FIGS. 5A and 5B are semiconductors according to this embodiment. It is sectional drawing which shows the process after forming the stress application film | membrane in the manufacturing method of an apparatus.

  In the following, an example in which a stress applying film is applied to an N-channel MISFET and a P-channel MISFET of a semiconductor device has been described. However, the configuration of the present embodiment is not limited to a MISFET, but a semiconductor element having a gate wiring Applicable to. Hereinafter, a method for manufacturing the semiconductor device of this embodiment will be described.

  First, as shown in FIGS. 1A to 1D, a P-type impurity is introduced into an N-channel MISFET formation region (first element formation region) 101 of a semiconductor substrate 122 by ion implantation or the like. 121 is formed, and an N-type impurity is introduced into a P-channel MISFET formation region (second element formation region) 102 to form an N-well 120. Here, in the semiconductor substrate 122, a region for forming an N-channel MISFET is an N-channel MISFET formation region 101, and a region for forming a P-channel MISFET is a P-channel MISFET formation region 102. The N channel MISFET formation region 101 and the P channel MISFET formation region 102 are adjacent to each other.

  Next, an element isolation region 106 made of silicon oxide or the like is formed on the upper portion of the semiconductor substrate 122 made of silicon or the like, having a shallow trench isolation (STI) structure or the like. As a result, the P-type active region 104 that is a portion surrounded by the element isolation region 106 in the P well 121 and the N-type active region that is a portion surrounded by the element isolation region 106 in the N well 120. 105 is formed.

  Next, gate insulating films 113a and 113b made of silicon oxide or the like are respectively formed on the active regions 104 and 105 by a known method, and the element isolation region 106 is straddled from the gate insulating film 113a (active region 104). Then, a polysilicon film (silicon film / conductive film) 112 having a thickness of, for example, 100 nm is formed on the gate insulating film 113b (active region 105). The width (gate length) of the polysilicon film 112 is, for example, 50 nm.

  Next, in order to prevent depletion of the gate electrode during the operation of the MISFET, an N-type impurity is implanted into a portion of the polysilicon film 112 formed on the N-channel type MISFET formation region 101 to form a P-channel type. P-type impurities are implanted into the portion formed on the MISFET formation region 102. Here, a boundary between the region into which the N-type impurity is implanted and the region into which the P-type impurity is implanted in the gate wiring 103 is referred to as a doping boundary 109. The doping boundary 109 coincides with the boundary between the N channel MISFET formation region 101 and the P channel MISFET formation region 102 in plan view.

  Next, by selectively implanting N-type impurities into the active region 104 using the polysilicon film 112 as a mask, N-type extension regions 135 are formed in regions of the active region 104 located on both sides of the polysilicon film 112. Form. In addition, by selectively implanting P-type impurities into the active region 105 using the polysilicon film 112 as a mask, P-type extension regions 145 are formed in regions of the active region 105 located on both sides of the polysilicon film 112. To do.

  Subsequently, sidewall spacers made of silicon oxide are formed on the side surfaces of the polysilicon film 112. Of the sidewall spacers, a portion formed on the N channel MISFET formation region 101 is referred to as a sidewall spacer 131a, and a portion formed on the P channel MISFET formation region 102 is referred to as a sidewall spacer 131b.

  Next, N-type impurities are selectively ion-implanted into the active region 104 using the polysilicon film 112 and the sidewall spacer 131a as a mask, so that both sides of the polysilicon film 112 and the sidewall spacer 131a in the active region 104 can be obtained. Thus, an N-type source / drain region 132 is formed in a region located outside the N-type extension region 135. Further, by selectively implanting P-type impurities into the active region 105 using the polysilicon film 112 and the sidewall spacer 131b as a mask, both sides of the polysilicon film 112 and the sidewall spacer 131b in the active region 105 can be obtained. Thus, a P-type source / drain region 142 is formed in a region located outside the P-type extension region 145. Also in this step, the doping boundary 109 serves as an impurity introduction boundary.

  Next, the upper surface portion of the N-type source / drain region 132, the upper surface portion of the P-type source / drain region 142, and the upper surface portion of the polysilicon film 112 are selectively silicided to form silicide films 134, 144, and 111. . Here, the gate wiring 103 is a combination of the polysilicon film 112 and the silicide film 111 formed thereon.

  Through the above steps, an N channel MISFET is formed on the active region 104 and a P channel MISFET is formed on the active region 105. Note that a region located between the two N-type source / drain regions 132 in the active region 104 and immediately below the gate wiring 103 is a channel region 80 of the N-channel MISFET. Of these, the region located between the two P-type source / drain regions 142 and immediately below the gate wiring 103 is the channel region 90 of the P-channel MISFET.

  In the above-described silicide formation step, the upper surface portion of the polysilicon film 112 is partially silicided. However, the entire polysilicon film 112 other than the upper surface portion of the polysilicon film 112 may be silicided.

  Next, a process for forming the stress application film will be described.

  First, as shown in FIG. 2A, a tensile stress film 151 made of, for example, silicon nitride is formed on the entire surface of the semiconductor substrate 122 with a thickness of about 50 nm. As a method of forming the tensile stress film 151, for example, a method of forming a silicon nitride film by a thermal chemical vapor deposition (thermal CVD method) is used. As another method, there is a method of forming a silicon nitride film by a Low Pressure CVD (LPCVD) method, and further annealing is performed after a silicon oxynitride film (SiON film) is formed by a Plasma Enhanced CVD (PECVD) method. There are also a method and a method of forming a silicon oxide film to which a tensile stress is applied as a tensile stress film. Note that the tensile stress film 151 formed in this step is a stress application film, and is a film that applies a tensile stress to a member in contact therewith.

  Next, a photoresist 152 is formed so as to cover a portion of the tensile stress film 151 formed on the N channel MISFET formation region 101. Here, the photoresist 152 is formed up to a region on the P-channel MISFET formation region 102 side by a predetermined distance (for example, about 0.1 μm) as a planar distance from the doping boundary 109 in the gate wiring 103. The position of the doping boundary 109 overlaps with the boundary position between the N channel MISFET formation region 101 and the P channel MISFET formation region 102 in plan view.

  Next, as shown in FIG. 2B, the tensile stress film 151 is patterned by using a known selective etching technique using the photoresist 152 as a mask, and the tensile stress film 151a covering the N-channel MISFET formation region 101 is formed. Form.

  Next, as shown in FIG. 2C, the surface portion of the photoresist 152 is ashed to retract the photoresist 152, thereby forming a photoresist 152 a having a smaller size than the photoresist 152. With this step, the end position of the photoresist 152a in the gate width direction (the direction parallel to the extending direction of the gate wiring 103) enters the N channel MISFET formation region 101 side from the doping boundary 109. For this reason, the peripheral portion of the tensile stress film 151a covered with the photoresist 152 is exposed from the photoresist 152a. Note that the retraction amount (reduction width) of the photoresist 152 in the gate width direction can be easily adjusted by changing the ashing conditions.

  Next, as shown in FIG. 3A, the tensile stress film 151a partially exposed in the process shown in FIG. 2C is formed by using a known selective etching technique using the photoresist 152a as a mask. Only part of the film is etched in the thickness direction to reduce the film thickness of the exposed part. Here, in FIG. 3A, the thinned portion of the tensile stress film 151 is shown as a tensile stress film 151b, and the remaining portion covered with the photoresist 152a is shown as a tensile stress film 151a.

  As described above, since the tensile stress film 151b is formed by the self-alignment technique by the retraction (reduction) of the photoresist 152, the retraction amount (reduction width) can be accurately controlled, and the number of additional steps for processing is further increased. Therefore, a stress relaxation region described later can be formed at a low cost.

  A tensile stress is applied in the vicinity of the upper surface of the active region 104 by the tensile stress film 151a. In accordance with the tensile stress, tensile strain is generated in the channel region 80 under the gate wiring 103, and the mobility of electrons in the channel region of the N-channel type MISFET is improved by the tensile strain. Further, tensile stress is also applied to portions of the gate wiring 103 covered with the tensile stress films 151a and 151b.

  Here, FIG. 9 is a diagram illustrating an example of the relationship between the thickness of the stress application film and the stress generated in the gate wiring. As shown in the figure, generally, when the stress application film exerts stress on the lower structure, the stress generated in the lower structure increases as the thickness of the stress application film increases. It tends to saturate as the thickness increases. In the manufacturing method according to the present embodiment, the stress in the gate wiring 103 covered with the tensile stress film 151b is relaxed to about half of the stress in the gate wiring 103 covered with the tensile stress film 151a. The film 151b is processed to have a thickness of 30 nm. In order to more effectively relieve stress, it is preferable that the resist receding amount from the photoresist 152 to the photoresist 152a is, for example, about 1 to 2 times the width (ie, gate length) 50 nm of the gate wiring 103.

  Next, as shown in FIG. 3B, after removing the photoresist 152 a, an etching stop film 153 made of, for example, silicon oxide is formed on the entire surface of the semiconductor substrate 122.

  Subsequently, as shown in FIG. 3C, a compressive stress film 155 is formed on the entire surface of the semiconductor substrate 122 with a thickness of 50 nm, for example, and then a photoresist 156 is formed so as to cover the P-channel type MISFET formation region 102. To do. The photoresist 156 is formed up to a region entering the N channel MISFET formation region 101 side by a predetermined distance (for example, about 0.1 μm) from the doping boundary 109. The compressive stress film 155 formed in this step is a stress applying film, and is a film that applies compressive stress to a member in contact therewith.

  As the compressive stress film 155, for example, a silicon nitride film formed by PECVD, a silicon nitride film formed at a low temperature of about 200 to 400 ° C., or a silicon oxide film having a compressive stress may be used. In this embodiment, an example using a silicon nitride film will be described.

  Next, as shown in FIG. 4A, an N channel MISFET is formed by using a known selective etching technique having a sufficient selection ratio with respect to the etching stop film 153 using the photoresist 156 as a mask. The compressive stress film 155 on the region 101 is selectively removed, and a compressive stress film 155a is formed on the P-channel type MISFET formation region 102. At this time, it is assumed that a part of the compressive stress film 155a rides on the tensile stress film 151b.

  Next, as shown in FIG. 4B, the photoresist 156 is retracted by ashing the surface portion of the photoresist 156, and a photoresist 156a having a size smaller than that of the photoresist 156 is formed. By this step, the end position of the photoresist 156a in the gate width direction enters the P channel MISFET formation region 102 side from the doping boundary 109. For this reason, the peripheral portion of the compressive stress film 155a covered with the photoresist 156 is exposed from the photoresist 156a. The receding amount (reduction width) of the photoresist 156 in the gate width direction is preferably about 1 to 3 times the gate wiring width.

  Next, as shown in FIG. 5A, using the photoresist 156a as a mask, the compression stress film 155a partially exposed in the step shown in FIG. 4B is formed using a known selective etching technique. Only part of the film is etched in the thickness direction to reduce the film thickness of the exposed part. Here, in FIG. 5A, the thinned portion of the compressive stress film 155 is shown as a compressive stress film 155b, and the remaining portion covered with the photoresist 156a is shown as a compressive stress film 155a. The thickness of the compressive stress film 155b is, for example, 30 nm, and the stress inside the gate wiring 103 covered with the compressive stress film 155b is adjusted to be about half of the stress inside the gate wiring 103 covered with the compressive stress film 155a.

  Thus, compressive stress is applied to the vicinity of the upper surface of the active region 105 by the compressive stress film 155a. The compressive stress causes compressive strain in the channel region 90, and the compressive strain improves the hole mobility in the channel region 90 of the P-channel type MISFET. Further, compressive stress is also applied to portions of the gate wiring 103 covered with the compressive stress films 155a and 155b.

  Next, as shown in FIG. 5B, the photoresist 156a is removed, a passivation film 250 made of silicon oxide or silicon oxynitride is formed on the entire surface of the semiconductor substrate 122, and then a mask 260 is used. The passivation film 250 is partially etched to form contact holes 252 that reach the silicide film 111 of the gate wiring 103 and the silicide film on the P-type source / drain region and the silicide film on the N-type source / drain region. The position where the contact hole 252 is formed is not limited to the position where the tensile stress film 151b and the compressive stress film 155b overlap. Next, after removing the mask 260, a contact plug for filling the contact hole 252 or a wiring is formed by a known method. Through the above steps, the semiconductor device of this embodiment can be manufactured.

  In the manufacturing method of this embodiment, as shown in FIG. 5A, the thinned tensile stress film 151b and the compressive stress film 155b are formed so as to overlap each other. By adopting such a shape, in addition to the effect of relieving the stress applied under the region where the two stress applying films overlap, there are the following two effects. FIGS. 6A and 6B are cross-sectional views showing a semiconductor device according to a reference example, and are diagrams for explaining the effect of the above shape.

  First, the first effect is reduction of processing damage to the silicide film 111 on the gate wiring 103.

  If the tensile stress film 1151 and the compressive stress film 1155 do not overlap with each other and are spaced from each other as in the semiconductor device according to the reference example shown in FIG. 6A, the tensile stress film 1151 is provided. And the compressive stress film 1155 on the polysilicon film 112 overlap the etching damage at the time of pattern processing of the tensile stress film 151 and the etching damage at the time of pattern processing of the compressive stress film 155. Receive. Further, in this reference example, since the silicide film 111 located between the tensile stress film 1151 and the compressive stress film 1155 is exposed until the interlayer insulating film or the passivation film is formed, a cleaning process is performed thereafter. Will be exposed to the cleaning solution. For this reason, the silicide film 111 is subjected to erosion and the like, and a problem that the erosion part easily breaks occurs. However, the occurrence of the above-described problem can be avoided by adopting a structure in which the tensile stress film 151b and the compressive stress film 155b overlap as in the semiconductor device of the present embodiment.

  The second effect is that by forming the thinned tensile stress film 151b and the compressive stress film 155b so as to overlap each other, both stresses are applied in the region where the tensile stress film 151 and the compressive stress film 155b overlap each other. The total thickness of the stress application film can be reduced as compared with the case where the application films are stacked without being thinned. That is, in the semiconductor device of the present embodiment shown in FIG. 5A, the total thickness of the stress application films where the tensile stress film 151b and the compressive stress film 155b overlap is the reference example shown in FIG. In the semiconductor device according to the above, the total thickness of the stress application films in the portion where the tensile stress film 1151 and the compressive stress film 1155 overlap is, for example, about half.

  In addition, after the stress application film is formed, in the formation process of the contact hole 252 shown in FIG. 5B, only the passivation film 250 is first etched using a known lithography technique and dry etching technique. The dry etching used at this time is performed under a condition having a sufficient selection ratio with respect to the tensile stress films 151a and 151b and the compressive stress films 155a and 155b under the passivation film 250. Therefore, the tensile stress films 151a and 151b are used. The compressive stress films 155a and 155b can be used as etching stoppers. Therefore, by setting appropriate over-etching conditions, even if the thickness of the passivation film 250 on the semiconductor substrate 122 varies from place to place, etching can be performed without causing an etching residue of the passivation film 250. Next, the underlying tensile stress films 151 a and 151 b and the compressive stress films 155 a and 155 b are etched to open the contact hole 252 to the upper surface of the semiconductor substrate 122 or the upper surface of the gate wiring 103.

  However, as in the reference example shown in FIG. 6A, if there is a portion of the semiconductor substrate 122 and the gate wiring 103 that is not covered with the tensile stress film 1151 or the compressive stress film 1155 when the passivation film is etched, Etching cannot be stopped at that portion during etching. Therefore, when overetching, the semiconductor substrate 122 and the gate wiring 103 are etched. Therefore, in the semiconductor device according to the reference example shown in FIG. 6A, a contact hole cannot be arranged in a portion not covered with the tensile stress film 1151 or the compressive stress film 1155, and the circuit layout is restricted. . As a result, the chip size increases and the cost of the semiconductor device increases.

  On the other hand, in the reference example shown in FIG. 6B, in the semiconductor device to which the DSL technology is applied, the tensile stress film 1151 and the compressive stress film 1155 used as an etching stopper are formed so as to overlap each other at the end portions. This prevents damage to the gate wiring and the like during overetching. However, in the portion where the tensile stress film 1151 and the compressive stress film 1155 overlap with each other, the thickness of the etching stopper becomes thicker than the other portions. Therefore, when a contact hole is arranged in this place, the passivation film 1250 using the mask 1200 is used. When the tensile stress film 1151 and the compressive stress film 1155 are etched after the etching is completed, the etching becomes insufficient. Therefore, even in the semiconductor device according to the reference example shown in FIG. 6B, a good contact hole cannot be formed in the region where the tensile stress film 1151 and the compressive stress film 1155 overlap with each other, and the circuit layout is restricted.

  On the other hand, in the semiconductor device according to the present embodiment, as shown in FIG. 5B, the thinned tensile stress film 151b and the compressive stress film 155b are formed so as to overlap each other. The thickness of the functioning film can be made substantially the same as that of the single layer of the tensile stress film 151a or the compressive stress film 155a that is not thinned. Therefore, even if the contact hole 252 is disposed in the region where the tensile stress film 151b and the compressive stress film 155b are overlapped, insufficient etching may occur when the tensile stress film 151b and the compressive stress film 155b functioning as an etching stopper are etched. Therefore, a good contact hole 252 can be formed.

  Due to the above two effects, as in the semiconductor device according to the present embodiment, the peripheral portion of the tensile stress film and the peripheral portion of the compressive stress film are overlapped in a thinned state, thereby forming a silicide film on the gate wiring. Damage can be avoided, and the contact hole can also be arranged in the overlap region of the tensile stress film and the compressive stress film.

  FIG. 7 is a cross-sectional view showing the semiconductor device of this embodiment obtained through the above steps, and FIG. 8 is a plan view showing the semiconductor device of this embodiment. 7 and 8 show a state in which the photoresist 156a is removed from the semiconductor device shown in FIG. 5B.

  Hereinafter, how the stress relaxation region is formed in the semiconductor device according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 7, in the semiconductor device of this embodiment, the thinned tensile stress film 151b is thinned near the boundary between the N-channel MISFET formation region 101 and the P-channel MISFET formation region 102. There is a region 161 where the compressive stress film 155b overlaps. On both sides of the region 161 in the gate width direction, the region 162 where the semiconductor substrate 122 and the gate wiring 103 are covered only with the tensile stress film 151b, and the semiconductor substrate 122 and the gate wiring 103 are covered only with the compressive stress film 155b. Region 163 is formed.

  First, in the region 162, only the tensile stress film 151b having a small thickness covers the gate wiring 103, so that the stress generated inside the gate wiring 103 is gated in the region 164 covered by the tensile stress film 151a. The stress is in the same direction as the stress generated in the wiring 103 and is about half the magnitude. That is, the tensile stress that the region 162 of the gate wiring 103 has is about half of the tensile stress that the region 164 has.

  Next, in the region 161, since the gate wiring 103 is covered with both the tensile stress film 151b and the compressive stress film 155b, the stress is almost canceled and the stress inside the gate wiring 103 becomes almost zero.

  In the region 163, since the gate wiring 103 is covered only by the compressive stress film 155b, the stress generated inside the gate wiring 103 is about half that of the region 165 covered by the compressive stress film 155a. In other words, the compressive stress that the region 163 has is about half of the compressive stress that the region 165 has.

  As described above, in the gate wiring 103, when the tensile stress direction is defined as +, the stress ratio in the regions 164, 162, 161, 163, 165 is approximately 1: 0.5: 0: -0.5:-. It can be seen that the stress is relaxed in three stages of regions 162, 161, and 163. That is, the region 160 where the region 162 where the stress is alleviated, the region 161, and the region 163 are combined can be regarded as the stress relaxation region.

  Further, the doping boundary 109 in the gate wiring 103 is not necessarily in the region 160 which is a stress relaxation region, but it is more preferable if it is in the region 160. Further, it is particularly preferable that the doping boundary 109 in the gate wiring 103 is in the region 161 where the stress in the gate wiring 103 is almost zero. This is because the film quality of the polysilicon film 112 and the film quality of the silicide film 111 formed on the polysilicon film 112 change discontinuously at the doping boundary 109, and there is a risk that the gate wiring 103 is disconnected at this portion. Is the highest. Therefore, by placing the doping boundary 109 in the region 161 with the lowest stress, the disconnection of the gate wiring 103 can be most effectively prevented.

  As shown in FIG. 6B, when the ends are overlapped without partially reducing the tensile stress film 1151 and the compressive stress film 1155, the stress applied to the gate wiring 103 in the overlap region. And the stress in the gate wiring 103 can be made substantially zero. However, as described above, if the stress application films are overlapped without being thinned, contact holes cannot be formed satisfactorily in the overlapped portion. Further, in this case, since the stress ratio in the gate wiring 103 can almost cancel the stress only in the overlapping region, the region where only the tensile stress film 1151 is provided, the region where the stress application film is overlapped, and the compressive stress film 1155. The stress ratio in the gate wiring 103 is 1: 0: −1 in the region where only the gate electrode is provided. Therefore, the stress change in each region is not sufficiently small.

  Further, as in the reference example shown in FIG. 6A, even if the tensile stress film 1151 and the compressive stress film 1155 are arranged with a space therebetween, they are positioned between the tensile stress film 1151 and the compressive stress film 1155. Since the stress in the gate wiring 103 under the region can be substantially zero, there is an effect as stress relaxation. However, if the tensile stress film 1151 and the compressive stress film 1155 are arranged with a space therebetween as described above, the stress application film is formed when the contact hole is formed under the region located between the tensile stress film 1151 and the compressive stress film 1155. Etching cannot be stopped by the above process, and the silicide film 111 on the polysilicon film 112 may be exposed in a subsequent process, and thus may be damaged. Further, in this case, since the stress can only be reduced to 0 in the void portion, in the region where only the tensile stress film 1151 is provided, the region where the stress application film is overlapped, and the region where only the compressive stress film 1155 is provided, The stress ratio inside the gate wiring 103 is 1: 0: -1. Therefore, the stress change cannot be sufficiently reduced at the boundary between the regions.

  As described above, according to the method according to the present embodiment, the two types of stress application films are partially thinned by the self-alignment technique, thereby reducing the stress generated in the gate wiring 103 in three stages. Since the region can be formed, disconnection of the gate wiring 103 can be effectively prevented, and a semiconductor device with high yield and high reliability can be provided at low cost.

  In the region 160 which is a stress relaxation region, an element isolation region 106 is provided and is sufficiently separated from both the channel region 80 of the N-channel MISFET and the channel region 90 of the P-channel MISFET. The effect of improving the carrier mobility in the N-channel type MISFET by the stress film 151a and the effect of improving the carrier mobility in the P-channel type MISFET by the compressive stress film 155a are the same as when the stress relaxation region is not formed.

  In this embodiment, the tensile stress film 151 is formed in front of the compressive stress film 155, but the same effect can be obtained even if this order is reversed.

  The semiconductor device of this embodiment manufactured by the above method includes a semiconductor substrate 122 in which an N-channel MISFET formation region 101 and a P-channel MISFET formation region 102 are formed adjacent to each other, and an upper portion of the semiconductor substrate 122. The formed element isolation region 106, a P well 121 formed in the N channel MISFET formation region 101 of the semiconductor substrate 122, and an N well 120 formed in the P channel MISFET formation region 102 of the semiconductor substrate 122 The P-type active region 104 formed in the region surrounded by the element isolation region 106 above the N well 120 and the element isolation region above the semiconductor substrate 122 (P-channel MISFET formation region 102). 106 and adjacent to the active region 104 with the element isolation region 106 interposed therebetween. An N-type active region 105 formed in the region to be formed, a gate insulating film 113a formed on the active region 104, a gate insulating film 113b formed on the active region 105, and an element from at least the gate insulating film 113a A gate wiring 103 extending over the isolation region 106 to the gate insulating film 113 b and a sidewall spacer formed on the side surface of the gate wiring 103 are provided. N-type source / drain regions (not shown) are formed in regions on both sides of the gate wiring 103 in the active region 104, and in regions on the both sides of the gate wiring 103 in the active region 105. P-type source / drain regions are formed.

  In FIG. 7, a portion of the sidewall spacer formed on the N channel MISFET formation region 101 is shown as a sidewall spacer 131a for convenience, and the portion of the sidewall spacer formed on the P channel MISFET formation region 102 is shown. This portion is shown as a sidewall spacer 131b.

  The gate wiring 103 includes a polysilicon film 112 formed on the active regions 104 and 105 and the element isolation region 106, and a silicide film 111 formed on the polysilicon film 112. A portion of the gate wiring 103 positioned on the active region 104 serves as a gate electrode of the N channel MISFET, and a portion of the gate wiring 103 positioned on the active region 105 includes a gate electrode of the P channel MISFET. It has become. Further, an N-type impurity is introduced into a portion of the gate wiring 103 formed on the N-channel MISFET formation region 101, and a portion of the gate wiring 103 formed on the P-channel MISFET formation region 102 is P Type impurities have been introduced. In FIG. 7 and the like, a boundary between portions where impurities of different conductivity types are introduced in the gate wiring 103 is illustrated as a doping boundary 109.

  In addition, an N-type extension region and an N-type source / drain region (not shown) are formed in regions of the active region 104 located on both sides of the gate wiring 103, and two N-types of the active region 104 are formed. A channel region 80 of an N-channel type MISFET is formed in a region located between the source / drain regions and immediately below the gate wiring 103.

  P-type extension regions and P-type source / drain regions (not shown) are formed in regions of the active region 105 located on both sides of the gate wiring 103, and two P-type source / drain regions in the active region 105 are formed. A channel region 90 of a P-channel type MISFET is formed in a region sandwiched between the drain regions and located immediately below the gate wiring 103.

  Further, a tensile stress film 151 covering at least a part of the gate wiring 103 and the sidewall spacer 131a is formed on the N channel MISFET formation region 101 including the active region 104, and a P channel type including the active region 105 is formed. On the MISFET formation region 102, a compressive stress film 155 that covers at least a part of the gate wiring 103 and the sidewall spacer 131b is formed.

  The peripheral portion of the tensile stress film 151 is thinner than the other portions, and this thinned portion (that is, the tensile stress film 151b) is formed, for example, in the N channel MISFET formation region 101 and the P channel MISFET formation. At least the boundary with the region 102 (doping boundary 109) is covered. A portion of the tensile stress film 151 that is not thinned (that is, the tensile stress film 151 a) covers at least the active region 104 and the gate wiring 103 thereon. Since the stress applied from the tensile stress film 151 a is applied to the channel region 80 through the gate electrode that is a part of the gate wiring 103, tensile strain is generated in the channel region 80.

  The peripheral portion of the compressive stress film 155 is thinner than the other portions, and this thinned portion (that is, the compressive stress film 155b) forms, for example, an N-channel MISFET at the same position as the doping boundary 109. At least the boundary between the region 101 and the P-channel type MISFET formation region 102 is covered. A portion of the compressive stress film 155 that is not thinned (that is, the compressive stress film 155a) covers at least the active region 105 and the gate wiring 103 thereon. Since the stress applied from the compressive stress film 155 a is applied to the channel region 90 through the gate electrode which is a part of the gate wiring 103, compressive strain is generated in the channel region 90.

  Further, as described above, the tensile stress film 151 b and the compressive stress film 155 b are partially overlapped with the etching stop film 153 on the tensile stress film 151 interposed therebetween. As described above, the gate wiring 103 includes the region 162 covered only by the tensile stress film 151b of the stress application film, the region 161 where the tensile stress film 151b and the compression stress film 155b overlap, and the compression of the stress application film. It has the area | region 160 comprised by the area | region 163 covered only by the stress film | membrane 155b. This region 160 is a stress relaxation region in which the total stress received from both stress application films is relaxed. If the doping boundary 109 in the gate wiring 103 is within this region 160, the stress inside the gate wiring 103 in the vicinity of the doping boundary 109 is more effective than in the semiconductor device according to the reference example shown in FIGS. Therefore, the frequency of occurrence of problems such as damage to the silicide film 111 and disconnection of the gate wiring 103 can be greatly reduced.

  In the region 161, since a contact hole can be formed as described above, the degree of design freedom can be improved.

  In the present embodiment, an example in which the stress of the gate wiring 103 in the region 161 is almost zero has been described. However, depending on the thickness of the tensile stress film 151b and the thickness of the compressive stress film 155b, the region 162 and the region 163 may be used. The region 161 may have a tensile stress or a compressive stress within a reduced range.

(Second Embodiment)
10 (a) to 10 (c) and FIGS. 11 (a) to 11 (c) are cross-sectional views showing steps after forming a stress applying film in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. Hereinafter, a method for manufacturing the semiconductor device of this embodiment will be described.

  First, in the process shown in FIG. 10A, the process up to the process of forming the tensile stress film 151 with a thickness of about 50 nm is common to the first embodiment (see FIG. 2A). After the formation of the tensile stress film 151, an etching stop film 170 made of, for example, silicon oxide is formed on the tensile stress film 151. Next, a photoresist 171 is patterned so as to cover the N channel MISFET formation region 101.

  Next, as shown in FIG. 10B, the etching stop film 170 and the tensile stress film 151 are partially removed using a known etching technique using the photoresist 171 as a mask, and an N channel MISFET formation region is formed. A tensile stress film 151c covering 101 and an etching stop film 170a thereon are formed.

  Next, as shown in FIG. 10C, after the photoresist 171 is removed, a compressive stress film 172 having a thickness of about 50 nm is formed on the entire surface of the semiconductor substrate 122. Next, a photoresist 173 is patterned so as to cover the P-channel type MISFET formation region 102.

  Next, as shown in FIG. 11A, etching is performed under conditions having a sufficient selection ratio with respect to the etching stop film 170 using the photoresist 173 as a mask, and the compressive stress film 172 is partially removed. Then, the compressive stress film 172a is formed. Here, the compressive stress film 172a is formed so as to partially overlap the tensile stress film 151c above the element isolation region 106 located between the active region 104 and the active region 105. Thereafter, the photoresist 173 is removed. In this step, the length in the gate width direction of the region where the tensile stress film 151c and the compressive stress film 172a are overlapped is appropriately set according to the design rule.

  Next, as shown in FIG. 11B, after the photoresist 174 is formed, the photoresist 174 is patterned so as to open a region 176 serving as a stress relaxation region in the semiconductor device. The region 176 includes a region where the tensile stress film 151c and the compressive stress film 172a overlap, a region where only the tensile stress film 151c is provided on both sides in the gate width direction, and a region where only the compressive stress film 172a is provided. including. In the method of this embodiment, the width of the gate wiring 103 is 50 nm, but the length of the region 176 in the gate width direction is preferably about 2 to 4 times the gate wiring width.

Thereafter, stress relaxation element ions 175 are implanted using the photoresist 174 as a mask. As the stress relaxation element, an element having an atomic radius larger than that of Si is desirable. However, Si may be used as the stress relaxation element. Further, as the ion implantation conditions in this step, the thickness of the tensile stress film 151c and the compressive stress film 172a is taken into consideration, and the silicide film 111 in the gate wiring 103 under both stress application films or the N-type of the N-channel type MISFET. The conditions are such that the implanted ions do not reach the silicide film (not shown) on the source / drain region and the silicide film on the P-type source / drain region of the P-channel MISFET. Specifically, the ion implantation energy is set to a range of about 5 KeV to 100 KeV, and the dose is set to a range of about 0.5 × 10 ^{14 to} 1.0 × 10 ¹⁵ / cm ² . As a result of this ion implantation, for example, when a silicon nitride film (SiN) is used as the tensile stress film 151c and the compressive stress film 172a, the implanted stress relaxation element ions 175 break the Si-N bond, and the stress relaxation element ions 175 The stress of the tensile stress film 151c and the compressive stress film 172a in the region into which is injected can be locally relaxed or eliminated.

  Next, as shown in FIG. 11C, by removing the photoresist 174, the semiconductor device of this embodiment can be manufactured.

  The semiconductor device of this embodiment manufactured by the above method is different in the configuration of the tensile stress film 151c and the compressive stress film 172a, and the other configuration is the same as that of the first embodiment shown in FIG. It is.

  As shown in FIG. 11C, the gate wiring 103 includes a region 180 covered only by a portion of the tensile stress film 151c where the tensile stress is not relaxed, and a stress relaxation element ion 175 of the tensile stress film 151c. The region 177 covered only by the portion where the tensile stress is relaxed by the implantation and the portion where the compressive stress is relaxed by the implantation of the stress relaxation element ions 175 of the tensile stress film 151c and the compressive stress film 172a are overlapped. A region 179 covered only by a portion of the compressive stress film 172a where the compressive stress is relieved, and a region 181 covered only by a portion of the compressive stress film 172a where the compressive stress is not relieved. Will have.

  In the regions 177 and 179, the stress in the gate wiring 103 is greatly reduced as compared with the stress in the gate wiring 103 in the regions 180 and 181. In the region 178, a stress obtained by subtracting the stress after the relaxation of the compressive stress film 172a from the stress applied from the tensile stress film 151c is applied to the gate wiring 103, but the gate wiring 103 is compared with the regions 180 and 181. The stress that is subjected to is small.

  As described above, in this embodiment, the region 176 including the region 177, the region 178, and the region 179 can be formed as a stress relaxation region. For this reason, occurrence of disconnection of the gate wiring 103 in the stress relaxation region can be suppressed. The doping boundary 109 in the gate wiring 103 is preferably in the region 176 that is a stress relaxation region. This is because the film quality of the polysilicon film 112 and the film quality of the silicide film 111 formed on the polysilicon film 112 change discontinuously in the vicinity of the doping boundary 109, so that the disconnection of the gate wiring 103 is likely to occur at this portion. Because.

  In the semiconductor device of this embodiment, the tensile stress film 151c and the compressive stress film 172a are overlapped without being thinned unlike the semiconductor device of the first embodiment. For this reason, in the semiconductor device of this embodiment, the degree of freedom in layout when forming the contact hole is lowered. However, the degree of stress relaxation can be finely controlled by the implantation conditions of the stress relaxation element ions 175, and local stress relaxation can be achieved by using an ion implantation method using a photoresist. Layout flexibility is high.

  In the manufacturing method according to this embodiment, the tensile stress film 151 is formed before the compressive stress film 172, but the same effect can be obtained even if this order is reversed.

  Further, after the step shown in FIG. 11C, the semiconductor device is completed through processes such as formation of contact holes and contact plugs and formation of wirings.

  As described above, according to the manufacturing method of the semiconductor device of this embodiment, the stress applied from the stress application film by the implantation of the stress relaxation element ions 175 can be locally eliminated or relaxed in the gate wiring 103. A stress relaxation region with a high degree of freedom can be set in 103, and a semiconductor device with high yield and high reliability can be realized.

(Third embodiment)
12 (a) to 12 (c), 13 (a), and 13 (b) are cross-sectional views showing steps after forming a stress applying film in the method of manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. FIG. 13C is a plan view showing the semiconductor device in the step shown in FIG. Hereinafter, a method for manufacturing the semiconductor device of this embodiment will be described.

  First, in the process shown in FIG. 12A, an N channel MISFET formation region 101 and a P channel MISFET formation region 102 are formed on a semiconductor substrate 122, and an N channel MISFET or a P channel MISFET is formed thereon, respectively. The process up to forming is the same as the method according to the first embodiment. However, the process of forming the silicide films 134, 144, and 111 on the N-type source / drain region 132, the P-type source / drain region 142, and the polysilicon film 112 has not been performed yet.

  Next, after forming an N channel MISFET and a P channel MISFET, a tensile stress film 201 is formed on the entire surface of the semiconductor substrate 122 to a thickness of, for example, 50 nm. As the tensile stress film 201, for example, a silicon nitride film formed by thermal chemical vapor deposition or LPCVD may be used. Alternatively, the tensile stress film 201 may be formed by a method of annealing after forming a silicon oxynitride film (SiON film) by PECVD. The tensile stress film 201 may be a silicon oxide film that applies a tensile stress.

  After the formation of the tensile stress film 201, the photoresist 202 is patterned so as to cover at least the N channel MISFET formation region 101. Note that the photoresist 202 is not formed on the P-channel MISFET formation region 102 except near the boundary with the N-channel MISFET formation region 101. That is, the photoresist 202 is formed on the side of the P channel MISFET formation region 102 by a predetermined distance (for example, about 1 to 3 times the width (gate length) of the polysilicon film 112) from the doping boundary 109 in the gate wiring 103. It is formed up to the area where it enters.

  Next, as shown in FIG. 12B, the N channel MISFET is formed on the N channel MISFET formation region 101 and the P channel MISFET formation region 102 by using a known etching technique using the photoresist 202 as a mask. A patterned tensile stress film 201a is formed on a region whose distance from the boundary with the formation region 101 is, for example, within 1 to 3 times the gate length.

  Next, as shown in FIG. 12C, the photoresist 202 is moved backward by ashing the surface portion of the photoresist 202, and a photoresist 202a having a size smaller than that of the photoresist 202 is formed.

  Next, as shown in FIG. 13A, the exposed portion of the tensile stress film 201a that is not covered with the photoresist 202a is etched in the film thickness direction to reduce the thickness of the exposed portion. . Here, in FIG. 13A, the thinned portion of the tensile stress film 201a is shown as a tensile stress film 201b. The thickness of the tensile stress film 201b left without being etched in this step is, for example, 30 nm.

  With this configuration, the stress exerted on the polysilicon film 112 under the tensile stress film 201b can be relaxed to about half of the stress exerted on the polysilicon film 112 under the tensile stress film 201a. it can. The length of the tensile stress film 201b is preferably about 1 to 3 times the width (gate length) of the polysilicon film 112 which is a gate electrode.

  As described above, since the tensile stress film 201b is formed by the self-alignment technique by the receding of the photoresist 202, the receding amount can be controlled with high accuracy. Furthermore, since the number of additional steps for processing can be reduced, the stress relaxation region can be formed at low cost.

  Subsequently, as shown in FIGS. 13B and 13C, the photoresist 202a is removed.

  Thereafter, the entire semiconductor substrate 122 is heat-treated at, for example, 1000 ° C. by rapid thermal annealing (RTA). At this time, the tensile stress applied from the tensile stress film 201a and the tensile stress film 201b is stored in the regions 204 and 203 of the polysilicon film 112, respectively, and further from the tensile stress film 201a to the channel region 80 of the N channel MISFET. The strain caused by the applied stress is stored.

  Next, although not shown, after removing the tensile stress film 201a and the tensile stress film 201b, the upper surface portion of the polysilicon film 112, the N-type source / drain region and the P-type source / drain region are formed by a known method. A silicide film is formed by siliciding the upper surface portion. Thereafter, the semiconductor device is completed through processes such as contact hole formation, contact plug formation, and wiring formation by a known method. When forming the contact hole, an etching stopper may be separately provided. Note that the gate wiring formed in the above steps is composed of the polysilicon film 112 and the silicide film formed thereon, but the silicide film is not formed, and the gate wiring is composed only of the polysilicon film. May be.

  Here, in the step shown in FIG. 13B, the polysilicon film 112 constituting the gate wiring is formed into the region 204 covered with the tensile stress film 201a and the tensile stress film 201b as shown in FIG. 13B. It is divided into three regions: a region 203 where the tensile stress is covered and a region 205 where the tensile stress film 201a and the tensile stress film 201b are not covered. The ratio of the magnitude of the tensile stress applied to the polysilicon film 112 in the regions 204, 203, and 205 is approximately 1: 0.5: 0, and the region 203 that is covered with the tensile stress film 201b and is subjected to stress relaxation is not provided. In comparison, it can be seen that the amount of stress change at the boundary of each region of the gate wiring is greatly reduced.

  The tensile stress applied to the polysilicon film 112 in the regions 204, 203, and 205 is stored in the gate wiring of the semiconductor device manufactured by the above method.

  The doping boundary 109 in the gate wiring (polysilicon film 112) is preferably in the region 203 which is a stress relaxation region. This is because the film quality of the polysilicon film 112 and the silicide film on the polysilicon film 112 changes discontinuously at the doping boundary 109, so that the risk of disconnection of the gate wiring is highest at this portion. Therefore, by providing the doping boundary 109 in the region 203 with the lowest stress, the disconnection of the gate wiring 103 can be most effectively prevented.

  As described above, according to the semiconductor device of this embodiment, even when the SMT is used as a strain applying technique, the end portion of the stress applying film is thinned by using the self-alignment technique. Since the stress relaxation region can be formed, it is possible to effectively prevent disconnection of the gate wiring due to a sudden change in stress inside the gate wiring, and to realize a semiconductor device with high yield and high reliability at low cost.

  In the semiconductor device according to the present embodiment, an example in which the tensile stress is stored in the channel region 80 of the N-channel MISFET using the tensile stress films 201a and 201b is shown. However, in the tensile stress films 201a and 201b, Alternatively, a compressive stress film may be formed, and the compressive stress may be stored in the channel region 90 of the P channel MISFET by using the compressive stress film. Also, as shown in FIG. 7, after forming a tensile stress film having a shape with a thin end portion and a compressive stress film having a shape having a thin end portion, the end portions are overlapped with each other, and then about 1000 ° C. The stress applied from these stress application films may be stored in the channel regions 80 and 90 and the gate wiring by thermal annealing.

  In this embodiment, after the step shown in FIG. 13B, the tensile stress films 201a and 201b are removed and a silicide film is formed. However, in the step shown in FIG. Even if the silicide film is formed in advance before forming the n-type MISFET and the tensile stress films 201a and 201b are not removed after the step shown in FIG. 13B, the mobility of the N-channel MISFET is improved. However, the stress change between the regions in the gate wiring can be alleviated.

(Fourth embodiment)
FIGS. 14A to 14C and 15 are cross-sectional views showing a process after the stress application film is formed in the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention.

  First, in the step shown in FIG. 14A, an N-channel MISFET is formed on the active region 104 and formed on the active region 105, as in the step shown in FIG. 12A in the method of the third embodiment. A P-channel MISFET is formed. Note that the step of forming a silicide film on the N-type source / drain region, the P-type source / drain region, and the polysilicon film 112 has not been performed yet.

  Next, a tensile stress film 400 is formed on the entire surface of the semiconductor substrate 122 to a thickness of, for example, 50 nm. As the tensile stress film 400, for example, a silicon nitride film formed by thermal chemical vapor deposition or LPCVD may be used. Alternatively, the tensile stress film 201 may be formed by a method of annealing after forming a silicon oxynitride film by PECVD. The tensile stress film 201 may be a silicon oxide film that applies a tensile stress. In this embodiment, a silicon nitride film is used as the tensile stress film 400.

  After the formation of the tensile stress film 400, a photoresist 401 having an opening in a region 403 serving as a stress relaxation region in the semiconductor device is formed on the tensile stress film 400.

Subsequently, stress relaxation element ions 402 are implanted into the tensile stress film 400 using the photoresist 401 as a mask. As the stress relaxation element, an element having an atomic radius larger than that of Si is desirable. However, Si may be used as the stress relaxation element. Here, the ion implantation conditions are set so that the implanted ions do not reach the upper surfaces of the active regions 104 and 105 and the polysilicon film 112 in consideration of the thickness of the tensile stress film 400. Specifically, the ion implantation energy is set to a range of 5 Kev to 100 Kev, and the dose is set to a range of about 0.5 × 10 ^{14 to} 1.0 × 10 ¹⁵ / cm ² .

  As a result of this ion implantation, the implanted stress relaxation element ions 402 break the Si—N bond in the tensile stress film 400 and locally relieve or eliminate the stress of the tensile stress film. In this embodiment, the implantation conditions of the stress relaxation element ions 402 are adjusted so that the tensile stress of the tensile stress film 400 in the region 403 is about half of the tensile stress in the other regions.

  Next, as shown in FIG. 14B, after the photoresist 401 is removed, a photoresist 404 is formed on the tensile stress film 400, and then the photoresist 404 is patterned. The photoresist 404 is formed so as to cover at least the N-channel MISFET formation region 101.

  Next, as shown in FIG. 14C, the tensile stress film 400 is selectively removed using a known etching technique using the photoresist 404 as a mask, and the N channel MISFET formation region 101 including the active region 104 is removed. A covering tensile stress film 400a is formed.

  Next, the photoresist 404 is removed to obtain the semiconductor device shown in FIG. The polysilicon film 112 constituting the gate electrode covers the region 406 covered with the portion where the stress relaxation element is not implanted in the tensile stress film 400a and the portion where the stress relaxation element is implanted in the tensile stress film 400a. The region 405 is divided into three regions: a region 405 that is broken and a region 407 that is not covered with the tensile stress film 400a. In these regions 406, 405, and 407, the magnitude of the tensile stress applied to the polysilicon film 112 is approximately 1: 0.5: 0, and the region 405 covered with the tensile stress film 400a into which the stress relaxation element is implanted is not provided. Compared to the case, it can be seen that the amount of change in stress at the region boundary in the polysilicon film 112 is greatly relaxed.

  Thereafter, the entire semiconductor substrate 122 is heat-treated at, for example, 1000 ° C. by RTA. At this time, the tensile stress applied by the tensile stress film 400a is stored in the regions 406 and 405 of the polysilicon film 112, respectively, and the tensile stress applied by the tensile stress film 400a is also stored in the channel region 80 of the N channel MISFET. Is done.

  Next, after removing the tensile stress film 400a, a silicide film is formed by siliciding the upper surface portion of the polysilicon film 112 and the upper surface portions of the N-type source / drain region and the P-type source / drain region. (Not shown). Thereafter, the semiconductor device is completed through processes such as contact hole formation, contact plug formation, and wiring formation by a known method. The polysilicon film 112 and the silicide film formed thereon constitute a gate wiring.

  Here, the doping boundary 109 in the gate wiring (polysilicon film 112) is preferably in the region 405 which is a stress relaxation region. This is because the film quality of the polysilicon film 112 and the silicide film 111 on the polysilicon film 112 changes discontinuously at the doping boundary 109, so that there is the highest risk of disconnection of the gate wiring at this portion. . Therefore, by providing the doping boundary 109 in the region 405 with the lowest stress, disconnection of the gate wiring 103 can be most effectively prevented.

  As described above, according to the semiconductor device of this embodiment, even when the SMT is used as a strain application technique, the stress relaxation region ions are implanted into the end portion of the stress application film, so that the stress relaxation region is formed in the gate wiring. Therefore, it is possible to effectively prevent disconnection of the gate wiring due to a sudden change in stress inside the gate wiring. For this reason, according to the manufacturing method of the present embodiment, it is possible to realize a semiconductor device with high yield and high reliability.

  In addition, according to the method of the present embodiment that uses stress relaxation element ions to form the stress relaxation region, the degree of stress relaxation can be easily controlled by the implantation conditions of the stress relaxation element ions. Further, since a fine implantation region can be set by the photoresist 401, a fine stress relaxation region with a high degree of layout freedom can be formed, so that a semiconductor device with high yield and high reliability can be realized.

  In the method of the present embodiment, an example in which a tensile stress film is stored in the channel region 80 of the N-channel type MISFET using the tensile stress film is shown. However, the channel region 90 of the P-channel type MISFET is compressed by the same method. Even when the stress is memorized using the stress film, the same effect can be obtained by implanting stress relaxation element ions at the end of the compressive stress film.

  In this embodiment, after the step shown in FIG. 15, the tensile stress films 201a and 201b are removed and the silicide film is formed. However, the tensile stress film 400 is formed in the step shown in FIG. Even in the case where a silicide film is formed in advance and the tensile stress films 201a and 201b are not removed after the process shown in FIG. 15, the mobility of the N-channel MISFET is improved, The stress change between the regions can be relaxed.

  In the configuration and manufacturing method of the semiconductor device described above, the constituent material, size, shape, order of forming the members, and the like can be changed as appropriate without departing from the spirit of the present invention.

  For example, in the semiconductor device according to the first embodiment, the gate wiring 103 is composed of the polysilicon film 112 and the silicide film 111, but the gate wiring 103 is made of a metal material or the like manufactured by a so-called gate first process. Even if configured, the same disconnection preventing effect as that of the semiconductor device of the first embodiment can be obtained. Further, the case where the semiconductor device includes a MISFET has been described above, but the structure according to each embodiment can be applied to a case where the semiconductor device includes another semiconductor element having a gate wiring (gate electrode) instead of the MISFET. .

  As described above, the present invention can be widely applied to semiconductor devices having gate wirings, and can be applied to various semiconductor devices such as complementary MOS (CMOS) and SRAM as an example.

80, 90 channel region 101 N channel MISFET formation region 102 P channel MISFET formation region 103 Gate wiring 104, 105 Active region 106 Element isolation region 109 Doping boundary 111, 134, 144 Silicide film 112 Polysilicon film 113a, 113b Gate insulation Film 120 N well 121 P well 122 Semiconductor substrate 131a, 131b Side wall spacer
132 N-type source / drain region 135 N-type extension region 142 P-type source / drain region 145 P-type extension regions 151, 151a, 151b, 151c Tensile stress films 152, 152a, 156, 156a, 171, 173, 174 Photoresist 153 , 170, 170a Etching stop film 155, 155a, 155b Compressive stress film 160, 161, 162, 163, 164, 162, 161, 163, 165 Region 172, 172a Compressive stress film 175, 402 Stress relaxation element ions 176, 177, 178, 179, 180, 181, 203, 204, 205 Regions 201, 201a, 201b Tensile stress films 202, 202a, 401, 404 Photoresist 250 Passivation film 252 Contact hole 260 Mask 400, 400a Tensile stress film 403, 405, 406, 407 region

Claims (21)

A semiconductor substrate having a first element formation region and a second element formation region, a first active region formed above the first element formation region, and an upper portion of the second element formation region A second active region formed adjacent to the first active region, a gate wiring extending from at least the first active region to the second active region, and the first active region First channel region of the first conductivity type formed in a region located immediately below the gate wiring, and a second channel formed in a region located immediately below the gate wiring in the second active region. A second channel region of conductivity type,
The gate wiring is
A first region formed on at least the first active region and having a first stress that is a tensile stress or a compressive stress;
A second region having a first stress that is closer to the second active region than the first region, is adjacent to the first region, and is more relaxed than the first region; Have
A semiconductor device in which a strain corresponding to the first stress is generated in the first channel region. The semiconductor device according to claim 1,
The gate wiring is
A third region formed on at least the second active region and having a second stress that is tensile stress or compressive stress opposite to the first stress;
A fourth region having a second stress that is located closer to the first active region than the third region, is adjacent to the third region, and is more relaxed than the third region; Further comprising
A stress relaxation region including the second region and the fourth region is formed between the first region and the third region of the gate wiring.
The semiconductor device, wherein the second channel region is distorted according to the second stress. The semiconductor device according to claim 2,
A first stress application for applying the first stress is formed on the first element formation region so as to cover at least the first region, the second region, and the first active region. A membrane,
A second stress application for applying the second stress is formed on the second element formation region so as to cover at least the third region, the fourth region, and the second active region. A semiconductor device, further comprising a film. The semiconductor device according to claim 3.
The stress relaxation region further includes a fifth region formed between the second region and the fourth region and having a stress smaller than that of the second region and the fourth region,
The first stress application film is thinned on the stress relaxation region,
The second stress applying film is thinned on the stress relaxation region,
The thinned portion of the first stress applying film and the thinned portion of the second stress applying film are overlapped on the fifth region. . The semiconductor device according to claim 3.
The stress relaxation region further includes a sixth region formed between the second region and the fourth region,
The first stress applying film and the second stress applying film are overlapped on the sixth region,
The first stress included in at least a part of the first stress application film formed on the stress relaxation region is formed on the first active region of the first stress application film. Is relaxed from the first stress of the portion formed
The second stress included in at least a part of the second stress application film formed on the stress relaxation region is formed on the second active region of the second stress relaxation film. A semiconductor device characterized in that the semiconductor device is more relaxed than the second stress of the formed portion. In the semiconductor device according to any one of claims 3 to 5,
A portion of the gate wiring formed on the first element formation region is doped with a second conductivity type impurity, and a portion of the gate wiring formed on the second element formation region. Is doped with a first conductivity type impurity, and a region of the gate wiring located on the boundary between the first element formation region and the second element formation region is a doping boundary,
The semiconductor device, wherein the doping boundary is formed in the stress relaxation region. The semiconductor device according to claim 1 or 2,
The first stress is stored in the first region,
The relaxed first stress is stored in the second region,
The semiconductor device according to claim 1, wherein a strain corresponding to the first stress is stored in the first channel region. The semiconductor device according to claim 7,
A portion of the gate wiring formed on the first element formation region is doped with a second conductivity type impurity, and a portion of the gate wiring formed on the second element formation region. Is doped with a first conductivity type impurity, and a region of the gate wiring located on the boundary between the first element formation region and the second element formation region is a doping boundary,
The semiconductor device, wherein the doping boundary is formed in the second region. In the semiconductor device according to claim 1,
An element isolation region that is provided between the first active region and the second active region and electrically isolates the first active region and the second active region;
At least the second region is formed on the element isolation region. In the semiconductor device according to any one of claims 1 to 9,
The semiconductor device according to claim 1, wherein the first stress applying film is made of silicon oxide, silicon oxynitride, or silicon nitride. In the semiconductor device according to claim 1,
The first channel region is P-type;
The first stress is a tensile stress;
Tensile strain has occurred in the first channel region,
An N-channel MISFET having a part of the first gate wiring as a gate electrode is formed on the first active region. In the semiconductor device according to claim 1,
The first channel region is N-type;
The first stress is a compressive stress;
The first channel region has a compressive strain;
A P-channel MISFET having a part of the first gate wiring as a gate electrode is formed on the first active region. In the semiconductor device according to any one of claims 1 to 12,
The semiconductor device according to claim 1, wherein the gate wiring includes a silicon film and a metal silicide film formed on the silicon film. A first active region is formed in the first element formation region of the semiconductor substrate having the first element formation region and the second element formation region, and the first element is formed in the second element formation region. Forming a second active region adjacent to the active region of (a),
A first region that extends from at least the first active region to the second active region and is located on the first active region; and the second active than the first region. Forming a gate wiring having a second region close to the region and adjacent to the first region on the first element formation region;
A first stress that is a tensile stress or a compressive stress is applied so as to cover the first region and the second region on the first element formation region including the first active region. By forming the stress applying film, distortion is generated in the first channel region of the first conductivity type located immediately below the gate wiring in the first active region, and the first region and the first region Generating the first stress in the region of 2 (c);
A step (d) of processing a portion of the first stress application film formed on the second region to reduce the first stress applied to the second region. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 14,
The gate line includes a third region located on the second active region, a fourth region closer to the first active region than the third region, and adjacent to the third region, In addition,
After the step (d), opposite to the first stress so as to cover the third region and the fourth region on the second element formation region including the second active region. By forming the second stress applying film for applying the second stress, distortion is generated in the second channel region of the second conductivity type located immediately below the gate wiring in the second active region. And (e) generating the second stress in the third region and the fourth region;
A step (f) of processing a portion of the second stress applying film formed on the fourth region to reduce the second stress applied to the fourth region; A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 15,
The gate wiring has a stress relaxation region including the second region and the fourth region between the first region and the third region,
The stress relaxation region further includes a fifth region formed between the second region and the fourth region,
In the step (d), a portion of the first stress application film formed on the stress relaxation region is thinned,
In the step (f), a portion of the second stress application film formed on the stress relaxation region is thinned,
The thinned portion of the first stress applying film and the thinned portion of the second stress applying film overlap each other on the fifth region. Method. In the manufacturing method of the semiconductor device according to claim 15,
The gate wiring has a stress relaxation region including the second region and the fourth region between the first region and the third region,
The stress relaxation region further includes a sixth region formed between the second region and the fourth region;
The step (d) is performed simultaneously with the step (f) after the step (e),
In the steps (d) and (f), stress relaxation element ions are implanted into a portion of the first stress application film and the second stress application film formed on the stress relaxation region,
The method of manufacturing a semiconductor device, wherein the first stress applying film and the second stress applying film are overlapped on the sixth region. A first active region is formed in the first element formation region of the semiconductor substrate having the first element formation region and the second element formation region, and the first element is formed in the second element formation region. Forming a second active region adjacent to the active region of (a),
A first region that extends from at least the first active region to the second active region and is located on the first active region; and the second active than the first region. Forming a silicon film having a second region close to the region and adjacent to the first region on the first element formation region;
Stress application for applying a first stress that is a tensile stress or a compressive stress so as to cover the first region and the second region on the first element formation region including the first active region. By forming the film, distortion is generated in the channel region of the first conductivity type located immediately below the silicon film in the first active region, and the first region and the second region are in the first region. (C) producing a stress of 1;
A step (d) of processing a portion of the stress application film formed on the second region to reduce the first stress applied to the second region;
After the step (d), the semiconductor substrate is thermally annealed so that the first stress is stored in the first region, and strain generated according to the first stress is stored in the channel region. Step (e), and
And a step (f) of removing the stress applying film. In the manufacturing method of the semiconductor device according to claim 18,
After the step (f), there is further provided a step (g) of forming a gate wiring having a metal silicide film by siliciding the upper part or the whole of the silicon film. Method. In the manufacturing method of the semiconductor device according to claim 17 or 18,
In the step (d), a portion of the stress application film formed on the second region is thinned. In the manufacturing method of the semiconductor device according to claim 17 or 18,
In the step (d), a stress relaxation element ion is implanted into a portion of the stress application film formed on the second region.

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