JP2012244389A - Glitch processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently extend the pulse width of a glitch to prevent a through current from occurring in circuits at following stages.SOLUTION: A glitch processing circuit comprises: a single-phase/differential conversion circuit 10 which generates a differential signal in nodes N1 and N2 from a single-phase input signal; a masking circuit 30 which masks a signal of the node N1 with a signal of a node N3 before being output to a node 4 and masks a signal of the node N2 with a signal of a node N5 before being output to a node 6; a latch circuit 30 which accepts signals of the nodes N4 and N6 as its input and sends its output signals to nodes N7 and N8; and a delay circuit 40 which delays a signal of the node N7 by only a time T0 before being output to the node N5 and delays a signal of the node N8 by only a time T0 before being output to the node N3. The signal of the node N8 is made the output signal of the glitch processing circuit.

Description

  The present invention relates to a glitch processing circuit for extending the pulse width of a glitch mixed in a signal.

  FIG. 9 shows a pre-driver circuit 200 in a class D amplifier. The pre-driver circuit 200 includes an OR circuit OR1, an AND circuit AND1, delay elements DL3 and DL4, a PMOS transistor MP1, and an NMOS transistor MN1. The OR circuit OR1, the AND circuit AND1, and the delay elements DL3 and DL4 constitute a masking circuit for turning on the transistors MP1 and MN1 at the same time so that no through current flows. The mask time of the masking circuit is set by the delay time T1 of the delay elements DL3 and DL4.

  Therefore, in the pre-driver circuit 200, when the pulse width of the input signal is longer than the delay time T1 of the delay elements DL3 and DL4, an off period of time T1 is formed as shown in FIG. No through current flows between MP1 and MN1, but when the input signal is a glitch shorter than the delay time T1, normal masking operation is not performed, and the transistors MP1 and MN1 are simultaneously connected as shown in FIG. When it is turned on, a through current flows, and the transistors MP1 and MN1 may be greatly damaged.

  Therefore, as a method for preventing such a problem due to glitches, there is a method in which a glitch removal circuit is constituted by a delay circuit, a comparison circuit, and a latch circuit, as seen in Patent Document 1. In this example, when the signal changes, the comparison circuit reacts and the latch circuit performs an operation of taking in data. Since the hold time in the latch circuit is determined by the delay time of the delay circuit, the influence of noise can be eliminated by making this time longer than the time when the signal is affected by noise.

  In addition, as seen in Patent Documents 2 to 4, there is also a low-pass filter provided in the signal path to remove a high frequency component generated by noise. In some cases, after the signal is taken back into the DFF by the clock, the time width of the signal of the same logic is counted by a counter to remove the noise.

JP 2002-208844 A (FIGS. 10 and 11) JP-A-8-237087 (FIG. 12) JP-A-7-336201 (FIG. 13) Japanese Patent Laying-Open No. 2007-74294 (FIG. 14) US Pat. No. 6,337,649 (FIG. 2)

  However, the device described in Patent Document 1 as described above has a drawback in that erroneous data is held if the timing of taking in the delay element is incorrect. Moreover, in the thing of patent documents 2-4, there existed a fault which a propagation delay produced by inserting a low-pass filter in a signal wire | line. In particular, in the case of entering the negative feedback path, there is a drawback that the phase margin is impaired. Further, the device described in Patent Document 5 has a drawback that a clock having a frequency sufficiently higher than that of a signal is required.

  An object of the present invention is to provide a glitch processing circuit that does not remove the glitch as described above but sufficiently expands its pulse width so that no through current is generated in a subsequent circuit.

To achieve the above object, a glitch processing circuit according to a first aspect of the present invention is a simple circuit that outputs an inverted signal of an input signal to a first node and outputs a non-inverted signal of the input signal to a second node. The phase / differential conversion circuit and the signal of the first node are masked with the signal of the third node and output to the fourth node, and the signal of the second node is masked with the signal of the fifth node And a SRFF that changes the signal of the seventh node and the signal of the eighth node according to the change of the signal of the fourth node or the change of the signal of the sixth node. A latch circuit comprising: a signal delayed from the seventh node by a first time and output to the fifth node; and an eighth node signal delayed from the first time by the third time. A delay circuit that outputs to the node Provided, characterized in that the said eighth node and the seventh node signal the output signal of the of.
According to a second aspect of the present invention, in the glitch processing circuit according to the first aspect, the first time of the delay circuit is equal to or equal to a mask time for preventing a through current of a subsequent circuit to which the output signal is input. Characterized by longer.
According to a third aspect of the present invention, in the glitch processing circuit according to the first or second aspect, the masking circuit determines whether the signal of the second node is a signal when the signal of the fifth node is a first logic. Regardless, the signal of the sixth node is set to the second logic, and when the signal of the third node is the first logic, the signal of the fourth node is set to the second logic regardless of the signal of the first node. It is characterized by the following logic.
According to a fourth aspect of the present invention, in the glitch processing circuit according to the first, second, or third aspect, the latch circuit includes the seventh circuit when the fourth node changes from the second logic to the first logic. And the eighth node as the first logic, and when the sixth node changes from the second logic to the first logic, the seventh node becomes the first logic. It is characterized in that it is logical and the eighth node is the second logic.
The invention according to claim 5 is the glitch processing circuit according to claim 1, 2, 3 or 4, wherein an impedance conversion circuit is connected to one of the seventh and eighth nodes, and the impedance conversion circuit is connected to the other. A load capacitance generation circuit equal to the input impedance is connected.

  According to the glitch processing circuit of the present invention, since the pulse width of the glitch can be extended by the delay time of the delay circuit, even if the output signal of the glitch processing circuit is output to the pre-driver circuit in the subsequent stage, the pre-driver circuit Through current generation can be prevented. In addition, since a low-pass filter is not required in the signal line, the system can be stabilized even when a negative feedback circuit is used. Furthermore, since no clock is required, there is no need to provide a separate oscillation circuit.

It is a circuit diagram of a glitch processing circuit for explaining the principle of the present invention. 1 is a circuit diagram of a glitch processing circuit according to a first embodiment of the present invention. FIG. It is a circuit diagram of the glitch processing circuit of the 2nd example of the present invention. It is a circuit diagram of the glitch processing circuit of the 3rd example of the present invention. It is a circuit diagram of the glitch processing circuit of the 4th example of the present invention. It is a circuit diagram of the glitch processing circuit of the 5th example of the present invention. It is a circuit diagram of the glitch processing circuit of the 6th example of the present invention. It is an operation | movement waveform diagram of the glitch processing circuit of 1st Example of this invention. It is a circuit diagram of the pre-driver circuit of the conventional class D amplifier. FIG. 10 is an operation waveform diagram of the pre-driver circuit of FIG. 9.

<Principle of the present invention>
FIG. 1 shows a principle configuration of a glitch processing circuit 100 of the present invention. The glitch processing circuit 100 of the present invention includes a single-phase / differential conversion circuit 10, a masking circuit 20, a latch circuit 30, and a delay circuit 40.

  The single-phase / differential conversion circuit 10 outputs an inverted signal obtained by inverting the input signal of the input terminal IN to the node N1, and outputs a non-inverted signal to the node N2. Masking circuit 20 masks the signal at node N1 with the signal at node N3 and outputs it to node N4, and masks the signal at node N2 with the signal at node N5 and outputs it to node N6. The latch circuit 30 is configured by an SRFF (set / reset flip-flop) that changes the signal of the node N7 and the signal of the node N8 by the change of the signal of the node N4 or the change of the signal of the node N6. Delay circuit 40 delays the signal at node N7 by time T0 and outputs it to node N5, and delays the signal at node N8 by time T0 and outputs it to node N3. The delay time T0 is set to be equal to or longer than the delay time T1 of the delay elements DL3 and DL4 of the pre-driver circuit 200 described in FIG.

  In this glitch processing circuit 100, when a pulse having a duration longer than the delay time T0 in the delay circuit 40 is input to the input terminal IN, the signal does not change during the hold period of the latch circuit 30, and the output signal of the node N8 Has the same waveform as the input signal of the input terminal IN, and the waveform of the output signal of the node N7 is a waveform obtained by inverting the input signal of the input terminal IN. However, when a pulse having a time width shorter than the delay time T0 in the delay circuit 40 is input to the input terminal IN, the signal held by the latch circuit 30 is output, so the waveforms of the output signals at the nodes N7 and N8 are delayed. It is shaped into a pulse width of time T0 and output. As a result, even if a glitch with a pulse width shorter than the delay time T0 is input, the glitch is output with the pulse width expanded to the time T0 (≧ T1). Even if it is input to the circuit, there is no risk of generating a through current there.

<First embodiment>
FIG. 2 shows a glitch processing circuit 100 according to the first embodiment of the present invention. The single-phase / differential conversion circuit 10 includes inverters INV1 and INV2. A signal input to the input terminal 11 is inverted by the inverter INV1 and output to the node N1 as an inverted signal. Output to N2. At this time, the input signal IN is impedance-converted by the inverters INV1 and INV2 and output to the nodes N1 and N2.

  The masking circuit 20 masks the signal at the node N2 with the signal at the node N5 and outputs it to the node N6. The NAND circuit NAND2 masks the signal at the node N1 with the signal at the node N3 and outputs the signal to the node N4. Is provided. That is, the NAND circuit NAND1 outputs an “H” signal to the node N6 regardless of the signal of the node N2 when the signal of the node N5 is “L”, but the node N5 outputs a node when the signal of the node N5 is “H”. The signal of N2 is inverted and output to the node N6. The NAND circuit NAND2 outputs an “H” signal to the node N4 regardless of the signal of the node N1 when the signal of the node N3 is “L”, but the node N3 outputs a node when the signal of the node N3 is “H”. The signal of N1 is inverted and output to the node N4.

  The latch circuit 30 is composed of an SRFF composed of NAND circuits NAND3 and NAND4. When the signal at the node N4 changes from “H” to “L”, the signal at the node N7 changes to “H” and the signal at the node N8 changes to “ Change to L ″. When the signal at the node 6 changes from “H” to “L”, the signal at the node N7 is changed to “L”, and the signal at the node N8 is changed to “H”.

  Delay circuit 40 includes a delay element DL2 that delays the signal of node N8 by time T0 and outputs the delayed signal to node N3, and a delay element DL1 that delays the signal of node N7 by time T0 and outputs the delayed signal to node N5.

Next, the operation will be described with reference to the waveform diagram of FIG.
(1) When the node logic is N7 ≠ N5 and N8 ≠ N3,
(1-1) When N7 = “H” and N8 = “L”, N5 = “L” and N3 = “H”, and the masking circuit 20 has N6 = “N” regardless of the logic of the node N2. The node N4 becomes an inverted signal of the signal at the node N1. However, the latch circuit 30 has N7 = “H” and N8 = when the node N4 becomes “L” or “H”. Hold “L”.
(1-2) When N7 = “L” and N8 = “H”, N5 = “H” and N3 = “L”, and the masking circuit 20 has N4 = “N” regardless of the logic of the node N1. The node N6 becomes an inverted signal of the signal of the node N2, but the latch circuit 30 is configured such that N7 = “L”, N8 = when the node N6 becomes “L” or “H”. Hold “H”.
(1-3) As a result, even if the signal of the input terminal 11 that generates a signal at the nodes N1 and N2 changes to either “H” or “L”, the logic of the nodes N7 and N8 of the latch circuit 30 is Retained.

(2) When the logic of the node is N7 = N5 and N8 = N3,
(2-1) When N7 = “H” and N8 = “L”, N5 = “H” and N3 = “L”, and the masking circuit 20 has N4 = N4 regardless of the logic of the node N1. It is fixed at “H”, and the node N6 becomes an inverted signal of the logic of the input terminal 11 and can be written to the latch circuit 30. At this time, even when N6 = “H”, N8 = “L” → “L”, but when N6 = “L”, N8 = “L” → “H”.
(2-2) When N7 = “L” and N8 = “H”, N5 = “L” and N3 = “H”, and the masking circuit 20 has N6 = It is fixed at “H”, and the node N 4 becomes an inverted signal of the logic of the input terminal 11 and can be written to the latch circuit 30. At this time, even if N4 = “H”, N7 = “L” → “L”, but when N4 = “L”, N7 = “L” → “H”.
(2-3) As a result, an operation of writing the signal of the input terminal 11 that generates a signal to the nodes N1 and N2 to the latch circuit 30 is performed.

  Thus, as shown in FIG. 8, nodes N7 and N8 have a signal with a pulse width Ta whose pulse width of the input signal inputted to the input terminal 11 is longer than the delay time T0 of the delay elements DL1 and DL2, respectively. A signal having a pulse width Tb shorter than the delay time T0 is output after being extended to the delay time T0.

<Second embodiment>
FIG. 3 shows a glitch processing circuit 100A of the second embodiment. Here, the NAND circuits NAND1 to NAND4 of the glitch processing circuit 100 in FIG. 2 are replaced with NOR circuits NOR1 to NOR4 to form a masking circuit 20A and a latch circuit 30A. The overall operation is the same as that described in FIG.

<Third embodiment>
FIG. 4 shows a third embodiment in which the impedance conversion circuit 50 is connected to the node N8 of the glitch processing circuit 100 of FIG. 2 to extract the output signal. The impedance conversion circuit 50 includes an inverter INV3 and a NAND circuit NAND5 that is the same as the NAND circuits NAND1 to NAND4 of the masking circuit 20 and the latch circuit 30. With this, the propagation delays of rising and falling can be made close to each other. it can. In addition, a large capacity load can be driven.
<Fourth embodiment>

FIG. 5 shows a fourth embodiment in which an impedance conversion circuit 50A is connected to the node N8 of the glitch processing circuit 100A of FIG. 3 to extract an output signal. The impedance conversion circuit 50A is composed of the inverter INV4 and the same NOR circuit NOR5 as the NOR circuits NOR1 to NOR4 of the masking circuit 20A and the latch circuit 30A, thereby making it possible to make the propagation delays of rising and falling close to the same. it can. In addition, a large capacity load can be driven.
<Fifth embodiment>

FIG. 6 shows a sixth embodiment in which the load capacitance generation circuit 60 is connected to the node N7 of the glitch processing circuit 100 of FIG. 4 to balance the load capacitances of the nodes N7 and N8. The load capacity generation circuit 60 is composed of a NAND circuit NAND6.
<Sixth embodiment>

  FIG. 7 shows a seventh embodiment in which the load capacitance generation circuit 60A is connected to the node N7 of the glitch processing circuit 100A of FIG. 5 to balance the load capacitances of the nodes N7 and N8. The load capacity generation circuit 60A is configured by a NOR circuit NOR6.

100, 100A: Gritch processing circuit 200: Pre-driver circuit 10: Single phase / differential conversion circuit 20, 20A: Masking circuit 30, 30A: Latch circuit 40: Delay circuit 50, 50A: Impedance conversion circuit 60, 60A: Load capacity Generator circuit

Claims (5)

A single-phase / differential conversion circuit for outputting an inverted signal of the input signal to the first node and outputting a non-inverted signal of the input signal to the second node;
The signal of the first node is masked with the signal of the third node and output to the fourth node, and the signal of the second node is masked with the signal of the fifth node and output to the sixth node. Masking circuit to
A latch circuit comprising an SRFF that changes the signal of the seventh node and the signal of the eighth node by the change of the signal of the fourth node or the change of the signal of the sixth node;
A delay circuit that delays the signal of the seventh node by a first time and outputs the delayed signal to the fifth node, and delays the eighth node signal by the first time and outputs the delayed signal to the third node. And
A glitch processing circuit characterized in that the signal of the eighth node or the seventh node is used as an output signal. The glitch processing circuit according to claim 1,
The glitch processing circuit according to claim 1, wherein the first time of the delay circuit is equal to or longer than a mask time for preventing a through current of a subsequent circuit to which the output signal is input. In the glitch processing circuit according to claim 1 or 2,
The masking circuit sets the signal of the sixth node to the second logic regardless of the signal of the second node when the signal of the fifth node is the first logic, and sets the signal of the third node. A glitch processing circuit characterized in that when the signal is the first logic, the signal of the fourth node is set to the second logic regardless of the signal of the first node. In the glitch processing circuit according to claim 1, 2, or 3,
The latch circuit sets the seventh node to the second logic and the eighth node to the first logic when the fourth node changes from the second logic to the first logic, A glitch process characterized in that when the sixth node changes from the second logic to the first logic, the seventh node becomes the first logic and the eighth node becomes the second logic. circuit. In the glitch processing circuit according to claim 1, 2, 3, or 4,
A glitch processing circuit, wherein an impedance conversion circuit is connected to one of the seventh and eighth nodes, and a load capacitance generation circuit equal to the input impedance of the impedance conversion circuit is connected to the other.

Images