JP2012243205A - Semiconductor integrated circuit and data evacuating method - Google Patents

Abstract

A semiconductor integrated circuit capable of saving data via a path in which normality is ensured is provided. A semiconductor integrated circuit according to the present invention includes a CPU core and a CPU core. The normal memory 14 that holds the calculation result and the first sample data, the sample data storage memory 24 that holds the second sample data identical to the first sample data, and the first data output from the normal memory 14 A data comparison / determination unit 26 that compares the sample data of the first sample data and the second sample data output from the sample data storage memory 24 via a path that does not overlap with the path through which the first sample data is output. The core 12 compares the calculation result when the first sample data and the second sample data match, and the first sample data compares the data. It is intended to retract from the CPU core 12 via the same path as the output route to Joki 26.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit and a data saving method, and more particularly to a semiconductor integrated circuit and a data saving method for determining the normality of a data saving path.

  In recent years, since it is necessary to ensure high safety for semiconductor integrated circuits such as in-vehicle products, the need for improved reliability is increasing. As a result, semiconductor integrated circuits equipped with a self-diagnosis function have become widespread. Functional safety standard IEC 61508 (functional safety of electrical / electronic / programmable electronic safety-related systems) was issued in 2000, and Europe obligates the acquisition of ECU-level functional safety certification installed in automobiles. Therefore, the MCU (Micro Control Unit) is required to support IEC61508 SIL3, and the reliability of the system is required to be improved by adopting a redundant CPU (Central Processing Unit) and adopting a self-diagnosis function.

  The following methods are widely used as self-diagnosis methods for satisfying the above standards. In a semiconductor integrated circuit equipped with two CPUs, one CPU is a master CPU and the other CPU is a check CPU. In such a semiconductor integrated circuit, two operation results are compared to diagnose the presence or absence of a failure in the semiconductor integrated circuit.

  In a semiconductor integrated circuit equipped with the above self-diagnosis method, if a mismatch occurs in the calculation results of each CPU due to an external factor that is not a physical failure, for example, an error caused by the influence of noise or cosmic rays, the semiconductor It has been considered that the integrated circuit uses a fault life extension means that is reset and restarts the operation immediately before the occurrence of the error.

  A semiconductor integrated circuit such as an in-vehicle product may be restarted by self-diagnosis during operation of an automobile equipped with the semiconductor integrated circuit. In this case, it is necessary to shorten the time from the reset during operation to the restart of the operation of the semiconductor integrated circuit. Therefore, after a mismatch occurs in the calculation results of the respective CPUs, the CPU saves the data immediately before the mismatch occurs in the nonvolatile memory, and reads and reads the data saved in the nonvolatile memory when the operation is resumed. A method of using data for setting an operating state is being studied. In order to save the data to the nonvolatile memory after the mismatch of the CPU operation results, it is necessary to determine that there is no failure in the portion related to the data saving of the semiconductor integrated circuit. Furthermore, there is a need for a technology that can reliably execute failure life extension means in two CPUs.

  A configuration of a semiconductor integrated circuit in which failure life extending means is used will be described using Patent Document 1. Specifically, the configuration of the semiconductor integrated circuit disclosed in Patent Document 1 will be described with reference to FIGS.

  The semiconductor integrated circuit outputs data from the CPU 110 to the main memory 170 via the data buses 190, 210 and 230, and outputs data from the CPU 120 to the main memory 180 via the data buses 200, 220 and 240.

  In normal processing, data output from the CPU 110 to the main memory 170 passes through the data buses 190, 210, and 230. Data output from the CPU 120 to the main memory 180 passes through the data buses 200, 220, and 240. In normal processing, these routes are standard. Each time the CPUs 110 and 120 output data to the data bus, they save the data in the save registers 130 and 140 built in the CPU.

  As shown in processing block 320, comparator 160 stores the data output from CPU 110 to data buses 190 and 210 and the data output from CPU 120 to data buses 200 and 220. The data is output to 250 and 260 and the data is compared.

  If the data output from the CPU 110 and the CPU 120 are equal as a result of the comparison in the comparator 160, the processing continues as shown in the processing block 325. If the data output from the CPU 110 and the CPU 120 do not match as a result of the comparison in the comparator 160, the comparator 160 notifies the CPUs 110 and 120 of the occurrence of the mismatch as shown in a processing block 330. Discrepancy detection signals 270 and 280 are output. As shown in processing block 340, the CPUs 110 and 120 detect the mismatch detection signals 270 and 280, generate an interrupt at the same time, and transfer the processing to the mismatch detection interrupt handler. The mismatch detection interrupt handler disconnects one data bus as shown in process block 350 and outputs the data in the save register 130 of the CPU 110 as shown in process block 360.

  As shown in processing block 370, the comparator 160 compares the value of the save register 250 of the comparator 160 with the value of the save register 130 output from the CPU 110.

  Subsequently, the connected data bus is disconnected, and the disconnected data bus is connected. As shown in a processing block 370, the comparator 160 saves the save register 250 output from the comparator 160 and the CPU 110. The values of the register 130 are compared. As a result of the comparison, when the processing results of the two data buses coincide with each other, the same processing is performed on the other CPU as shown in processing block 380. As a result of the comparison, if both are inconsistent, the CPU is stopped as shown in the processing block 400, and the same processing is performed on the other CPU. As a result of the comparison, if either one does not match, the data bus in which the mismatch is detected is disconnected as shown in processing block 390, and the same processing is performed for the other CPU.

  That is, in the semiconductor integrated circuit disclosed in Patent Document 1, in a system composed of two CPUs, the value of the save register in the comparator and the value of the save register output from the CPU via the data bus are used. By comparing, an error in the data bus is detected, the data bus in which the error has occurred is disconnected, and the processing is continued using the data bus in which no error has occurred.

JP-A-9-274609

  However, in the semiconductor integrated circuit disclosed in Patent Document 1, when an error occurs in the data bus 190 or the data bus 200, the error location is not determined and the processing is continued. Therefore, the data saved from the CPU to the memory via the data bus 190 or the data bus 200 is damaged, and incorrect data is stored in the memory. As a result, there is a problem that after the mismatch occurs, the semiconductor integrated circuit cannot restart the operation immediately before the occurrence of the mismatch using the data stored in the memory, and the life extension of the failure cannot be realized while ensuring the reliability.

  Specifically, in FIG. 7, for example, when there is an error in the data bus 190, the comparator 160 displays the value of the save register 130 from the CPU 110 via the data bus 190 and the data bus 210 and the data from the CPU 110 when an error occurs. The value of the save register 250 storing the value of the save register 130 via the bus 190 and the data bus 210 is compared. However, the comparison results match, and the comparator 160 erroneously determines that there is no error in the data bus 190. The reason is that since the value of the save register 250 is always rewritten, an incorrect value is stored in the save register 250 when an error occurs in the data bus 190, which is the same as the save register 130 via the data bus 190 and the data bus 210. This is because it becomes a value. Although there is an error in the data bus 190, it is erroneously determined that there is no error, and the operation is continued, and data is saved to the main storage device 170 via the failed data bus 190. Incorrect data is stored.

  A semiconductor integrated circuit according to a first aspect of the present invention includes a processor, a first memory that holds a calculation result of the processor, and first sample data, and a second same as the first sample data. A second memory for holding the second sample data, the first sample data output from the first memory, and the second sample via a path that does not overlap with a path from which the first sample data is output. A data comparison / determination unit that compares the second sample data output from the memory of the first processor and the processor when the first sample data matches the second sample data. The result is saved from the first memory via the same path as the path where the first sample data is output to the data comparison / determination unit.

  By using such a semiconductor integrated circuit, the calculation result stored in the first memory is saved via the same path as the path where the first sample data is output. Therefore, when the data comparison / determination unit confirms the normality of the path from which the first sample data is output, the calculation result is also saved through the path where the normality is confirmed. Reliability is improved.

  A data saving method according to a second aspect of the present invention includes a processor, a first memory for holding a calculation result of the processor, and first sample data, and a second same as the first sample data. And a second memory for holding the sample data of the semiconductor integrated circuit, wherein the first sample data output from the first memory and the first sample data are output. Comparing the second sample data output from the second memory via a path that does not overlap with the determined path, and the first sample data and the second sample data match, The calculation result is saved from the first memory through the same path as the path from which the first sample data is output.

  By using such a data saving method, the calculation result stored in the first memory is saved via the same path as the path where the first sample data is output. Therefore, when the normality of the path where the first sample data is output is confirmed based on the comparison result of the first and second sample data, the calculation result is also saved via the path where the normality is confirmed. Therefore, the reliability of the saved calculation result is improved.

  According to the present invention, it is possible to provide a semiconductor integrated circuit and a data saving method capable of saving data via a path in which normality is ensured.

1 is a configuration diagram of a CPU-mounted circuit according to a first embodiment; FIG. 3 is a configuration diagram of a CPU operation determination circuit according to the first exemplary embodiment; 3 is a flowchart of normal operation stop processing according to the first exemplary embodiment; 3 is a flowchart of reset processing of the semiconductor integrated circuit according to the first embodiment; 4 is a flowchart of processing for starting normal operation after reset of the semiconductor integrated circuit according to the first exemplary embodiment; 6 is a flowchart of normal operation stop processing according to the second exemplary embodiment; 1 is a configuration diagram of a semiconductor integrated circuit according to Patent Document 1. FIG. 10 is a flowchart of normality determination processing of a semiconductor integrated circuit according to Patent Document 1.

(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings. First, a configuration example of the CPU-mounted circuit 10 included in the semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to FIG. The CPU mounting circuit 10 includes a CPU core 11, a CPU core 12, an operation result comparison circuit 13, and a normal memory 14. Further, the CPU core 11, the CPU core 12, and the calculation result comparison circuit 13 are each connected to the CPU operation determination circuit 20.

  The CPU core 11 and the CPU core 12 are included in the processor and execute program processing based on a program stored in a RAM (Random Access Memory) or a ROM (Read Only Memory). The CPU core 11 and the CPU core 12 execute the same process and are configured redundantly. Therefore, when no failure or the like occurs in the CPU core 11 and the CPU core 12, the CPU core 11 and the CPU core 12 output the same calculation result. The CPU core 11 and the CPU core 12 output the calculation result to the calculation result comparison circuit 13. Further, the CPU core 12 outputs the calculation result to the normal memory 14.

  The calculation result comparison circuit 13 compares the calculation result output from the CPU core 11 with the calculation result output from the CPU core 12. The operation result comparison circuit 13 determines that the CPU core 11 and the CPU core 12 are operating normally when the respective operation results match. The operation result comparison circuit 13 determines that a failure or error has occurred in either the CPU core 11 or the CPU core 12 when the operation results do not match, and the operation result comparison circuit 13 determines the operation result comparison result. Output to.

  The normal memory 14 receives and stores a calculation result during normal operation of the CPU core 12 from the CPU core 12. The normal operation in the CPU core 12 is, for example, an operation that is executed to realize an in-vehicle function if the semiconductor integrated circuit is in-vehicle. The normal memory 14 outputs the stored calculation result to the CPU core 12 when receiving a notification from the CPU core 12 that the calculation result saving process is to be executed. The CPU core 12 outputs the calculation result received from the normal memory 14 to the CPU operation determination circuit 20. The normal memory 14 may be a memory such as a RAM mounted on the CPU mounted circuit 10 or a storage device such as a hard disk device connected to the outside of the CPU mounted circuit 10.

  The normal memory 14 outputs sample data to the CPU core 12 when the calculation result comparison circuit 13 determines that the calculation results of the CPU core 11 and the CPU core 12 do not match. The sample data is used to determine whether or not a failure has occurred in the save path when saving the calculation result stored in the normal memory 14. When the CPU core 11 and the CPU core 12 start normal operation, the sample data is output from a sample data storage memory 24 described later and stored in the normal memory 14. Alternatively, the sample data may be stored in the normal memory 14 in advance when the CPU-mounted circuit 10 is manufactured.

  Here, the operation modes of the CPU core 11 and the CPU core 12 will be described. The CPU core 11 and the CPU core 12 operate by switching between a normal operation, a failure determination operation, and a save operation. As described above, the normal operation is an operation that is executed in order to realize an in-vehicle function if the semiconductor integrated circuit is in-vehicle, for example. The failure determination operation is an operation for determining whether or not a failure or a failure has occurred in the save path when saving the calculation result stored in the normal memory 14. The save operation is an operation in which the CPU core 12 saves data stored in the normal memory 14 to a nonvolatile memory or the like.

  The CPU core 11 and the CPU core 12 can be switched between a normal operation, a failure determination operation, and a save operation under the control of the CPU operation determination circuit 20.

  Although the configuration example of the circuit in which two CPU cores are mounted has been described with reference to FIG. 1, the CPU mounted circuit 10 may be mounted with three or more CPU cores.

  Next, a configuration example of the CPU operation determination circuit 20 included in the semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to FIG. The CPU operation determination circuit 20 includes a code switching circuit 21, a failure determination code storage memory 22, a data save code storage memory 23, a sample data storage memory 24, an operation control circuit 25, a data comparison determination unit 26, a nonvolatile storage Memory 27. The code switching circuit 21 is connected to the normal code storage memory 30. The normal code storage memory 30 may be provided outside the CPU operation determination circuit 20 as shown in FIG. 2, or may be provided inside the CPU operation determination circuit 20.

  The code switching circuit 21 includes any one of a normal code output from the normal code storage memory 30, a failure determination code output from the failure determination code storage memory 22, and a data save code output from the data save code storage memory 23. Select. The code switching circuit 21 outputs the selected code to the CPU core 11 and the CPU core 12 and controls the operation of the CPU core 11 and the CPU core 12.

  The code switching circuit 21 selects a code to be output to the CPU core 11 or the CPU core 12 according to the comparison result output from the operation result comparison circuit 13 or the comparison result output from the data comparison / determination unit 26. When the code switching circuit 21 receives a signal (hereinafter referred to as an operation comparison result signal) that includes a comparison result indicating that the operation results of the CPU core 11 and the CPU core 12 do not match from the operation result comparison circuit 13, The code is selected, and the operation of the CPU core 11 and the CPU core 12 is switched from the normal operation to the operation determination operation. In addition, when the code switching circuit 21 receives information from the data comparison / determination unit 26 that the failure has not occurred in the save path when saving the operation result stored in the normal memory 14, the data save code And the operation of the CPU core 11 and the CPU core 12 is switched from the operation determination operation to the data saving operation.

  The operation control circuit 25 outputs an interrupt signal to the CPU core 11 and the CPU core 12 and performs control for switching between a normal operation code, a failure determination code, and a data save code. The operation control circuit 25 also performs control to stop the operations of the CPU core 11 and the CPU core 12. The operation control circuit 25 receives an operation comparison result signal indicating that the operation results of the CPU core 11 and the CPU core 12 do not match from the operation result comparison circuit 13, and from the data comparison determination unit 26 to the normal memory 14. An interrupt signal is output to the CPU core 11 and the CPU core 12 when information indicating that a failure has not occurred in the save path when saving the stored calculation result is received.

  The data comparison / determination unit 26 compares the sample data output from the CPU core 12 with the sample data stored in the sample data storage memory 24. The data comparison / determination unit 26 receives the sample data output from the CPU core 12 and the sample data stored in the sample data storage memory 24 via non-overlapping paths.

  When receiving the failure determination code from the code switching circuit 21, the CPU core 12 extracts the sample data stored in the normal memory 14 and outputs it to the data comparison / determination unit 26. The data comparison / determination unit 26 compares the sample data output from the CPU core 12 with the sample data stored in the sample data storage memory 24 and determines whether or not they match. If the data comparison / determination unit 26 determines that the sample data output from the CPU core 12 and the sample data stored in the sample data storage memory 24 match, information indicating that they match is displayed. The included signal (hereinafter referred to as a data comparison result signal) is output to the code switching circuit 21 and the operation control circuit 25. When the data comparison / determination unit 26 determines that the sample data output from the CPU core 12 and the sample data stored in the sample data storage memory 24 do not match, the CPU mounted circuit 10 and the CPU operation The semiconductor integrated circuit including the determination circuit 20 is reset.

  The data comparison / determination unit 26 outputs a data comparison result signal including information indicating coincidence to the code switching circuit 21 and the operation control circuit 25, and then from the normal memory 14 via the CPU core 12 to the CPU. An operation result in the core 12 is received. The calculation result output from the normal memory 14 is output to the data comparison / determination unit 26 via the same path as the path where the sample data stored in the normal memory 14 is output to the data comparison / determination unit 26.

  The calculation result received by the data comparison / determination unit 26 is used to restart the operation immediately before the occurrence of the failure or error after the semiconductor integrated circuit is reset. The data comparison / determination unit 26 outputs the received calculation result to the nonvolatile memory 27. Thereby, the CPU core 12 can save the calculation result stored in the normal memory 14 to the nonvolatile memory 27. The data saved in the nonvolatile memory 27 is not deleted even when the semiconductor integrated circuit is reset.

  Next, the flow of the normal operation stop process according to the first embodiment of the present invention will be described with reference to FIG. First, the CPU core 11 and the CPU core 12 perform a normal operation (S1). The CPU core 11 and the CPU core 12 output respective calculation results to the calculation result comparison circuit 13 during normal operation.

  Next, the calculation result comparison circuit 13 compares the calculation results of the CPU core 11 and the CPU core 12 (S2). When the calculation result comparison circuit 13 determines that the calculation results of the CPU core 11 and the CPU core 12 match, the process returns to step S1, and the CPU core 11 and the CPU core 12 repeat the normal operation. When the calculation result comparison circuit 13 determines that the calculation results of the CPU core 11 and the CPU core 12 do not match, that is, when it is determined that they do not match, the calculation result comparison circuit 13 indicates that the calculation results of the CPU core do not match. A signal including information indicating that it is present (hereinafter referred to as an operation result mismatch signal) is output to the code switching circuit 21 and the operation control circuit 25. When receiving the calculation result mismatch signal, the operation control circuit 25 stops the normal operation of the CPU core 11 and the CPU core 12 (S3).

  Next, a reset process flow of the semiconductor integrated circuit according to the first exemplary embodiment of the present invention will be described with reference to FIG. The reset process of the semiconductor integrated circuit is performed after the normal operation stop process in FIG. First, when the code switching circuit 21 receives the calculation result mismatch signal, the code switching circuit 21 selects a failure determination code and outputs the selected failure determination code to the CPU core 11 and the CPU core 12 (S11). Next, when receiving the failure determination code, the CPU core 12 reads the sample data stored in the normal memory 14 and outputs it to the data comparison / determination unit 26 (S12). Here, for example, when the CPU core 12 receives the failure determination code, the operation confirmation range of the CPU core 12 can be expanded by including a simple calculation in the CPU core 12 in addition to reading the sample data. For example, if the sample data has a value of 16-bit AAAAH, the sample data is multiplied by 2 and 1 is added to check whether the value is 5555H. Thereby, the presence or absence of a failure can also be determined for a multiplier and an adder (not shown) included in the CPU core 12.

  Next, the data comparison / determination unit 26 compares the sample data received from the CPU core 12 with the sample data stored in the sample data storage memory 24 (S13). The data comparison / determination unit 26 outputs a signal including the comparison result (hereinafter referred to as a sample data comparison result signal) to the CPU core 12. When the CPU core 12 receives the sample data comparison result signal whose comparison result does not match, the semiconductor integrated circuit is reset (S16). The reset of the semiconductor integrated circuit may have a function of controlling the reset of the semiconductor integrated circuit by the CPU core 12 and may be performed by the control of the CPU core 12. Alternatively, a reset control circuit may be provided in a circuit or the like different from the CPU core 12, and the semiconductor integrated circuit may be reset under the control of the reset control circuit.

  When the CPU core 12 receives the sample data comparison result signal indicating that the comparison results match, the CPU core 12 reads the save target data stored in the normal memory 14 and outputs it to the data comparison determiner 26. The data comparison / determination unit 26 outputs the received save target data to the nonvolatile memory 27 (S14). As a result, the save target data stored in the normal memory 14 is saved in the nonvolatile memory 27.

  Here, the data to be saved is a calculation result set in the CPU core 11 and the CPU core 12 in order to shorten the time until the operation is restarted after resetting the semiconductor integrated circuit. The CPU core 11 and the CPU core 12 receive the calculation result (save target data) output from the CPU core 12 before the mismatch of the calculation results of the CPU core 11 and the CPU core 12 occurs after the semiconductor integrated circuit is reset. Set.

  Next, the CPU core 11 and the CPU core 12 set the value of the non-volatile memory use flag stored in the registers of the CPU core 11 and the CPU core 12 to 1 (S15). Next, the CPU core 12 or the reset control circuit resets the semiconductor integrated circuit (S16).

  Next, the flow of processing from the reset of the semiconductor integrated circuit according to the first embodiment of the present invention to the start of normal operation will be described with reference to FIG. First, after the semiconductor integrated circuit is reset, the CPU core 11 and the CPU core 12 are activated, and the operations of the CPU core 11 and the CPU core 12 are started (S21).

  Next, the CPU core 12 writes the same sample data as the sample data stored in the sample data storage memory 24 to the normal memory 14 (S22). The CPU core 12 executes normal code when performing normal operation. Here, the CPU core 12 reads the sample data from the sample data storage memory 24 along with the execution of the normal code by defining the reading of the sample data in the first or second order of the normal code. The CPU core 12 stores the read sample data in the normal memory 14. Alternatively, the sample data may be written in advance in the normal memory 14 when the CPU-mounted circuit 10 is manufactured.

  For example, the sample data is data to be saved, that is, data having the same bit width as the calculation result of the CPU core 12. Also, in order to guarantee the setting state of both 0 and 1 in all bits, for example, when the save target data is 16 bits, check the states of 0 and 1 of all bits of data, such as 5555H and AAAAH Use two possible data. As for the address where the sample data is written in the normal memory 14, an address where all bits of the address having the same bit width as the address where the save target data is stored can be confirmed. For example, if the address to which the save target data is written is 16 bits, the sample data is written at addresses 5555H and AAAAH.

  Next, the CPU core 11 and the CPU core 12 confirm the nonvolatile memory use flag (S23). The non-volatile memory use flag indicates whether or not the operation result is saved in the non-volatile memory 27. The nonvolatile memory use flag may be stored in, for example, the respective registers of the CPU core 11 and the CPU core 12. When the value of the nonvolatile memory use flag is 1, the CPU core 11 and the CPU core 12 read the save target data from the nonvolatile memory 27 (S24). As a result, the CPU core 11 and the CPU core 12 set the internal state of the semiconductor integrated circuit to the state immediately before the mismatch between the calculation results of the CPU core 11 and the CPU core 12 before resetting. The CPU core 11 and the CPU core 12 complete the reading of the save target data from the non-volatile memory 27, set the non-volatile memory use flag to 0, and perform normal operation (S25). In step S23, when the value of the nonvolatile memory use flag is 0, the CPU core 11 and the CPU core 12 start normal operation without accessing the nonvolatile memory 27 (S25).

  As described above, by using the semiconductor integrated circuit according to the first embodiment of the present invention, self-diagnosis using the calculation results of the CPU core 11 and the CPU core 12 can be performed. When a mismatch occurs in the calculation results of the CPU core 11 and the CPU core 12, the CPU core 12 is stored in the normal memory 14, and the calculation result before the mismatch occurs is saved in the CPU core 12. Here, by comparing the sample data stored in the normal memory 14 in advance with the sample data stored in the sample data storage memory 24, the path of the data to be saved from the CPU core 12 to the nonvolatile memory 27 is determined. The presence or absence of a failure can be determined. Thereby, when it is determined that there is no failure in the path, the CPU core 12 can save the correct calculation result to the nonvolatile memory 27.

  In addition, after the reset of the semiconductor integrated circuit, the CPU core 11 and the CPU core 12 use the calculation result saved in the nonvolatile memory 27 to perform the operation immediately before the calculation result mismatch between the CPU core 11 and the CPU core 12 occurs. By restarting, it is possible to shorten the time until the normal operation starts.

(Embodiment 2)
Subsequently, the flow of the normal operation stop process according to the second embodiment of the present invention will be described with reference to FIG. Steps S31 and S32 are the same as steps S1 and S2 in FIG. When it is determined in the operation result comparison circuit 13 that the operation comparison results output from the CPU core 11 and the CPU core 12 are inconsistent (S32), the CPU core 12 stores data to be stored in the normal memory 14, that is, Then, it is determined whether or not there is a mismatch in the operation comparison result of the save target data (S33).

  The save target data includes, for example, a calculation result when a program stored in a RAM or a ROM is executed, a storage destination address of the normal memory 14 storing the calculation result, a read enable signal for the normal memory 14, and the normal memory 14 For example, a write enable signal. In addition to the data for restarting the operation after resetting, the setting information optimized according to the user's specific usage method and the temperature and voltage setting information as the usage environment data are also referred to in later analysis and the like. Therefore, it may be saved data.

  Further, the data that is not to be saved is, for example, an interrupt signal for the CPU core 11 and the CPU core 12 or a memory access signal for accessing a memory other than the normal memory 14.

  The CPU core 12 determines whether or not a mismatch has occurred in the comparison result of the save target data based on the calculation comparison result output from the calculation result comparison circuit 13. When the CPU core 12 determines that the comparison results of the save target data match, it is estimated that the save target data is not damaged. Therefore, the operation result comparison circuit 13 outputs an operation result mismatch signal including information that the CPU core operation results do not match to the code switching circuit 21 and the operation control circuit 25. When receiving the calculation result mismatch signal, the operation control circuit 25 stops the normal operation of the CPU core 11 and the CPU core 12 (S34). Thereafter, the CPU core 12 saves the save target data that is not damaged to the nonvolatile memory 27.

  If it is determined by the CPU core 12 that the comparison result of the save target data is inconsistent, the save target data may be damaged, and the semiconductor integrated circuit is reset (S35). . That is, when the save target data that may have been damaged is set in the CPU core 11 and the CPU core 12 after resetting the semiconductor integrated circuit, the CPU core 11 and the CPU core 12 are in a state before the failure occurs. It is not set and normal operation cannot be continued. Therefore, in such a case, the semiconductor integrated circuit is reset without saving the save target data in the nonvolatile memory 27.

  As described above, the reliability of data saved in the nonvolatile memory 27 can be improved by using the normal operation stop process according to the second embodiment of the present invention.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 CPU mounting circuit 11 CPU core 12 CPU core 13 Computation result comparison circuit 14 Normal memory 20 CPU operation determination circuit 21 Code switching circuit 22 Failure determination code storage memory 23 Data saving code storage memory 24 Sample data storage memory 25 Operation control circuit 26 Data Comparison / determination unit 27 Non-volatile memory 30 Normal code storage memory

Claims (11)

A processor;
A first memory for holding the calculation result of the processor and first sample data;
A second memory holding second sample data identical to the first sample data;
The first sample data output from the first memory, and the second sample data output from the second memory via a path that does not overlap the path from which the first sample data is output And a data comparison / determination unit that compares
When the first sample data and the second sample data match, the calculation result is sent to the first sample data via the same route as the route from which the first sample data is output to the data comparison / determination unit. A semiconductor integrated circuit which is saved from the memory of 1. A comparison processor different from the processor;
An operation result comparison unit that compares the operation result in the processor and the operation result in the comparison processor;
The data comparison determination unit
The operation result comparison unit compares the first sample data with the second sample data when it is determined that the operation result in the processor and the operation result in the comparison processor are different. The semiconductor integrated circuit according to claim 1. When the operation result comparison unit determines that the operation result in the processor is different from the operation result in the comparison processor when the processor is operating normally,
The processor is
The semiconductor integrated circuit according to claim 2, wherein the first sample data is output from the first memory to the data comparison / determination unit. An operation control unit for switching the operation of the processor;
The operation controller is
In the operation result comparison unit, when it is determined that the operation result in the processor is different from the operation result in the comparison processor when the processor is operating normally, the processor performing the normal operation is 4. The semiconductor integrated circuit according to claim 3, wherein the operation is switched to a path failure determination operation for outputting the first sample data from the first memory to the data comparison / determination unit. The operation controller is
When the data comparison / determination unit determines that the first sample data and the second sample data match, the processor performing the path failure determination operation sends the calculation result to the first memory. The semiconductor integrated circuit according to claim 4, wherein the operation is switched to a save operation for saving to a save memory.   The semiconductor integrated circuit according to claim 5, wherein the save memory is a nonvolatile memory. A processor; a first memory that holds the calculation result of the processor; and first sample data; and a second memory that holds second sample data that is the same as the first sample data. A method of saving data in a semiconductor integrated circuit,
The first sample data output from the first memory, and the second sample data output from the second memory via a path that does not overlap the path from which the first sample data is output And compare
When the first sample data and the second sample data match, the calculation result is saved from the first memory through the same path as the path from which the first sample data is output. Data saving method. Comparing the operation result in the processor with the operation result in a comparison processor that performs the same processing as the processor,
8. The data saving according to claim 7, wherein the first sample data is compared with the second sample data when it is determined that an operation result in the processor is different from an operation result in the comparison processor. Method. When it is determined that the operation result in the processor and the operation result in the comparison processor are different when the processor is operating normally,
The data saving method according to claim 8, wherein the first sample data is output from the first memory.   When it is determined that the operation result in the processor is different from the operation result in the comparison processor when the processor is operating normally, the processor operating in normal operation is transferred from the first memory. The data saving method according to claim 9, wherein the operation is switched to a path failure determination operation for outputting the first sample data.   When it is determined that the first sample data and the second sample data match, the processor performing the path failure determination operation saves the calculation result from the first memory to the save memory. The data saving method according to claim 10, wherein the data saving method is switched to an operation.

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