JP2012138550A - Thin film transistor and thin film transistor manufacturing method - Google Patents

Abstract

【Task】
A thin film transistor capable of reducing the number of steps of a manufacturing process, having a simple element structure, and capable of suppressing cost.
A thin film transistor of the present invention includes a substrate having a main surface, a light shielding layer arranged in a stacking direction with respect to the main surface of the substrate, and the light blocking layer as viewed from the stacking direction. 111, an organic semiconductor layer 150 provided so as to be included in 111, a source electrode 120 and a drain electrode 130 which are provided so as to be in contact with the organic semiconductor layer 150 and which form channel regions opposite to each other, as viewed from the stacking direction, The gate insulation layer 160 includes the gate insulating layer 160 provided with a groove 165 that does not overlap the source electrode 120 and the drain electrode 130 on the outer periphery of the organic semiconductor layer 150, and the organic semiconductor layer 150 when viewed from the stacking direction. And a gate electrode 140 provided on the layer 160 and in the groove portion 165.
[Selection] Figure 1

Description

  The present invention relates to a thin film transistor using an organic semiconductor material or the like as a semiconductor material and a method for manufacturing the thin film transistor.

  In recent years, a thin film transistor using an organic semiconductor material has attracted attention in place of a thin film transistor made of an inorganic material typified by silicon. Since a thin film transistor made of an organic semiconductor material can be manufactured by a low-temperature process, a plastic substrate or a film can be used, and a flexible, lightweight, and hardly broken element can be formed. The thin film transistor can be formed using a liquid material by a simple method such as a coating method or a printing method, and an element can be formed in a short time. Therefore, there is also a very great merit that the process cost and the forming apparatus cost can be kept very low. In addition, since the organic semiconductor material easily changes its material characteristics by changing its molecular structure, etc., the thin film transistor using the organic semiconductor material includes functions that were difficult to realize with an inorganic material. It can support various functions.

  Such a thin film transistor includes a source electrode and a drain electrode, a channel region made of an organic semiconductor material between these regions, a gate electrode capable of applying an electric field to the channel region, and a gate insulation between the gate electrode and the channel region. Has a membrane. With such a structure, when an electric field is applied to the channel region, a current can flow between the source electrode and the drain electrode. The thin film transistor made of the organic semiconductor material as described above is disclosed in, for example, Japanese Patent Application Laid-Open No. 2009-141203.

The thin film transistor as described above has advantages such as being suitable for reduction in thickness and weight, flexibility, and low material cost, and is expected to be used as a switching element for flexible displays and the like. Yes. By the way, in the thin film transistor, it is necessary to appropriately shield the semiconductor layer in order to suppress the light leakage current. For this purpose, for example, in Patent Document 2 (Japanese Patent Laid-Open No. 2010-123909), an island-shaped convex portion 42a is formed on the interlayer film 42 formed on the semiconductor layer 1a, and a light shielding film is further formed thereon. By forming 25, the semiconductor layer 1a is shielded from light.
JP 2009-141203 A JP 2010-123909 A

  However, in the conventional technique described in Patent Document 2, it is necessary to go through a manufacturing process in which the light shielding film 25 is formed after forming the convex portion 42a in the interlayer film 42, and the number of steps of the manufacturing process is large. There is a problem in that the structure of the element is complicated and thus costs are increased.

The present invention is for solving the above-described problems, and the invention according to claim 1 is a substrate having a main surface and a light-shielding layer disposed in a stacking direction of the substrate with respect to the main surface. A semiconductor layer provided so as to be included in the light shielding layer as viewed from the stacking direction, a source electrode and a drain electrode provided so as to be in contact with the semiconductor layer and facing each other to form a channel region, and the stacked layer A gate insulating layer provided with a groove at a position that does not overlap the source electrode and the drain electrode on the outer periphery of the semiconductor layer when viewed from the direction, and the semiconductor layer including the semiconductor layer when viewed from the stacking direction. And a gate electrode provided in the groove.

  The invention according to claim 2 is the thin film transistor according to claim 1, wherein the semiconductor layer includes any one of an organic semiconductor, an oxide semiconductor, and a silicon semiconductor.

  The invention according to claim 3 is the thin film transistor according to claim 1 or 2, wherein a planarization layer is provided between the light shielding layer and the semiconductor.

  According to a fourth aspect of the present invention, in the thin film transistor according to any one of the first to third aspects, the light shielding layer has an OD value of 1 or more.

  According to a fifth aspect of the present invention, in the thin film transistor according to any one of the first to fourth aspects, the OD value of the gate electrode is 1 or more.

  The invention according to claim 6 is the thin film transistor according to any one of claims 1 to 5, wherein an angle formed by the main surface and the gate insulating layer on which the gate electrode is formed is θ. Then, θ <90 °.

  The invention according to claim 7 is the thin film transistor according to any one of claims 1 to 6, wherein an angle formed by the main surface and the gate insulating layer on which the gate electrode is formed is θ. When the thickness of the gate insulating layer is t, the minimum value of the width L of the groove is defined by L = t × tan (90 ° −θ) × 2.

  According to an eighth aspect of the present invention, there is provided a step of forming a light shielding layer on a base material having a main surface, a step of providing a source electrode and a drain electrode facing each other and forming a channel region, and the light shielding as viewed from the stacking direction. A step of providing a semiconductor layer in contact with the source electrode and the drain electrode so as to be included in the layer, a step of forming a gate insulating layer on the semiconductor layer, and the gate insulating layer as viewed from the stacking direction, A step of providing a groove at a position where the source electrode and the drain electrode do not overlap with the outer periphery of the semiconductor layer; and a gate electrode is formed on the gate insulating layer and in the groove so as to include the semiconductor layer as viewed from the stacking direction. A thin film transistor manufacturing method characterized by comprising the steps of:

  According to the thin film transistor of the present invention, it is possible to reduce the number of steps in the manufacturing process for imparting light shielding properties, and it is possible to suppress the cost because the structure of the element is simple.

It is a figure which shows the thin-film transistor 100 which concerns on embodiment of this invention. It is a figure explaining the appropriate dimension of the groove part 165 in the thin-film transistor 100 which concerns on embodiment of this invention. It is a figure explaining the light-shielding property of the thin-film transistor 100 which concerns on embodiment of this invention. 1 is a schematic view of a thin film transistor 100 according to an embodiment of the present invention applied to a transistor array for active matrix driving. It is a figure which shows the outline of the laminated structure of the transistor array by the thin-film transistor 100 which concerns on embodiment of this invention. It is a figure which shows the circuit structure corresponded to 1 pixel of a display element.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a view showing a thin film transistor 100 according to an embodiment of the present invention. FIG. 1A is a diagram illustrating only a groove portion formed in a conductor portion, a semiconductor portion, and a gate insulating layer of the thin film transistor 100, and FIG. 1B is a cross-sectional view taken along line XX ′ in FIG. It is.

  As the base material 110 used for the thin film transistor 100 according to the embodiment of the present invention, the base material 110 having an arbitrary function can be used according to the use of the thin film transistor element according to the embodiment. Such a substrate 110 may be a rigid substrate 110 having no flexibility, such as a glass substrate 110, or a flexible substrate 110 having flexibility, such as a film made of a plastic resin. It may be. In the present embodiment, any of the rigid base material 110 and the flexible base material 110 is preferably used, but among them, the flexible base material 110 is preferably used. By using the flexible substrate 110, the organic semiconductor layer of the present embodiment can be manufactured by a Roll to Roll process, so that the thin film transistor element of the present embodiment can be made more productive. It is.

  Here, examples of the plastic resin used for the flexible base material include PET, PEN, PES, PI, PEEK, PC, PPS, and PEI.

  Moreover, the base material 110 used in the present embodiment may be composed of a single layer, or may have a configuration in which a plurality of layers are laminated. Examples of the substrate 110 having a configuration in which a plurality of layers are stacked include a substrate having a configuration in which a barrier layer made of a metal material is stacked on a substrate made of the plastic resin. Here, the base material 110 made of the plastic resin has an advantage that the thin film transistor element of the present embodiment can be made flexible and flexible, but on the surface when the source electrode 120 and the drain electrode 130 are formed. It has been pointed out that it has the disadvantage of being easily damaged. However, by using the base material 110 on which the barrier layer is laminated, there is an advantage that the above disadvantages can be eliminated even when the base material made of the plastic resin is used.

  The thickness of the substrate 110 used in the present embodiment is usually preferably 1 mm or less, and particularly preferably in the range of 50 μm to 700 μm. Here, when the base material 110 used in the present embodiment has a configuration in which a plurality of layers are stacked, the above thickness means the sum of the thicknesses of the respective layers.

  Next, the light shielding layer 111 is provided on one main surface of the base material 110 as described above in the stacking direction with respect to the main surface. Such a light shielding layer 111 shields light that passes through the base 110 and enters the organic semiconductor layer 150.

  As a material for forming such a light shielding layer 111, a resin or a laminate of a metal and an oxide can be used. As the resin, a photosensitive resin containing a black pigment can be used. When forming the light shielding layer 111, the light shielding layer 111 is patterned by exposure and development using such a photosensitive resin. Moreover, as the laminate of the metal and oxide, for example, a laminate of chromium and chromium oxide can be used. Such chromium and chromium oxide films can be formed by photolithography. Further, as the optical characteristics of the light shielding layer 111, it is desirable that the OD value is 1 or more, more preferably, the OD value is 2 or more.

  Next, the planarization layer 112 is formed on the light shielding layer 111 as described above. As a material used for the planarization layer 112, a desired insulating property can be imparted to the planarization layer 112 and is transparent. When the organic semiconductor layer 150 is formed on the planarization layer 112, the organic semiconductor layer 150 There is no particular limitation as long as it does not impair the performance. Examples of such an insulating resin material include acrylic resins, phenol resins, fluorine resins, epoxy resins, cardo resins, vinyl resins, imide resins, and novolac resins.

  When the planarization layer 112 is formed by a printing method, a film made of an insulating resin material is formed on the entire surface of the substrate 110. In the case where the above printing method is used, as a method having a step of forming a film made of an insulating resin material on the entire surface of the substrate 110, any method can be used as long as a film having a uniform thickness and a smooth surface can be formed. It is not particularly limited. Examples of such methods include spin coating, die coating, roll coating, bar coating, dip coating, spray coating, blade coating, and gravure offset printing.

  Further, the thickness of the planarizing layer 112 is preferably within a range of 0.01 μm to 5 μm, particularly preferably within a range of 0.01 μm to 3 μm, and further within a range of 0.01 μm to 1 μm. It is preferable that

  Next, the source electrode 120 and the drain electrode 130 are formed on the upper surface portion of the planarization layer 112. The conductive material used for the source electrode 120 and the drain electrode 130 is not particularly limited as long as an electrode having desired conductivity can be formed. As such a conductive material, for example, a metal material such as Al, Cr, Au, Ag, Ta, Cu, C, Pt, and Ti, a light-shielding conductive organic material such as a carbon paste, or any of these materials (Preferably Al sandwiched between Cr and Ti). The thickness of the source electrode 120 and the drain electrode 130 (the total thickness when a stacked body is employed) is preferably in the range of 10 nm to several tens of μm.

  Next, an organic semiconductor layer 150 made of an organic material provided so as to be included in the light shielding layer 111 as viewed from the stacking direction is formed. In the present specification and claims, the first configuration includes the second configuration when viewed from the stacking direction. When projection is performed in the stacking direction, the projection by the first configuration is the second configuration. The state which includes the projection by a structure is shown.

  Such an organic semiconductor layer 150 is provided in contact with the source electrode 120 and the drain electrode 130, and a region between the source electrode 120 and the drain electrode 130 functions as a channel region.

The organic semiconductor material used for the organic semiconductor layer 150 of the present embodiment is not particularly limited as long as it is a material that can form the organic semiconductor layer 150 having desired semiconductor characteristics depending on the use of the thin film transistor element of the present embodiment. Instead, organic semiconductor materials generally used for organic semiconductor transistors can be used. Examples of such organic semiconductor materials include π-electron conjugated aromatic compounds, chain compounds, organic pigments, and organosilicon compounds. More specifically, low molecular organic semiconductor materials such as pentacene, and polypyrroles such as polypyrrole, poly (N-substituted pyrrole), poly (3-substituted pyrrole), and poly (3,4-disubstituted pyrrole). , Polythiophene, poly (3-substituted thiophene), poly (3,4-disubstituted thiophene), polythiophenes such as polybenzothiophene, polyisothianaphthenes such as polyisothianaphthene, and polychess such as polychenylene vinylene Nylene vinylenes, poly (p-phenylene vinylenes) such as poly (p-phenylene vinylene), polyanilines such as polyaniline and poly (N-substituted aniline), polyacetylenes such as polyacetylene, and polyazulenes such as polydiacetylene and polyazulene High molecular organic semiconductor materials such as Of these, pentacene or polythiophenes can be preferably used in the present embodiment.

  In addition, the thickness of the organic semiconductor layer 150 used in the present embodiment is not particularly limited as long as the organic semiconductor layer 150 having desired semiconductor characteristics can be formed according to the type of the organic semiconductor material. In particular, in this embodiment, the thickness of the organic semiconductor layer 150 formed on the channel region is preferably 1000 nm or less, more preferably in the range of 1 nm to 300 nm, and particularly in the range of 1 nm to 100 nm. It is preferable to be within.

  In the present embodiment, an organic semiconductor is described as an example of the semiconductor material. However, the semiconductor layer used in the thin film transistor according to the present invention may not be a semiconductor layer made of an organic semiconductor material. Examples of printable inorganic semiconductors that can be printed include zinc oxide, oxides containing In, Ga, and Zn having an amorphous structure, microcrystalline Si, and amorphous Si. These inorganic semiconductor materials can also be used.

  Next, on the organic semiconductor layer 150, the gate insulating layer 160 provided with a groove 165 is formed at a position where the source electrode 120 and the drain electrode 130 do not overlap with each other in the outer periphery of the organic semiconductor layer 150 when viewed from the stacking direction. Here, in the present specification and claims, the first configuration and the second configuration are superimposed when viewed from the stacking direction. When projection is performed in the stacking direction, the projection by the first configuration is the second. It overlaps with the projection by the composition.

  As an insulating material used for such a gate insulating layer 160, a desired insulating property can be imparted to the gate insulating layer 160, it is transparent, and when the gate insulating layer 160 is formed over the organic semiconductor layer 150, There is no particular limitation as long as the performance of the organic semiconductor layer 150 is not impaired. Examples of such an insulating resin material include acrylic resins, phenol resins, fluorine resins, epoxy resins, cardo resins, vinyl resins, imide resins, and novolac resins.

  When the groove 165 is formed by a printing method, a film made of an insulating resin material is once formed on the entire surface of the base material, and then a necessary portion of the film is removed and patterned. Become.

  In the case where the printing method is used, as a method having a step of forming a film made of an insulating resin material on the entire surface of the substrate, a method that can form a film having a uniform thickness and a smooth surface is particularly preferable. It is not limited. Examples of such methods include spin coating, die coating, roll coating, bar coating, dip coating, spray coating, blade coating, and gravure offset printing.

  The thickness of the gate insulating layer 160 used in the present embodiment is not particularly limited as long as the desired insulating property can be imparted to the gate insulating layer 160 according to the type of the insulating resin material constituting the gate insulating layer 160 and the like. It is not limited. The thickness of the gate insulating layer 160 formed on the organic semiconductor layer 150 is preferably in the range of 0.01 μm to 5 μm, particularly preferably in the range of 0.01 μm to 3 μm, and more preferably 0.01 μm. It is preferable to be within a range of ˜1 μm.

  Next, the gate electrode 140 is formed on the gate insulating layer 160 in which the groove 165 as described above is formed. Such a gate insulating layer 160 is provided on the gate insulating layer 160 and in the groove portion 165 so as to include the organic semiconductor layer 150 when viewed from the stacking direction.

  The conductive material used for the gate electrode 140 is not particularly limited as long as an electrode having desired conductivity can be formed. As such a conductive material, for example, a metal material such as Al, Cr, Au, Ag, Ta, Cu, C, Pt, and Ti, a light-shielding conductive organic material such as a carbon paste, or any of these materials (Preferably Al sandwiched between Cr and Ti). The thickness of the source electrode 120 and the drain electrode 130 (the total thickness when a stacked body is employed) is preferably in the range of 10 nm to several hundred nm. Moreover, as an optical characteristic, OD value should just be 1 or more, More preferably, OD value should just be 2 or more.

  Here, the gate electrode 140 needs to be provided also on the side wall (wall portion in the same direction as the stacking direction) of the groove portion 165. Also in the side wall portion of the groove portion 165, an OD value of 2 or more is ensured. For this purpose, for example, when Al is used as the conductive material, it is necessary to deposit on the side wall of the groove 165 with a film pressure of several nm or more.

As a preferable film forming method for providing the gate electrode 140 on the side wall of the groove 165 under the above conditions, specifically, sputtering is performed by DC discharge using argon as a sputtering gas and Al as a target electrode. Is preferred. The pressure at the time of film formation is generally less than 1 Pa. However, the higher the pressure, the better the coverage. Further, as a preferable film formation method for providing the gate electrode 140, high-frequency sputtering can be mentioned. In normal RF sputtering, 13.56 MHz is used as the frequency, but by using 60 MHz as the frequency, the ionization degree of the sputtered metal atoms is increased, and the adhesiveness is uniformly applied to a narrow hole having a large aspect ratio. It is possible to form a film well. Therefore, it is suitable for film formation on the side wall portion of the groove portion 165.

In consideration of appropriate film formation on the side wall of the groove 165, film formation by vacuum evaporation is not preferable.
This is because, in vacuum vapor deposition, material atoms fly linearly from the vapor deposition source to the film formation target, so that no film is formed on the shadowed portion of the vapor deposition source, such as the wall of a hole.

  In the thin film transistor 100 having the above configuration, for example, light from a direction such as L is blocked, and generation of a light leakage current in the organic semiconductor layer 150 is suppressed. Further, in configuring the thin film transistor 100 according to the present embodiment as described above, the process of providing the groove 165 in the gate insulating layer 160 as described above can be performed simultaneously with the process conventionally employed. Further, the process for forming the gate electrode 140 is also a conventionally performed process. Therefore, unlike the prior art described in Patent Document 2, the number of steps in the manufacturing process does not increase.

  According to the thin film transistor 100 as described above, it is possible to reduce the number of steps of the manufacturing process for imparting light shielding properties, and it is possible to reduce the cost because the structure of the element is simple.

  In the present embodiment, it is important that a part of the electrode material constituting the gate electrode 140 is appropriately disposed (film formation) also in the groove portion 165, but this is largely due to the size of the groove portion 165. Hereinafter, the dimensional relationship related to the groove 165 will be described. FIG. 2 is a view for explaining appropriate dimensions of the groove 165 in the thin film transistor 100 according to the embodiment of the present invention, and shows a state of a pre-process for providing the gate electrode 140.

  As shown in FIG. 2, the taper angle formed by the plane of the gate insulating layer 160 and the substrate 110 is defined as θ. The thickness of the gate insulating layer 160 is t, and the width of the groove 165 when viewed from the stacking direction is L.

  First, the taper angle θ of the gate insulating layer 160 is preferably less than 90 ° (θ <90 °). This is because, when the taper is inverse, it is difficult to form a film on the side wall portion of the gate insulating layer 160, and there is a possibility that defects such as a reduction in light shielding performance or disconnection may occur.

  The depth of the trench 165 is approximately 0 to several tens of nm shorter than the gate insulating layer 160. This tens of nanometers corresponds to the remaining part when the gate insulating layer 160 is etched. In order to form the groove 165 having such a depth, it is necessary to secure a minimum width of the groove 165 in the groove 165. The minimum value of the width L of the groove 165 can be defined by L = t × tan (90 ° −θ) × 2.

  Next, the light shielding property of the thin film transistor 100 according to the embodiment of the present invention will be described in more detail. FIG. 3 is a view for explaining the light shielding property of the thin film transistor 100 according to the embodiment of the present invention. FIG. 1A is a diagram illustrating only a groove portion formed in a conductor portion, a semiconductor portion, and a gate insulating layer of the thin film transistor 100, and FIG. 1B is a cross-sectional view of YY ′ in FIG. It is.

  In the thin film transistor 100 according to the present embodiment, the portion where the source electrode 120 and the drain electrode 130 overlap with each other on the outer periphery of the organic semiconductor layer 150 as viewed from the stacking direction, from the portion where the groove portion 165 is not provided, is illustrated in FIG. There is a possibility that light L as shown enters and reaches the organic semiconductor layer 150. However, for such incident light L from the vicinity of the source electrode 120 and the drain electrode 130, it is possible to attenuate the incident light L by setting the distance A from the channel large.

  In the thin film transistor 100 according to this embodiment, A needs a certain distance, but the distance shown in B of FIG. 3 can be reduced, so that the thin film transistor element can be reduced. This is because if there is no groove 165, B will be as large as A and the size of the transistor will increase.

  Next, a configuration in which the thin film transistor 100 according to the present invention as described above is applied to a transistor array for driving a display element will be described. FIG. 4 is a schematic view in which the thin film transistor 100 according to the embodiment of the present invention is applied to a transistor array for active matrix driving. FIG. 5 is a diagram showing an outline of a stacked structure of a transistor array by the thin film transistor 100 according to the embodiment of the present invention. FIG. 6 is a diagram illustrating a circuit configuration corresponding to one pixel of the display element, FIG. 6A is a diagram in the case where no common line is provided, and FIG. 6B is a common line. It is a figure when is provided.

The thin film transistor 100 according to the present invention has advantages such as being suitable for reduction in thickness and weight, flexibility, and low material cost, and can be expected to be used as a switching element for a flexible display or the like. . As an example of a transistor array for driving such a flexible display by an active matrix system, the transistor array shown in FIG. 4 can be given. Here, FIG. 4 is a diagram showing a conductive portion and a semiconductor portion extracted from the transistor array, and the configuration within the dotted circle in FIG. 4 is the thin film transistor 100 described so far. In order to control, it is formed at a lattice point composed of a plurality of scan lines and a plurality of data lines. In the thin film transistor 100 at each lattice point, the gate electrode 140 is electrically connected to the scan line, and the source electrode 120 is electrically connected to the data line. The drain electrode 140 is electrically connected to the pixel electrode 190. 5 is provided with an interlayer insulating layer 170 in addition to the structure described in FIGS. 1 and 3, and the pixel electrode 190 and the drain electrode 130 are electrically connected to each other through the interlayer insulating layer 170 and the gate insulating layer 160. The via hole conducting portion 180 is provided.

  For example, when a liquid crystal display is configured by a transistor array using the thin film transistor 100 according to the embodiment of the present invention, a configuration in which liquid crystal is sandwiched between a substrate on which a transistor array is formed and a substrate on which a transparent counter electrode is formed is shown in FIG. As in A), the storage capacitor is composed of the pixel electrode 190, the transparent counter electrode, and the liquid crystal therebetween.

  On the other hand, when the size of the storage capacitor is not sufficient, as shown in FIG. 6B, common lines composed of the same layers as the scan lines are arranged in parallel between the scan lines, A storage capacitor is formed by overlapping the source and drain electrodes that are not connected to the data line of the transistor. The common lines as described above are all short-circuited at the periphery of the display and further short-circuited with the transparent counter electrode. Usually, the storage capacitor formed by the pixel electrode 190 and the counter electrode is often insufficient, and thus the configuration shown in FIG. 6B is often employed.

  The above transistor array can also enjoy the same operations and effects as the thin film transistor 100 described so far.

  As described above, according to the thin film transistor of the present invention, it is possible to reduce the number of steps of the manufacturing process for providing light shielding properties, and it is possible to reduce the cost because the structure of the element is simple.

Hereinafter, the present invention will be specifically described with reference to examples.
1. Example 1
In Example 1, a thin film transistor element including an organic semiconductor transistor having a top gate structure was manufactured.
(1) Formation of light shielding layer 111 First, a black matrix made of a photosensitive resin was applied to a glass substrate of 150 mm × 150 mm × 0.7 mm by a spin coat method. After pre-baking, patterning was performed in an island shape by an ordinary photolithography method. The thickness was 2 um, the dimension was 60 um □, and the OD value was about 3.
(2) Formation of the planarization layer 112 A cardo resin solution (solid content concentration: 20 wt%) was spin-coated on the substrate. The spin coating at this time was held at 800 rpm for 10 seconds. Thereafter, the substrate was dried at 120 ° C. for 2 minutes and then exposed on the entire surface at 350 mJ / cm 2. It was dried in an oven at 120 ° C. for 30 minutes. The thickness of the planarizing layer was 1 μm.
(3) Formation of the source electrode 120 and the drain electrode 130 A gold film was formed by vacuum vapor deposition, and patterned into a source electrode / drain electrode shape by an ordinary photolithography method. When the formed source electrode and drain electrode were observed with a reflection optical microscope, the distance between the source electrode and the drain electrode (channel length) was 5 μm.
(4) Formation of the organic semiconductor layer 150 By applying a coating solution obtained by dissolving an organic semiconductor material (polythiophene) in a trichlorobenzene solvent at a solid content concentration of 0.2 wt% by an inkjet method between the source and drain electrodes. A pattern was applied between the source electrode and the drain electrode (channel forming portion) and the periphery thereof. The application direction by the ink jet method was set to be perpendicular to the source and drain electrodes. Thereafter, an organic semiconductor layer was formed by drying at 200 ° C. for 10 minutes on a hot plate under an N ₂ atmosphere. The film thickness of the formed organic semiconductor layer was 0.1 μm. The semiconductor was 10 um inside from the edge of the black matrix. (5) Formation of Gate Insulating Layer 160 A cardo resin solution (solid content concentration: 20 wt%) was spin-coated on the substrate. The spin coating at this time was held at 800 rpm for 10 seconds. Thereafter, the substrate was dried at 100 ° C. for 2 minutes and subjected to pattern exposure at 350 mJ / cm ² . Next, the resist development of the exposed part was performed, and then it was dried in an oven at 100 ° C. for 30 minutes. The gate insulating layer was formed on the organic semiconductor layer (channel forming portion) and on the source / drain electrodes. The formed gate insulating layer had a thickness of 1 μm. The distance between the edge part of the organic semiconductor layer and the groove part 165 of the gate insulating layer was 5 μm, and the distance between the source / drain electrode and the groove part was 5 μm.
(6) Formation of gate electrode 140 Aluminum was formed into a film by sputtering, and was patterned by a normal photolithography method. The inner edge of the groove 165 of the gate insulating layer was inside 5 μm of the edge of the gate electrode. (5) Evaluation As a result of measuring the transistor characteristics of the thin film transistor element having the organic semiconductor layer produced, it was confirmed that it was driven as a transistor. I understood. At this time, the ON current of the organic semiconductor transistor was 1 × 10 ⁻⁵ A or more, and the OFF current was 2 × 10 ⁻¹³ A or less. Further, no deterioration of characteristics such as threshold fluctuation was observed even when the fluorescent lamp was irradiated.

Comparative example

(1) Manufacturing Method Example 1 except that a gate insulating layer having no groove 165 is provided instead of the gate insulating layer having the groove 165. Same as. That is, the entire surface of the gate insulating layer was exposed without pattern exposure.
(2) Although the initial evaluation characteristics were almost the same, threshold fluctuations occurred due to fluorescent lamp irradiation.

DESCRIPTION OF SYMBOLS 100 ... Thin-film transistor 110 ... Base material 111 ... Light shielding layer 112 ... Planarization layer 120 ... Source electrode 130 ... Drain electrode 140 ... Gate electrode 150 ... Organic-semiconductor layer 160 ... Gate insulating layer 165 ... groove 170 ... interlayer insulating layer 180 ... via hole conduction part 190 ... pixel electrode

Claims (8)

A substrate having a main surface;
A light shielding layer disposed in a laminating direction with respect to the main surface of the substrate;
A semiconductor layer provided so as to be included in the light shielding layer as viewed from the stacking direction;
A source electrode and a drain electrode provided in contact with the semiconductor layer and facing each other to form a channel region;
A gate insulating layer provided with a groove in a position not overlapping with the source electrode and the drain electrode on the outer periphery of the semiconductor layer as viewed from the stacking direction;
A thin film transistor comprising: a gate electrode provided on the gate insulating layer and in the groove so as to include the semiconductor layer as viewed from the stacking direction. The thin film transistor according to claim 1, wherein the semiconductor layer includes any one of an organic semiconductor, an oxide semiconductor, and a silicon semiconductor. The thin film transistor according to claim 1, wherein a planarization layer is provided between the light shielding layer and the semiconductor. 4. The thin film transistor according to claim 1, wherein an OD value of the light shielding layer is 1 or more. 5. 5. The thin film transistor according to claim 1, wherein an OD value of the gate electrode is 1 or more. 6. The structure according to claim 1, wherein θ <90 °, where θ is an angle formed by the main surface and the gate insulating layer on which the gate electrode is formed. Thin film transistor. When the angle formed by the main surface and the gate insulating layer on which the gate electrode is formed is θ and the thickness of the gate insulating layer is t, the minimum value of the width L of the groove is L = t × tan ( The thin film transistor according to claim 1, which is defined by 90 ° −θ) × 2. Forming a light shielding layer on a substrate having a main surface;
Providing a source electrode and a drain electrode that face each other and form a channel region;
Providing a semiconductor layer in contact with the source electrode and the drain electrode so as to be included in the light shielding layer as viewed from the stacking direction;
Forming a gate insulating layer on the semiconductor layer;
Providing the gate insulating layer with a groove at a position that does not overlap the source electrode and the drain electrode on the outer periphery of the semiconductor layer when viewed from the stacking direction;
Forming a gate electrode on the gate insulating layer and in the groove so as to include the semiconductor layer when viewed from the stacking direction.

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