JP2012119559A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power MOS transistor which reduces contact resistances of a miniaturized N+ type source layer and a source electrode.SOLUTION: A P-type body layer 6 is formed on a surface of an N-type drift layer 2, and an N+type source layer 7 is formed on a surface of the P-type body layer 6. A first contact hole 9 is formed on an interlayer insulating film 8 covering the N+type source layer 7, and a part of the N+type source layer 7 is exposed. A second contact hole 10 is formed from a surface of the N+type source layer 7 exposed to a bottom surface of the first contact hole 9 to the P-type body layer 6. A P+type contact layer 11 is formed on the surface of the P-type body layer 6 exposed to a bottom surface of the second contact hole 10. An N+type layer 7a having a smaller width than the variation width of a mask alignment accuracy in a photolithography process, is formed on the bottom surface of the first contact hole 9 and the first and second holes 9, 10 are filled with a tungsten layer 12 and so on.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a power MOS transistor with reduced on-resistance and a manufacturing method thereof.

  Power MOS transistors, together with IGBTs, have excellent switching characteristics compared to bipolar power transistors and are stable and easy to use. Therefore, they are widely used in switching power supplies such as DC-DC converters, inverter circuits for lighting equipment, and inverter circuits for motors. in use.

  As an important characteristic of the power MOS transistor, there is an on-resistance. Regarding the reduction of the on-resistance, a number of prior arts have been disclosed as important problems in the trend of reducing power consumption. The magnitude of the on-resistance is mainly determined by the impurity concentration of the high-resistance drain-side drift layer, and then determined by the resistance of the channel layer formed of the inversion layer when a voltage is applied to the gate.

  In the vertical power MOS transistor, the on-current passes through the channel layer formed on the surface of the P-type body layer from the N + -type source layer, passes through the N-type drift layer having a low impurity concentration, and forms N + on the bottom surface of the semiconductor substrate. It flows to the mold drain layer. The following Patent Document 1 discloses the content of forming an N + type layer having a high impurity concentration in a part of the N type drift layer serving as a current path and reducing the on-resistance.

  Further, in order to increase the current capacity by widening the gate width, it is a common practice to reduce the on-resistance by arranging the gate electrodes in a miniaturized stripe shape or further in a lattice shape. As miniaturization progresses, mask alignment work in the photolithography process becomes difficult. In order to cope with such a problem, a self-alignment technique for forming a pattern without performing mask alignment work has been introduced.

  A part of the gate electrode is exposed on the semiconductor substrate, arsenic (As) or the like is ion-implanted using the exposed gate electrode as a mask, and an N + type source layer is formed by self-alignment. Further, Patent Document 2 discloses a content such as forming a P + type contact layer connected to a P type body layer by self-alignment using a side wall of a silicon oxide film formed on the side wall of the gate electrode.

  Further, a sidewall made of polysilicon doped with arsenic (As) or the like is formed on the sidewall of the insulating film formed by the CVD method covering the gate electrode formed in the trench, and the sidewall is configured. Arsenic (As) or the like is diffused from the polysilicon to be diffused into the P-type body layer, and an N + type source layer is formed by self-alignment.

  Next, the technical content of forming a source electrode connected to both the N + type source layer and the side wall, increasing the contact area between the source electrode and the N + type source layer, and reducing the contact resistance is as follows. 3 is disclosed. With the progress of miniaturization, the contact resistance between the source electrode and the N + type source layer occupying the on-resistance is not negligible.

JP 2007-5398 A JP 2004-11661 A JP 2002-158233 A

  With the progress of miniaturization, it has become difficult to form a P + type contact layer using a photomask in an N + type source layer, regardless of whether the gate electrode has a striped configuration or a lattice configuration. . Therefore, when a contact hole is formed in an interlayer insulating film covering the N + type source layer in order to connect the N + type source layer and the source electrode, the P type body layer is exposed from the N + type source layer exposed in the contact hole. At the same time, contact holes for forming P + type contacts are formed.

  Boron (B) or the like is implanted from the contact hole opened on the semiconductor substrate by a predetermined ion implantation method, and a P + type contact layer is formed on the P type body layer exposed at the bottom of the contact hole for P + type contact formation by self-alignment. Form.

  In this case, the source electrode is connected to a P + type contact layer formed in the P type body layer, and is connected to an N + type source layer exposed on the side wall of the contact hole for forming the P + type contact. When the depth in the P-type body layer of the N + type source layer is deep, the source electrode can secure a desired contact area with the N + type source layer, but as the miniaturization progresses, the depth of the N + type source layer becomes shallow. In some cases, the source electrode may not have a sufficient contact area with the N + type source layer. On-resistance increases accordingly.

  Under such circumstances, as the upper limit of the on-resistance standard becomes stricter, the problem is how to expand the contact area between the source electrode and the N + type source layer.

A semiconductor device of the present invention includes a first conductivity type drift layer formed on a semiconductor substrate, a trench formed extending from the surface of the drift layer to the inside, and a gate insulating film in the trench. Formed from the surface of the drift layer to a position shallower than the depth of the trench, and the first conductivity formed on the surface of the body layer. A source layer of a mold, a first contact opening formed in an interlayer insulating film deposited on the source layer, and from the surface of the source layer exposed at the bottom surface of the first contact opening to the inside of the body layer A second contact opening formed continuously with the first contact opening, a second conductivity type contact layer formed in the body layer exposed in the second contact opening, and the second contact opening Co Characterized by comprising a said source layer exposed to the bottom surface of the sandwiched first contact opening between the lower end of the upper end of the tact opening the first contact opening.
A method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductivity type drift layer on a semiconductor substrate, a step of forming a plurality of trenches extending from the surface of the drift layer, and Forming a gate electrode through a gate insulating film, forming a second conductivity type body layer on the surface of the drift layer, and forming a first conductivity type source layer on the surface of the body layer. A step of forming a first contact opening in an interlayer insulating film deposited on the source layer, and from the surface of the source layer exposed at the bottom surface of the first contact opening to the inside of the body layer, Forming a second contact opening continuously extending with the first contact opening; and forming a second conductivity type contact layer on the surface of the body layer exposed in the second contact opening. And forming a bottom surface of the first contact opening sandwiched between an upper end of the second contact opening and a lower end of the first contact opening by light etching the interlayer insulating film after forming the contact layer. And a step of exposing the source layer.

  According to the semiconductor device and the manufacturing method thereof of the present invention, a power MOS transistor in which the contact resistance between the miniaturized N + type source layer and the source electrode is reduced can be realized.

It is the top view and sectional drawing which show the semiconductor device in the 1st Embodiment of this invention, and its manufacturing method. It is sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention. 5 is a graph showing a relationship between a difference in pretreatment methods before forming a source electrode and on-resistance in the semiconductor device according to the first and second embodiments of the present invention. It is the top view and sectional drawing which show the semiconductor device in the 2nd Embodiment of this invention, and its manufacturing method. It is the top view and sectional drawing which show the comparative example with the 2nd Embodiment of this invention.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to this embodiment will be described below with reference to FIGS. The semiconductor device of the present embodiment is a power MOS transistor having a vertical trench gate. FIG. 1A shows an N + type source layer 7 on a gate electrode 5 formed in a lattice shape, It is a part of top view which shows a mode that the P + type contact layer 11 is surrounded.

  FIG. 1B is a cross-sectional view taken along line AA in FIG. On the N + type semiconductor substrate 1, an N drift type 2 made of an N type epitaxial layer having a predetermined specific resistance and thickness determined in a state where a desired breakdown voltage characteristic and on-resistance are balanced is deposited. A lattice-like trench 3 extending from the surface of the N-type drift layer 2 toward the inside is formed, and a gate electrode 5 is formed inside the trench 3 via a gate insulating film 4.

  A P-type body layer 6 shallower than the depth of the trench 3 is formed on the N-type drift layer 2 formed in each lattice between the lattice-shaped trenches 3 and 3. An N + type source layer 7 is formed on the surface of the P type body layer 6, and an interlayer insulating film 8 is formed on the N + type source layer 7 and the gate electrode 5. A first contact hole 9 is formed in the interlayer insulating film 8.

  A second contact hole 10 extending from the N + type source layer 7 to the inside of the P type body layer 6 is formed in the N + type source layer 7 exposed at the bottom surface of the first contact hole 9. A P + type contact layer 11 is formed on the surface of the P type body layer 6 exposed at the bottom surface of the second contact hole 10. The P + type contact layer 11 has a role of fixing the potential of the P type body layer 6 to the potential of the N + type source layer 7.

  The P + type contact layer 11 is exposed on the bottom surface of the second contact hole 10 and the N + type source layer 7b is exposed on the side wall thereof. The N + type source layer 7a having a width smaller than the variation width of the mask alignment accuracy in the lithography process is exposed. This N + type source layer 7a having a small width is a configuration that is the gist of the present invention.

  On the N + type source layers 7a and 7b and the P + type contact layer 11 exposed in the first contact hole 9 and the second contact hole 10, via a barrier metal made of a titanium film and a titanium nitride film (not shown), A tungsten (W) layer 12 filling the first contact hole 9 and the second contact hole 10 is formed.

  A source electrode 13 made of aluminum (Al) or the like is formed on the tungsten (W) layer 12. A metal electrode made of copper (Cu) or the like is formed on the back surface of the N + type semiconductor substrate 1.

The degree of improvement in the on-resistance R _DS (on) between the drain and source of the power MOS transistor of this embodiment will be described below with reference to FIG. The figure shows the relationship between the on-resistance R _DS (on) and the pretreatment conditions of the N + type semiconductor substrate 1 before the formation of a barrier layer (not shown) such as titanium (Ti). The horizontal axis indicates the time for light etching in dilute hydrofluoric acid solution, that is, the light etching amount of the interlayer insulating film 8, and the vertical axis indicates R _DS (on).

A circle indicates reverse sputtering of the surfaces of the N + type source layers 7a and 7b and the P + type contact layer 11 exposed in the first and second contact holes 9 and 10 after light etching in dilute hydrofluoric acid solution or the like. The relationship between R _DS (on) and the light etching time when the surface silicon layer is removed by about 100 mm is shown. The x mark indicates R _DS (on) when light etching is performed for 30 seconds in dilute hydrofluoric acid solution without reverse sputtering.

R _DS (on) is shown as a relative value when the reverse sputtering is performed only for about 100 mm and the light etching time in dilute hydrofluoric acid solution is 0 sec. When reverse sputtering is performed, R _DS (on) decreases due to an increase in the light etching time in dilute hydrofluoric acid solution or the like. However, even if etching is performed for a certain period of time, the degree of decrease decreases, and R _DS (on) Indicates a tendency to saturate.

On the other hand, in the case of the x mark that is light-etched for 30 seconds in a dilute hydrofluoric acid solution without reverse sputtering, R _DS (on) does not decrease as in the case of reverse sputtering and light etching for 30 seconds. The etching time is higher than that when only reverse sputtering is performed at 0 seconds. From this, it can be recognized that there is another reason for the improvement of R _DS (on) by reverse sputtering and the improvement of R _DS (on) by light etching in dilute hydrofluoric acid solution or the like.
In addition, even if light etching is performed for 30 seconds in the absence of reverse sputtering, R _DS (on) is not reduced as compared to the case of only reverse sputtering, but the reverse is large. If not, it can be estimated that R _DS (on) is a higher value. It was found from the result of the x mark that the degree of decrease in R _DS (on) is low even if light etching is performed in such a state.

  When the light etching time is 0 second only by performing reverse sputtering for about 100 mm, the N + type source layer 7 a portion shown at the bottom of the first contact hole 10 in FIG. 1B is buried under the interlayer insulating film 8. Since it is not exposed, it does not come into contact with tungsten (W) or the like embedded in the first and second contact holes. The portions in contact with tungsten (W) or the like are only the N + type source layer 7b and the P + type contact layer 11 exposed in the second contact hole 10 portion.

Therefore, the reason why R _DS (on) is improved by reverse sputtering is that the contact between the N + type source layer 7b and tungsten (W) or the like is improved, and the contact resistance of the portion can be reduced. The reason why the contact between the N + type source layer 7b and tungsten (W) or the like is improved by reverse sputtering is generated in the N + type source layer 7b or the like by ion implantation when forming the P + type contact layer 11 as described later. This is because the damaged layer is removed by reverse sputtering.

As shown in FIG. 3, contact resistance between tungsten (W) or the like and the N + type source layer 7b can be improved by performing reverse sputtering for about 100 mm, and R _DS (on) can be lowered to 1 as a relative value. Thereafter, as shown in the figure, R _DS (on) decreases with the light etching time because the light etching is newly exposed on the bottom surface of the first contact hole 9 shown in FIG. This is because the contact resistance decreases as the width of the N + type source layer 7a increases and the contact area with the tungsten (W) 12 or the like increases.

Even if the etching time is 30 seconds or more, the degree of decrease in R _DS (on) becomes saturated, but the reason is that R _DS (on) is dominated by the resistance of the N-type drift layer 2 and the like made of high resistance. It is.

R _DS (on) = R + Y. The resistance R is a parallel resistance of the contact resistance R ₀ between the N + type source layer 7 b and tungsten (W) 12 or the like, and the contact resistance r between the N + type source layer 7 a and tungsten (W) layer 12 or the like. The resistance Y is a dominant component of R _DS (on) due to the resistance of the N-type drift layer 2 and the like. Here, the width of the N + -type source layer 7 b is X ₀ , and the width of the N + -type source layer 7 a exposed from the interlayer insulating film 8 is x.

  When there is little progress in miniaturization and it is not necessary to form the P + type contact layer 11 by self-alignment as in this embodiment, the R component can be ignored. For example, as shown in FIG. 5B, since the tungsten layer 12 and the like are in contact with the wide area N + type source layer 7 formed on the stripe, the contact resistance of the portion is small.

The resistance R is expressed by the contact resistance R ₀ and the contact resistance r, from 1 / R = 1 / R ₀ + 1 / r to R = R ₀ / (1 + R ₀ / r). That is, the resistance R increases as the contact resistance r between the tungsten layer 12 and the N + type source layer 7a increases, and decreases as the contact resistance r decreases.

Also, the damage layer at the time of ion implantation is removed by reverse sputtering, and the contact state between the tungsten layer 12 and the N + type source layer 7b is improved, and the contact state similar to the N + type source layer 7a without the damage layer and the tungsten layer 12 and the like Then, A can be expressed as R ₀ = A / X ₀ and r = A / x, where A is a constant. By substituting this into the formula of R and rearranging it, it can be expressed as R = A / (x + X ₀ ).

Therefore, the width x of the N + type source layer 7a exposed on the bottom surface of the interlayer insulating film 8 increases due to the increase in the amount of light etching, but the resistance R decreases accordingly and approaches zero as much as possible. On the contrary, if the width x is reduced as the light etching amount is reduced, the resistance R is increased. If no light etching becomes R ₀ is a contact resistance of the N + -type source layer 7b of the tungsten layer 12 such as the width X _0.

In this embodiment, as shown in FIG. 3, R _DS (on) is greatly improved until the light etching time is about 30 seconds, but even if the light etching time is further increased, as described above, the N-type drift layer Since the resistance component such as 2 becomes dominant, R _DS (on) tends to be saturated. _{X 0} in the present embodiment is about 250 nm, x in light etching 30 seconds was about 20 nm.

In order to reduce R _DS (on), if X ₀ is large, that is, if the depth of the N + source layer 7 is deep, the amount of light etching can be reduced, and if X ₀ is small, that is, the N + source layer 7. If the depth of the film is shallow, the amount of light etching must be increased.

When the second contact hole 10 is formed by self-alignment with the first contact hole 9, the tungsten (W) layer 12 and the like are in contact with the narrow N + type source layer 7b. Therefore, the contact resistance R _{0 of the} portion increases, and R _DS (on) increases accordingly. In addition, the width, shape, and surface state of the N + type source layer 7b vary due to etching variations when forming the first and second contact holes 9, 10, variations during ion implantation, variations in the damage layer, and the like.

As a result, the contact state between the tungsten (W) layer 12 and the N + type source layer 7b portion changes, and the contact resistance of the portion increases. While R _DS (on) with a narrow standard width is required, if the contact resistance of the portion increases, a defect exceeding the upper limit of the standard of R _DS (on) occurs.

The invention of the present embodiment reduces the contact resistance between the tungsten (W) layer 12 and the N + type source layer 7 constituted by the contact between the tungsten (W) layer 12 and the like and the N + type source layer 7b. _This is intended to reduce defects exceeding the upper limit of the _DS (on) standard.

  Next, a method for manufacturing the semiconductor device of this embodiment will be briefly described with reference to the plan view, the cross-sectional view, and the cross-sectional view shown in FIG. First, as shown in FIG. 2A, an N-type epitaxial layer constituting the N-type drift layer 2 is deposited on an N + type semiconductor substrate 1 (not shown) by a predetermined epitaxial method. Next, a plurality of trenches 3 are formed from the surface of the N-type drift layer 2 toward the inside by a predetermined reactive ion etching method (RIE) using an insulating film or the like as a mask.

  Next, a gate insulating film 4 that covers at least the bottom and side walls of the trench 3 is formed by a predetermined method. Next, a polysilicon film covering the entire surface of the N + type semiconductor substrate 1 including the inside of the trench 3 is deposited, doped with phosphorus (P) or the like by ion implantation or the like, and then the polysilicon layer is formed on the entire surface by a predetermined method. Etch back is performed to form the gate electrode 5 embedded in the trench 3. The gate insulating film 4 may be only a silicon thermal oxide film, another insulating film, or a multilayer film thereof.

  Next, from each surface of the N-type drift layer 2 sandwiched between the lattice-like trenches 3, a P-type body layer 6 made of a layer shallower than the depth of the trench 3 is coated with boron (B) or the like by a predetermined method. It is formed by ion implantation. The interface between the gate insulating film 4 formed on the sidewall of the trench 3 and the P-type body layer 6 is a region that becomes a channel layer.

  Next, arsenic (As) or the like is ion-implanted into the surface of the P-type body layer 6 by a predetermined method to form an N + type source layer 7. In the present embodiment, the depth of the N + type source layer 7 in the P type body layer 6 is 250 nm. Next, through a predetermined process, an interlayer insulating film 8 covering the entire surface of the N + type semiconductor substrate 1 (not shown) including the N + type source layer 7 is formed by a predetermined CVD method.

  Next, as shown in FIG. 2B, using the contact hole forming photoresist mask C, the interlayer insulating film 8 is etched by the RIE method to form the first contact hole 9 that becomes the first contact opening. Form. Next, after removing the photoresist mask C, using the interlayer insulating film 8 as a mask, the N + type source layer 7 exposed at the bottom surface of the first contact hole formed in the interlayer insulating film 8 is subjected to a predetermined RIE method. Etching is performed to form a second contact hole 10 serving as a second contact opening extending to the inside of the P-type body layer 6.

  As shown in the figure, the N + type source layer 7b is exposed on the side wall of the second contact hole 10, and a part of the P type body layer 6 is exposed on the bottom surface thereof. On the other hand, there is only a space on the side wall and bottom surface of the first contact hole 9. The first contact hole 9 and the second contact hole 10 are slightly inclined, but this increases the contact area with the tungsten (W) layer 12 and the like, thereby reducing the contact resistance.

  Next, boron (B) or the like is ion-implanted from above the second contact hole 10 by a predetermined method to form a P + type contact layer 11 on the P type body layer 6 exposed on the bottom surface of the second contact hole 10. To do. In this case, boron (B) or the like is also implanted into the N + type source layer 7b, but there is no problem because the N + type source layer 7 is higher in impurity concentration. However, there is a problem that a damaged layer remains at the time of ion implantation.

  Next, as shown in FIG. 1B, the N + type source layer 7b and the like are exposed by exposing the N + type semiconductor substrate 1 on which the P + type contact layer 11 and the like are formed to an etching solution made of a diluted hydrofluoric acid solution and the like. The natural oxide film formed on the surface is removed, and a part of the interlayer insulating film 8 made of BPSG or the like covering the N + type source layer 7 is removed by etching.

  As a result, as shown in the figure, the interlayer insulating film 8 on the N + type source layer 7 is partially removed, and the width of the first contact hole 9 is wider than the variation width of the mask alignment accuracy in the photolithography process. The narrow N + type source layer 7a is exposed. In this embodiment, a width of about 20 nm is exposed by etching for 30 seconds. A feature of the present embodiment is that the N + type source layer 7 having a narrow width associated with the bottom surface of the first contact hole 9 is exposed.

  In addition to the above-described photoresist mask C for forming a contact hole, when a photoresist mask CP for forming a P + type contact layer is used, in addition to the problem of increasing mask alignment work in the photolithography process, the photoresist mask When C is miniaturized, the photoresist mask CP may be displaced from the center of the first contact hole 9 formed by the photoresist mask C in some cases.

  When such mask displacement occurs, a part of the photoresist mask CP is formed over the interlayer insulating film 8 which becomes the side wall of the first contact hole 9. As a result, the area of the N + type source layer 7 exposed in the photoresist mask CP becomes small and development cannot be performed well, or the P type body layer 6 is sufficiently wide on the bottom surface of the second contact hole 10. The problem of being unable to be exposed occurs.

  Next, about 10 nm of the surface layer of the N + type source layer 7b exposed on the side wall of the second contact hole 10 and the P + type contact layer 11 exposed on the bottom surface thereof is removed by reverse sputtering. This is to remove the damage layer remaining in the N + type source layer 7b and the like by the ion implantation of boron (B) or the like when forming the P + type contact layer 11. The surface of the N + type source layer 7a is also reverse sputtered.

  Next, as a barrier metal (not shown), a titanium film and a titanium nitride film are formed on the entire surface of the N + type semiconductor substrate including the N + type source layer 7b and the like by a predetermined sputtering method or the like. Next, a tungsten (W) layer 12 is deposited on the barrier metal layer by a predetermined CVD method, and the first contact hole 9 and the second contact hole 10 are buried. The tungsten (W) layer or the like deposited on unnecessary portions is removed by etching using a predetermined method.

Next, a metal film mainly composed of aluminum (Al) is deposited on the N + type semiconductor substrate 1 on which the tungsten (W) layer 12 and the like are formed by a predetermined sputtering method, and then a predetermined photoetching process is performed. Then, the source electrode 13 is formed. If necessary, multilayer wiring is performed, the uppermost layer is covered with a passivation film (not shown) made of a silicon nitride film, and a back electrode (not shown) is formed on the back surface of the N + type semiconductor substrate 1 by a predetermined method. The semiconductor device of the form is completed.
[Second Embodiment]
This embodiment will be described based on FIG. 4 and compared with FIG. 5 as a comparative example. The same components as those in the first embodiment are indicated by the same reference numerals in principle. FIG. 4A shows a part of a plan view of this embodiment. FIG. 4B is a cross-sectional view taken along line BB in FIG. In the first embodiment, the gate electrode 5 has a lattice configuration, and the N + -type source layer 7 and the like are formed for each lattice, whereas in the present embodiment, the gate electrode 5 and the N + -type source layer 7 are formed. Etc. are different in that they are formed in stripes.

  Accordingly, in the present embodiment, the first contact hole 9 and the second contact hole 10 of the first embodiment become the first contact groove 9a and the second contact groove 10a, respectively. Also in this embodiment, as shown in FIG. 4B, the N + type source layer 7a exposed on the bottom surface of the first contact groove 9a can increase the contact area with the tungsten (W) 12 or the like and reduce the resistance R. In addition, since a separate photoresist mask CP is not required, the effect of ensuring a sufficient P + type contact layer 11 is the same as that of the first embodiment.

  FIG. 5 shows a semiconductor device of a comparative example. FIG. 5A is a part of a plan view of a semiconductor device of a comparative example. FIG. 5B is a cross-sectional view taken along the line CC, which is a region including the P + type contact layer 11 of FIG. FIG. 5C is a cross-sectional view taken along the line DD, which is a region where the P + type contact layer 11 of FIG. 5A does not exist.

  In general, when the N + type source 7 has a stripe structure, as in the comparative example shown in FIGS. 5A and 5B, a photoresist mask C exposing the N + type source layer 7 and an opening from the photoresist mask C are used. A plurality of P + type contact layers 11 are formed in a separated state in the N + type source layer 7 using a photoresist mask CP that exposes the P type body layer 6 in the narrow P + type contact layer 11 formation region.

  In this case, depending on the degree of miniaturization, as shown in FIG. 5B, even when a photoresist mask CP having an opening smaller than the photoresist mask C is used, the second contact formed by the photoresist mask CP. P + type contact layer 11 having a sufficient area can be formed on the bottom surface of groove 10a.

As shown in FIG. 5C, the N + type source layer 7 is exposed in a large area on the bottom surface of the first contact groove 10a in a region where the P + type contact layer 11 does not exist. Therefore, the contact area between the tungsten (W) layer 12 and the N + type source layer 7 becomes large, the contact resistance at that portion is sufficiently low, and the influence on R _DS (on) is negligible.

  Therefore, the greatest feature of the present embodiment over the comparative example is the rationalization of the process by reducing the number of photomasks, which is configured by the contact of the tungsten (W) layer 12 and the like with the rationalization and the N + type source layer 7b. The contact resistance between the tungsten (W) layer 12 and the like and the N + type source layer 7 is reduced.

  That is, the surface state of the N + type source layer 7b is improved by reverse sputtering, and the N + type source layer 7a is exposed by introducing light etching, so that the tungsten (W) layer 12 and the like and the N + type source layer 7 The contact area was enlarged and a good contact state was formed between them.

  In addition, even when the gate electrode 5 and the like have a stripe configuration and miniaturization has progressed, the P + contact layer 11 having a sufficient area can be formed.

  Although the present invention relates to a power MOS transistor, it can also be applied to an IGBT as long as the technical idea is the same.

DESCRIPTION OF SYMBOLS 1 N + type semiconductor substrate 2 N type drift layer 3 Trench 4 Gate insulating film 5 Gate electrode 6 P type body layer 7, 7a, 7b N + type source layer 8 Interlayer insulating film 9 First contact hole 9a First contact groove 10 Second contact hole 10a Second contact groove
11 P + type contact layer 12 Tungsten layer 13 Source electrode

Claims (8)

A first conductivity type drift layer formed on a semiconductor substrate;
A trench formed extending from the surface of the drift layer to the inside;
A gate electrode formed in the trench through a gate insulating film;
A second conductivity type body layer formed extending from the surface of the drift layer to a position shallower than the depth of the trench;
A first conductivity type source layer formed on the surface of the body layer;
A first contact opening formed in an interlayer insulating film deposited on the source layer;
A second contact opening formed continuously with the first contact opening from the surface of the source layer exposed at the bottom surface of the first contact opening to the inside of the body layer;
A contact layer of a second conductivity type formed in the body layer exposed in the second contact opening;
A semiconductor device comprising: the source layer exposed between a top end of the second contact opening and a bottom end of the first contact opening sandwiched between the bottom end of the first contact opening. .   The width of the source layer exposed on the bottom surface of the first contact opening sandwiched between the upper end of the second opening and the lower end of the first opening is larger than the variation width of the mask alignment accuracy in the photolithography process. 2. The semiconductor device according to claim 1, wherein the semiconductor device is small.   The semiconductor device according to claim 1, wherein the trench is formed in a lattice shape.   The semiconductor device according to claim 1, wherein the trench is formed on a stripe. Forming a first conductivity type drift layer on a semiconductor substrate;
Forming a plurality of trenches extending inward from the surface of the drift layer;
Forming a gate electrode in the trench through a gate insulating film;
Forming a second conductivity type body layer on the surface of the drift layer;
Forming a first conductivity type source layer on the surface of the body layer;
Forming a first contact opening in an interlayer insulating film deposited on the source layer;
Forming a second contact opening continuously extending from the surface of the source layer exposed at the bottom surface of the first contact opening to the inside of the body layer;
Forming a second conductivity type contact layer on the surface of the body layer exposed in the second contact opening;
After the contact layer is formed, the interlayer insulating film is light-etched so that the bottom surface of the first contact opening is sandwiched between the upper end of the second contact opening and the lower end of the first contact opening. And a step of exposing the source layer. A method of manufacturing a semiconductor device, comprising:   The width of the source layer exposed on the bottom surface of the first contact opening sandwiched between the upper end of the second contact opening and the lower end of the first contact opening is a variation in mask alignment accuracy in the photolithography process. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the width is smaller than the width.   After the light etching of the interlayer insulating film, the source layer exposed on the side wall of the second contact opening, the contact layer exposed on the bottom surface of the second contact opening, and the respective surface layers are reverse sputtered. 7. The method for manufacturing a semiconductor device according to claim 5, wherein the semiconductor device is manufactured.   The method for manufacturing a semiconductor device according to claim 5, wherein the surface layer is reverse-sputtered with a thickness of 10 nm or more.

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