JP2012118174A - Plasma display device - Google Patents

Abstract

Power consumption of a data electrode driving circuit of a plasma display device is reduced.
A data electrode driving circuit includes a recovery capacitor charged to an intermediate voltage and an output buffer having a high-voltage side switch, a low-voltage side switch, and a recovery switch, and the output voltage is changed from the low-voltage side voltage to the high-voltage side voltage. In the output buffer to be shifted to, the recovery switch is turned on during the first transition period provided in each of the write cycles, and after the transition from the low voltage side voltage to the intermediate voltage, the recovery switch is turned off and the high voltage side switch is turned on to An output buffer that transitions the output voltage from the voltage to the high-voltage side voltage and transitions the output voltage from the high-voltage side voltage to the low-voltage side voltage is provided in each of the write cycles and does not overlap in time with the first transition period The recovery switch is turned on during the period to transition from the high-voltage side voltage to the intermediate voltage, and then the recovery switch is turned off and the pre-pressure side switch is turned on. Transitioning the output voltage to the low voltage-side voltage from the intermediate voltage by.
[Selection] Figure 7

Description

  The present invention relates to a plasma display device which is an image display device using an AC surface discharge type plasma display panel.

  A plasma display panel (hereinafter abbreviated as “panel”) includes a front substrate on which a plurality of display electrode pairs composed of scan electrodes and sustain electrodes long in the row direction are formed, and a back substrate on which a plurality of data electrodes long in the column direction are formed. Are arranged opposite to each other, and discharge cells are formed at respective positions where the display electrode pair and the data electrode cross three-dimensionally. The plasma display device includes a scan electrode drive circuit, a sustain electrode drive circuit, and a data electrode drive circuit, and displays an image by applying a necessary drive voltage waveform to each electrode.

  As a method for driving the panel, a sub-field method, that is, one field period is divided into a plurality of sub-fields, and gradation display is performed by a combination of sub-fields that emit light. Each subfield has an initialization period, an address period, and a sustain period. In the initialization period, an initialization discharge is generated, and an initialization operation for forming wall charges necessary for the subsequent address operation is performed. In the address period, an address pulse is applied to each of the data electrodes in accordance with an image to be displayed, and an address discharge is selectively generated in the discharge cells to form wall charges. In the sustain period, a sustain pulse corresponding to the luminance weight is alternately applied to the scan electrode and the sustain electrode to generate a sustain discharge, and the phosphor layer of the corresponding discharge cell emits light to display an image.

  In recent years, as the screen of the panel is increased and the definition is increased, the power for the writing operation becomes so large that it cannot be ignored, and the power consumption of the data electrode driving circuit greatly increases the power consumption of the entire plasma display device. The issue has arisen.

  Therefore, various methods for reducing the power consumption of the data electrode driving circuit have been proposed. For example, it is noted that the data electrode is a capacitive load when viewed from the drive circuit side, and a plasma in which a power recovery unit is added to a power supply that resonates the load capacitance and the inductor and supplies power to the data electrode drive circuit. A display device is disclosed (for example, see Patent Document 1). However, since the load capacity of the data electrode varies greatly depending on the image data, the power consumption may rather increase depending on the displayed image. In order to improve this point, a plasma display device that controls the output amplitude of the power recovery unit added to the power supply so as to change according to the image data is also disclosed (for example, see Patent Document 2).

JP 2002-278509 A JP 2004-212699 A

  Thus, power consumption can be reduced by adding a power recovery unit to a power source that supplies power to the data electrode driving circuit. However, when the power recovery unit is added to the power source, the voltage supplied to the data electrode driving circuit becomes unstable, the address discharge becomes unstable, and the image display quality is deteriorated.

  The present invention has been made in view of such a problem, and supplies power to a data electrode driving circuit from a power source having a constant voltage to perform stable address discharge and reduce power consumption of the data electrode driving circuit. An object is to provide a plasma display device.

  In order to achieve the above object, the present invention comprises a plasma display panel having a plurality of display electrode pairs and a plurality of data electrodes, and a data electrode driving circuit for applying a write pulse to the data electrodes. A plasma display device that applies a high-voltage side voltage of an address pulse or a low-voltage side voltage of an address pulse to each of the data electrodes at each write cycle, wherein the data electrode drive circuit is lower than the high-voltage side voltage and higher than the low-voltage side voltage. An output buffer having a recovery capacitor charged to a voltage and having a high voltage side switch for outputting a high voltage, a low voltage side switch for outputting a low voltage, and a recovery switch connected to the recovery capacitor is provided for each of the data electrodes. The output buffer that transitions the output voltage from the low voltage to the high voltage In the first transition period provided in each cycle, the recovery switch is turned on to make a transition from the low voltage side voltage to the intermediate voltage, and then the recovery switch is turned off and the high voltage side switch is turned on to output the intermediate voltage to the high voltage side voltage. And an output buffer for transitioning the output voltage from the high-voltage side voltage to the low-voltage side voltage is provided in each of the write cycles and the recovery switch is turned on in the second transition period that does not overlap with the first transition period in time. After the transition from the high-voltage side voltage to the intermediate voltage, the recovery switch is turned off and the pre-pressure side switch is turned on to transition the output voltage from the intermediate voltage to the low-voltage side voltage. With this configuration, it is possible to provide a plasma display device in which power is supplied from a power supply having a constant voltage to the data electrode driving circuit to perform stable address discharge and power consumption of the data electrode driving circuit is reduced.

  In addition, the start time of at least one of the first transition period and the second transition period of the plasma display device of the present invention is set for each of the output buffers, and the output to the data electrode in which only the voltage of the adjacent data electrode transitions. The start time of the buffer is set earlier than the start time of the output buffer for the data electrode where the voltage of the adjacent data electrodes on both sides transitions, and the start of the output buffer for the data electrode where the voltages of the adjacent data electrodes do not transition together The time may be set earlier than the start time of the output buffer for the data electrode in which only the voltage of the adjacent data electrode transitions.

  In addition, the data electrode driving circuit of the plasma display apparatus of the present invention is configured by using a plurality of integrated circuits in which a plurality of output buffers are integrated, and the start time of at least one of the first transition period and the second transition period is set in each integrated circuit. The output buffer for the data electrode in which the voltage of the data electrode on which at least one side of the adjacent electrode is set and the voltage of the data electrode on which at least one side of the adjacent data electrode does not transition is present The start time of an integrated circuit in which an output buffer for a data electrode that is set earlier than the start time of the nonexistent integrated circuit and the voltage of the adjacent data electrodes on both sides does not transition is the same for both the voltages of the adjacent data electrodes Integrated circuit start without output buffer for non-transition data electrodes It may be set earlier than the time.

  According to the present invention, it is possible to provide a plasma display apparatus in which power is supplied from a power supply having a constant voltage to the data electrode driving circuit to perform stable address discharge and power consumption of the data electrode driving circuit is reduced. It becomes.

It is a disassembled perspective view of the panel of the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array figure of the panel of the plasma display apparatus. It is the figure which showed typically the capacity | capacitance between electrodes of the panel of the plasma display apparatus. It is a figure which shows the drive voltage waveform applied to each electrode of the panel of the same plasma display apparatus. It is a circuit block diagram of the plasma display device. It is a circuit diagram of the output buffer of the data electrode drive circuit of the plasma display device. It is a figure which shows an example of the write-in pulse of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a figure explaining the reason which can reduce the electric power of the data electrode drive circuit of the plasma display apparatus. It is a circuit diagram of the data electrode drive circuit of the plasma display device. It is a circuit block diagram of the plasma display apparatus in Embodiment 2 of the present invention. It is a circuit diagram of the data electrode drive circuit of the plasma display device. It is a timing chart which shows operation | movement of the data electrode drive circuit of the plasma display apparatus. It is a figure which shows the other structural example of the output buffer in Embodiment 1 and Embodiment 2 of this invention. It is a figure which shows the other structural example of the output buffer in Embodiment 1 and Embodiment 2 of this invention.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 of the plasma display device in accordance with the first exemplary embodiment of the present invention. On the glass front substrate 11, a plurality of display electrode pairs 14 made up of scanning electrodes 12 and sustaining electrodes 13 are formed. A dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. A phosphor layer 25 that emits red, green, and blue light is provided on the side surface of the partition wall 24 and on the dielectric layer 23.

  The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 cross each other across a minute discharge space, and the outer peripheral portion thereof is sealed with a sealing material such as glass frit. It is worn. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrode pairs 14 and data electrodes 22 intersect. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

FIG. 2 is an electrode array diagram of panel 10 of the plasma display device in accordance with the first exemplary embodiment of the present invention. The panel 10 includes n scan electrodes SC ₁ to SC _n (scan electrode 12 in FIG. 1) and n sustain electrodes SU ₁ to SU _n (in FIG. 1) that are long in the row direction (line direction). sustain electrodes 13) are arranged, the long m data electrodes D _{1 ~} data electrodes D _m in the row direction _(data electrodes 22 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SC _i (i = 1 to n) and sustain electrode SU _i intersects with one data electrode D _j (j = 1 to m). M × n are formed in the discharge space.

There is an interelectrode capacitance between the electrodes arranged in this way. FIG. 3 is a diagram schematically showing the interelectrode capacitance of panel 10 of the plasma display device in accordance with the first exemplary embodiment of the present invention, showing the interelectrode capacitance related to data electrode D ₁ to data electrode D _m. Yes. Each of the portions where the display electrode pair 14 and the data electrode 22 intersect each other has a capacitance Cs. In addition, a capacitance Cc exists between the adjacent data electrodes 22. FIG. 3 shows an intersection of five scan electrodes SC _i−2 to scan electrode SC _{i + 2} and sustain electrode SU _i−2 to sustain electrode SU _{i + 2} and six data electrodes D _j−2 to data electrode D _{j + 3.} , And the capacitance Cc between the six data electrodes D _j−2 to the data electrode D _{j + 3} . However, the display electrode pair composed of the scan electrode SC _i and the sustain electrode SU _i is indicated by one thick horizontal line, and the capacitance between the display electrode pair and the data electrode D _j is indicated by Cs. Since one data electrode D _j crosses _n scan electrodes SC ₁ to scan electrode SC _n and n sustain electrodes SU ₁ to sustain electrode SU _n , it is between data electrode D _j and the entire display electrode pair. Has a capacitance n × Cs. Hereinafter, this capacitance n × Cs is referred to as capacitance Cg.

  Thus, each of the data electrodes has a capacitance Cg between the entire display electrode pair, a capacitance Cc between the data electrode adjacent on the right side, and a capacitance Cc between the data electrode adjacent on the left side. Yes, the total load capacity is the capacity (Cg + 2Cc).

  Next, a method for driving the panel 10 will be described. In this embodiment, the subfield method is used as a method for displaying gradation. The subfield method is a method of performing gradation display by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  FIG. 4 is a diagram showing drive voltage waveforms applied to each electrode of panel 10 of plasma display device 30 in accordance with the first exemplary embodiment of the present invention. FIG. 4 shows drive voltages for two subfields SF1 and SF2. The waveform is shown.

In the initializing period of the subfield SF1, while voltage 0 (V) is applied to the data electrodes _{D 1} ~ data electrodes _{D m} and sustain electrodes SU ₁ ~ sustain electrodes SU _n, gradually rises toward the voltage Vi1 to voltage Vi2 the ramp voltage applied to scan electrodes SC ₁ ~ scan electrodes SC _n. Then, while applying a voltage Ve to the sustain electrodes SU ₁ ~ sustain electrodes SU _n, applies a ramp voltage that gently decreases from voltage Vi3 to the voltage Vi4 to the scan electrodes SC ₁ ~ scan electrodes SC _n. Then, a weak initializing discharge occurs in each discharge cell, and wall charges necessary for the subsequent address operation are formed on each electrode. As the operation of the initializing period, as shown in the initializing period of the subfield SF2, may only apply a ramp voltage that gently decreases to the voltage Vi4 to the scan electrodes SC 1 _~ scan electrodes SC _n .

In the subsequent address period, the shape of the address pulse applied to the data electrode D ₁ to the data electrode D _m is devised to reduce power consumption. The details of the address pulse will be described later. An outline of the write operation in FIG.

A voltage Ve to the sustain electrodes SU ₁ ~ sustain electrodes SU _n, the voltage Vc to the scan electrodes SC ₁ ~ scan electrodes SC _n, respectively applied voltage 0 (V) to the data electrodes _{D 1} ~ data electrodes _{D m.} Then, while applying a scan pulse voltage Va to scan electrodes SC ₁ of the first line in the first write cycle, the data electrode D _k corresponding to the discharge cell that should emit light _(k = 1 to m) of the voltage Vd Apply the write pulse. Then write discharge is generated in the first line of discharge cells and scan pulse and the write pulse is applied simultaneously, the write operation for accumulating wall charges is performed in the scan electrodes SC ₁ and the sustain electrodes SU _1. On the other hand, in the discharge cells to which no address pulse is applied, no address discharge occurs, and the wall voltage after the end of the initialization period is maintained.

Then, while applying a scan pulse of the second line scan electrode SC ₂ to the voltage Va at the second write cycle, an address pulse of voltage Vd is applied to data electrode D _k corresponding to the discharge cell to be emitted. Then write discharge is generated in the second line of discharge cells and scan pulse and the write pulse is applied simultaneously, the write operation for accumulating wall charges is performed in the scan electrodes SC ₂ and sustain electrode SU _2.

Similarly, in the i-th address period, a scan pulse of voltage Va is applied to the scan electrode SC _i of the i-th line, and an address pulse of voltage Vd is applied to the data electrode D _k corresponding to the discharge cell to emit light. . Then, an address discharge occurs in the i-th line discharge cell to which the scan pulse and the address pulse are simultaneously applied, and an address operation for accumulating wall charges in the scan electrode SC _i and the sustain electrode SU _i is performed.

  This address operation is performed up to the discharge cell on the nth line, and an address discharge is selectively generated in the discharge cells to emit light to form wall charges.

In the subsequent sustain period, voltage 0 (V) is applied to the sustain electrodes SU ₁ ~ sustain electrodes SU _n. And sustain pulse voltage Vs is applied to scan electrodes SC ₁ ~ scan electrodes SC _n. Then, a sustain discharge occurs in the discharge cell in which the address discharge has occurred and emits light. Next, the applied voltage 0 (V) to the scan electrodes SC ₁ ~ scan electrodes SC _n, sustain pulse voltage Vs is applied to sustain electrodes SU ₁ ~ sustain electrodes SU _n. Then, in the discharge cell in which the sustain discharge has occurred, the sustain discharge occurs again to emit light. Thereafter, a number of sustain pulses corresponding to the luminance weight are alternately applied to scan electrode SC ₁ -scan electrode SC _n and sustain electrode SU ₁ -sustain electrode SU _n to cause the discharge cells to emit light. Then terminated sustain period performs erasing wall charges by applying a ramp voltage gradually rises toward the voltage Vr to the scan electrodes SC 1 _~ scan electrodes SC _n.

  Also in the subsequent subfield, the discharge cell is caused to emit light by repeating the same operation as the above-described subfield operation except for the number of sustain pulses.

  FIG. 5 is a circuit block diagram of plasma display device 30 according to the first exemplary embodiment of the present invention. The plasma display device 30 includes a panel 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 31 outputs image data in which light emission / non-light emission in each subfield is associated with “1” and “0” of each bit of the digital signal.

Data electrode driving circuit 32 converts the write pulse corresponding to image data output from the image signal processing circuit 31 to each of the data electrodes D _{1 ~} data electrodes D _m, each of the data electrodes D _{1 ~} data electrodes D _m Apply. Specifically, the data electrode drive circuit 32 includes a recovery capacitor charged to an intermediate voltage that is lower than the high-voltage side voltage of the write pulse and higher than the low-voltage side voltage, and includes a high-voltage side switch that outputs the high-voltage side voltage and a low-voltage side An output buffer having a low voltage side switch for outputting a voltage and a recovery switch connected to the recovery capacitor is provided for each of the data electrodes D ₁ to D _m . Then, the high voltage side voltage of the write pulse or the low voltage side voltage of the write pulse is applied to each of the data electrodes D ₁ to D _m for each write cycle of the write period described later.

FIG. 6 is a circuit diagram of the output buffer of the data electrode drive circuit 32 of the plasma display device 30 according to the first exemplary embodiment of the present invention. The output buffer of the data electrode driving circuit 32 includes a recovery capacitor C40, a high voltage side switch QH ₁ to a high voltage side switch QH _m , a low voltage side switch QL ₁ to a low voltage side switch QL _m , and a recovery switch QC ₁ to a recovery switch QC _m . In FIG. 6, each of the recovery switches QC ₁ to QC _m is configured by back-to-back connection of two FETs, but other configurations may be used.

The recovery capacitor C40 has a sufficiently large capacity compared to the interelectrode capacity, and is charged to an intermediate voltage (Vd / 2) lower than the high voltage Vd of the write pulse and higher than the low voltage 0 (V). The intermediate voltage to the data electrode _{D j} by turning on the recovery switch QC _j a (Vd / 2) is applied, voltage 0 (V) is applied to data electrode _{D j} by turning on the low-side switch QL _j Then, the voltage Vd is applied to the data electrode D _j by turning on the high-voltage side switch QH _j .

The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to the respective circuits. Scan electrode driving circuit 33 drives each of scan electrode SC ₁ to scan electrode SC _n based on the timing signal. Sustain electrode driving circuit 34 drives sustain electrodes SU ₁ ~ sustain electrodes SU _n based on the timing signal.

Next, details of the address pulse applied to the data electrodes D ₁ to D _m will be described along with the operation of the data electrode drive circuit 32. In the present embodiment, the first transition period Ta is provided at the beginning of each write cycle, and the voltage applied to the data electrode _Dk is switched from the low voltage 0 (V) of the sustain pulse to the high voltage Vd. Makes a voltage transition during the first transition period Ta. In addition, a second transition period Tb is provided at the end of each write cycle, and this second transition period is used when the voltage applied to the data electrode _Dk is switched from the high-voltage side voltage Vd of the sustain pulse to the low-voltage side voltage 0 (V). The voltage is shifted to Tb.

FIG. 7 is a diagram illustrating an example of an address pulse of the plasma display device 30 according to the first exemplary embodiment of the present invention, and scan electrodes SC _i−1 to 3 for three address periods T _{i−1 to} T _{i + 1 in} the address period. Details of drive voltage waveforms applied to scan electrode SC _{i + 1} , data electrode D _j−2 to data electrode D _{j + 3} are shown. In the following, as shown in FIG. 7, in the write cycle T _i-2 immediately before the write cycle T _i−1, no write pulse is applied to the data electrode D _j−2 to the data electrode D _{j + 3} and the write cycle T _{i−. 1} , an address pulse is applied to the data electrode D _j−2 , the data electrode D _j−1 , the data electrode D _j , and the data electrode D _{j + 2,} and an address pulse is applied to the data electrode D _{j + 1} and the data electrode D _{j + 3} in the address period T _i. It is assumed that the write pulse is applied to the data electrode D _j−1 , the data electrode D _j , and the data electrode D _{j + 3} in the write cycle T _{i + 1} .

First, in the (i-1) th write cycle T _i-1 , a scan pulse of voltage Va is applied to the scan electrode SC _i-1 of the (i-1) th line. Then, at the start time t11 of the first transition period Ta, the recovery switch QC _j-2 , recovery switch QC _j-1 , recovery switch QC _j , recovery switch QC _{j + 2} of the output buffer is turned on, and the data electrode D _j-2 , The voltage of the data electrode D _j−1 , the data electrode D _j , and the data electrode D _{j + 2} is changed from the voltage 0 (V) to the intermediate voltage (Vd / 2).

At time t14, the output buffer recovery switch QC _j-1 is turned off, the high-voltage side switch QH _j-1 is turned on, and the voltage of the data electrode D _j-1 is changed from the intermediate voltage (Vd / 2) to the voltage Vd. Let At time t15, the output buffer recovery switch QC _j-2 and recovery switch QC _j are turned off, the output buffer high-voltage side switch QH _j-2 and high _- voltage side switch QH _j are turned on, and the data electrodes D _j-2 , shifting the voltage of the data electrode _{D j} from the intermediate voltage (Vd / 2) to the voltage Vd. At time t16, the output buffer recovery switch QC _{j + 2} is turned off and the output buffer high-voltage side switch QH _{j + 2} is turned on, so that the voltage of the data electrode D _{j + 2} is changed from the intermediate voltage (Vd / 2) to the voltage Vd.

In this way, when the address pulse of the voltage Vd is applied to the data electrode D _j-2 , the data electrode D _j−1 , the data electrode D _j , and the data electrode D _{j + 2} , the scan pulse and the address pulse are simultaneously applied i In the discharge cells on the -1 line, an address discharge occurs and an address operation is performed. Thereafter, each of the high voltage side switches of the output buffer is turned off.

Next, the voltage of the scan electrode SC _{i-1 in} the (i-1) th line is returned to the voltage Vc. In the second transition period Tb, the voltages of the data electrode D _j-2 , the data electrode D _j−1 , the data electrode D _j , and the data electrode D _{j + 2} are changed from the voltage Vd to the voltage 0 (V). At this time, as shown in FIG. 7, the start time of the second transition period Tb is set independently for each data electrode. Specifically, at the start time t21 of the second transition period Tb1, the recovery switch QC _{j + 2} of the output buffer is turned on to change the voltage of the data electrode D _{j + 2} from the voltage Vd to the intermediate voltage (Vd / 2), and at the time t24. The output buffer recovery switch QC _{j + 2} is turned off and the low-voltage side switch QL _{j + 2} is turned on to change the voltage of the data electrode D _{j + 2} from the intermediate voltage (Vd / 2) to the voltage 0 (V). The recovery switches _{QC j-2} of the output buffer at the start time t22 of the second transition period Tb2, turn on the recovery switch QC _j data electrode _{D j-2,} an intermediate voltage a voltage of the data electrode _{D j} from the voltage Vd (Vd / 2), at time t25, the recovery switch QC _j-2 and recovery switch QC _j of the output buffer are turned off, the low-voltage side switch QL _j-2 and the low _- voltage side switch QL _j are turned on, and the data electrode D _j-2 shifts the voltage of the data electrode _{D j} from the intermediate voltage (Vd / 2) to the voltage 0 (V). Further, at the start time t23 of the second transition period Tb3, the recovery switch QC _j-1 of the output buffer is turned on to change the voltage of the data electrode D _j-1 from the voltage Vd to the intermediate voltage (Vd / 2), and at time t26. The output buffer recovery switch QC _j-1 is turned off and the low-voltage side switch QL _j-1 is turned on to change the voltage of the data electrode D _j-1 from the intermediate voltage (Vd / 2) to the voltage 0 (V).

Thus, the data electrode _{D j-2,} a second transition period Tb2 to the data electrode _{D j} is longer than the second transition period Tb3 to the data electrode _{D j-1,} than the second transition period Tb1 to the data electrode _{D j + 2} Is also set short.

Next, in the i-th write cycle T _i , a scan pulse of voltage Va is applied to the scan electrode SC _i of the i-th line. Then, at the start time t31 of the first transition period Ta, the recovery switch QC _{j + 1} and the recovery switch QC _{j + 3} of the output buffer are turned on, and the voltage of the data electrode D _{j + 1} and the data electrode D _{j + 3} is changed from the voltage 0 (V) to the intermediate voltage ( Transition to Vd / 2). At time t35, the output buffer recovery switch QC _{j + 3} is turned off and the high-voltage side switch QH _{j + 3} is turned on, so that the voltage of the data electrode D _{j + 3} is changed from the intermediate voltage (Vd / 2) to the voltage Vd. At time t36, the recovery switch QC _{j + 1} of the output buffer is turned off and the high voltage side switch QH _{j + 1} is turned on, so that the voltage of the data electrode D _{j + 1} is changed from the intermediate voltage (Vd / 2) to the voltage Vd.

In this way, when an address pulse of voltage Vd is applied to data electrode D _{j + 1} and data electrode D _{j + 3} , an address discharge occurs in the i-th line discharge cell to which a scan pulse and an address pulse are simultaneously applied, and an address operation is performed. Is done. Thereafter, the high-voltage side switch QH _{j + 1} of the output buffer is turned off.

Next, the voltage of the scan electrode SC _{i in} the i-th line is returned to the voltage Vc. Then, at the start time t41 of the second transition period Tb1, the output buffer recovery switch QC _{j + 1} is turned on to change the voltage of the data electrode D _{j + 1} from the voltage Vd to the intermediate voltage (Vd / 2). At time t44, the output buffer recovery is performed. The switch QC _{j + 1} is turned off and the low-voltage side switch QL _{j + 1} is turned on to change the voltage of the data electrode D _{j + 1} from the intermediate voltage (Vd / 2) to the voltage 0 (V).

Next, in the (i + 1) th write cycle T _{i + 1} , a scan pulse of voltage Va is applied to the scan electrode SC _{i + 1} of the (i + 1) th line. Then, at the start time t51 of the first transition period Ta, the recovery switch QC _j-1 and the recovery switch QC _j of the output buffer are turned on, and the voltages of the data electrode D _j-1 and the data electrode D _j are set to the voltage 0 (V). To the intermediate voltage (Vd / 2). At time t55, the recovery switch QC _j-1 and recovery switch QC _j of the output buffer are turned off, the high voltage side switch QH _j-1 and the high voltage side switch QH _j of the output buffer are turned on, and the data electrodes D _j-1 , shifting the voltage of the data electrode _{D j} from the intermediate voltage (Vd / 2) to the voltage Vd. Note that the voltage of the data electrode D _{j + 3} remains at the voltage Vd.

In this way, when the address pulse of the voltage Vd is applied to the data electrode D _j−1 , the data electrode D _j , and the data electrode D _{j + 3} , the address is written in the discharge cell of the (i + 1) th line to which the scan pulse and the address pulse are simultaneously applied. A discharge occurs and an address operation is performed. Thereafter, the high voltage side switch QH _j-1 and the high voltage side switch QH _{j + 3 of} the output buffer are turned off.

Next, the voltage of the scan electrode SC _{i + 1} of the (i + 1) th line is returned to the voltage Vc. In the second transition period Tb, the voltage of the data electrode D _j−1 and the data electrode D _{j + 3} is changed from the voltage Vd to the voltage 0 (V). Also at this time, specifically, at the start time t61 of the second transition period Tb1, the recovery switch QC _j-1 of the output buffer is turned on to change the voltage of the data electrode D _j-1 from the voltage Vd to the intermediate voltage (Vd / 2). At time t64, the output buffer recovery switch QC _j-1 is turned off and the low-voltage side switch QL _j-1 is turned on to change the voltage of the data electrode D _j-1 from the intermediate voltage (Vd / 2) to the voltage 0 ( Transition to V). At the start time t62 of the second transition period Tb2, the output buffer recovery switch QC _{j + 3} is turned on to change the voltage of the data electrode D _{j + 3} from the voltage Vd to the intermediate voltage (Vd / 2). At time t65, the output buffer recovery is performed. The switch QC _{j + 3} is turned off and the low-voltage side switch QL _{j + 3} is turned on to cause the voltage of the data electrode D _{j + 3} to transition from the intermediate voltage (Vd / 2) to the voltage 0 (V).

Again, the second transition period Tb2 for the data electrode D _{j + 3} is set shorter than the second transition period Tb1 for the data electrode D _j−1 .

  As described above, in this embodiment, the output buffer that changes the output voltage from the low-voltage side voltage 0 (V) to the high-voltage side voltage Vd turns on the recovery switch in the first transition period provided in each of the write cycles. After the transition from the low-voltage side voltage 0 (V) to the intermediate voltage Vd / 2, the recovery switch is turned off and the high-voltage side switch is turned on to transition the output voltage from the intermediate voltage Vd / 2 to the high-voltage side voltage Vd. An output buffer for transitioning the output voltage from the high-voltage side voltage Vd to the low-voltage side voltage 0 (V) is provided in each write cycle and the recovery switch is turned on in the second transition period that does not overlap with the first transition period in time. After the transition from the high-voltage side voltage Vd to the intermediate voltage Vd / 2, the recovery switch is turned off and the low-voltage side switch is turned on to transition the output voltage from the intermediate voltage Vd / 2 to the low-voltage side voltage 0 (V). . As a result, power can be supplied from the power supply having a constant voltage Vd to the data electrode drive circuit 32 to perform stable address discharge, and the power consumption of the data electrode drive circuit 32 can be reduced. The reason will be described below.

  First, the first transition period in which the low-voltage side voltage 0 (V) is changed to the high-voltage side voltage Vd and the second transition period in which the high-voltage side voltage Vd is changed to the low-voltage side voltage 0 (V) do not overlap in time. Explain why.

8A to 8C and FIGS. 9A to 9E are diagrams for explaining the reason why the power of the data electrode drive circuit 32 of the plasma display device 30 in the first exemplary embodiment of the present invention can be reduced. _The output buffer for _j and data electrode D _{j + 1} and the current flowing there are shown. Capacitor Cc represents the interelectrode capacitance between data electrode D _j and data electrode D _{j + 1} . The high-pressure side switch QH _j , the high-pressure side switch QH _{j + 1} , the low-pressure side switch QL _j , the low-pressure side switch QL _{j + 1} , the recovery switch QC _j , and the recovery switch QC _{j + 1} are indicated by the symbol “switch”.

Here, to transition from state to the data electrodes D _j no application of address pulse to a state of applying a write pulse shifts from a state in which the data electrode D _{j + 1} are applied to write pulse in a state where no application of address pulse Think about the case. In the initial state in this case, as shown in FIG. 8B, the terminal voltage on the data electrode D _j side of the capacitor Cc is the voltage 0 (V), and the terminal voltage on the data electrode D _{j + 1} side is the positive voltage Vd. .

First, for comparison, it is assumed that the voltage at both ends of the capacitor Cc is simultaneously changed without temporally separating the first transition period and the second transition period. That is, as shown in FIG. 8C, the high-voltage side switch QH _j and the low-voltage side switch QL _{j + 1} are simultaneously turned on, and the current from the power source of the voltage Vd to the high-voltage side switch QH _j , capacitor Cc, low-voltage side switch QL _{j + 1} , and ground potential Ia is supplied to charge the capacitor Cc. Since this time, the voltage across the terminals of the capacitor Cc changes from a voltage (-Vd) to the voltage Vd, the charge supplied from the power supply is Q = Cc × 2Vd next, the power becomes QV = 2CcVd ^2.

On the other hand, in the present embodiment, first, in the second transition period, the recovery switch QC _{j + 1} is turned on from the initial state shown in FIG. 9A. Then, as shown in FIG. 9B, a current Ib flows from the ground potential to the parasitic diode of the low-voltage side switch QL _j , the capacitor Cc, the recovery switch QC _{j + 1} , and the recovery capacitor C40, and the terminal voltage on the data electrode D _{j + 1} side of the capacitor Cc. Decreases to the intermediate voltage Vd / 2.

Next, the recovery switch QC _{j + 1} is turned off and the low-pressure side switch QL _{j + 1} is turned on. Then, as shown in FIG. 9C, the current Ic flows from the ground potential to the parasitic diode of the low-voltage side switch QL _j , the capacitor Cc, the low-voltage side switch QL _{j + 1} , and the ground potential, the capacitor Cc is discharged, and the terminal voltage of the capacitor Cc is In both cases, the voltage is 0 (V).

Next, the recovery switch QC _j is turned on while the low-pressure side switch QL _{j + 1} is turned on. Then, as shown in FIG. 9D, the current Id flows from the recovery capacitor C40 to the recovery switch QC _j , the capacitor Cc, the low-voltage side switch QL _{j + 1} , and the ground potential, and the terminal voltage on the data electrode D _j side of the capacitor Cc is intermediate. The voltage rises to Vd / 2. During this time, no power is supplied from the power source.

Thereafter, the recovery switch QC _j is turned off and the high-voltage side switch QH _j is turned on. Then, as shown in FIG. 9E, the current Ie flows from the power source of the voltage Vd to the high-voltage side switch QH _j , the capacitor Cc, the low-voltage side switch QL _{j + 1} , and the ground potential, and the terminal voltage on the data electrode D _j side of the capacitor Cc The voltage rises to Vd. At this time, power is supplied from the power source of the voltage Vd, and the voltage between the terminals of the capacitor Cc changes from the voltage Vd / 2 to the voltage Vd. Therefore, the charge supplied from the power source is Q = Cc × Vd / 2, and the power is QV = the CcVd ^2/2.

  When adjacent data electrodes transition to voltages opposite to each other as described above, in the present embodiment, the charge / discharge power of the interelectrode capacitance Cc between adjacent data electrodes is reduced to approximately ¼. be able to.

Next, the reason why the low voltage side voltage 0 (V) and the high voltage side voltage Vd are transitioned from one to the other using the recovery capacitor C40 and the recovery switch QC _j is temporarily changed to the intermediate voltage Vd / 2. To do.

10A to 10E are diagrams for explaining the reason why the power of the data electrode driving circuit 32 of the plasma display device 30 according to the first exemplary embodiment of the present invention can be reduced, and an output buffer for the data electrode D _j , The current flowing there is shown. Capacitor Cx indicates a substantial load capacity of the data electrodes _{D j,} capacitance Cg, (Cg + Cc), is either (Cg + 2Cc). Here, the high-pressure side switch QH _j , the low-pressure side switch QL _j , and the recovery switch QC _j are indicated by “switch” symbols.

Here, consider the case for shifting the voltage of the data electrode D _j from the voltage 0 (V) to the voltage Vd. The initial state in this case is shown in FIG. 10B.

For comparison first assumed, and the voltage of the data electrode D _j, without transitioning to an intermediate voltage Vd / 2, and to transition from the direct voltage 0 (V) to the voltage Vd. That is, as shown in FIG. 10C, the high-voltage side switch QH _j is turned on, and the current If flows from the power source of the voltage Vd to the high-voltage side switch QH _j , the capacitor Cx, and the ground potential, thereby charging the capacitor Cx. Since this time, the voltage across the terminals of the capacitor Cx is changed from the voltage 0 (V) to the voltage Vd, the charge supplied from the power supply is Q = Cx × Vd, and the power becomes QV = CxVd ^2.

On the other hand, in the present embodiment, in the first transition period, first, the recovery switch QC _j is turned on from the initial state shown in FIG. 10B. Then, as shown in FIG. 10D, a current Ig flows from the recovery capacitor C40 to the recovery switch QC _j , the capacitor Cx, and the ground potential, and the terminal voltage of the capacitor Cx rises to the intermediate voltage Vd / 2.

Next, the recovery switch QC _j is turned off and the high voltage side switch QH _j is turned on. Then, as shown in FIG. 10E, a current Ih flows from the power source of the voltage Vd to the high-voltage side switch QH _j , the capacitor Cx, and the ground potential, and the terminal voltage of the capacitor Cx rises to the high-voltage side voltage Vd. At this time, power is supplied from the power source of the voltage Vd and the terminal voltage of the capacitor Cx changes from the voltage Vd / 2 to the voltage Vd. Therefore, the charge supplied from the power source is Q = Cx × Vd / 2, and the power is QV = CxVd. the ^2/2.

  As described above, in the present embodiment, the power for charging / discharging the substantial load capacitance Cx of the data electrode can be reduced to about ½.

Note that although the case of the transition voltage of the data electrode D _j from the voltage Vd to voltage 0 (V), the power is from the power supply in each case is not supplied.

  For the above reason, the power consumption of the data electrode drive circuit 32 can be reduced in the present embodiment.

Next, the reason why the start time of the second transition period Tb is set independently for each data electrode will be described. As described above, the load capacitance of the data electrode D _j is between the capacitance Cg between the entire display electrode pair, the capacitance Cc between the data electrode adjacent on the right side, and the data electrode adjacent on the left side. The total capacity (Cg + 2Cc) with the capacity Cc. However, when the voltage applied to the data electrode D _j is transitioned, the substantial additional capacitance viewed from the output buffer changes depending on the voltage applied to the adjacent data electrode.

For example, when attention is paid to the data electrode D _j-1 in the second transition period of the write cycle T _i-1 shown in FIG. 7, both the voltage of the adjacent data electrode D _{j-2 and} the voltage of the data electrode D _j are both data electrodes. Similarly to D _j−1 , the voltage transitions from the voltage Vd to the voltage 0 (V). Therefore, the capacitance Cc between the adjacent data electrodes can be ignored, and the substantial load capacitance of the data electrode D _j−1 is the capacitance Cg. As a result, the time required to change the voltage of the data electrode D _j−1 from the voltage Vd to the voltage 0 (V) is shortened.

Further, when attention is paid to data electrode _{D j,} the voltage of the data electrode _{D j-1} adjacent to data electrode _{D j} is changed from the voltage Vd to the voltage 0 (V), the data electrodes _{D j + 1} of the voltage the voltage 0 (V) Constant and unchanging. Therefore, the capacitance Cc between the data electrode D _j−1 can be ignored, but the capacitance Cc between the data electrode D _{j + 1} cannot be ignored, and the substantial load capacitance of the data electrode D _j is Capacity (Cg + Cc). As a result, the time required to transition the voltage of the data electrode D _j from the voltage Vd to the voltage 0 (V) is required to transition the voltage of the data electrode D _j−1 from the voltage Vd to the voltage 0 (V). Longer than time.

Further attention to the data electrode D _{j + 2,} the voltage of both adjacent data electrodes D _{j + 1} and the data electrode D _{j + 3} is not changed, the capacitance between the adjacent data electrodes when to transition the voltage applied to data electrode D _{j + 2} Cc cannot be ignored. Therefore, the substantial load capacity is the capacity (Cg + 2Cc), and the time required for the voltage of the data electrode D _{j + 2} to transition from the voltage Vd to the voltage 0 (V) is the voltage of the data electrode D _j from the voltage Vd to the voltage 0 ( It becomes longer than the time required for the transition to V). Thus, the time required for the transition of the voltage applied to the data electrode is not constant.

  Therefore, in the present embodiment, the start time of the second transition period is set for each of the output buffers, and the start time of the output buffer for the data electrode in which only the voltage of the adjacent data electrode transitions is adjacent. The voltage is set earlier than the start time of the output buffer for the data electrode in which the voltages of both data electrodes transition together. In addition, the output buffer start time for the data electrode in which the voltage of the adjacent data electrodes does not change is set earlier than the output buffer start time for the data electrode in which only the voltage of one adjacent data electrode changes. . In this way, when the time required for the voltage transition is long, the transition is started earlier, and when the time required for the voltage transition is short, the transition is started later, thereby applying the write pulse voltage Vd. And a write operation using the drive time effectively can be performed.

  In the first transition period, when the time required for the transition from the low voltage 0 (V) to the intermediate voltage Vd / 2 is long, the transition from the intermediate voltage Vd / 2 to the high voltage Vd is started later. When the time required for the transition from the low voltage 0 (V) to the intermediate voltage Vd / 2 is short, the transition from the intermediate voltage Vd / 2 to the high voltage Vd is started earlier. As a result, a write operation using the drive time more effectively is performed.

  FIG. 11 is a circuit diagram of data electrode drive circuit 32 of plasma display device 30 in the first exemplary embodiment of the present invention. The data electrode drive circuit 32 includes a shift register unit 41, a self load calculation unit 42, an adjacent load calculation unit 44, and an output buffer unit 48.

The shift register unit 41 is a shift register having at least the same number of latches 41 _j as the number of data electrodes. Then, the bit Q (hereinafter simply abbreviated as “image data Q”) corresponding to the subfield of the serially transferred image data is serial / parallel converted. That, and outputs the image data Q _j for each of the data electrodes D _j by successively shifting the image data Q which is serially transferred by the clock Dck.

The self-load calculating unit 42 includes a one-line delay 42 _j and a logic gate 43 _j provided corresponding to each of the data electrodes D _j . The one-line delay 42 _j delays the image data Q _j corresponding to the data electrode D _j by one horizontal blanking period and outputs the image data DQ _j . The logic gate 43 _j detects a change in the write pulse applied to the corresponding data electrode D _j based on the image data DQ _j and the image data Q _j . Specifically, when the image data Q _j changes from “H” to “L”, the output of the logic gate 43 _j becomes “H”, otherwise it becomes “L”.

Adjacent load calculation unit 44 has a logic gate 44 _j ~ logic gate 47 _j provided corresponding to respective data electrodes _{D j,} adjacent data electrodes _{D j-1,} an image corresponding to the data electrode _{D j + 1} based on a change in the data, it calculates the magnitude of the substantial load capacitance between adjacent data electrodes to corresponding data electrodes D _j. Specifically, when the image data Q _j−1 and the image data Q _{j + 1} of the adjacent data electrode D _j−1 and data electrode D _{j + 1} do not change from “H” → “L”, the logic gate 46 _j The output becomes “H”. The data electrode D _j-1 adjacent to data electrode D _j, the output of the logic gate 47 _j in the case where the image data of one data electrode D _{j + 1} only changes to "H" → "L" and "H" Become. In other cases, the output of the logic gate 46 _{j and} the output of the logic gate 47 _j are “L”.

Thus if the output of the logic gate 46 _j is "H", the substantial load capacity of the data electrodes D _j when the image data of the data electrode D _j is changed to "H" → "L" is the capacitance (Cg + 2Cc) If the output of the logic gate 47 _j is “H”, it is a capacity (Cg + Cc), otherwise it is a capacity Cg.

The output buffer unit 48 includes an output buffer 48 _j that generates an address pulse to be applied to each of the data electrodes D _j . Each of the output buffers 48 _j includes a high voltage side switch QH _j that outputs the high voltage Vd of the write pulse, a low voltage switch QL _j that outputs a low voltage 0 (V) of the write pulse, and an intermediate voltage Vd. And a recovery switch QC _j connected to a recovery capacitor C40 (not shown) charged to / 2.

At this time, when each of the output buffers 48 _j switches the voltage applied to the corresponding data electrode D _j from the high voltage side voltage to the low voltage side voltage via the intermediate voltage Vd / 2, the output of the corresponding logic gate 46 _j is “ If “H”, the voltage is shifted at the earliest timing so that the time of the second transition period becomes the longest. If the output of the logic gate 47 _j is “H”, the voltage is shifted at the second earliest timing so that the second transition period becomes the second longest. If the outputs of the logic gate 46 _j and the logic gate 47 _j are both “L”, the voltage is transitioned at the latest timing so that the time of the second transition period becomes the shortest.

  Thus, by setting the start time of the second transition period in accordance with the substantial load capacitance between adjacent data electrodes, the panel can be driven using the driving time effectively.

  In the present embodiment, it has been described that the start time of the second transition period is set for each of the output buffers. However, the present invention is not limited to this. For example, when the data electrode driving circuit 32 is configured by using a plurality of integrated circuits in which a plurality of output buffers are integrated, the start time of the second transition period may be set for each of the integrated circuits. Such an example will be described below as a second embodiment.

(Embodiment 2)
FIG. 12 is a circuit block diagram of plasma display device 60 in accordance with the second exemplary embodiment of the present invention. The plasma display device 60 includes a panel 10, an image signal processing circuit 31, a data electrode drive circuit 62, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit that supplies necessary power to each circuit block. (Not shown). The same circuit blocks as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted.

Similar to the data electrode drive circuit 32, the data electrode drive circuit 62 converts the image data output from the image signal processing circuit 31 into address pulses corresponding to the data electrodes D ₁ to D _m , respectively. applied to the electrode _{D 1} ~ data electrodes _{D m.} The data electrode driving circuit 62 in the second embodiment is divided into circuits for driving a predetermined number of data electrodes, and each circuit is integrated as one integrated circuit. This integrated circuit is hereinafter referred to as a “data driver”. That is, the data electrode drive circuit 62 is configured using a plurality of data drivers. In the present embodiment, a predetermined number of 384 data electrode drive circuits are integrated as one data driver. The data electrode driving circuit 62 is configured by using ₁₅ data drivers 80 ₁ to 80 ₁₅ .

FIG. 13 is a circuit diagram of data electrode drive circuit 62 of plasma display device 60 in accordance with the second exemplary embodiment of the present invention. FIG. 14 is a timing chart showing the operation of the data electrode drive circuit 62 of the plasma display device 60 in the second exemplary embodiment of the present invention. The data electrode drive circuit 62 includes a recovery capacitor C80 _p provided corresponding to each of the data driver 80 ₁ to data driver 80 ₁₅ and the data driver 80 _p (p = 1 to 15), and each of the data driver 80 _p . The maximum load calculation unit 72 _p provided corresponding to each of the data drivers 80 _p and the timing pulse selection unit 74 _p provided corresponding to each of the data drivers 80 _p .

Each of the maximum load calculators 72 _p calculates a substantial load capacity of each of the data electrodes D _j driven by the corresponding data driver 80 _p , and further calculates a maximum value thereof.

Each timing pulse selecting section 74 _p, based on the maximum value of a substantial load capacity calculated maximum load calculation unit 72 _p corresponding, one of the three timing signals LLP1~ timing signal LLP3 shown in FIG. 14 by selecting one output as a write timing signal LP _p. Here, the fall of the timing signals LLP1 to LLP3 indicates the timing when the recovery switch is turned on in the first transition period or the second transition period, and the rise of the timing signals LLP1 to LLP3 is the first transition period or the second transition period. The timing at which the recovery switch is turned off and the high-pressure side switch or the low-pressure side switch is turned on in the transition period is shown. Thus by selecting a timing signal LLP1 time of the second transition period the longest as a write timing signal LP _p, selecting timing signal LLP2 time for the second transition period becomes long in the second, by selecting the timing signal LLP3 first The time of 2 transition periods becomes the shortest.

Each of the timing pulse selectors 74 _p has a capacity (Cg + 2Cc) if the maximum value of the substantial load capacity in the first transition period or the second transition period of the data electrode D _j driven by the corresponding data driver 80 _p is the capacity (Cg + 2Cc). select timing signal LLP1 as write timing signal LP _p, selects the timing signal LLP2 if capacitance (Cg + Cc), if the capacitance Cg, selects the timing signal LLP3.

Each of the data drivers 80 ₁ to 80 ₁₅ has a shift register unit 81, a data latch unit 83, and an output buffer unit 85.

The shift register unit 81 is a shift register having at least as many latches 81 _j as the number of data electrodes D _j driven by the data driver 80 _p . Then, the bit Q corresponding to the subfield of the serially transferred image data (also simply abbreviated as “image data Q”) is serial / parallel converted. That, and outputs the image data Q _j for each of the data electrodes D _j by successively shifting the image data Q which is serially transferred by the clock Dck.

Data latch unit 83 includes a latch 83 _j to the data driver 80 _p correspond to the respective data electrodes _{D j} to drive, latches image data _{Q j} corresponding to each of data electrode _{D j} by the write timing signal LP _p The image data is output to the output buffer unit 85.

The output buffer unit 85 includes an output buffer 85 _j that generates an address pulse to be applied to each of the data electrodes D _j driven by the data driver 80 _p . Each of the output buffers 85 _j includes a high voltage side switch QH _j that outputs a high voltage Vd of the write pulse, a low voltage side switch QL _j that outputs a low voltage 0 (V) of the write pulse, and a recovery switch QC _j . Have. Then, in accordance with the image data, and generates a write pulse by the output voltage Vd of the high voltage side, an intermediate voltage Vd / 2 or the voltage of the low voltage side 0 (V) according to the timing of the write timing signal LP _p.

For example, as shown in FIG. 14, a timing pulse selecting section 74 _p corresponding to the data driver 80 _p selects the timing signal LLP1 in the first transition period of the write cycle _{T i-1,} the write period _{T i-1} select timing signal LLP3 in the second transition period, select the timing signal LLP2 in the first transition period of the write cycle _{T i,} selects the timing signal LLP1 in the second transition period of the write cycle _{T i,} the write period _{T i + 1} Assume that the timing signal LLP3 is selected in the first transition period and the timing signal LLP2 is selected in the second transition period of the write cycle T _{i + 1} . Then second transition period of the write cycle _{T i-1} for the data driver 80 _p starts at time t23, the second transition period of the write cycle _{T i} starts at time t41, the second transition period of the write cycle _{T i + 1} is Start at time t62.

The data driver _{80 p;} timing pulse selecting section _{74 p} corresponds to _{1; 1} selects the timing signal LLP3 in the first transition period of the write cycle _{T i-1,} the second transition period of the write cycle _{T i-1} select timing signal LLP1 in, select the timing signal LLP1 in the first transition period of the write cycle _{T i,} selects the timing signal LLP2 in the second transition period of the write cycle _{T i,} the first transition of the write period _{T i + 1} Assume that the timing signal LLP2 is selected in the period, and the timing signal LLP3 is selected in the second transition period of the write cycle T _{i + 1} . Then the data driver _{80 p;} second transition period of the write cycle _{T i-1} for ₁ starts at time t21, the second transition period of the write cycle _{T i} starts at time t42, the second transition of the write period _{T i + 1} The period starts at time t63.

Thus, in the present embodiment, the start time of the second transition period is set for each of the data driver 80 _p, an output buffer for the adjacent at least one side data electrode voltage of the data electrodes are not transition exists start time of the data driver 80 _p, the voltage of the adjacent at least one side of the data electrodes is set earlier than the start time of the data driver 80 _p output buffer does not exist for the data electrode not transition. In addition, there is no output buffer for the data electrode in which the voltage of the data electrode on both sides does not change at the start time of the data driver 80 _p where the output buffer for the data electrode on which the voltage of the adjacent data electrode does not change exists. It is set earlier than the start time of the data driver 80 _p.

Thereby, the time of the 1st transition period and the 2nd transition period can be set up, without overlapping in time. Also, once although the timing for switching the high side voltage Vd or low side voltage 0 (V) after the transition to an intermediate voltage Vd / 2 is not inferior to the first embodiment since common to one data driver 80 _p Thus, it is possible to perform a writing operation using the driving time effectively.

In the first and second embodiments, each of the recovery switches QC ₁ to QC _m is configured by back-to-back connection of two FETs, but the present invention is not limited to this. Absent. FIG. 15A is a diagram showing another configuration example of the output buffer in the first and second embodiments of the present invention, and is an example in which the recovery switch QC _j is configured using a P-channel MOSFET. FIG. 15B is a diagram showing another configuration example of the output buffer in the first and second embodiments of the present invention, and is an example in which the recovery switch QC _j is configured using an N-channel MOSFET. If the output buffer is configured in this way, the recovery switch can be realized by one switching element.

  In the first and second embodiments, when the voltage applied to the data electrode is transitioned, first, the high voltage side voltage is switched to the low voltage side voltage, and then the low voltage side voltage is switched to the high voltage side voltage. Therefore, the start time of the second transition period is set for each output buffer or each data driver. However, after switching from the low voltage to the high voltage, the high voltage may be switched to the low voltage. In this case, the start time of the first transition period may be set for each output buffer or each data driver.

  The specific circuits described in Embodiments 1 and 2 are examples of circuit configurations, and the present invention is not limited to this. The structure which implement | achieves the function mentioned above using another circuit may be sufficient.

  Furthermore, the specific numerical values used in the first and second embodiments are merely examples, and are appropriately set to optimum values according to the panel characteristics, the specifications of the plasma display device, and the like. It is desirable.

  INDUSTRIAL APPLICABILITY The present invention is useful as a plasma display device because power can be supplied from a power supply having a constant voltage to a data electrode driving circuit to perform stable address discharge and power consumption of the data electrode driving circuit can be reduced.

DESCRIPTION OF SYMBOLS 10 Panel 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 22 Data electrode 30, 60 Plasma display apparatus 31 Image signal processing circuit 32, 62 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 41 Shift register Unit 42 self-load calculation unit 44 adjacent load calculation unit 48 output buffer unit 48j output buffer 72p maximum load calculation unit 74p timing pulse selection unit 80p data driver 81 shift register unit 83 data latch unit 85 output buffer unit 85j output buffer QH1, QHj, QHm High pressure side switch QL1, QLj, QLm Low pressure side switch

Claims (3)

A plasma display panel having a plurality of display electrode pairs and a plurality of data electrodes, and a data electrode drive circuit for applying a write pulse to the data electrodes, the data electrode drive circuit having a high voltage of the write pulse for each write cycle A plasma display device for applying a side voltage or a low-voltage side voltage of the write pulse to each of the data electrodes,
The data electrode driving circuit includes a recovery capacitor charged to an intermediate voltage lower than the high-voltage side voltage and higher than the low-voltage side voltage, and outputs a high-voltage side switch that outputs the high-voltage side voltage and the low-voltage side voltage. An output buffer having a low-voltage side switch and a recovery switch connected to the recovery capacitor for each of the data electrodes;
The output buffer for transitioning the output voltage from the low-voltage side voltage to the high-voltage side voltage turns on the recovery switch during the first transition period provided in each of the write cycles, and transitions from the low-voltage side voltage to the intermediate voltage. After turning off the recovery switch and turning on the high voltage side switch to transition the output voltage from the intermediate voltage to the high voltage side voltage,
An output buffer for transitioning the output voltage from the high-voltage side voltage to the low-voltage side voltage is provided in each of the write cycles and turns on the recovery switch in a second transition period that does not overlap in time with the first transition period. The plasma display apparatus is characterized in that after the transition from the high-voltage side voltage to the intermediate voltage, the recovery switch is turned off and the low-voltage side switch is turned on to transition the output voltage from the intermediate voltage to the low-voltage side voltage. . A start time of at least one of the first transition period and the second transition period is set for each of the output buffers;
The start time of the output buffer for the data electrode in which only the voltage of the adjacent one of the data electrodes transitions is set earlier than the start time of the output buffer for the data electrode in which the voltages of the adjacent data electrodes on both sides transition together,
The start time of the output buffer for the data electrode in which the voltages of the adjacent data electrodes are not transitioned together is set earlier than the start time of the output buffer for the data electrode in which only the voltage of the adjacent data electrode is transitioned. The plasma display device according to claim 1. The data electrode driving circuit is configured by using a plurality of integrated circuits in which a plurality of the output buffers are integrated,
A start time of at least one of the first transition period and the second transition period is set for each of the integrated circuits;
The integrated circuit in which there is an output buffer for a data electrode in which the voltage of at least one adjacent data electrode does not transition is present at the start time of the integrated circuit in which there is no output buffer for the data electrode in which the voltage of at least one adjacent data electrode does not transition Is set earlier than the start time of
The integrated circuit in which there is an output buffer for the data electrode in which the voltages of the adjacent data electrodes do not transition together is the integrated circuit in which there is no output buffer for the data electrode in which the voltages of the adjacent data electrodes do not transition together The plasma display apparatus according to claim 1, wherein the plasma display apparatus is set earlier than the start time.

Images