JP2012114838A - Solid state imaging device and camera system - Google Patents

Abstract

A solid-state imaging device capable of suppressing random noise without causing shading and a driving method thereof.
A plurality of unit pixels, a vertical signal line, a feedback amplifier, a feedback line, a pixel reset signal line, a timing control circuit, and a reset signal output from the timing control circuit. A reset signal control circuit 60 that adjusts the waveform of the reset signal 36 so as to give a slope to the waveform of the trailing edge of the reset pulse included in the unit 36, and the unit pixel 42 includes the amplification transistor 4, the selection transistor 5, and the reset transistor 3. The soft reset time from the start of the change of the trailing edge of the reset pulse that controls the on / off of the reset transistor 3 to the time when the reset transistor 3 is turned off is the same for each unit pixel 42 in the same row. It is aligned.
[Selection] Figure 1

Description

  The present invention relates to a solid-state imaging device, and more particularly to a stacked solid-state imaging device and a camera system.

  In a general solid-state imaging device, an embedded photodiode structure is used as a light receiving unit.

  In Patent Document 1, a photoelectric conversion layer is formed on a control electrode constituting a solid-state amplification device, a transparent electrode layer is provided thereon, and the action of the voltage applied thereto is controlled via the photoelectric conversion layer. A device that changes optical information into an electrical signal with a good S / N ratio, that is, a so-called stacked solid-state imaging device is disclosed.

Japanese Patent Laid-Open No. 55-120182

  A stacked solid-state imaging device has a configuration in which a photoelectric conversion film is formed on a semiconductor substrate on which a pixel circuit is formed via an insulating film. For this reason, it is possible to use a material having a large light absorption coefficient such as amorphous silicon for the photoelectric conversion film. For example, in the case of amorphous silicon, green light having a wavelength of 550 nm is almost absorbed at a thickness of about 0.4 nm.

  In addition, since the embedded photodiode structure is not used, the capacity of the photoelectric conversion unit can be increased, and the saturation charge amount can be increased. Furthermore, it is possible to add an additional capacitor positively because it does not transfer charges completely, a sufficiently large capacity can be realized even in a miniaturized unit pixel, and further, the stack cell of the dynamic random access memory can be realized. Such a structure is also possible.

  However, the solid-state imaging device disclosed in Patent Document 1 has a problem that random noise is larger than that of a general embedded photodiode type solid-state imaging device.

  First, since a general embedded photodiode type solid-state imaging device can transfer charges almost completely, sampling of (signal level + fixed pattern noise) − (black level + fixed pattern noise) = signal level is performed by the CDS circuit. If this is done, it is possible to cancel the fixed pattern noise. Therefore, when resetting a signal, a method of suppressing the noise to 1 / √2 by combining a strong inversion operation and a weak inversion operation of the reset transistor is used. However, this method is used for a stacked solid-state imaging device. I can't.

  Moreover, in the solid-state imaging device disclosed in Patent Document 1, noise is generated when signal charges are reset. That is, when the reset signal for controlling the reset transistor is a steep rectangular wave, random noise is generated due to the trailing edge of the reset pulse included in the reset signal. Since the stacked solid-state imaging device cannot transfer charges completely, the next signal charge is added in a state where noise is generated, and the signal charge on which reset noise is superimposed is read out. For this reason, random noise increases. The trailing edge (rear edge) of the reset pulse is a falling edge when the reset pulse included in the reset signal is a positive pulse (upward pulse), and the reset pulse is a negative pulse (downward pulse). The case is a rising edge.

  Furthermore, in recent years, there is a video standard that requires a frame rate of 60 frames per second called HD (High Definition), and there is a demand for a high frame rate for moving images. The method of slowing down the frame rate cannot be used.

  At this time, in order to solve the problem of the random noise, it is conceivable to perform a soft reset that gently turns off the reset transistor in the terminal pixel, or to connect a feedback amplifier to the unit pixel for each column. However, when performing a soft reset, since the wiring resistance and parasitic capacitance of the reset signal line that controls the reset transistor wired in the row direction depend on the wiring length, the reset transistor of each unit pixel arranged in the row direction The reset signal with the same waveform cannot be input. Also, when connecting a feedback amplifier, the feedback amplifiers arranged in each column have different wiring resistance and parasitic capacitance until the output of each unit pixel aligned in the column direction is connected to the drain of the reset transistor. The output gain of the amplifier and the delay amount cannot be aligned. As a result, the effect of reducing random noise by the soft reset and the feedback amplifier differs for each row and column, and row and column shading occurs in the captured image.

  In view of the above problems, an object of the present invention is to provide a solid-state imaging device and a camera system capable of suppressing random noise without causing shading.

  The present invention has the following configuration as one means for achieving the above object.

  In order to solve the above problems, a solid-state imaging device according to the present invention includes a plurality of unit pixels arranged in a matrix on a semiconductor substrate, a vertical signal line provided for each column of the unit pixels, and the vertical signal line. In order to reset a signal of the unit pixel, a feedback line provided for each column of the unit pixels in order to feed back the output signal of the inverting amplifier to the unit pixels of the corresponding column A reset signal line provided for each row of the unit pixels, a timing control circuit that generates a reset signal that transmits the reset signal line, and a trailing edge of a reset pulse included in the reset signal output from the timing control circuit A reset signal control circuit that adjusts a waveform of the reset signal so as to give a slope to the waveform of A selection transistor, a reset transistor, and a photoelectric conversion unit, wherein the photoelectric conversion unit includes a photoelectric conversion film formed above the semiconductor substrate, and a pixel formed on a surface of the photoelectric conversion film on the semiconductor substrate side. An amplifying transistor having a gate connected to the pixel electrode and a source connected to the vertical signal line; and a transparent electrode formed on a surface opposite to the pixel electrode of the photoelectric conversion film. The drain is connected to a power supply line, the gate is connected to the reset signal line, the source is connected to the pixel electrode, the drain is connected to the feedback line, and the selection transistor is the amplification transistor The reset signal is inserted between the source of the transistor and the vertical signal line or between the drain of the amplification transistor and the power line. Wherein the start edge change after the reset pulse to control the on-off of the transistor reset transistor is soft reset time until off, characterized in that aligned with each of the unit pixels in the same row.

  With such a configuration, since a soft reset operation is performed, random noise generated in the reset transistor in the unit pixel can be reduced, and high image quality can be achieved. At this time, since the soft reset time is aligned for each unit pixel in the same row, the effect of reducing random noise is aligned for each unit pixel, and shading is suppressed.

  Here, the row selection signal supplied to the gate of the selection transistor includes a row selection pulse for controlling on / off of the selection transistor, and the soft reset time is from the start of the change of the trailing edge of the row selection pulse. It may be ten times or more of the time until the selection transistor is turned off.

  With such a configuration, since the soft reset time becomes long, random noise can be greatly reduced, and further image quality can be improved.

  The solid-state imaging device may further include an amplifier provided on the reset signal line, and a gate of at least one reset transistor may be connected to the reset signal line via the amplifier.

  With such a configuration, it is possible to suppress delay and attenuation by inserting a voltage follower or the like into the reset signal line to convert the impedance of the reset signal and strengthening the signal drive capability. As a result, the soft reset time can be made uniform for the unit pixels arranged in the row direction, and column shading can be suppressed.

  The solid-state imaging device further includes a multiplexer circuit that is provided between the timing control circuit and the unit pixel and selectively supplies the reset signal to the reset signal line corresponding to the unit pixel in a predetermined row. The reset signal line has a wiring resistance in a portion connecting the multiplexer circuit and the first unit pixel at a distance close to the multiplexer circuit, and the second unit pixel at a distance far from the multiplexer circuit and the first unit pixel. It may be larger than the wiring resistance of the portion connecting the unit pixel.

  With such a configuration, the wiring resistance can be made uniform, the soft reset time can be made uniform in the unit pixels arranged in the row direction, and column shading can be suppressed.

  The solid-state imaging device further includes a multiplexer circuit that is provided between the timing control circuit and the unit pixel and selectively supplies the reset signal to the reset signal line corresponding to the unit pixel in a predetermined row. The gate size of the reset transistor of the unit pixel in the same row may be large in the first unit pixel close to the multiplexer circuit and small in the second unit pixel far from the multiplexer circuit.

  By changing the gate size of the unit pixels arranged in the row direction, the resistance component of the reset transistor can be changed, the soft reset time can be made uniform, and column shading can be suppressed.

  The solid-state imaging device further includes a multiplexer circuit that is provided between the timing control circuit and the unit pixel and selectively supplies the reset signal to the reset signal line corresponding to the unit pixel in a predetermined row. The threshold voltage of the reset transistor of the unit pixel in the same row may be high in the first unit pixel near the multiplexer circuit and low in the second unit pixel far from the multiplexer circuit.

  For unit pixels arranged in the row direction, the soft reset time can be made uniform by changing the threshold value of the reset transistor, and column shading can be suppressed.

  In order to solve the above problems, a solid-state imaging device according to the present invention includes a plurality of unit pixels arranged in a matrix on a semiconductor substrate, a vertical signal line provided for each column of the unit pixels, and the vertical signal. An inverting amplifier connected to the line, and a feedback line provided for each column of the unit pixels in order to feed back an output signal of the inverting amplifier to the unit pixels of the corresponding column. A transistor, a selection transistor, a reset transistor, and a photoelectric conversion unit, wherein the photoelectric conversion unit is formed on the surface of the semiconductor substrate side of the photoelectric conversion film and the photoelectric conversion film formed above the semiconductor substrate A pixel electrode and a transparent electrode formed on a surface of the photoelectric conversion film opposite to the pixel electrode; the amplification transistor has a gate connected to the pixel electrode; The source is connected to the vertical signal line, the drain is connected to the power supply line, the reset transistor is connected to the pixel electrode, the drain is connected to the feedback line, and the selection transistor is the amplification transistor The phase of the signal input to the unit pixel of the output signal of the inverting amplifier is inserted between the source of the inverting amplifier and the drain of the amplification transistor and the power supply line. It is characterized by being aligned in each unit pixel.

  With such a configuration, since a soft reset operation is performed, random noise generated in the reset transistor in the unit pixel can be reduced, and high image quality can be achieved. At this time, since the phase of the output signal of the feedback amplifier input to the unit pixel is aligned with each unit pixel in the same column, the random noise reduction effect is aligned with each unit pixel, and shading is suppressed.

  The solid-state imaging device may further include an amplifier provided on the feedback line, and a drain of at least one reset transistor may be connected to the feedback line via the amplifier.

  With such a configuration, it is possible to suppress delay and attenuation by inserting a voltage follower or the like into the feedback line, impedance-converting the output signal of the feedback amplifier, and enhancing the signal drive capability. As a result, the phase of the output signal of the feedback amplifier input to the unit pixel is aligned in each unit pixel in the same column, so that the random noise reduction effect is aligned in each unit pixel, and row shading can be suppressed.

  Further, in the feedback line, a wiring resistance at a portion connecting the output of the inverting amplifier and the first unit pixel close to the output of the inverting amplifier has a second unit pixel far from the output of the inverting amplifier and the first unit pixel. It may be larger than the wiring resistance of the portion connecting the unit pixels.

  With such a configuration, the wiring resistance can be made uniform, and the phase of the output signal of the feedback amplifier input to the unit pixel can be made uniform, so that row shading can be suppressed.

  In addition, the drain diffusion capacitance of the reset transistor of the unit pixel in the same column is large in the first unit pixel close to the output of the inverting amplifier and in the second unit pixel far from the output of the inverting amplifier. It may be small.

  According to this configuration, since the output of the feedback amplifier and the reset drain of each unit pixel in the column corresponding to the output are 1: 1, the output of the feedback amplifier is adjusted by adjusting the drain diffusion capacitance of the reset transistor of each unit pixel. Gain and delay can be adjusted. As a result, the phase of the output signal of the feedback amplifier input to the unit pixel can be made uniform and returned to the drain of the reset transistor of the unit pixel in the same column, so that row shading can be suppressed.

  The inverting amplifier may be a one-input type.

  According to such a configuration, the amplifier can be made smaller than a general differential amplifier, and the reference signal can be generated internally, so that no noise countermeasure is required, and miniaturization, cost reduction, and high performance can be achieved. It can be realized at the same time.

  In order to solve the above problems, a camera system of the present invention includes the solid-state imaging device.

  According to such a configuration, since the solid-state imaging device capable of suppressing random noise without causing shading is provided, high image quality can be realized.

  ADVANTAGE OF THE INVENTION According to this invention, the random noise which generate | occur | produces in a unit pixel can be reduced, Furthermore, the high quality laminated | stacked image sensor which suppressed the shading of the row and column direction can be provided.

1 is a diagram illustrating a chip configuration of a stacked solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating details of a configuration of a pixel unit and its peripheral circuits according to the same embodiment. It is sectional drawing of the unit pixel which concerns on the same embodiment. It is a circuit diagram for demonstrating operation | movement of the solid-state imaging device concerning the embodiment. 3 is a diagram illustrating a circuit example of a reset signal control circuit according to the same embodiment. FIG. 3 is a diagram illustrating a circuit example of a reset signal control circuit according to the same embodiment. FIG. 3 is a diagram illustrating a circuit example of a reset signal control circuit according to the same embodiment. FIG. 3 is a diagram illustrating a circuit example of a reset signal control circuit according to the same embodiment. FIG. 3 is a diagram illustrating a circuit example of a reset signal control circuit according to the same embodiment. FIG. 6 is a timing chart for explaining the operation of the solid-state imaging device according to the embodiment. It is a timing chart for demonstrating operation | movement of the solid-state imaging device as a comparative example. It is a figure which shows the waveform of the reset signal in the solid-state imaging device as a comparative example, and the solid-state imaging device concerning the embodiment. It is a figure which shows the structure of the unit pixel of the solid-state imaging device concerning the embodiment, and the waveform of the reset signal in the unit pixel arranged in a row direction. It is a figure which shows the structure of the unit pixel of the laminated | stacked solid-state imaging device concerning the 2nd Embodiment of this invention, and the waveform of the reset signal in the unit pixel arranged in a line direction. It is a figure which shows the structure of the unit pixel of the laminated | stacked solid-state imaging device concerning the 3rd Embodiment of this invention, and the waveform of the reset signal in the unit pixel arranged in a line direction. It is a figure which shows the chip | tip structure of the laminated | stacked solid-state imaging device which concerns on the 4th Embodiment of this invention. FIG. 2 is a diagram illustrating details of a configuration of a pixel unit and its peripheral circuits according to the same embodiment. It is a figure which shows the chip | tip structure of the laminated | stacked solid-state imaging device concerning the 5th Embodiment of this invention. FIG. 10 is a circuit diagram of a stacked solid-state imaging device according to a sixth embodiment of the present invention. It is a figure which shows the waveform of the feedback signal in the unit pixel arranged in the column direction in the solid-state imaging device concerning the embodiment. It is a figure which shows the structure of the unit pixel of the laminated | stacked solid-state imaging device concerning the 7th Embodiment of this invention, and the waveform of the reset signal in the unit pixel arranged in a line direction. It is a figure which shows the chip | tip structure of the laminated | stacked solid-state imaging device which concerns on the 8th Embodiment of this invention. FIG. 2 is a diagram illustrating details of a configuration of a pixel unit and its peripheral circuits according to the same embodiment. It is a figure which shows the chip | tip structure of the laminated | stacked solid-state imaging device which concerns on the 9th Embodiment of this invention. FIG. 10 is a circuit diagram of a stacked solid-state imaging device according to a tenth embodiment of the present invention. It is a block diagram of the camera system which concerns on the 11th Embodiment of this invention.

  Hereinafter, a solid-state imaging device and a camera system according to embodiments of the present invention will be described with reference to the drawings.

  In the drawings, elements that represent substantially the same configuration, operation, and effect are denoted by the same reference numerals. In addition, the numerical values described below are all exemplified for specifically explaining the present invention, and the present invention is not limited to the illustrated numerical values. Furthermore, the connection relationship between the components is exemplified for specifically explaining the present invention, and the connection relationship for realizing the function of the present invention is not limited to this. Furthermore, the source electrode and the drain electrode of an FET are almost the same in structure and function, and are often not clearly distinguished. However, in the following description, for convenience, an electrode to which a signal is input is referred to as a source electrode and an output. This electrode is referred to as a drain electrode.

(First embodiment)
FIG. 1 shows a chip configuration of a stacked solid-state imaging device according to this embodiment. FIG. 2A shows details of the configuration of the pixel portion 43 and its peripheral circuits. FIG. 2B shows a cross-sectional view of the unit pixel 42. FIG. 3 is a circuit diagram of the solid-state imaging device according to the present embodiment. In FIG. 2A, the unit pixels 42 are described for “2 rows and 2 columns”, but the number of rows and the number of columns of the unit pixels 42 may be arbitrarily set.

  As shown in FIG. 1, the solid-state imaging device, that is, the sensor chip 52 includes a pixel reset signal line 7, a pixel address signal line 8, a vertical signal line 9, a feedback line 16, a column selection transistor 27, a column scanning circuit (horizontal scanning unit). 29, horizontal signal line 30, output amplifier 31, row scanning circuit (vertical scanning unit) 33, multiplexer circuit (MUX) 41, VOUT terminal 32, pixel unit 43, feedback circuit 44, CDS (Correlated Double Sampling) circuit 45, timing A control circuit 50, a reference voltage generation circuit 51, and a reset signal control circuit 60 are provided.

  In the pixel unit 43, a plurality of unit pixels 42 are arranged in a matrix on a semiconductor substrate, and the vertical signal line 9 is provided for each column of the unit pixels 42. In the sensor chip 52, the unit pixel 42 of the pixel unit 43 is selected by the row scanning circuit 33 and the multiplexer circuit 41.

  As shown in FIG. 2A, each unit pixel 42 includes a photoelectric conversion unit 1, a storage unit 2 having one end connected to the photoelectric conversion unit 1, a source connected to the vertical signal line 9, and a drain connected to the power supply line 6. The amplifying transistor 4 is connected in series, the gate is connected to the storage unit 2, the gate is connected to the pixel reset signal line 7, the drain is connected to the feedback line 16, and the amplifying transistor 4 is connected in series. And a selection transistor 5. The selection transistor 5 is inserted between the source of the amplification transistor 4 and the vertical signal line 9, but may be inserted between the drain of the amplification transistor 4 and the power supply line 6.

  As shown in FIG. 2B, an amplification transistor 4, a selection transistor 5, and a reset transistor 3 are formed on a semiconductor substrate 71 made of silicon. The amplification transistor 4 includes a gate electrode 72, a diffusion layer 73 that is a drain, and a diffusion layer 74 that is a source. The selection transistor 5 includes a gate electrode 75, a diffusion layer 74 that is a drain, and a diffusion layer 76 that is a source. The source of the amplification transistor 4 and the drain of the selection transistor 5 are a common diffusion layer 74. The reset transistor 3 includes a gate electrode 77, a diffusion layer 78 that is a drain, and a diffusion layer 79 that is a source. The diffusion layer 73 and the diffusion layer 78 are separated by the element isolation region 80.

  An insulating film 84 is formed on the semiconductor substrate 71 so as to cover each transistor. The photoelectric conversion unit 1 is formed on the insulating film 84. The photoelectric conversion unit 1 includes a photoelectric conversion film 81 made of amorphous silicon or the like formed above a semiconductor substrate, a pixel electrode 82 formed on the surface of the photoelectric conversion film 81 on the semiconductor substrate 71 side, and photoelectric conversion. A transparent electrode 83 formed on the surface of the film 81 opposite to the pixel electrode 82; The pixel electrode 82 is connected to the gate electrode 72 of the amplification transistor 4 and the diffusion layer 78 that is the source of the reset transistor 3 through a contact 85. The diffusion layer 78 connected to the pixel electrode 82 functions as a storage diode (storage unit 2).

  The row scanning circuit 33 supplies various timing signals to the pixel unit 43 via the pixel reset signal line 7, the pixel address signal line 8, and the like. The column scanning circuit 29 supplies the column selection signal 28 to the column selection transistor 27 to sequentially read out the signal of the pixel unit 43 to the horizontal signal line 30. The output amplifier 31 amplifies the signal transmitted through the horizontal signal line 30 and outputs the amplified signal to the VOUT terminal 32.

  The pixel reset signal line 7 is a signal line through which a reset signal is transmitted, and is provided for each row of the unit pixels 42 in order to reset the signal of the unit pixel 42 in the corresponding row.

  The feedback circuit 44 includes an inverting amplifier, and has an input connected to the vertical signal line 9 and an output connected to the feedback line 16. The feedback line 16 is provided for each vertical signal line 9 in order to feed back the output signal (feedback signal) of the feedback circuit 44 (feedback amplifier 12) to the unit pixel 42 of the corresponding column.

  The feedback circuit 44 includes a feedback amplifier 12 which is an inverting amplifier connected to the vertical signal line 9, a vertical signal line reset transistor 14 whose gate is controlled by a vertical signal line reset transistor control signal 15, and a feedback line reset transistor control signal. And a feedback line reset transistor 17 whose gate is controlled by 18. The output of the feedback amplifier 12 is connected to the drain of the reset transistor 3, and when the selection transistor 5 and the reset transistor 3 are in a conductive state, the output of the selection transistor 5 is received so that the gate potential of the amplification transistor 4 becomes constant. To feedback operation. At this time, the output of the feedback amplifier 12 becomes 0V or a positive voltage near 0V.

  The CDS circuit 45 is provided for each vertical signal line 9, and a potential difference at any two different timings in the corresponding vertical signal line 9, that is, a potential during a reset operation (a vertical signal line when the reset transistor 3 is on). 9 is output from the CDS output node 26 in accordance with the difference between the potential at the time of signal output and the potential at the time of signal output (the potential of the vertical signal line 9 when the reset transistor 3 is off).

  The CDS circuit 45 includes capacitors 19 and 25, a sample transistor 20 whose on / off is controlled by a sample transistor control signal 21, and a clamp transistor 22 whose on / off is controlled by a clamp transistor control signal 23 and connected to the clamp signal line 24. Have

  The vertical signal line 9 is connected to a pixel load transistor 10 whose on / off is controlled by a pixel load transistor control line 11.

  The timing control circuit 50 supplies a vertical scanning signal 40 to the row scanning circuit 33, supplies a row selection signal 35 and a reset signal 36 to the multiplexer circuit 41, and supplies a horizontal scanning signal 39 to the column scanning circuit 29. The timing control circuit 50 generates a row selection signal 35 and a reset signal 36.

  The multiplexer circuit 41 includes a pixel reset signal switch 37 and a pixel address signal switch 38, and controls the output of the row selection signal 35 and the reset signal 36 to the pixel unit 43 based on the row selection signal 34. The multiplexer circuit 41 is provided between the timing control circuit 50 and the unit pixel 42 and selectively supplies a reset signal 36 to the pixel reset signal line 7 corresponding to the unit pixels 42 in a predetermined row.

  The reference voltage generation circuit 51 supplies the feedback AMP reference signal 13 to the feedback circuit 44.

  The reset signal control circuit 60 is a waveform adjustment unit that adjusts the waveform of the reset signal 36 to be applied to the gate of the reset transistor 3. The reset signal control circuit 60 gives a slope to the waveform of the trailing edge of the reset pulse (pulse for controlling on / off of the reset transistor 3) included in the reset signal 36 output from the timing control circuit 50, in other words, a falling edge. The waveform of the reset signal 36 is adjusted so as to give a slope to the gate of the reset transistor 3 and supplied to the gate of the reset transistor 3.

  Circuit examples of the reset signal control circuit 60 are shown in FIGS. 4A to 4E.

  The reset signal control circuit 60 may be configured by a resistance element 1001 having a resistance value R as shown in FIG. 4A or an RC filter circuit having a resistance element 1002 and a capacitor 1003 as shown in FIG. 4B. 4B shows the RC filter circuit, the filter circuit configuration can be adjusted if the falling waveform of the trailing edge of the reset pulse included in the reset signal 36 output from the timing control circuit 50 can be adjusted. It is not limited to. Further, the reset signal control circuit 60 in FIG. 4B may be configured to be able to change the values of the resistance element 1002 and the capacitor 1003 to a plurality of filter coefficients by changing the values of the resistance element 1002 and the capacitor 1003 as shown in FIG. 4C.

  As shown in FIG. 4D, the reset signal control circuit 60 includes a plurality of resistance elements, that is, a resistance element 1004 having a resistance value R1, a resistance element 1005 having a resistance value R2, a resistance element 1006 having a resistance value R3, and a selector 1008. A circuit that can select a value may be used. The resistance value in the reset signal control circuit 60 is R3> R2> R1, and the resistance value selection signal 1007 passes the resistance value selected by the selector 1008 and the reset signal 36 is input to the gate of the reset transistor 3. The In the reset signal control circuit 60 of FIG. 4D, since the resistance value of R3 is larger than that of R1, the reset signal becomes dull and the time required for resetting becomes longer. In FIG. 4D, the case where three types of resistance values can be selected is described, but the number of selectable resistance values is not limited.

  The reset signal control circuit 60 may be configured by a tapered circuit as shown in FIG. 4E. In this case, a DAC circuit (D / A converter circuit) used for digital conversion of the analog output of each unit pixel 42 may also be used as the reset signal control circuit 60. Specifically, the waveform used for the analog / digital conversion generated by the DAC circuit may be used as the tapered reset signal. When the DAC circuit is not used for the analog / digital conversion, the DAC circuit is used to taper the signal. A reset signal may be generated. In this case, a signal for selecting a tapered reset signal is output from the timing control circuit 50 and is selected by the reset signal control circuit 60. If applicable, the tapered reset signal is applied to the gate of the reset transistor 3.

  The reset signal control circuit 60 may be provided in the timing control circuit 50.

  Next, the operation of the solid-state imaging device according to this embodiment will be described.

  FIG. 5 is a timing chart for explaining the operation of the solid-state imaging device according to the present embodiment. FIG. 6 is a timing chart for explaining the operation of a solid-state imaging device as a comparative example. FIG. 7A is a diagram illustrating a waveform of a reset signal in a solid-state imaging device as a comparative example, and FIG. 7B is a diagram illustrating a waveform of the reset signal in the solid-state imaging device according to the present embodiment.

  In the solid-state imaging device according to the present embodiment, light is converted into an electric signal S by the photoelectric conversion unit 1 that is a laminated film, and the electric signal S is stored in the storage unit 2. When the selection transistor 5 is turned on, the electrical signal S is impedance-converted by the source follower circuit formed by the amplification transistor 4 and the pixel load transistor 10 and input to the CDS circuit 45 via the vertical signal line 9. Is done. The electrical signal S is once sampled and held by the CDS circuit 45.

  Next, when a reset signal 36 for controlling the gate of the reset transistor 3 is input into the unit pixel 42 via the pixel reset signal line 7 and the reset transistor 3 is turned on, the electrical signal S stored in the storage unit 2 is stored. Is reset (initialized).

  At this time, assuming that the electrical signal of the storage unit 2 at the time of reset is N, the pixel signal N including random noise is input to the feedback line 16 as a signal inverted and amplified by the feedback circuit 44 instead of a constant voltage. The thermal noise of the storage unit 2 can be canceled out.

  However, when the reset signal 36 is applied as a steep rectangular wave as shown in FIG. 7A, thermal noise is generated in the storage unit 2 as shown in FIG. That is, the storage unit 2 is to be reset at the signal level of the feedback line 16 by the reset signal 36, but is further in a state where thermal noise is superimposed, which causes random noise. At this time, the electric signal N is input to the CDS circuit 45 through the same path as the previous electric signal S in a state where random noise is placed, and is sampled and held by the CDS circuit 45.

  On the other hand, the reset signal 36 applied to the pixel reset signal line 7 is not a steep rectangular wave but a waveform having a gentle slope at the trailing edge of the reset pulse as shown in FIG. By performing the soft reset operation for resetting with the reset signal 36, the amount of generation of thermal noise itself can be reduced as shown in FIG. Thereby, the random noise of the electric signal N can be greatly reduced. Furthermore, as shown in FIG. 7B, the trailing edge of the reset pulse in the soft reset operation takes a time during which the generation of thermal noise can be sufficiently suppressed, for example, a period of several hundred nsec to several tens of μsec. By using a so-called tapered waveform that falls, the thermal noise can be greatly reduced, and high image quality can be reliably achieved.

  For example, the time of the taper waveform from the start of the change (falling) of the trailing edge of the reset pulse until the reset transistor 3 is turned off, that is, the soft reset time of the reset transistor 3 is the row supplied to the gate of the selection transistor 5. With respect to the time from the start of the change (falling) of the trailing edge of the row selection pulse (pulse for controlling on / off of the selection transistor 5) included in the selection signal 35 until the selection transistor 5 is turned off, for example, several tens of nsec Ten times or more, for example, 100 times longer.

  Next, the electric signal S and the electric signal N are differentiated by the CDS circuit 45, and the difference is output to the CDS output node 26 and treated as the pixel signal P. At this time, in FIG. 6, the influence of the previous random noise component remains in the pixel signal P.

  Finally, when the column selection transistor 27 is turned on by the column selection signal 28 from the column scanning circuit 29, the previous pixel signal P is read out to the horizontal signal line 30 and amplified by the output amplifier 31 from the VOUT terminal 32. Output externally.

  Here, in the solid-state imaging device according to the present embodiment, the gate length of the reset transistor 3 is larger as the reset transistor 3 of the unit pixel 42 (first unit pixel) closer to the multiplexer circuit 41 and is farther from the multiplexer circuit 41 ( The reset transistor 3 of the unit pixel 42 (second unit pixel) which is far from the multiplexer circuit 41 in comparison with the unit pixel 42 having a short distance is smaller.

  FIG. 8 is a diagram illustrating a configuration of the unit pixel 42 of the solid-state imaging device according to the present embodiment and a relationship with a reset signal in the unit pixel 42 arranged in the row direction.

  Since the pixel reset signal line 7 in the unit pixel 42 has resistance and parasitic capacitance, the influence of the CR time constant cannot be ignored. In particular, in the case of the sensor chip 52 having a large number of pixels, it is difficult to apply a voltage to the unit pixels 42 that are far from the source of the reset signal 36, so that an ideal soft reset can be uniformly performed on all the unit pixels 42. difficult. However, in the solid-state imaging device according to the present embodiment, the gate size (gate length) of the reset transistor 3 of the unit pixel 42 in the same row is larger as the unit pixel 42 is closer to the multiplexer circuit 41 and is farther from the multiplexer circuit 41. The distance unit pixel 42 is smaller. In other words, the reset transistor 3 of the unit pixel 42 farther from the multiplexer circuit 41 has a smaller on-resistance component. Therefore, the reset signal 36 having a uniform waveform can be applied to all the unit pixels 42, and the soft reset time of the reset transistor 3 can be made uniform in the unit pixels 42 in the same row aligned in the row direction. As a result, the same soft reset can be applied to each unit pixel 42 in the row direction, and the same level of random noise can be reduced in all the unit pixels 42, so that column shading can be suppressed.

  As described above, according to the solid-state imaging device according to the present embodiment, since the soft reset operation is performed, the thermal noise generated in the reset transistor 3 in the unit pixel 42 can be reduced, and the image quality can be improved. Become. At this time, since reset signals having the same waveform can be input to the reset transistors 3 of the unit pixels 42 in the same row aligned in the row direction, the effect of reducing random noise is aligned in each unit pixel 42 and shading is suppressed.

  In the solid-state imaging device according to the present embodiment, the gate size of the reset transistor 3 may be changed according to the wiring distance from the timing control circuit 50 instead of the wiring distance from the multiplexer circuit 41.

(Second Embodiment)
The solid-state imaging device according to the present embodiment is the first in that the threshold voltage Vt of the reset transistor 3 is changed instead of changing the gate length of the reset transistor 3 by the unit pixel 42 at a different distance from the multiplexer circuit 41. This is different from the solid-state imaging device of the embodiment.

  FIG. 9 is a diagram illustrating a configuration of the unit pixel 42 of the stacked solid-state imaging device according to the present embodiment and a waveform of a reset signal in the unit pixel 42 arranged in the row direction.

  In the solid-state imaging device according to the present embodiment, the threshold voltage Vt of the reset transistors 3 of the unit pixels 42 in the same row is high in the unit pixels 42 at a short distance from the multiplexer circuit 41, and compared with the unit pixels 42 at a short distance. The unit pixel 42 at a distance far from the multiplexer circuit 41 is low. As a result, the soft reset times can be made uniform and uniform for the unit pixels 42 in the same row in the row direction, the same random noise reduction effect can be applied, and column shading can be suppressed.

  As described above, the solid-state imaging device according to the present embodiment can suppress random noise without causing shading.

  In the solid-state imaging device according to the present embodiment, the threshold voltage Vt of the reset transistor 3 may be changed according to the wiring distance from the timing control circuit 50 instead of the wiring distance from the multiplexer circuit 41.

(Third embodiment)
In the solid-state imaging device according to the present embodiment, the gate resistance of the reset transistor 3 is not changed by the unit pixel 42 at a different distance from the multiplexer circuit 41, but the wiring resistance per unit length of the pixel reset signal line 7 is changed. This is different from the solid-state imaging device of the first embodiment in that

  FIG. 10 is a diagram illustrating a configuration of the unit pixel 42 of the stacked solid-state imaging device according to the present embodiment and a waveform of a reset signal in the unit pixel 42 arranged in the row direction.

  In the solid-state imaging device according to the present embodiment, the wiring resistance per unit length of the pixel reset signal line 7 connecting the multiplexer circuit 41 and the unit pixel 42 close to the multiplexer circuit 41 is the same as that of the unit pixel 42 close to the multiplexer circuit 41. It is larger than the wiring resistance per unit length of the pixel reset signal line 7 that connects the unit pixel 42 far from the multiplexer circuit 41. That is, as the distance between the multiplexer circuit 41 and the gate of the reset transistor 3 increases, the resistance per unit of the pixel reset signal line 7 decreases. As a result, the pixel reset signal line 7 connects the wiring resistance at the portion connecting the multiplexer circuit 41 and the unit pixel 42 at a distance close to the multiplexer circuit 41 to the multiplexer circuit 41 and the unit pixel 42 at a distance far from the multiplexer circuit 41. The difference with the wiring resistance of the part becomes small. As a result, the influence of the CR time constant due to the wiring resistance can be eliminated as much as possible, and the soft reset time is made uniform by aligning the unit pixels 42 in the same row in the row direction, thereby providing the same random noise reduction effect. Shading can be suppressed.

  For example, the pixel reset signal line 7 that connects the multiplexer circuit 41 and the unit pixel 42 close to the multiplexer circuit 41, and the pixel reset signal line 7 that connects the unit pixel 42 close to the multiplexer circuit 41 and the unit pixel 42 far from the multiplexer circuit 41. And a different wiring structure. Specifically, the pixel reset signal line 7 from the multiplexer circuit 41 to the unit pixel 42 close to the multiplexer circuit 41 is composed of only polysilicon wiring. The pixel reset signal line 7 from the unit pixel 42 with a short distance to the unit pixel 42 slightly far from the multiplexer circuit 41 is configured by a polysilicon wiring lined with a single-layer metal wiring such as an aluminum wiring and a copper wiring. Is done. Furthermore, the pixel reset signal line 7 from the unit pixel 42 that is a little far from the unit pixel 42 to the unit pixel 42 that is considerably far from the multiplexer circuit 41 is formed by lining the polysilicon wiring with a plurality of layers of metal wiring such as aluminum wiring and copper wiring. Composed.

  As described above, the solid-state imaging device according to the present embodiment can suppress random noise without causing shading.

  In the solid-state imaging device according to the present embodiment, the resistance per unit of the pixel reset signal line 7 may be changed according to the wiring distance from the timing control circuit 50 instead of the wiring distance from the multiplexer circuit 41. .

  In the solid-state imaging device according to the present embodiment, the wiring resistance per unit length of the pixel reset signal line 7 may be changed by changing the number of wiring layers of the polysilicon wiring. Further, the wiring resistance per unit length of the pixel reset signal line 7 may be changed by changing the thickness of the wiring.

(Fourth embodiment)
FIG. 11 shows a chip configuration of the stacked solid-state imaging device according to the present embodiment. FIG. 12 shows details of the configuration of the pixel unit 43 and its peripheral circuits. In FIG. 12, the unit pixels 42 are described for “2 rows and 2 columns”, but the number of rows and the number of columns of the unit pixels 42 may be arbitrarily set.

  The solid-state imaging device according to the present embodiment does not change the gate length of the reset transistor 3 in the unit pixel 42 having a different distance from the multiplexer circuit 41, but instead has a voltage follower with a gain of 1 on the pixel reset signal line 7 at a constant interval. This is different from the solid-state imaging device of the first embodiment in that an amplifier 61 such as the above is arranged.

  The gate of at least one reset transistor 3 is connected to the pixel reset signal line 7 via the amplifier 61.

  In the case where 2000 unit pixels 42 are arranged in the row direction in the pixel unit 43, one amplifier 61 is provided for, for example, 500 unit pixels 42. The amplifier 61 impedance-converts the reset signal 36 and strengthens the drive capability of the reset signal 36 to suppress delay and attenuation. As a result, the soft reset times are made uniform for the unit pixels 42 in the same row aligned in the row direction, and the same random noise reduction effect can be applied to suppress column shading.

  As described above, the solid-state imaging device according to the present embodiment can suppress random noise without causing shading.

(Fifth embodiment)
FIG. 13 shows a chip configuration of the stacked solid-state imaging device according to this embodiment.

  The solid-state imaging device according to this embodiment is different from the solid-state imaging device of the fourth embodiment in that only one amplifier 61 is arranged on the pixel reset signal line 7.

  The gates of all reset transistors 3 in the same row are connected to the pixel reset signal line 7 via the amplifier 61.

  The amplifier 61 impedance-converts the reset signal 36 and strengthens the drive capability of the reset signal 36 to suppress delay and attenuation. As a result, the soft reset times are made uniform for the unit pixels 42 in the same row aligned in the row direction, and the same random noise reduction effect can be applied to suppress column shading.

  Since the circuit scale of the amplifier 61 is increased in order to secure the drive capability in one amplifier 61, when the pixel pitch is reduced, the small-sized amplifier 61 is ticked at regular intervals as shown in FIG. Is preferably inserted. However, if the pixel reset signal line 7 to be driven has a small number of pixels, the parasitic capacitance or resistance of the pixel reset signal line 7 is small, or the pixel pitch is large like a single-lens reflex camera, the circuit scale of the amplifier 61 may be increased. One amplifier 61 is applied.

  As described above, the solid-state imaging device according to the present embodiment can suppress random noise without causing shading.

(Sixth embodiment)
In the stacked solid-state imaging device according to the present embodiment, the gate length of the reset transistor 3 is not changed by the unit pixel 42 having a different distance from the multiplexer circuit 41, but the unit pixel 42 having a different distance from the output of the feedback amplifier 12 is used. This is different from the solid-state imaging device of the first embodiment in that the capacitance of the diffusion region constituting the drain of the reset transistor 3 is changed.

  FIG. 14 is a circuit diagram of the solid-state imaging device according to the present embodiment.

  In the solid-state imaging device according to the present embodiment, a feedback selection transistor 46 is inserted between the output of the feedback amplifier 12 and the drain of the reset transistor 3 in each unit pixel 42. Then, the unit pixel 42 (for example, the drain capacitance (for example, drain area and impurity concentration) of the drain of the reset transistor 3 of the unit pixel 42 in the same column connected to the same feedback amplifier 12 is close to the output of the feedback amplifier 12. It is large at the first unit pixel) and small at the unit pixel 42 (second unit pixel) at a distance far from the output of the feedback amplifier 12.

  FIG. 15 is a diagram illustrating a waveform of a feedback signal in the unit pixels 42 arranged in the column direction in the solid-state imaging device according to the present embodiment. In FIG. 15, “countermeasure non-feedback signal” indicates a feedback signal in the unit pixel 42 when the diffusion capacitance of the drain is the same in each unit pixel 42, and “post-measurement feedback signal” relates to the present embodiment. A feedback signal in each unit pixel 42 is shown.

  Since the feedback line 16 has resistance and parasitic capacitance, the influence of the CR time constant cannot be ignored. Further, since the reset time is as short as several μsec, the soft reset operation is finished before the feedback signal is stabilized. In the unit pixel 42 that is far from the feedback signal generation source (feedback amplifier 12), the delay amount of the signal is large, and it is difficult to supply the feedback signal having the same phase to the unit pixels 42 arranged in the column direction. However, in the solid-state imaging device according to the present embodiment, since the output of the feedback amplifier 12 and the drain of the reset transistor 3 of each unit pixel 42 are one-to-one at the time of reset, the drain of the reset transistor 3 of each unit pixel 42 By adjusting the diffusion capacitance, the delay amount of the feedback signal can be adjusted by the unit pixel 42 in the column direction. Therefore, by equalizing the wiring delay, the phases of the feedback signals input to the unit pixels 42 are aligned with the unit pixels 42 in the same column aligned in the column direction, that is, the unit pixels in the same column aligned in the column direction of the feedback signal. The phase difference at 42 can be suppressed, and a uniform feedback signal can be returned to the drain of the reset transistor 3. As a result, each unit pixel 42 in the same column aligned in the column direction can achieve the same degree of random noise reduction effect and suppress row shading.

  As described above, the solid-state imaging device according to the present embodiment can suppress random noise without causing shading.

(Seventh embodiment)
The solid-state imaging device according to the present embodiment does not change the drain diffusion capacitance of the reset transistor 3 by the unit pixel 42 at a distance different from the output of the feedback amplifier 12 but changes the wiring resistance per unit length of the feedback line 16. It differs from the solid-state imaging device of the sixth embodiment in that it is changed.

  FIG. 16 is a diagram illustrating a configuration of the unit pixel 42 of the stacked solid-state imaging device according to the present embodiment and a waveform of a reset signal in the unit pixel 42 arranged in the row direction. In FIG. 16, “countermeasure non-feedback signal” indicates a feedback signal in the unit pixel 42 when the wiring resistance per unit length of the feedback line 16 is the same in each unit pixel 42. Indicates a feedback signal in each unit pixel 42 according to the present embodiment.

  In the solid-state imaging device according to the present embodiment, the wiring resistance per unit length of the feedback line 16 from the output of the feedback amplifier 12 to the unit pixel 42 close to the output of the feedback amplifier 12 is a unit pixel close to the output of the feedback amplifier 12. It is larger than the wiring resistance per unit length of the feedback line 16 from the unit 42 to the unit pixel 42 (second unit pixel) far from the output of the feedback amplifier 12. That is, as the distance between the output of the feedback amplifier 12 and the drain of the reset transistor 3 increases, the resistance per unit of the feedback line 16 decreases. As a result, the wiring resistance of the part connecting the output of the feedback amplifier 12 and the unit pixel 42 close to the output of the feedback amplifier 12 by the feedback line 16 is the output of the unit pixel 42 and the feedback amplifier 12 close to the output of the feedback amplifier 12. This is larger than the wiring resistance of the portion connecting the farther unit pixel 42. As a result, the influence of the CR time constant due to the wiring resistance is minimized, and the wiring delay is made uniform, thereby suppressing the phase difference in the unit pixels 42 in the same column aligned in the column direction of the feedback signal input to the unit pixels 42, A uniform feedback signal can be returned to the drain of the reset transistor 3. As a result, each unit pixel 42 in the same column aligned in the column direction can achieve the same degree of random noise reduction effect and suppress row shading.

  For example, the feedback line 16 that connects the output of the feedback amplifier 12 and the unit pixel 42 close to the output of the feedback amplifier 12, the unit pixel 42 close to the output of the feedback amplifier 12, and the unit pixel 42 far from the output of the feedback amplifier 12 A different wiring structure is used for the feedback line 16 to be connected. Specifically, the feedback line 16 from the output of the feedback amplifier 12 to the unit pixel 42 close to the output of the feedback amplifier 12 is composed of one layer of polysilicon wiring. The feedback line 16 from the unit pixel 42 close to the output of the feedback amplifier 12 to the unit pixel 42 a little farther than the output of the feedback amplifier 12 is constituted by two layers of polysilicon wiring. Further, the feedback line 16 from the unit pixel 42 slightly far from the output of the feedback amplifier 12 to the unit pixel 42 far from the output of the feedback amplifier 12 is constituted by three layers of polysilicon wiring.

  As described above, the solid-state imaging device according to the present embodiment can suppress random noise without causing shading.

  In the solid-state imaging device according to the present embodiment, the wiring resistance per unit length may be changed by changing the wiring material of the feedback line 16 as in the third embodiment. Further, the wiring resistance per unit length of the feedback line 16 may be changed by changing the thickness of the wiring.

(Eighth embodiment)
FIG. 17 shows a chip configuration of the stacked solid-state imaging device according to this embodiment. FIG. 18 shows details of the configuration of the pixel unit 43 and its peripheral circuits. In FIG. 18, the unit pixels 42 are described for “2 rows and 2 columns”, but the number of rows and the number of columns of the unit pixels 42 may be arbitrarily set.

  The solid-state imaging device according to the present embodiment does not change the drain diffusion capacitance of the reset transistor 3 by the unit pixel 42 at a distance different from the output of the feedback amplifier 12, but gains a voltage of gain 1 at a constant interval on the feedback line 16. It differs from the solid-state imaging device of the first embodiment in that an amplifier 61 such as a follower is arranged.

  The drain of at least one reset transistor 3 is connected to the feedback line 16 via the amplifier 61.

  In the case where 2000 unit pixels 42 are arranged in the column direction in the pixel unit 43, one amplifier 61 is provided, for example, for 500 unit pixels 42. The amplifier 61 impedance-converts the feedback signal, and suppresses delay and attenuation by enhancing the drive capability of the feedback signal. As a result, the phases of the feedback signals input to the unit pixels 42 are aligned in the unit pixels 42 in the same column aligned in the column direction, and a uniform feedback signal having the same phase can be returned to the drain of the reset transistor 3. As a result, each unit pixel 42 in the same column aligned in the column direction can achieve the same degree of random noise reduction effect and suppress row shading.

  As described above, the solid-state imaging device according to the present embodiment can suppress random noise without causing shading.

  Further, according to the solid-state imaging device according to the present embodiment, the amplifier 61 is inserted between the output of the feedback amplifier 12 and the wiring capacitance of the feedback line 16. Accordingly, it is possible to prevent the wiring capacitance of the feedback line 16 from varying between the unit pixels 42 in the same column aligned in the column direction due to the input / output capacitance of the feedback amplifier 12, and the same random noise reduction effect can be achieved. Can be used to suppress row shading.

(Ninth embodiment)
FIG. 19 shows a chip configuration of the stacked solid-state imaging device according to this embodiment.

  The solid-state imaging device according to the present embodiment is different from the solid-state imaging device of the eighth embodiment in that only one amplifier 61 is arranged on the feedback line 16.

  The drains of all reset transistors 3 in the same column are connected to the feedback line 16 via the amplifier 61.

  The amplifier 61 impedance-converts the feedback signal, and suppresses delay and attenuation by enhancing the drive capability of the feedback signal. Thereby, a uniform feedback signal having a uniform phase can be returned to the drain of the reset transistor 3. As a result, each unit pixel 42 in the same column aligned in the column direction can achieve the same degree of random noise reduction effect and suppress row shading.

  Since the circuit scale of the amplifier 61 is increased in order to secure drive capability with one amplifier 61, when the pixel pitch is reduced, the small-sized amplifier 61 is ticked at regular intervals as shown in FIG. Is preferably inserted. However, when the number of pixels is small, the parasitic capacitance and resistance of the feedback line 16 to be driven are small, or when the pixel pitch is large as in the case of a single lens reflex, the circuit scale of the amplifier 61 may be increased. The amplifier 61 is applied.

  As described above, the solid-state imaging device according to the present embodiment can suppress random noise without causing shading.

  Further, according to the solid-state imaging device according to the present embodiment, the amplifier 61 is inserted between the output of the feedback amplifier 12 and the wiring capacitance of the feedback line 16. Accordingly, it is possible to prevent the wiring capacitance of the feedback line 16 from varying between the unit pixels 42 in the same column aligned in the column direction due to the input / output capacitance of the feedback amplifier 12, and the same random noise reduction effect can be achieved. Can be used to suppress row shading.

(Tenth embodiment)
FIG. 20 is a circuit diagram of the stacked solid-state imaging device according to the present embodiment.

  The solid-state imaging device according to this embodiment is different from the solid-state imaging devices of the first to ninth embodiments in that the inverting amplifier is not a differential amplification type but a one-input type (for example, an inverter). According to this configuration, the inverting amplifier can be made smaller than a general differential amplifier, and the reference signal can be generated internally. Therefore, noise countermeasures are not required, and miniaturization, cost reduction, and high performance can be realized at the same time.

  As described above, the solid-state imaging device according to the present embodiment can suppress random noise without causing shading.

(Eleventh embodiment)
FIG. 21 is a block diagram of the camera system according to the present embodiment.

  This camera system includes a lens 600, the solid-state imaging device 601 of the first to tenth embodiments, a drive circuit 602, and an external interface unit 604.

In the camera having the above configuration, processing until a signal is output to the outside is performed in the following order.
(1) Light passes through the lens 600 and enters the solid-state imaging device 601.
(2) The signal processing unit 603 drives the solid-state imaging device 601 through the drive circuit 602 and takes in an output signal from the solid-state imaging device 601.
(3) The signal processed by the signal processing unit 603 is output to the outside through the external interface unit 604.

  As described above, since the camera system according to the present embodiment includes the solid-state imaging device 601 that can suppress random noise without causing shading, high image quality can be realized.

  As described above, the solid-state imaging device and the camera system of the present invention have been described based on the embodiment. However, the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.

  For example, in the above embodiment, the reset transistor 3 and the selection transistor 5 are n-type MOS transistors, and the reset pulse and the row selection pulse included in the reset signal and the row selection signal input to the gates thereof are positive pulses (upward pulses). In the above example, the trailing edge of the reset pulse and the row selection pulse is a falling edge. However, when the reset transistor 3 and the selection transistor 5 are p-type MOS transistors, the reset pulse and the row selection pulse included in the reset signal and the row selection signal input to the gates thereof are negative pulses (downward pulses). Yes, the trailing edge of the reset pulse and row selection pulse is the rising edge.

  Each of the above embodiments may be combined. In order to suppress both column shading and row shading, for example, the solid-state imaging devices of the sixth to ninth embodiments are added to the configuration of the solid-state imaging devices of the first to fifth embodiments. The configuration may be added. In this case, for example, the gate length of the reset transistor 3 is changed by the unit pixel 42 having a different distance from the multiplexer circuit 41, and the drain of the reset transistor 3 is formed by the unit pixel 42 having a different distance from the output of the feedback amplifier 12. The capacity of the diffusion region is changed.

  The present invention can be applied to a solid-state imaging device and a camera system. Particularly, the random noise is low and shading correction between matrices is possible, and a high-quality digital still camera, digital video camera, mobile terminal camera, vehicle-mounted camera, It can be applied to street cameras, security cameras and medical cameras.

DESCRIPTION OF SYMBOLS 1 Photoelectric conversion part 2 Accumulation part 3 Reset transistor 4 Amplification transistor 5 Selection transistor 6 Power supply line 7 Pixel reset signal line 8 Pixel address signal line 9 Vertical signal line 10 Pixel load transistor 11 Pixel load transistor control line 12 Feedback amplifier 13 Feedback AMP reference | standard Signal 14 Vertical signal line reset transistor 15 Vertical signal line reset transistor control signal 16 Feedback line 17 Feedback line reset transistor 18 Feedback line reset transistor control signal 19, 25, 1003 Capacitor 20 Sample transistor 21 Sample transistor control signal 22 Clamp transistor 23 Clamp transistor 23 Control signal 24 Clamp signal line 26 CDS output node 27 Column selection transistor 28 column selection signal 29 column scanning circuit 30 horizontal signal line 31 output amplifier 32 VOUT terminal 33 row scanning circuit 34, 35 row selection signal 36 reset signal 37 pixel reset signal switch 38 pixel address signal switch 39 horizontal scanning signal 40 vertical scanning signal 41 Multiplexer circuit 42 Unit pixel 43 Pixel unit 44 Feedback circuit 45 CDS circuit 46 Feedback selection transistor 50 Timing control circuit 51 Reference voltage generation circuit 52 Sensor chip 60 Reset signal control circuit 61 Amplifier 71 Semiconductor substrate 72, 75, 77 Gate electrodes 73, 74 , 76, 78, 79 Diffusion layer 80 Element isolation region 81 Photoelectric conversion film 82 Pixel electrode 83 Transparent electrode 84 Insulating film 85 Contact 600 Lens 601 Solid-state imaging device 602 Drive circuit 603 Signal processing unit 604 External interface unit 1001, 1002, 1004, 1005, 1006 Resistance element 1007 Resistance value selection signal 1008 Selector

Claims (12)

A plurality of unit pixels arranged in a matrix on a semiconductor substrate;
A vertical signal line provided for each column of the unit pixels;
An inverting amplifier connected to the vertical signal line;
A feedback line provided for each column of the unit pixels in order to feed back the output signal of the inverting amplifier to the unit pixels of the corresponding column;
A reset signal line provided for each row of the unit pixels in order to reset the signal of the unit pixels;
A timing control circuit for generating a reset signal for transmitting the reset signal line;
A reset signal control circuit that adjusts the waveform of the reset signal so as to give a slope to the waveform of the trailing edge of the reset pulse included in the reset signal output from the timing control circuit,
The unit pixel includes an amplification transistor, a selection transistor, a reset transistor, and a photoelectric conversion unit,
The photoelectric conversion unit includes a photoelectric conversion film formed above the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the semiconductor substrate side, and a side opposite to the pixel electrode of the photoelectric conversion film. A transparent electrode formed on the surface of
The amplification transistor has a gate connected to the pixel electrode, a source connected to the vertical signal line, a drain connected to a power supply line,
The reset transistor has a gate connected to the reset signal line, a source connected to the pixel electrode, a drain connected to the feedback line,
The selection transistor is inserted between the source of the amplification transistor and the vertical signal line or between the drain of the amplification transistor and the power line.
The soft reset time from the start of the change of the trailing edge of the reset pulse for controlling on / off of the reset transistor to the time when the reset transistor is turned off is aligned in each of the unit pixels in the same row. The row selection signal supplied to the gate of the selection transistor includes a row selection pulse for controlling on / off of the selection transistor,
2. The solid-state imaging device according to claim 1, wherein the soft reset time is ten times or more of a time from the start of a change in the trailing edge of the row selection pulse to when the selection transistor is turned off. The solid-state imaging device further includes an amplifier provided on the reset signal line,
The solid-state imaging device according to claim 1, wherein a gate of at least one of the reset transistors is connected to the reset signal line via the amplifier. The solid-state imaging device further includes a multiplexer circuit that is provided between the timing control circuit and the unit pixel and selectively supplies the reset signal to the reset signal line corresponding to the unit pixel of a predetermined row,
In the reset signal line, the wiring resistance of the portion connecting the multiplexer circuit and the first unit pixel at a distance close to the multiplexer circuit is the second unit pixel and the first unit pixel at a distance far from the multiplexer circuit. The solid-state imaging device of any one of Claims 1-3. The solid-state imaging device further includes a multiplexer circuit that is provided between the timing control circuit and the unit pixel and selectively supplies the reset signal to the reset signal line corresponding to the unit pixel of a predetermined row,
The gate size of the reset transistor of the unit pixel in the same row is large in the first unit pixel close to the multiplexer circuit and small in the second unit pixel far from the multiplexer circuit. The solid-state imaging device according to any one of the above. The solid-state imaging device further includes a multiplexer circuit that is provided between the timing control circuit and the unit pixel and selectively supplies the reset signal to the reset signal line corresponding to the unit pixel of a predetermined row,
The threshold voltage of the reset transistor of the unit pixel in the same row is high in the first unit pixel close to the multiplexer circuit and low in the second unit pixel far from the multiplexer circuit. The solid-state imaging device according to any one of the above. A plurality of unit pixels arranged in a matrix on a semiconductor substrate;
A vertical signal line provided for each column of the unit pixels;
An inverting amplifier connected to the vertical signal line;
A feedback line provided for each column of the unit pixels in order to feed back the output signal of the inverting amplifier to the unit pixels of the corresponding column;
The unit pixel includes an amplification transistor, a selection transistor, a reset transistor, and a photoelectric conversion unit,
The photoelectric conversion unit includes a photoelectric conversion film formed above the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the semiconductor substrate side, and a side opposite to the pixel electrode of the photoelectric conversion film. A transparent electrode formed on the surface of
The amplification transistor has a gate connected to the pixel electrode, a source connected to the vertical signal line, a drain connected to a power supply line,
The reset transistor has a source connected to the pixel electrode, a drain connected to the feedback line,
The selection transistor is inserted between the source of the amplification transistor and the vertical signal line or between the drain of the amplification transistor and the power line.
The phase of the signal input to the unit pixel of the output signal of the inverting amplifier is aligned in each of the unit pixels in the same column. The solid-state imaging device further includes an amplifier provided on the feedback line,
The solid-state imaging device according to claim 7, wherein a drain of at least one reset transistor is connected to the feedback line via the amplifier. In the feedback line, the wiring resistance of the portion connecting the output of the inverting amplifier and the first unit pixel close to the output of the inverting amplifier is the second unit pixel far from the output of the inverting amplifier and the first unit. The solid-state imaging device according to claim 7 or 8, wherein the solid-state imaging device is larger than a wiring resistance of a portion connecting the pixel. The drain diffusion capacitance of the reset transistor of the unit pixel in the same column is large in the first unit pixel close to the output of the inverting amplifier and small in the second unit pixel far from the output of the inverting amplifier. Item 9. The solid-state imaging device according to Item 7 or 8. The solid-state imaging device according to claim 1, wherein the inverting amplifier is a one-input type. A camera system comprising the solid-state imaging device according to claim 1.

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