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JP2012114260A - Solar cell electrode wire rod and base material thereof and base material manufacturing method - Google Patents

Solar cell electrode wire rod and base material thereof and base material manufacturing method Download PDF

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JP2012114260A
JP2012114260A JP2010262228A JP2010262228A JP2012114260A JP 2012114260 A JP2012114260 A JP 2012114260A JP 2010262228 A JP2010262228 A JP 2010262228A JP 2010262228 A JP2010262228 A JP 2010262228A JP 2012114260 A JP2012114260 A JP 2012114260A
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electrode wire
base material
solar cell
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Kenji Okamoto
健児 岡本
Shin Oikawa
伸 及川
Kishio Akakabe
貴志郎 赤壁
Masato Mitsui
真人 三井
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Mitsubishi Shindoh Co Ltd
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Abstract

【課題】はんだめっきとの密着性が良好で、はんだめっき後も0.2%耐力の上昇が少ない純銅薄板のスリット材で形成されためっき前の太陽電池用電極線材の平角状基材、その製造方法、耐久性に優れた太陽電池用電極線材を提供する。
【解決手段】Cuを99.90質量%以上含む純銅薄板のスリット材で形成され、表面の算術平均粗さRaが0.05〜0.3μm、最大高さRzが0.5〜2.5μm、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が0.06〜1.1であり、EBSD法にて、ステップサイズ0.5μmにて表面の測定面積内の全ピクセルの方位を測定し、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、測定面積の80〜95%であり、測定面積内に存在する結晶粒の面積平均GAMが4°未満である。
【選択図】図1
A flat rectangular base material for an electrode wire for a solar cell before plating, which is formed by a slit material of a pure copper thin plate having good adhesion to solder plating and little increase in 0.2% yield strength after solder plating, A manufacturing method and an electrode wire for solar cells excellent in durability are provided.
It is formed of a pure copper sheet slit material containing 99.90% by mass or more of Cu, and has an arithmetic average roughness Ra of 0.05 to 0.3 μm and a maximum height Rz of 0.5 to 2.5 μm. The ratio of the root mean square roughness Rq to the maximum height Rz (Rq / Rz) is 0.06 to 1.1, and all pixels within the measurement area of the surface with a step size of 0.5 μm by the EBSD method. Of the crystal grains in which the average orientation difference between all the pixels in the crystal grain is less than 4 degrees when the boundary where the orientation difference between adjacent pixels is 5 ° or more is regarded as the grain boundary. The area ratio is 80 to 95% of the measurement area, and the area average GAM of crystal grains existing in the measurement area is less than 4 °.
[Selection] Figure 1

Description

本発明は、太陽電池用電極線材、その基材および基材の製造方法に関し、特に詳しくは、表面に施されるはんだめっきとの密着性が良好であり、はんだめっき後も0.2%耐力の上昇が少ない純銅薄板のスリット材で形成された太陽電池用電極線材用の平角状基材およびその製造方法に関する。   The present invention relates to an electrode wire for solar cells, a base material thereof, and a method for producing the base material, and in particular, has good adhesion to solder plating applied to the surface, and 0.2% yield strength after solder plating. The present invention relates to a flat substrate for a solar cell electrode wire formed of a slit material of a pure copper thin plate with a small increase in the temperature and a method for producing the same.

太陽電池は、通常はPN接合を有するシリコン半導体で形成された半導体基板と、半導体基板の表面に線状に設けられた複数の表面電極に交叉するように形成されたはんだ帯にはんだ付けされた接続用電極線材を備えており、所望の起電力を得るためには、複数の太陽電池を直列に接続して使用される。直列接続は、一つの太陽電池の表面電極に接続用電極線材の一方の表面(下面)をはんだ付けし、他方の表面(上面)を隣接する太陽電池の比較的大きな領域の裏面電極にはんだ付けすることによってなされる。   Solar cells are usually soldered to a semiconductor substrate formed of a silicon semiconductor having a PN junction and a solder band formed so as to cross a plurality of surface electrodes provided linearly on the surface of the semiconductor substrate. A connecting electrode wire is provided, and a plurality of solar cells are connected in series to obtain a desired electromotive force. In series connection, one surface (lower surface) of the connecting electrode wire is soldered to the surface electrode of one solar cell, and the other surface (upper surface) is soldered to the back electrode of a relatively large area of the adjacent solar cell. Made by doing.

接続用電極線材の基材となる平角電極材の製造方法は、タフピッチCu、無酸素Cu、リン脱酸Cu、高純度Cu(99.9999%以上)などの丸形断面の銅線を圧延して平坦状に潰す圧延加工方法、タフピッチCu、無酸素Cu、リン脱酸Cu、高純度Cu(99.9999%以上)などの純銅板を圧延機にて熱間圧延、冷間圧延、焼鈍後にスリッターにより切断するスリット加工方法があり、何れも形成された平角電極材の表面にはんだめっきを施して接続用電極線材が製造されている。   The manufacturing method of the flat electrode material used as the base material for the electrode wire for connection is to roll a copper wire having a round cross section such as tough pitch Cu, oxygen-free Cu, phosphorus deoxidized Cu, and high purity Cu (99.9999% or more). After hot rolling, cold rolling and annealing of pure copper plate such as tough pitch Cu, oxygen free Cu, phosphorus deoxidized Cu, high purity Cu (99.9999% or more) in a rolling mill There is a slit processing method of cutting with a slitter, and the electrode wire for connection is manufactured by performing solder plating on the surface of the formed flat electrode material.

しかし、近年、半導体基板の薄板化に伴って、接続用電極線材を半導体基板にろう付けする際、半導体基板にクラックが入るという問題が生じている。これは接続用電極線材の平角基材となる銅の熱膨張率が半導体基板に比して大きく、ろう付け後の冷却収縮の際に電極線材の収縮が半導体基板に曲げ応力を発生させるからである。   However, in recent years, with the thinning of the semiconductor substrate, there has been a problem that the semiconductor substrate is cracked when the connecting electrode wire is brazed to the semiconductor substrate. This is because the thermal expansion coefficient of copper, which is a flat base material for connecting electrode wires, is larger than that of a semiconductor substrate, and the shrinkage of the electrode wires generates bending stress in the semiconductor substrate during cooling shrinkage after brazing. is there.

これらの問題点を解決するために、特許文献1では、基材の表面に溶融はんだめっきが施された太陽電池用電極線材のめっき前の基材がCuを99.90mass%以上含む純銅の圧延材で形成され、圧延方向の結晶方位<100>、<114>、<112>のX線回折によるピーク強度をそれぞれP<100>、P<114>、P<112>と表すとき、結晶方位のピーク強度比PR(%)=(P<114>+P<112>)・100/(P<100>+P<114>+<112>)が50〜90%とされた、従来よりも優れた塑性変形能を備えた太陽電池用電極線材および基材の製造方法が開示されている。   In order to solve these problems, Patent Document 1 discloses rolling of pure copper in which the base material before plating of the electrode wire for solar cells in which the surface of the base material is subjected to molten solder plating contains 99.90 mass% or more of Cu. When the peak intensities by X-ray diffraction of the crystal orientation <100>, <114>, <112> in the rolling direction are expressed as P <100>, P <114>, P <112>, respectively. The peak intensity ratio PR (%) = (P <114> + P <112>) · 100 / (P <100> + P <114> + <112>) is 50 to 90%, which is superior to the conventional one. A method of manufacturing an electrode wire for solar cells and a base material having plastic deformability is disclosed.

特許文献2では、平角状に形成された導体の表面の一部又は全部にはんだめっきが被覆された太陽電池用はんだめっき線において、導体の引張り試験における0.2%耐力値が90MPa以下であり、かつ導体の結晶粒径が20μm以上300μm以下であり、太陽電池を薄板化した場合でも接続用リード線の接合時に太陽電池の反りもしくは破損が生じにくい太陽電池用はんだめっき線が開示されている。   In Patent Document 2, in a solder plating wire for a solar cell in which a part or all of the surface of a conductor formed in a rectangular shape is coated with solder plating, a 0.2% proof stress value in a conductor tensile test is 90 MPa or less. In addition, there is disclosed a solar cell solder-plated wire that has a conductor crystal grain size of 20 μm or more and 300 μm or less and is less likely to warp or break the solar cell when the connecting lead wire is joined even when the solar cell is thinned. .

特開2009−16593号公報JP 2009-16593 A 特開2008−140787号公報JP 2008-140787 A

特許文献1には、Cuを99.90mass%以上含む純銅板を種々の圧下率で最終圧延し、圧延方向に沿って線状にスリットした後、軟化焼鈍して基材を製造し、従来よりも優れた塑性変形能を備えた太陽電池用電極線基材についての開示はあるが、基材となる平角電極材とその表面に施されるはんだめっきとの密着性の向上やはんだめっき後に形成されるCu−Sn合金層に起因する0.2%耐力の上昇防止対策についての開示はなされていない。
特許文献2では、太陽電池を薄板化した場合でも接続用リード線の接合時に太陽電池の反りもしくは破損が生じにくい太陽電池用はんだめっき線が開示されているが、基材となる平角電極材とその表面に施されるはんだめっきとの密着性の向上やはんだめっき後に形成されるCu−Sn合金層に起因する0.2%耐力の上昇防止対策についての開示はなされていない。
In Patent Document 1, a pure copper plate containing 99.90 mass% or more of Cu is finally rolled at various rolling reductions, slit in a linear shape along the rolling direction, and then softened and annealed to produce a base material. Although there are disclosures about the electrode wire base material for solar cells with excellent plastic deformability, it is improved after adhesion and the adhesion between the flat electrode material used as the base material and the solder plating applied to the surface thereof There is no disclosure of measures for preventing the 0.2% proof stress from increasing due to the Cu—Sn alloy layer.
Patent Document 2 discloses a solar cell solder-plated wire that is less likely to warp or break the solar cell when the connecting lead wire is joined even when the solar cell is thinned. No disclosure has been made about measures for improving the adhesion with solder plating applied to the surface and preventing the 0.2% proof stress from increasing due to the Cu—Sn alloy layer formed after solder plating.

本発明は、表面に施されるはんだめっきとの密着性が良好であり、はんだめっき後も0.2%耐力の上昇が少ない純銅薄板のスリット材で形成されためっき前の太陽電池用電極線材の平角状基材およびその製造方法、並びに、耐久性に優れた太陽電池用電極線材を提供することを目的とする。   The present invention provides an electrode wire for a solar cell before plating, which is formed of a pure copper thin plate slit material having good adhesion to the solder plating applied to the surface and little increase in 0.2% proof stress after solder plating. An object of the present invention is to provide a flat rectangular substrate, a method for producing the same, and an electrode wire for a solar cell excellent in durability.

本発明者らは、上記の事情を鑑みて鋭意検討の結果、Cuを99.90質量%以上含む純銅板に熱間圧延、中間冷間圧延、焼鈍、最終冷間圧延を施して純銅薄板材を作製し、その薄板材を切断機にてスリット加工し、更に最終焼鈍を施して平角状基材を作製し、その表面の一部又は全てにはんだめっきが施された太陽電池用電極線材を製造するに際して、めっき前の平角状基材がCuを99.90質量%以上含む純銅薄板のスリット材で形成され、後方散乱電子回折像システム付の走査型電子顕微鏡によるEBSD法にて、ステップサイズ0.5μmにて平角状基材の表面の測定面積内の全ピクセルの方位を測定し、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、前記測定面積の80〜95%であり、前記測定面積内に存在する結晶粒の面積平均GAMが4°未満であると、はんだめっき後に、その表面に硬くて脆いCu−Sn合金層、主にCuSn層が形成されにくく、はんだめっき後の0.2%耐力の上昇が少ないことを見出した。
Cu−Sn合金層は、はんだめっき密着性を向上させる上で重要なものであるが、硬くて脆く、その形成量が多いとはんだめっき後の太陽電池用電極線材の0.2%耐力が上昇し、ろう付け後の冷却収縮の際に、電極線材の収縮が半導体基板に曲げ応力を発生させ、クラックを発生させる要因となる。
As a result of intensive investigations in view of the above circumstances, the inventors of the present invention have been subjected to hot rolling, intermediate cold rolling, annealing, and final cold rolling on a pure copper plate containing 99.90% by mass or more of Cu, and a pure copper sheet material A thin plate material is slit with a cutting machine, and further subjected to final annealing to produce a flat base material, and a solar cell electrode wire having a part or all of its surface plated with solder. When manufacturing, a rectangular base material before plating is formed of a pure copper thin plate slit material containing 99.90% by mass or more of Cu, and the step size is measured by an EBSD method using a scanning electron microscope with a backscattered electron diffraction image system. Crystal grains when measuring the orientation of all pixels within the measurement area of the surface of a flat substrate at 0.5 μm and considering a boundary where the orientation difference between adjacent pixels is 5 ° or more as a grain boundary The average azimuth difference between all pixels is 4 ° When the area ratio of the crystal grains that are full is 80 to 95% of the measurement area and the area average GAM of the crystal grains existing in the measurement area is less than 4 °, the surface is hard after solder plating. And a brittle Cu—Sn alloy layer, mainly a Cu 6 Sn 5 layer, was hardly formed, and it was found that the 0.2% yield strength increase after solder plating was small.
The Cu-Sn alloy layer is important for improving the solder plating adhesion, but it is hard and brittle. If the amount of the Cu-Sn alloy layer is large, the 0.2% yield strength of the electrode wire for solar cells after solder plating increases. However, during the cooling shrinkage after brazing, the shrinkage of the electrode wire material causes a bending stress in the semiconductor substrate and causes a crack.

また、平角状基材の表面の算術平均粗さRaが0.05〜0.3μmであり、最大高さRzが0.5〜2.5μmであり、二乗平均平方根粗さRqと最大高さRzの比Rq/Rzが0.06〜1.1であると、平角状基材の表面の一部又は全てに施されるはんだめっきとの密着性が向上し、太陽電池用電極線材の厳しい使用条件化でもはんだめっきが剥離せずに耐久性が向上することも見出した。   In addition, the arithmetic average roughness Ra of the surface of the flat substrate is 0.05 to 0.3 μm, the maximum height Rz is 0.5 to 2.5 μm, and the root mean square roughness Rq and the maximum height. When the ratio Rq / Rz of Rz is 0.06 to 1.1, the adhesion with solder plating applied to part or all of the surface of the flat substrate is improved, and the electrode wire for solar cells is severe. It has also been found that the durability is improved without peeling of the solder plating even under use conditions.

即ち、本発明の太陽電池用電極線材のめっき前の平角状基材は、表面の一部又は全てにはんだめっきが施された太陽電池用電極線材のめっき前の平角状基材であり、Cuを99.90質量%以上含む純銅薄板のスリット材で形成され、表面の算術平均粗さRaが0.05〜0.3μmであり、最大高さRzが0.5〜2.5μmであり、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が0.06〜1.1であり、後方散乱電子回折像システム付の走査型電子顕微鏡によるEBSD法にて、ステップサイズ0.5μmにて表面の測定面積内の全ピクセルの方位を測定し、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、前記測定面積の80〜95%であり、前記測定面積内に存在する結晶粒の面積平均GAMが4°未満であることを特徴とする。   That is, the flat substrate before plating of the electrode wire for solar cell of the present invention is a flat substrate before plating of the electrode wire for solar cell in which a part or all of the surface is solder-plated, Cu Is formed of a slit material of a pure copper thin plate containing 99.90% by mass or more, the arithmetic average roughness Ra of the surface is 0.05 to 0.3 μm, and the maximum height Rz is 0.5 to 2.5 μm. The ratio of the root mean square roughness Rq to the maximum height Rz (Rq / Rz) is 0.06 to 1.1, and the step size is 0 by the EBSD method using a scanning electron microscope with a backscattered electron diffraction image system. When measuring the orientation of all the pixels within the measurement area of the surface at 5 μm and considering the boundary where the orientation difference between adjacent pixels is 5 ° or more as the grain boundary, between all the pixels in the crystal grain The area ratio of crystal grains with an average misorientation of less than 4 ° is It is 80 to 95% of the measurement area, and the area average GAM of the crystal grains existing in the measurement area is less than 4 °.

この場合、平角状基材の表面の算術平均粗さRaが0.05μm未満、或いは、最大高さRzが0.5μm未満、或いは、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が0.06未満であると、その表面の一部又は全てに施されるはんだめっきとの密着性が悪くなる。平角状基材の表面の算術平均粗さRaが0.3μmを超える、或いは、最大高さRzが2.5μmを超える、或いは、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が1.1を超えると、その表面の一部又は全てに施されるはんだめっきとの密着性、特に、耐熱剥離性が悪くなり不都合となる。   In this case, the arithmetic average roughness Ra of the surface of the rectangular substrate is less than 0.05 μm, or the maximum height Rz is less than 0.5 μm, or the ratio of the root mean square roughness Rq to the maximum height Rz (Rq If / Rz) is less than 0.06, the adhesion with the solder plating applied to a part or all of the surface is deteriorated. Arithmetic average roughness Ra of the surface of the rectangular substrate exceeds 0.3 μm, or maximum height Rz exceeds 2.5 μm, or ratio of root mean square roughness Rq to maximum height Rz (Rq / If Rz) exceeds 1.1, adhesion to solder plating applied to a part or all of the surface, particularly heat-resistant peelability, is deteriorated, which is inconvenient.

また、後方散乱電子回折像システム付の走査型電子顕微鏡によるEBSD法にて、ステップサイズ0.5μmにて表面の測定面積内の全ピクセルの方位を測定し、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、測定面積の80%未満では、0.2%耐力に関する効果がなく、測定面積の95%を超える、或いは、測定面積内に存在する結晶粒の面積平均GAMが4°以上であると、はんだめっきとの密着性が悪くなる。
ここで、本発明で意味する測定面積内に存在する結晶粒の面積平均GAMとは、次の手法により算出したものである。
GAMは同一結晶粒内における隣接する測定点(ピクセル)間のミスオリエンテーションの平均値であり、隣接測定点の境界iにおける方位差を(1)式とすると、結晶粒内にピクセル間の境界がm個存在する場合、この結晶粒のGAM値は(2)式で表される。
Further, the azimuth of all the pixels within the measurement area of the surface is measured with a step size of 0.5 μm by an EBSD method using a scanning electron microscope with a backscattered electron diffraction image system, and the azimuth difference between adjacent pixels is 5 When the boundary that is greater than or equal to ° is regarded as a crystal grain boundary, the area ratio of crystal grains having an average orientation difference between all the pixels in the crystal grains of less than 4 ° is less than 80% of the measured area, and is 0.2. If there is no effect on% proof stress and the measured area exceeds 95% or the area average GAM of the crystal grains existing in the measured area is 4 ° or more, the adhesion with the solder plating deteriorates.
Here, the area average GAM of the crystal grains existing within the measurement area meant in the present invention is calculated by the following method.
GAM is the average value of misorientation between adjacent measurement points (pixels) in the same crystal grain. When the difference in orientation at the boundary i between adjacent measurement points is expressed by equation (1), the boundary between pixels in the crystal grain is When m exist, the GAM value of this crystal grain is expressed by the equation (2).

Figure 2012114260
Figure 2012114260

Figure 2012114260
Figure 2012114260

個々の結晶粒におけるGAMの値を(GAM)、各結晶粒の面積をSとすると、測定範囲内にM個の結晶粒が存在する場合、面積平均GAMは(3)式で表される。 When the value of the GAM in individual grains (GAM) k, the area of each crystal grain and S k, if there are M grain within the measurement range, area average GAM is expressed by equation (3) The

Figure 2012114260
Figure 2012114260

また、本発明の太陽電池用電極線材のめっき前の平角状基材の製造方法は、Cuを99.90質量%以上含む純銅板に熱間圧延、中間冷間圧延、焼鈍、最終冷間圧延をこの順で施して純銅薄板とし、当該薄板を切断機にてスリット加工して平角状基材とし、当該平角状基材を最終焼鈍して太陽電池用電極線材のめっき前の平角状基材を製造する方法において、前記中間冷間圧延の圧下率を50〜70%にて実施し、前記最終冷間圧延の圧下率を50〜70%にて実施し、前記最終焼鈍を700〜900℃の雰囲気に5〜60秒間保持して行なうことを特徴とする。   Moreover, the manufacturing method of the flat base material before plating of the electrode wire for solar cells of this invention is hot rolling, intermediate | middle cold rolling, annealing, and final cold rolling to the pure copper plate which contains 99.90 mass% or more of Cu. Are made in this order to form a pure copper thin plate, and the thin plate is slit by a cutting machine to form a flat rectangular substrate, and the flat rectangular substrate is finally annealed to plate the flat electrode substrate for solar cell electrode wire. The rolling reduction of the intermediate cold rolling is performed at 50 to 70%, the rolling reduction of the final cold rolling is performed at 50 to 70%, and the final annealing is performed at 700 to 900 ° C. It is characterized in that it is carried out in an atmosphere of 5 to 60 seconds.

この場合、中間冷間圧延の圧下率を50〜70%にて実施することにより、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合と測定面積内に存在する結晶粒の面積平均GAMを所定内の範囲に収める素地をつくり、最終焼鈍を700〜900℃での雰囲気に5〜60秒間保持することにより、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合と測定面積内に存在する結晶粒の面積平均GAMを所定内の範囲に収める。
中間冷間圧延の圧下率が50%未満、或いは、70%を超えると素地効果は不足し、最終焼鈍の温度が700℃未満、或いは、時間が5秒未満では、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、測定面積の80%未満となり、最終焼鈍の温度が900℃を超える、或いは、時間が60秒を超えると、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、測定面積の95%を超える、或いは、測定面積内に存在する結晶粒の面積平均GAMが4°以上となる。
In this case, by carrying out the rolling reduction of the intermediate cold rolling at 50 to 70%, the boundary in which the orientation difference between adjacent pixels is 5 ° or more is regarded as the crystal grain boundary. Create a substrate that keeps the area ratio of crystal grains whose average orientation difference between all pixels is less than 4 ° and the area average GAM of crystal grains existing in the measurement area within a predetermined range, and final annealing at 700 to 900 ° C. Is held in the atmosphere for 5 to 60 seconds, the average orientation difference between all the pixels in the crystal grain is 4 ° when a boundary where the orientation difference between adjacent pixels is 5 ° or more is regarded as a grain boundary. The area ratio of the crystal grains that are less than the average area and the area average GAM of the crystal grains existing in the measurement area are within a predetermined range.
If the rolling reduction of the intermediate cold rolling is less than 50% or more than 70%, the substrate effect is insufficient, and if the final annealing temperature is less than 700 ° C. or the time is less than 5 seconds, the orientation difference between adjacent pixels When the boundary where the angle is 5 ° or more is regarded as the crystal grain boundary, the area ratio of the crystal grains in which the average orientation difference between all the pixels in the crystal grains is less than 4 ° is less than 80% of the measured area. When the annealing temperature exceeds 900 ° C. or the time exceeds 60 seconds, the area ratio of the crystal grains in which the average orientation difference between all the pixels in the crystal grains is less than 4 ° exceeds 95% of the measurement area. Alternatively, the area average GAM of the crystal grains existing in the measurement area is 4 ° or more.

また、最終冷間圧延の圧下率を50〜70%にて実施することにより、平角状基材の表面の算術平均粗さRaが0.05〜0.3μmであり、最大高さRzが0.5〜2.5μmであり、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が0.06〜1.1となる。
最終冷間圧延の圧下率が50%未満では、最適に選択された圧延ワークロールの表面粗さが被圧延物である純銅薄板の表面粗さに反映されず、平角状基材の表面の算術平均粗さRa、最大高さRz、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)を上記の所定の範囲内に収めることが出来ず、圧下率が70%を超えると、効果が飽和するばかりでなく、平角状基材の耐力に悪影響を及ぼす可能性がある。また、最終冷間圧延の圧下率を50〜70%とすることにより、その後のスリット加工が容易になり、スリット加工材にバリが発生し難くなるという副次的効果もある。
Further, by carrying out the rolling reduction of the final cold rolling at 50 to 70%, the arithmetic average roughness Ra of the surface of the flat substrate is 0.05 to 0.3 μm, and the maximum height Rz is 0. The ratio of the root mean square roughness Rq to the maximum height Rz (Rq / Rz) is 0.06 to 1.1.
When the rolling reduction of the final cold rolling is less than 50%, the surface roughness of the optimally selected rolling work roll is not reflected in the surface roughness of the pure copper sheet as the rolled material, and the surface of the flat base material is arithmetic If the average roughness Ra, maximum height Rz, root mean square roughness Rq and maximum height Rz ratio (Rq / Rz) cannot fall within the predetermined range, and the rolling reduction exceeds 70% In addition to saturation of the effect, there is a possibility of adversely affecting the yield strength of the flat substrate. Further, by setting the reduction ratio of the final cold rolling to 50 to 70%, there is a secondary effect that subsequent slit processing becomes easy and burrs are hardly generated in the slit processed material.

更に、本発明の太陽電池用電極線材は、本発明の製造方法により製造された太陽電池用電極線材のめっき前の平角状基材の表面の一部又は全てに、はんだめっきを40〜150μmの厚さに施すことにより製造されたことを特徴とする。
この場合、めっき厚が40μm未満であるとめっき密着性が不足し、めっき厚が150μmを超えると太陽電池用電極線材の耐力が大きくなり、シリコンセルの反りに悪影響を及ぼす。
また、はんだめっきは、製造コストおよび太陽電池用電極線材の耐力の変動を少なくする観点から、平角状基材の最終焼鈍がなされた直後に連続して施されることが好ましく、はんだめっき浴の下流側に大径の巻き取りドラムを設けておき、最終焼鈍が施された直後の平角状基材をはんだ合金の融点より50〜100℃程度高い温度に調整されたはんだめっき浴に通し、適切な張力を掛けて引っ張りながら巻き取り、これにより平角状基材をはんだめっき浴に連続的に浸漬し、引き上げる方法により行われることが製造コストの観点から好ましい。この場合、平角状基材に張力が掛かり、はんだめっき後の太陽電池用電極線材の耐力が上昇するので張力の調整に注意を要する。
Furthermore, the electrode wire for solar cells of the present invention has a solder plating of 40 to 150 μm on part or all of the surface of the flat substrate before plating of the electrode wire for solar cells manufactured by the manufacturing method of the present invention. It was manufactured by applying to thickness.
In this case, when the plating thickness is less than 40 μm, the plating adhesion is insufficient, and when the plating thickness exceeds 150 μm, the proof stress of the solar cell electrode wire is increased, which adversely affects the warpage of the silicon cell.
Moreover, it is preferable that the solder plating is performed continuously immediately after the final annealing of the flat base material from the viewpoint of reducing the manufacturing cost and the fluctuation in the yield strength of the electrode wire for solar cells. A large-diameter winding drum is provided on the downstream side, and the rectangular substrate immediately after the final annealing is passed through a solder plating bath adjusted to a temperature higher by about 50 to 100 ° C. than the melting point of the solder alloy, From the viewpoint of production cost, it is preferable to wind the film while pulling it with a proper tension, thereby immersing the flat substrate in a solder plating bath and pulling it up. In this case, tension is applied to the flat base material, and the proof stress of the solar cell electrode wire after solder plating is increased, so care must be taken in adjusting the tension.

本発明により、はんだめっきとの密着性が良好であり、はんだめっき後も0.2%耐力の上昇が少ない純銅薄板のスリット材で形成されためっき前の太陽電池用電極線材の平角状基材およびその製造方法、並びに、耐久性に優れた太陽電池用電極線材が提供される。   According to the present invention, a flat base material for an electrode wire for a solar cell before plating, which is formed of a slit material of a pure copper thin plate having good adhesion to solder plating and little increase in 0.2% proof stress after solder plating In addition, a solar cell electrode wire excellent in durability is provided.

本発明の太陽電池用電極線材のめっき前の平角状基材の横断面図である。It is a cross-sectional view of the flat base material before plating of the solar cell electrode wire of the present invention. 本発明の太陽電池用電極線材を所定の長さに切断した接続用リードを備えた太陽電池の概略図である。It is the schematic of the solar cell provided with the connection lead which cut | disconnected the electrode wire for solar cells of this invention by predetermined length.

以下、図面を参照に、本発明の太陽電池用電極線材、その基材と製造方法の一実施形態について説明する。
図1は、本発明の太陽電池用電極線材の横断面を示しており、太陽電池用電極線材1はCuを99.90質量%以上含む純銅で形成された方形断面を有する平角状基材2と、この平角状基材2の表面の一部又は全てに40〜150μmの厚さに施されたはんだめっき層3とからなる。
Hereinafter, with reference to drawings, one embodiment of the electrode wire for solar cells of the present invention, its substrate, and a manufacturing method is described.
FIG. 1 shows a cross section of a solar cell electrode wire according to the present invention. A solar cell electrode wire 1 has a rectangular base 2 having a square cross section formed of pure copper containing 99.90% by mass or more of Cu. And a solder plating layer 3 applied to a part or all of the surface of the flat substrate 2 to a thickness of 40 to 150 μm.

平角状基材2は、Cu含有量が99.90質量%以上であり、好ましくは99.99質量%以上のものがよい。また、不純物としては、As、Sb、Bi、Pb、S、Fe、O、Pなどが含まれるが、特にO、Pは微量で塑性変形能が低下するため、O量は0〜500ppm、好ましくは0〜100ppmとし、P量は0〜150ppm、好ましくは0〜50ppmに規制することが望ましい。タプピッチ銅、無酸素銅、リン脱酸銅は上記成分を満足するため好適な素材である。   The flat substrate 2 has a Cu content of 99.90% by mass or more, preferably 99.99% by mass or more. Further, as impurities, As, Sb, Bi, Pb, S, Fe, O, P, etc. are included. Particularly, since O and P are small amounts and the plastic deformability is reduced, the amount of O is preferably 0 to 500 ppm, preferably Is 0 to 100 ppm, and the P content is 0 to 150 ppm, preferably 0 to 50 ppm. Tappitch copper, oxygen-free copper, and phosphorus deoxidized copper are suitable materials because they satisfy the above components.

この平角状基材2は、上記のCuを99.90質量%以上含む純銅板に熱間圧延、中間冷間圧延、焼鈍、最終冷間圧延をこの順で施して純銅薄板とし、その薄板を切断機にてスリット加工して平角状基材とし、その平角状基材を最終焼鈍することにより製造され、その表面の算術平均粗さRaが0.05〜0.3μmであり、最大高さRzが0.5〜2.5μmであり、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が0.06〜1.1であり、、後方散乱電子回折像システム付の走査型電子顕微鏡によるEBSD法にて、ステップサイズ0.5μmにて平角状基材2の表面の測定面積内の全ピクセルの方位を測定し、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、前記測定面積の80〜95%であり、前記測定面積内に存在する結晶粒の面積平均GAMが4°未満である。   The flat substrate 2 is obtained by subjecting a pure copper plate containing 99.90% by mass or more of Cu to hot rolling, intermediate cold rolling, annealing, and final cold rolling in this order to form a pure copper thin plate. It is manufactured by slitting with a cutting machine to form a flat substrate, and the flat substrate is finally annealed. The arithmetic average roughness Ra of the surface is 0.05 to 0.3 μm, and the maximum height Rz is 0.5 to 2.5 μm, the ratio of the root mean square roughness Rq to the maximum height Rz (Rq / Rz) is 0.06 to 1.1, and the backscattered electron diffraction image system is attached. The orientation of all pixels within the measurement area of the surface of the flat substrate 2 is measured with a step size of 0.5 μm by an EBSD method using a scanning electron microscope, and the orientation difference between adjacent pixels is 5 ° or more. Between all pixels in a crystal grain when the boundary is regarded as a grain boundary Area ratio of crystal grains average misorientation is less than 4 ° is a 80% to 95% of the measured area, the crystal grains of the area average GAM that existing in the measurement area is less than 4 °.

ここで、後方散乱電子回折像システム付の走査型電子顕微鏡によるEBSD法にて、ステップサイズ0.5μmにて平角状基材2の表面の測定面積内の全ピクセルの方位を測定し、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、測定面積の80%未満では、0.2%耐力に対する効果がなく、測定面積の95%を超える、或いは、測定面積内に存在する結晶粒の面積平均GAMが4°以上となると、はんだめっきとの密着性が悪くなる。
本発明で意味する測定面積内に存在する結晶粒の面積平均GAMとは、次の手法により算出したものである。
GAMは同一結晶粒内における隣接する測定点(ピクセル)間のミスオリエンテーションの平均値であり、隣接測定点の境界iにおける方位差を(1)式とすると、結晶粒内にピクセル間の境界がm個存在する場合、この結晶粒のGAM値は(2)式で表される。
Here, by the EBSD method using a scanning electron microscope with a backscattered electron diffraction image system, the orientations of all the pixels within the measurement area of the surface of the flat substrate 2 are measured with a step size of 0.5 μm and adjacent to each other. When a boundary having an orientation difference between pixels of 5 ° or more is regarded as a grain boundary, an area ratio of crystal grains having an average orientation difference between all pixels in the crystal grain of less than 4 ° is 80% of the measurement area. If it is less than%, there is no effect on 0.2% proof stress, and if it exceeds 95% of the measurement area, or if the area average GAM of the crystal grains present in the measurement area is 4 ° or more, the adhesion with the solder plating is Deteriorate.
The area average GAM of crystal grains existing within the measurement area as used in the present invention is calculated by the following method.
GAM is the average value of misorientation between adjacent measurement points (pixels) in the same crystal grain. When the difference in orientation at the boundary i between adjacent measurement points is expressed by equation (1), the boundary between pixels in the crystal grain is When m exist, the GAM value of this crystal grain is expressed by the equation (2).

Figure 2012114260
Figure 2012114260

Figure 2012114260
Figure 2012114260

個々の結晶粒におけるGAMの値を(GAM)、各結晶粒の面積をSとすると、測定範囲内にM個の結晶粒が存在する場合、面積平均GAMは(3)式で表される。 When the value of the GAM in individual grains (GAM) k, the area of each crystal grain and S k, if there are M grain within the measurement range, area average GAM is expressed by equation (3) The

Figure 2012114260
Figure 2012114260

また、平角状基材2の表面の算術平均粗さRaが0.05μm未満、或いは、最大高さRzが0.5μm未満、或いは、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が0.06未満であると、その表面の一部又は全てに施されるはんだめっき又は溶融はんだめっきとの密着性が悪くなる。平角状基材2の表面の算術平均粗さRaが0.3μmを超える、或いは、最大高さRzが2.5μmを超える、或いは、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が1.1を超えると、その表面の一部又は全てに施されるはんだめっきとの密着性、特に、耐熱剥離性が悪くなる。   Further, the arithmetic average roughness Ra of the surface of the flat substrate 2 is less than 0.05 μm, the maximum height Rz is less than 0.5 μm, or the ratio of the root mean square roughness Rq to the maximum height Rz (Rq When / Rz) is less than 0.06, the adhesion with solder plating or hot-dip solder plating applied to a part or all of the surface is deteriorated. The arithmetic average roughness Ra of the surface of the flat substrate 2 exceeds 0.3 μm, or the maximum height Rz exceeds 2.5 μm, or the ratio of the root mean square roughness Rq to the maximum height Rz (Rq If / Rz) exceeds 1.1, adhesion to solder plating applied to a part or all of the surface, particularly heat-resistant peelability, deteriorates.

はんだめっき層3の厚みは、40〜150μmであり、めっき厚が40μm未満であるとめっき密着性が不足し、めっき厚が150μmを超えると太陽電池用電極線材の耐力が大きくなり、シリコンセルの反りに悪影響を及ぼす。
はんだめっきは、Sn系はんだ、または第2成分としてPb、In、Bi、Sb、Ag、Zn、Ni、Cuから選択される少なくとも1種の元素を0.1質量%以上含むSn系合金はんだとする。
The thickness of the solder plating layer 3 is 40 to 150 μm. If the plating thickness is less than 40 μm, the plating adhesion is insufficient, and if the plating thickness exceeds 150 μm, the yield strength of the solar cell electrode wire increases, It has an adverse effect on warpage.
Solder plating includes Sn-based solder or Sn-based alloy solder containing 0.1% by mass or more of at least one element selected from Pb, In, Bi, Sb, Ag, Zn, Ni, and Cu as a second component. To do.

また、はんだめっきは、製造コストおよび設備面から、溶融はんだめっきであることが特に好ましく、融点が130〜300℃程度のSn−Pb合金、Sn−(0.5〜5質量%)Ag合金、Sn−(0.5〜5質量%)Ag−(0.3〜1.0質量%)Cu合金、Sn−(0.3〜1.0質量%)Cu合金、Sn−(1.0〜5.0質量%)Ag−(5〜8質量%)In合金、Sn−(1.0〜5.0質量%)Ag−(40〜50質量%)Bi合金、Sn−(40〜50質量%)Bi合金、Sn−(1.0〜5.0質量%)Ag−(40〜50質量%)Bi−(5〜8質量%)In合金などが使用される。Pbは人体に有害であり、自然環境を汚染するおそれがあるので、汚染防止の観点からはPbフリーのSn−Ag合金、Sn−Ag−Cu合金、Sn−Cu合金、Sn−Ag−In合金、Sn−Ag−Bi合金などのはんだ材が特に好ましい。
また、各はんだ材において、溶融はんだ自体の酸化防止のため、50〜200ppm程度のP、数〜数10ppmのGa、数〜数10ppmのGd、数〜数10ppmのGeの内から1種または2種以上を添加することができる。
In addition, the solder plating is particularly preferably a molten solder plating from the viewpoint of manufacturing cost and equipment, and a Sn—Pb alloy having a melting point of about 130 to 300 ° C., a Sn— (0.5 to 5 mass%) Ag alloy, Sn- (0.5-5 mass%) Ag- (0.3-1.0 mass%) Cu alloy, Sn- (0.3-1.0 mass%) Cu alloy, Sn- (1.0- 5.0 mass%) Ag- (5-8 mass%) In alloy, Sn- (1.0-5.0 mass%) Ag- (40-50 mass%) Bi alloy, Sn- (40-50 mass%) %) Bi alloy, Sn- (1.0-5.0 mass%) Ag- (40-50 mass%) Bi- (5-8 mass%) In alloy, etc. are used. Since Pb is harmful to the human body and may contaminate the natural environment, Pb-free Sn—Ag alloy, Sn—Ag—Cu alloy, Sn—Cu alloy, Sn—Ag—In alloy are used from the viewpoint of pollution prevention. A solder material such as Sn—Ag—Bi alloy is particularly preferable.
Moreover, in each solder material, in order to prevent oxidation of the molten solder itself, one or two of P of about 50 to 200 ppm, Ga of several to several tens of ppm, Gd of several to several tens of ppm, and Ge of several to several tens of ppm are used. More seeds can be added.

このような平角状基材2は、Cuを99.90質量%以上含む純銅板に熱間圧延、中間冷間圧延、焼鈍、最終冷間圧延をこの順で施して純銅薄板とし、その薄板を切断機にてスリット加工して平角状基材とし、その平角状基材を最終焼鈍して製造されるが、中間冷間圧延の圧下率を50〜70%にて実施し、最終冷間圧延の圧下率を50〜70%にて実施し、最終焼鈍を700〜900℃で5〜60秒間実施することが重要である。   Such a flat substrate 2 is obtained by subjecting a pure copper plate containing 99.90% by mass or more of Cu to hot rolling, intermediate cold rolling, annealing, and final cold rolling in this order to form a pure copper thin plate. It is manufactured by slitting with a cutting machine to form a flat base material, and the flat base material is finally annealed. The rolling reduction of the intermediate cold rolling is performed at 50 to 70%, and the final cold rolling is performed. It is important that the rolling reduction is performed at 50 to 70% and the final annealing is performed at 700 to 900 ° C. for 5 to 60 seconds.

この場合、中間冷間圧延の圧下率を50〜70%にて実施することにより、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合と測定面積内に存在する結晶粒の面積平均GAMを所定内の範囲に収める素地をつくり、最終焼鈍を700〜900℃の雰囲気に5〜60秒間保持して行なうことにより、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合と測定面積内に存在する結晶粒の面積平均GAMを所定内の範囲に収める。
中間冷間圧延の圧下率が50%未満、或いは、70%を超えると、前述した平均方位差が4°未満である結晶粒の面積割合と面積平均GAMを所定内の範囲に収めるための素地をつくる効果(素地効果)は不足し、最終焼鈍の雰囲気温度が700℃未満、或いは、時間が5秒未満では、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、測定面積の80%未満となり、最終焼鈍の雰囲気温度が900℃を超える、或いは、時間が60秒を超えると、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、測定面積の95%を超える、或いは、測定面積内に存在する結晶粒の面積平均GAMが4°以上となる。
In this case, by carrying out the rolling reduction of the intermediate cold rolling at 50 to 70%, the boundary in which the orientation difference between adjacent pixels is 5 ° or more is regarded as the crystal grain boundary. Create a substrate that keeps the area ratio of crystal grains whose average orientation difference between all pixels is less than 4 ° and the area average GAM of crystal grains existing in the measurement area within a predetermined range, and the final annealing is 700 to 900 ° C. By maintaining the atmosphere in the atmosphere for 5 to 60 seconds, the average orientation difference between all the pixels in the crystal grain is 4 when the boundary where the orientation difference between adjacent pixels is 5 ° or more is regarded as the grain boundary. The area ratio of crystal grains that are less than 0 ° and the area average GAM of crystal grains existing in the measurement area are within a predetermined range.
When the rolling reduction ratio of intermediate cold rolling is less than 50% or more than 70%, the above-mentioned base ratio for keeping the area ratio of the crystal grains whose average orientation difference is less than 4 ° and the area average GAM within a predetermined range If the atmosphere temperature of the final annealing is less than 700 ° C or the time is less than 5 seconds, the boundary where the orientation difference between adjacent pixels is 5 ° or more is regarded as a grain boundary. In this case, the area ratio of the crystal grains in which the average orientation difference between all the pixels in the crystal grains is less than 4 ° is less than 80% of the measurement area, and the atmosphere temperature of the final annealing exceeds 900 ° C., or the time Exceeds 60 seconds, the area ratio of the crystal grains in which the average orientation difference between all the pixels in the crystal grains is less than 4 ° exceeds 95% of the measurement area, or the crystal grains existing within the measurement area The area average GAM is 4 ° or more.

また、最終冷間圧延の圧下率を50〜70%にて実施することにより、平角状基材の表面の算術平均粗さRaが0.05〜0.3μmであり、最大高さRzが0.5〜2.5μmであり、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が0.06〜1.1となる。
最終冷間圧延の圧下率が50%未満では、最適に選択された圧延ワークロールの表面粗さが被圧延物である純銅薄板の表面粗さに反映されず、平角状基材の表面の算術平均粗さRa、最大高さRz、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)を上記の所定の範囲内に収めることが出来ず、圧下率が70%を超えると、効果が飽和するばかりでなく、平角状基材の耐力に悪影響を及ぼす可能性がある。また、最終冷間圧延の圧下率を50〜70%とすることにより、その後のスリット加工が容易になり、スリット加工材にバリが発生し難くなるという副次的効果もある。
Further, by carrying out the rolling reduction of the final cold rolling at 50 to 70%, the arithmetic average roughness Ra of the surface of the flat substrate is 0.05 to 0.3 μm, and the maximum height Rz is 0. The ratio of the root mean square roughness Rq to the maximum height Rz (Rq / Rz) is 0.06 to 1.1.
When the rolling reduction of the final cold rolling is less than 50%, the surface roughness of the optimally selected rolling work roll is not reflected in the surface roughness of the pure copper sheet as the rolled material, and the surface of the flat base material is arithmetic If the average roughness Ra, maximum height Rz, root mean square roughness Rq and maximum height Rz ratio (Rq / Rz) cannot fall within the predetermined range, and the rolling reduction exceeds 70% In addition to saturation of the effect, there is a possibility of adversely affecting the yield strength of the flat substrate. Further, by setting the reduction ratio of the final cold rolling to 50 to 70%, there is a secondary effect that subsequent slit processing becomes easy and burrs are hardly generated in the slit processed material.

この様にして製造された平角状基材2の表面の一部又は全てに40〜150μmの厚さに施されたはんだめっき層3を形成するには、平角状基材2を所定長さに切断した後、この短尺基材にはんだめっきを施す方法よりも、はんだめっき浴の下流側に大径の巻き取りドラムを設けておき、最終焼鈍が施された直後の平角状基材2をはんだ合金の融点より50〜100℃程度高い温度に調整されたはんだめっき浴に通し、適切な張力を掛けて引っ張りながら巻き取り、これにより平角状基材2をはんだめっき浴に連続的に浸漬し、引き上げる方法により行われることが製造コストの観点から好ましい。この場合、平角状基材2に張力が掛かり、はんだめっき後の太陽電池用電極線材1の耐力が上昇するので張力の調整に注意を要する。   In order to form the solder plating layer 3 having a thickness of 40 to 150 μm on a part or all of the surface of the flat substrate 2 manufactured in this way, the flat substrate 2 is formed to a predetermined length. After cutting, a large-diameter winding drum is provided on the downstream side of the solder plating bath, rather than the method of performing solder plating on this short substrate, and the rectangular substrate 2 immediately after final annealing is soldered. It is passed through a solder plating bath adjusted to a temperature about 50-100 ° C. higher than the melting point of the alloy, wound while pulling with an appropriate tension, whereby the flat substrate 2 is continuously immersed in the solder plating bath, It is preferable from a viewpoint of manufacturing cost to be performed by the method of pulling up. In this case, tension is applied to the flat rectangular base material 2, and the proof stress of the solar cell electrode wire 1 after solder plating is increased, so care must be taken in adjusting the tension.

図2は、本発明の太陽電池用電極線材1を所定の長さに切断した接続用リード14を備えた太陽電池の概略図であり、この太陽電池11は、PN接合を有するシリコン半導体で形成された半導体基板12と、半導体基板12の表面に線状に設けられた複数の表面電極13にはんだ付けされた接続用リード線14を備えている。半導体基板12の裏面には、40〜80mm程度の大形表面の裏面電極が複数個設けられている。接続用リード線14がはんだ付けされる前の半導体基板12には、複数の線状表面電極13に導通するように、これらの表面電極13に直交して配置されたはんだ帯が形成されている。太陽電池用電極線材1のめっき層3をはんだ帯に当接するように接続用リード線14を半導体基板12に載置し、半導体基板12の表面にはんだ付けされる。 FIG. 2 is a schematic view of a solar cell provided with a connection lead 14 obtained by cutting the solar cell electrode wire 1 of the present invention into a predetermined length. The solar cell 11 is formed of a silicon semiconductor having a PN junction. And a connecting lead wire 14 soldered to a plurality of surface electrodes 13 linearly provided on the surface of the semiconductor substrate 12. On the back surface of the semiconductor substrate 12, a plurality of back electrodes having a large surface of about 40 to 80 mm 2 are provided. On the semiconductor substrate 12 before the connection lead wires 14 are soldered, solder bands arranged perpendicular to the surface electrodes 13 are formed so as to be electrically connected to the plurality of linear surface electrodes 13. . The connecting lead wire 14 is placed on the semiconductor substrate 12 so that the plating layer 3 of the solar cell electrode wire 1 is in contact with the solder band, and is soldered to the surface of the semiconductor substrate 12.

厚さ3.0mmの三菱マテリアル株式会社製の無酸素銅板(Cu:99.96%、O:5ppm、P:0ppm)およびタフピッチ銅(Cu:99.92%、O:300ppm、P:0ppm)板に、熱間圧延、中間冷間圧延(圧下率は表1に示す)、焼鈍をこの順で施して無酸素銅薄板およびタフピッチ銅薄板を作製し、次に、最終冷間圧延(圧下率は表1に示す)を実施して厚み0.15mmの無酸素銅薄板およびタフピッチ銅薄板を得た。次に、これらの無酸素銅薄板およびタフピッチ銅薄板を切断機にてスリット加工し、幅2mmの平角状薄板とした。更に、これらの平角状薄板を表1に示す条件にて最終焼鈍を施し、実施例1〜6、比較例1〜6のめっき前の平角状基材を得た。   An oxygen-free copper plate (Cu: 99.96%, O: 5 ppm, P: 0 ppm) and tough pitch copper (Cu: 99.92%, O: 300 ppm, P: 0 ppm) manufactured by Mitsubishi Materials Corporation with a thickness of 3.0 mm The plate is subjected to hot rolling, intermediate cold rolling (the rolling reduction is shown in Table 1) and annealing in this order to produce an oxygen-free copper sheet and a tough pitch copper sheet, and then the final cold rolling (rolling ratio) Are shown in Table 1) to obtain an oxygen-free copper thin plate and a tough pitch copper thin plate having a thickness of 0.15 mm. Next, the oxygen-free copper thin plate and the tough pitch copper thin plate were slit with a cutting machine to obtain a flat rectangular plate having a width of 2 mm. Furthermore, these flat rectangular thin plates were subjected to final annealing under the conditions shown in Table 1 to obtain flat rectangular base materials before plating in Examples 1 to 6 and Comparative Examples 1 to 6.

これらの平角状基材の表面粗さRa、Rz、Rq/Rz、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合、測定面積内に存在する結晶粒の面積平均GAM、0.2%耐力を測定した。測定結果を表2、表3に示す。   The surface roughness Ra, Rz, Rq / Rz of these rectangular substrates, the area ratio of crystal grains in which the average orientation difference between all the pixels in the crystal grains is less than 4 °, and the crystal grains present in the measurement area Area average GAM, 0.2% yield strength was measured. The measurement results are shown in Tables 2 and 3.

表面粗さRa、Rz、Rqは、各平角状基材から切出した試料の表面をオリンパス株式会社製の走査型共焦点レーザ顕微鏡LEXT OLS−3000を用い、対物レンズ100倍の条件でレーザ光を照射して、その反射光から距離を測定し、そのレーザ光を試料の表面に沿って直線的にスキャンしながら距離を連続的に測定することにより求めた。   The surface roughness Ra, Rz, and Rq were measured using a scanning confocal laser microscope LEXT OLS-3000 manufactured by Olympus Corporation on the surface of a sample cut out from each rectangular substrate, and the laser light was irradiated under the condition of 100 times the objective lens. Irradiation was performed, the distance was measured from the reflected light, and the distance was continuously measured while the laser light was scanned linearly along the surface of the sample.

結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合は、次のように求めた。
前処理として、平角状基材から採取した2mm×2mmの試料を10%硫酸に10分間浸漬した後、水洗、エアブローにより散水した後に、散水後の試料を日立ハイテクノロジーズ社製フラットミリング(イオンミリング)装置で、加速電圧5kV、入射角5°、照射時間1時間にて表面処理を施した。
次に、TSL社製EBSDシステム付の日立ハイテクノロジーズ社製走査型電子顕微鏡S−3400Nで試料表面を観察した。観察条件は、加速電圧25kV、測定面積150μm×150μm(結晶粒を1000個以上含む)とした。
観察結果より、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の全測定面積に対する面積割合は次の条件にて求めた。
ステップサイズ0.5μmにて、測定面積範囲内の全ピクセルの方位を測定し、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした。次に、結晶粒界で囲まれた個々の結晶粒について、結晶粒内の全ピクセル間の方位差の平均値を計算し、平均値が4°未満の結晶粒の面積を算出し、それを全測定面積で割って、全結晶粒に占める結晶粒内の平均方位差が4°未満の結晶粒の面積の割合を求めた。なお、2ピクセル以上が連結しているものを結晶粒とした。
この方法にて測定箇所を変更して5回測定を行い、それぞれの面積割合の平均値を面積割合とした。
The area ratio of the crystal grains in which the average orientation difference between all the pixels in the crystal grains is less than 4 ° was determined as follows.
As a pretreatment, a 2 mm × 2 mm sample collected from a flat substrate was immersed in 10% sulfuric acid for 10 minutes, then rinsed with water and air blown. ) The apparatus was subjected to surface treatment at an acceleration voltage of 5 kV, an incident angle of 5 °, and an irradiation time of 1 hour.
Next, the sample surface was observed with a scanning electron microscope S-3400N manufactured by Hitachi High-Technologies Corporation equipped with an EBSD system manufactured by TSL. The observation conditions were an acceleration voltage of 25 kV and a measurement area of 150 μm × 150 μm (including 1000 or more crystal grains).
From the observation results, the area ratio with respect to the total measurement area of the crystal grains in which the average orientation difference between all the pixels in the crystal grains is less than 4 ° was obtained under the following conditions.
At a step size of 0.5 μm, the orientation of all pixels within the measurement area range was measured, and a boundary where the orientation difference between adjacent pixels was 5 ° or more was regarded as a crystal grain boundary. Next, for each crystal grain surrounded by the crystal grain boundary, the average value of the orientation difference between all the pixels in the crystal grain is calculated, and the area of the crystal grain whose average value is less than 4 ° is calculated. Dividing by the total measurement area, the ratio of the area of the crystal grains having an average orientation difference of less than 4 ° in the crystal grains in the total crystal grains was determined. In addition, what connected 2 pixels or more was made into the crystal grain.
The measurement location was changed by this method and measurement was performed 5 times, and the average value of the respective area ratios was defined as the area ratio.

測定面積内に存在する結晶粒の面積平均GAMは次のように求めた。
前処理として、平角状基材から採取した2mm×2mmの試料を10%硫酸に10分間浸漬した後、水洗、エアブローにより散水した後に、散水後の試料を日立ハイテクノロジーズ社製フラットミリング(イオンミリング)装置で、加速電圧5kV、入射角5°、照射時間1時間にて表面処理を施した。
次に、TSL社製EBSDシステム付きの日立ハイテクノロジーズ社製走査型電子顕微鏡S−3400Nでその試料表面を観察した。観察条件は、加速電圧25kV、測定面積150μm×150μm(結晶粒を1000個以上含む)とした。
観察結果より、同一結晶粒内の隣接するピクセル間の方位差の平均値は次のようにして求めた。
ステップサイズ0.5μmにて、測定面積範囲内の全ピクセルの方位を測定し、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした。次に、結晶粒界で囲まれた個々の結晶粒について、結晶粒の面積平均GAMを前述の数3の式にて計算して求めた。なお、2ピクセル以上が連結しているものを結晶粒とした。
0.2%耐力は、各平角状基材から長さ150mmの引張試験片を採取し、JIS Z2241に規定の方法により、長さ方向(圧延方向)に引っ張る引張試験により求めた。
The area average GAM of the crystal grains existing within the measurement area was determined as follows.
As a pre-treatment, a 2 mm × 2 mm sample collected from a flat substrate was immersed in 10% sulfuric acid for 10 minutes, then washed with water and sprinkled with air blow, and the sprinkled sample was flat milled by Hitachi High-Technologies Corporation (ion milling) ) The apparatus was subjected to surface treatment at an acceleration voltage of 5 kV, an incident angle of 5 °, and an irradiation time of 1 hour.
Next, the sample surface was observed with a scanning electron microscope S-3400N manufactured by Hitachi High-Technologies Corporation equipped with an EBSD system manufactured by TSL. The observation conditions were an acceleration voltage of 25 kV and a measurement area of 150 μm × 150 μm (including 1000 or more crystal grains).
From the observation results, the average value of the orientation difference between adjacent pixels in the same crystal grain was determined as follows.
At a step size of 0.5 μm, the orientation of all pixels within the measurement area range was measured, and a boundary where the orientation difference between adjacent pixels was 5 ° or more was regarded as a crystal grain boundary. Next, for each crystal grain surrounded by the crystal grain boundary, the area average GAM of the crystal grain was calculated by the above equation (3). In addition, what connected 2 pixels or more was made into the crystal grain.
The 0.2% proof stress was obtained by a tensile test in which a tensile test piece having a length of 150 mm was sampled from each rectangular base material and pulled in the length direction (rolling direction) by the method specified in JIS Z2241.

次に、実施例1〜6、比較例1〜6の最終焼鈍が施された直後の各平角状基材に、溶融はんだめっき浴の下流側で10MPa程度の張力を掛けて引っ張りながら、溶融はんだめっき浴に通して溶融はんだめっきを施し、太陽電池用電極線材を作製した。溶融はんだめっき浴は、はんだ組成がSn−3.0%Ag−0.5%Cu(融点:218℃)であり、浴温を300℃とした。   Next, while soldering each flat rectangular substrate immediately after the final annealing of Examples 1 to 6 and Comparative Examples 1 to 6 with a tension of about 10 MPa on the downstream side of the molten solder plating bath, molten solder It passed through the plating bath and was subjected to molten solder plating to produce a solar cell electrode wire. The molten solder plating bath had a solder composition of Sn-3.0% Ag-0.5% Cu (melting point: 218 ° C) and a bath temperature of 300 ° C.

これらの溶融はんだめっき後の各試料のめっき密着性、めっき耐熱剥離性、0.2%耐力を測定した。測定結果を表3に示す。
めっき密着性は、JIS H8504に規定されるめっき密着性試験にて測定した。試験片の寸法は幅2mm、長さ5mm、厚さ0.15mmとし、熱衝撃を加えた後の試験片の表面を4倍の拡大鏡で観察し、皮膜の剥離の有無及び程度を調べた。試験片の全面にわたり熱衝撃による層状剥離が認められなかった場合を○、一部に層状剥離が認められた場合を×とした。
めっき耐熱剥離性は、各試験片(幅2mm、長さ5mm、厚さ0.15mm)を105℃の恒温槽(大気雰囲気)中で500時間保持した後に、曲げ軸が圧延方向に対し平行方向となる90°W曲げ(R=0.6、ただしRは曲げ半径(mm))を行い、曲げ加工部表面について、JISZ1522に規定されるセロハン粘着テープを使用してめっき剥離試験を実施し、目視によりめっき層の剥離が認められなかったものを○、認められたものを×とした。
0.2%耐力は、各電極線材から長さ150mmの引張試験片を採取し、JIS Z2241に規定の方法により、長さ方向(圧延方向)に引っ張る引張試験により求めた。
The plating adhesion, plating heat release resistance, and 0.2% proof stress of each sample after the molten solder plating were measured. Table 3 shows the measurement results.
The plating adhesion was measured by a plating adhesion test defined in JIS H8504. The dimensions of the test piece were 2 mm in width, 5 mm in length, and 0.15 mm in thickness. The surface of the test piece after the thermal shock was applied was observed with a 4 × magnifier, and the presence or absence and degree of peeling of the film were examined. . The case where no delamination due to thermal shock was observed over the entire surface of the test piece was rated as “◯”, and the case where a layer delamination was observed partially was marked as “X”.
Plating heat-resistant peelability is determined by holding each test piece (width 2 mm, length 5 mm, thickness 0.15 mm) in a constant temperature bath (atmosphere) at 105 ° C. for 500 hours, and then the bending axis is parallel to the rolling direction. 90 ° W bend (R = 0.6, where R is the bend radius (mm)), and the surface of the bent portion is subjected to a plating peeling test using a cellophane adhesive tape specified in JISZ1522. The case where peeling of the plating layer was not observed by visual observation was evaluated as “◯”, and the case where it was recognized as “×”.
The 0.2% proof stress was obtained by a tensile test in which a tensile test piece having a length of 150 mm was taken from each electrode wire and pulled in the length direction (rolling direction) by the method specified in JIS Z2241.

Figure 2012114260
Figure 2012114260

Figure 2012114260
Figure 2012114260

Figure 2012114260
Figure 2012114260

表1、表2、表3の結果より、本発明の純銅薄板のスリット材で形成されためっき前の太陽電池用電極線材の平角状基材は、はんだめっきとの密着性が良好であり、はんだめっき後も0.2%耐力の上昇が少ないことがわかる。また、本発明の製造方法により製造された太陽電池用電極線材は耐久性に優れていることがわかる。   From the results of Table 1, Table 2, and Table 3, the flat substrate of the solar cell electrode wire before plating formed with the slit material of the pure copper thin plate of the present invention has good adhesion to the solder plating, It can be seen that the 0.2% yield strength increase is small even after solder plating. Moreover, it turns out that the electrode wire for solar cells manufactured by the manufacturing method of this invention is excellent in durability.

以上、本発明の実施形態の製造方法について説明したが、本発明はこの記載に限定されることはなく、中間冷間圧延と最終冷間圧延との間に適切な中間焼鈍を施すなど、本発明の趣旨を逸脱しない範囲において種々の変更を加えることが可能である。   As mentioned above, although the manufacturing method of embodiment of this invention was demonstrated, this invention is not limited to this description, such as performing appropriate intermediate annealing between intermediate cold rolling and final cold rolling. Various modifications can be made without departing from the spirit of the invention.

1 太陽電池用電極線材
2 平角状基材
3 はんだめっき層
11 太陽電池
12 半導体基板
13 線状表面電極
14 接続用リード
DESCRIPTION OF SYMBOLS 1 Solar cell electrode wire 2 Flat base material 3 Solder plating layer 11 Solar cell 12 Semiconductor substrate 13 Linear surface electrode 14 Lead for connection

Claims (3)

表面の一部又は全てにはんだめっきが施された太陽電池用電極線材のめっき前の平角状基材であり、Cuを99.90質量%以上含む純銅薄板のスリット材で形成され、表面の算術平均粗さRaが0.05〜0.3μmであり、最大高さRzが0.5〜2.5μmであり、二乗平均平方根粗さRqと最大高さRzの比率(Rq/Rz)が0.06〜1.1であり、後方散乱電子回折像システム付の走査型電子顕微鏡によるEBSD法にて、ステップサイズ0.5μmにて表面の測定面積内の全ピクセルの方位を測定し、隣接するピクセル間の方位差が5°以上である境界を結晶粒界とみなした場合の、結晶粒内の全ピクセル間の平均方位差が4°未満である結晶粒の面積割合が、前記測定面積の80〜95%であり、前記測定面積内に存在する結晶粒の面積平均GAMが4°未満であることを特徴とする太陽電池用電極線材のめっき前の平角状基材。   It is a flat rectangular base material before plating of an electrode wire for a solar cell in which a part or all of the surface is solder-plated, and is formed of a pure copper thin plate slit material containing 99.90% by mass or more of Cu, and the surface arithmetic The average roughness Ra is 0.05 to 0.3 μm, the maximum height Rz is 0.5 to 2.5 μm, and the ratio of the root mean square roughness Rq to the maximum height Rz (Rq / Rz) is 0. .06 to 1.1, the orientation of all pixels within the measurement area of the surface is measured with an EBSD method using a scanning electron microscope with a backscattered electron diffraction image system at a step size of 0.5 μm, and adjacent to each other. When the boundary where the orientation difference between the pixels is 5 ° or more is regarded as a crystal grain boundary, the area ratio of the crystal grains where the average orientation difference between all the pixels in the crystal grain is less than 4 ° is the measurement area. 80% to 95%, and the presence of the crystals within the measurement area A flat substrate before plating of an electrode wire for a solar cell, wherein the area average GAM of crystal grains is less than 4 °. Cuを99.90質量%以上含む純銅板に熱間圧延、中間冷間圧延、焼鈍、最終冷間圧延をこの順で施して純銅薄板とし、当該薄板を切断機にてスリット加工して平角状基材とし、当該平角状基材を最終焼鈍して太陽電池用電極線材のめっき前の平角状基材を製造する方法において、前記中間冷間圧延の圧下率を50〜70%にて実施し、前記最終冷間圧延の圧下率を50〜70%にて実施し、前記最終焼鈍を700〜900℃の雰囲気に5〜60秒間保持して行なうことを特徴とする太陽電池用電極線材のめっき前の平角状基材の製造方法。   A pure copper sheet containing 99.90% by mass or more of Cu is subjected to hot rolling, intermediate cold rolling, annealing, and final cold rolling in this order to form a pure copper sheet, and the sheet is slitted with a cutting machine to have a rectangular shape. In the method of producing a flat base material before plating of a solar cell electrode wire by subjecting the flat base material to final annealing, a reduction rate of the intermediate cold rolling is performed at 50 to 70%. The plating of a solar cell electrode wire, wherein the rolling reduction of the final cold rolling is performed at 50 to 70%, and the final annealing is performed in an atmosphere of 700 to 900 ° C. for 5 to 60 seconds. The manufacturing method of the previous flat base material. 請求項2に記載の製造方法により製造された太陽電池用電極線材のめっき前の平角状基材の表面の一部又は全てにはんだめっきを40〜150μmの厚さに施すことにより製造された太陽電池用電極線材。   A solar battery manufactured by applying solder plating to a thickness of 40 to 150 μm on part or all of the surface of a flat substrate before plating of an electrode wire for a solar battery manufactured by the manufacturing method according to claim 2. Battery electrode wire.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015017286A (en) * 2013-07-09 2015-01-29 三菱伸銅株式会社 Plated copper alloy plate with excellent gloss

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015017286A (en) * 2013-07-09 2015-01-29 三菱伸銅株式会社 Plated copper alloy plate with excellent gloss

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