JP2012114120A - Led device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LED device which can ensure electrical and thermal conduction of a support substrate in the vertical direction without using a so-called through hole conductor, and to provide a method of manufacturing the same.SOLUTION: An LED device 1 comprises a submount substrate 10, and an LED die 20 mounted on the upper surface of the submount substrate 10. The submount substrate 10 has a sandwich structure where an internal electrode layer 11 and an insulation layer 12 are arranged alternately in one direction parallel with the main surface of the submount substrate. Each internal electrode layer 11 penetrates the submount substrate 10 in the vertical direction, at least a part of the internal electrode layer 11 on the upper surface side is exposed to the upper surface of the submount substrate 10 and connected with contact pads 13a, 13b, and at least a part of the internal electrode layer 11 on the bottom face side is exposed to the bottom face of the submount substrate 10 and connected with terminal electrodes 14a, 14b.

Description

  The present invention relates to an LED device and a manufacturing method thereof, and more particularly to a structure of a submount substrate on which an LED die is mounted and a manufacturing method thereof.

  An LED (Light Emitting Diode), which is one of the light emitting elements, is mounted on many electronic devices and control devices due to the characteristics of the elements such as low power consumption and long life.

  As a conventional LED device, one in which an LED chip is mounted on a support substrate and packaged is well known (for example, see Patent Documents 1 and 2). When a pair of electrodes (anode / cathode electrodes) of the LED are on the upper surface of the chip, these electrodes are connected to contact pads on the surface of the support substrate via bonding wires. Further, when the pair of electrodes of the LED are on the bottom surface of the chip, these electrodes are flip-chip connected to the contact pads on the surface of the support substrate via the bumps. The support substrate is provided with through-hole conductors that penetrate the front and back surfaces, and the contact pads formed on the surface of the support substrate are connected to external terminal electrodes formed on the bottom surface of the support substrate via the through-hole conductors. The The through-hole conductor in this case is a type that penetrates from the front surface to the back surface of the support substrate at once, or a type that finally connects the front and back surfaces while changing the position in the plane direction for each layer.

  Patent Document 1 discloses an LED device having a varistor function for protecting an LED chip from ESD (Electro-Static Discharge). One or more layers made of a metal oxide such as ZnO are formed inside a ceramic substrate as a support substrate, and this functions as a varistor. By taking ESD protection measures for LEDs with a varistor, the ESD resistance can be increased, and a large ESD protection effect can be obtained.

US Patent Publication No. 2007/297108 JP 2000-216439 A

  However, when a through-hole conductor is used as a vertical conductive line that penetrates the support substrate, a process for forming a through hole at a predetermined position of the support substrate is required, which complicates the manufacturing process. There is a problem. In addition, the LED is an element that generates heat. If the heat dissipation is poor, the life of the LED is reduced. However, in the conventional LED device described above, the only conductor that passes through the support substrate in the vertical direction is the through-hole conductor. There is a problem that sex is not enough.

  The present invention has been made to solve the above problems, and the object of the present invention is to ensure vertical and vertical electrical and thermal conduction without using a so-called through-hole conductor for the support substrate. An object of the present invention is to provide a low-cost and excellent heat dissipation LED device and a manufacturing method thereof.

  The LED device according to the present invention includes a submount substrate and at least one LED die mounted on the first main surface of the submount substrate, and the submount substrate is formed on the first main surface. A contact pad and a terminal electrode formed on a second main surface opposite to the first main surface, wherein the submount substrate includes a plurality of internal electrode layers and a plurality of insulating layers. A second structure including a sandwich structure alternately arranged along a first direction parallel to the main surface, wherein the internal electrode layer is parallel to the first main surface and perpendicular to the first direction; And extending from the first main surface of the submount substrate to the second main surface, and at least a part of the internal electrode layer on the first main surface side is: The first of the submount substrate; The terminal electrode is exposed to the surface and connected to the contact pad, and at least a part of the internal electrode layer on the second main surface side is exposed to the second main surface of the submount substrate. It is characterized by being connected to.

  According to the present invention, since the electrode pattern of the sandwich structure in the submount substrate becomes a conductive line between the upper and lower sides of the substrate, it is not necessary to form individual conductive lines such as through holes. Therefore, it is easy to secure the conductive line, the number of steps for forming the conductive line is small, the damage of the substrate due to the formation of the through hole can be avoided, and the LED device having excellent electrical and thermal characteristics can be obtained. Can be provided.

  In the present invention, the LED die includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer sandwiched between the n-type semiconductor layer and the p-type semiconductor layer, and the contact pad includes the first and second contact layers. A plurality of internal electrode layers including a second contact pad, wherein the plurality of internal electrode layers are connected to the first contact pad and insulated from the second contact pad; A plurality of second internal electrode layers connected to a contact pad and insulated from the first contact pad, wherein the first internal electrode layer and the second internal electrode layer are arranged in the first direction; The n-type semiconductor layers of the LED die are connected in parallel to the plurality of first internal electrode layers via the first contact pads, and the LED die p-type semiconductor Layers are preferably connected in parallel to the second internal electrode layers of the plurality via said second contact pad. According to this configuration, a large number of internal electrode layers can be connected to the corresponding contact pads, and a conductive line with low DC resistance and high heat dissipation can be provided.

  In the present invention, it is preferable that the insulating layer is a ceramic layer having nonlinear resistance characteristics, and the submount substrate functions as a varistor. According to this configuration, the submount substrate can be used as a varistor, and a countermeasure against static electricity can be applied to the LED.

  In the present invention, the LED die includes a first electrode electrically connected to the n-type semiconductor layer and a second electrode electrically connected to the p-type semiconductor layer. And the electrode surface of the second electrode is formed on the same side of the LED die and facing the same direction, the first electrode is connected to the first contact pad, and the second electrode is It is preferable to be connected to the second contact pad. According to this configuration, the plurality of LED dies formed on the wafer and the submount wafer can be connected to each other by bonding.

  In the present invention, the first and second electrodes are made of an alloy material, the first electrode is directly connected to the n-type semiconductor layer, and the second electrode is directly connected to the p-type semiconductor layer. It is preferable that According to this configuration, it is not necessary to previously form an electrode on the semiconductor layer of the LED die, and the semiconductor layer of the LED die and the submount wafer can be directly connected.

  In the present invention, the first main surface of the n-type semiconductor layer of the LED die is an open surface from which the growth substrate of the n-type semiconductor layer is removed, and the first main surface of the n-type semiconductor layer. It is preferable that the 2nd main surface which opposes is in contact with the said light emitting layer. According to this configuration, when manufacturing the LED device, the wafer can be diced after the LED wafer is bonded onto the submount wafer and the growth substrate is peeled off from the LED wafer, so that the wafer can be easily processed. .

  In the present invention, the open surface of the n-type semiconductor layer of the LED die is preferably roughened. According to this configuration, the light emission efficiency of the LED can be improved.

  In the present invention, an underfill is preferably filled between the submount substrate and the LED die. According to this configuration, the mechanical strength of the LED die can be improved, and in particular, the mechanical strength of the LED die that becomes a problem when the growth substrate is peeled from the LED die can be ensured.

  The LED device manufacturing method according to the present invention includes a step of forming a laminate formed by laminating a plurality of insulating sheets on which internal electrode patterns are formed, and slicing the laminate in parallel with the laminating direction. Manufacturing a submount wafer having a sandwich structure in which internal electrode patterns and a plurality of insulating sheets are alternately arranged along a first direction parallel to the stacking direction; and a first of the submount wafers Forming a contact pad covering at least a part of the first end surface of the internal electrode pattern exposed on the main surface; and a second end surface of the internal electrode pattern exposed on the second main surface of the submount wafer. A step of forming a terminal electrode covering at least a part of the LED, and a growth substrate, an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer stacked in this order Preparing a wafer and bonding the p-type semiconductor layer to the submount wafer of the LED wafer with the p-type semiconductor layer facing the submount wafer, and dicing the submount wafer to divide it into individual LED chips. It is characterized by providing.

  According to the present invention, an electrode pattern is formed on the surface of the insulating layer, a plurality of the insulating layers are prepared, the insulating layers are bonded together, and then the submount substrate is formed by cutting perpendicularly to the substrate surface. In addition, since the electrode pattern provided in advance serves as a conductive line between the upper and lower sides of the substrate, the step of forming individual conductive lines such as through holes can be omitted. Accordingly, it is possible to provide a method for manufacturing an LED device that has fewer man-hours, can easily form a conductive line, can avoid damage to the ceramic substrate due to formation of a through hole, and has excellent electrical and thermal characteristics. Can do.

  In the present invention, the step of forming a laminate of insulating sheets includes forming a first insulating sheet on which a first internal electrode pattern is formed, and a second internal electrode pattern different from the first internal electrode pattern. And the step of forming the contact pad includes forming a first contact pad at an exposed position on the first main surface side of the first internal electrode pattern. And forming the second contact pad at an exposed position on the first main surface side of the second internal electrode pattern, and the step of forming the terminal electrode includes the step of forming the first internal electrode. A first terminal electrode is formed at an exposed position on the second main surface side of the pattern, and a second terminal electrode is formed at an exposed position on the second main surface side of the second internal electrode pattern. Including processes It is preferred. According to this method, a large number of internal electrode patterns can be connected to each of the first and second contact pads, and the heat dissipation of the LED can be enhanced.

  In the present invention, the step of bonding the LED wafer to the submount wafer includes a step of connecting the contact pad of the submount wafer and the semiconductor layer of the LED wafer by an alloy reaction of two kinds of metals. Is preferred. According to this method, it is not necessary to previously form an electrode on the surface of the semiconductor layer of the LED wafer, and the LED semiconductor layer and the contact pad of the submount wafer can be directly connected. Thereby, joining at a wafer level can be performed easily and reliably.

  In the LED device manufacturing method according to the present invention, it is preferable to use a ceramic material having nonlinear resistance characteristics as the material of the insulating sheet. When a non-linear resistance material is used for the insulating sheet, the submount wafer can be configured as a varistor, and an ESD protection measure for the LED can be realized.

  The method for manufacturing an LED device according to the present invention preferably further comprises a step of peeling the growth substrate from the LED wafer on the submount wafer to open one main surface of the n-type semiconductor layer. This process facilitates wafer dicing. Further, the light emission characteristics of the LED can be improved.

  The LED device manufacturing method according to the present invention preferably further comprises a step of roughening the one main surface of the n-type semiconductor layer of the LED wafer. According to this step, the light emission characteristics of the LED can be improved.

  Preferably, the LED device manufacturing method according to the present invention further includes a step of filling an underfill between the submount substrate and the LED wafer before the LED wafer is bonded to the submount wafer. According to this step, the mechanical strength of the LED die can be improved, and in particular, the mechanical strength of the LED die that becomes a problem when the growth substrate is peeled from the LED die can be ensured.

  According to the present invention, there is provided an LED device that can ensure electrical and thermal conduction in the vertical direction of a support substrate without using a so-called through-hole conductor, and has low cost and excellent heat dissipation, and a method for manufacturing the LED device. can do.

FIG. 1 is a schematic external perspective view showing a configuration of an LED device according to a preferred embodiment of the present invention. 2 is a side cross-sectional view of the LED device shown in FIG. 1, wherein (a) is a side cross-sectional view along the line AA in FIG. 1, and (b) is a side cross-sectional view along the line BB. It is. FIG. 3 is a schematic exploded perspective view showing the layer structure of the submount substrate 10 in which the X direction in FIG. 4A and 4B are schematic plan views of the submount substrate, in which FIG. 4A shows the upper surface side and FIG. 4B shows the bottom surface side. FIG. 5 is a schematic plan view of an LED die, particularly showing an electrode pattern. FIG. 6 is a schematic diagram showing the overall flow of the manufacturing process of the LED device. FIG. 7 is a schematic cross-sectional view showing a state where an LED wafer is bonded to a submount wafer. FIG. 8 is a schematic cross-sectional view showing another example of a state in which an LED wafer is bonded to a submount wafer. FIG. 9 is a schematic cross-sectional view for explaining a method for bonding an LED wafer. FIG. 10 is a schematic cross-sectional view showing another bonding method of the LED wafer. FIG. 11 is a schematic diagram illustrating an overall flow of another manufacturing process of the LED device. 12 is a schematic cross-sectional view for explaining an application example of the slit machining shown in FIG. FIG. 13 is a schematic plan view showing the configuration of an LED device according to another preferred embodiment of the present invention, where (a) shows a state in which an LED die is mounted, and (b) shows a state in which no LED die is mounted. Each state is shown.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic external perspective view showing a configuration of an LED device according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the LED device 1 according to the present embodiment includes a submount substrate 10 and an LED die 20 mounted on one main surface (upper surface) of the submount substrate 10. The LED die 20 is mounted with its main light emitting surface facing upward, and is face-down bonded to the upper surface 10 a of the submount substrate 10.

  2 is a side sectional view of the LED device 1 shown in FIG. 1, wherein (a) is a side sectional view taken along the line AA in FIG. 1, and (b) is a side sectional view taken along the line BB. FIG. 3 is a schematic exploded perspective view showing the layer structure of the submount substrate 10 in which the X direction in FIG.

  As shown in FIGS. 2A and 2B, the submount substrate 10 includes a plurality of internal electrode layers 11. Each internal electrode layer 11 is a conductive film extending in the vertical direction (Z direction) of the submount substrate 10. The internal electrode layers 11 are arranged at equal intervals in the X direction shown in the figure, and their main surfaces are orthogonal to the upper surface (one main surface) 10a and the bottom surface (the other main surface) 10b of the submount substrate 10. . Each internal electrode layer 11 is a rectangular pattern having a main surface parallel to the YZ plane. The area of the internal electrode layer 11 is preferably as large as possible.

  First and second contact pads 13a and 13b for electrically and mechanically connecting the LED die 20 are formed on the top surface 10a of the submount substrate 10, and the bottom surface 10b of the submount substrate 10 is formed on the bottom surface 10b. First and second external terminal electrodes 14a and 14b for mounting the LED device 1 itself on the printed circuit board are formed. The size of the submount substrate 10 is, for example, 1.6 × 1.2 × 0.3 mm.

  In the present embodiment, the plurality of internal electrode layers 11 includes a plurality of first internal electrode layers 11a connected to the first contact pads 13a and a plurality of second internal electrodes connected to the second contact pads 13b. A distinction is made between the electrode layers 11b. The first and second contact pads 13a and 13b are alternately arranged in the X direction, and the insulating layer 12 is interposed between them. As shown in FIG. 3, the submount substrate 10 has an insulating layer 12 on which the first internal electrode layer 11a is formed and an insulating layer 12 on which the second internal electrode layer 11b is formed in the X direction. This is realized by alternately and repeatedly laminating. That is, the stacking direction of the layer structure of the submount substrate 10 according to the present embodiment is the X direction parallel to the main surface of the substrate, and is not a normal layer structure stacked in the Z direction perpendicular to the main surface of the substrate.

  As shown in FIG. 2B, a part of the upper end of the first internal electrode layer 11a is exposed on the upper surface 10a of the submount substrate 10 and is connected to the first contact pad 13a. Further, a part of the lower end of the first internal electrode layer 11a is exposed at the bottom surface 10b of the submount substrate 10 and is connected to the first external terminal electrode 14a. Therefore, the first contact pad 13a is electrically and thermally connected to the first external terminal electrode 14a through the plurality of first internal electrode layers 11a.

  A part of the upper end of the second internal electrode layer 11b is exposed from the upper surface 10a of the submount substrate 10 and is connected to the first contact pad 13a. Further, a part of the lower end of the second internal electrode layer 11b is exposed on the bottom surface 10b of the submount substrate 10 and is connected to the second external terminal electrode 14b. Therefore, the second contact pad 13b is electrically and thermally connected to the second external terminal electrode 14b through the plurality of second internal electrode layers 11b.

  The submount substrate 10 according to the present embodiment preferably functions as a varistor. As shown in FIG. 3, the submount substrate 10 has a sandwich structure in which the first internal electrode layers 11a and the second internal electrode layers 11b are alternately stacked. A varistor element is realized by interposing an insulating layer 12 made of a metal oxide such as zinc oxide (ZnO) between 11a and the second internal electrode layer 11b. The varistor according to the present embodiment has a structure in which the first internal electrode layers 11a and the second internal electrode layers 11b that are insulated and separated by the insulating layer 12 made of a metal oxide such as ZnO are alternately stacked. A plurality of varistor elements are connected in parallel. The thickness of each insulating layer 12 is preferably 3 to 60 μm. However, it is not necessary that all the insulating layers 12 in one submount substrate 10 have the same thickness.

  The varistor functions in the same way as reversely connecting Zener diodes, and when a high voltage spike or power surge is applied between the terminals of the LED, it generates a low resistance current path in parallel with the terminals, Protects the LED from damage by diverting electrostatic energy. Thereby, the ESD protection function with respect to LED can be provided. In order to improve the performance as a varistor, it is preferable that the opposing areas of the first and second internal electrode layers 11a and 11b be as large as possible.

  The LED die 20 is, for example, a gallium nitride-based LED, in which the sapphire growth substrate is removed from the LED layer 21 grown on the sapphire growth substrate, and includes an n-type semiconductor layer 22, a p-type semiconductor layer 24, A light emitting layer 23 (active layer) made of InGaN sandwiched between the p-type semiconductor layer 22 and the p-type semiconductor layer 24 is provided. The LED layer 21 is formed on the growth substrate via a low-temperature growth buffer layer (not shown) made of GaN, AlN, or the like.

  The LED die 20 includes a cathode electrode (n-side electrode) 25a electrically connected to the n-type semiconductor layer 22 and an anode electrode (p-side electrode) 25b electrically connected to the p-type semiconductor layer 24. The n-type semiconductor layer 22 is connected to the first contact pad 13a on the submount substrate 10 side through the cathode electrode 25a, and the p-type semiconductor layer 24 is on the submount substrate 10 side through the anode electrode 25b. Is connected to the second contact pad 13b. Although details will be described later, the cathode electrode 25 a and the anode electrode 25 b are directly bonded to the surfaces of the n-type semiconductor layer 22 and the p-type semiconductor layer 24 when the LED die 20 and the submount substrate 10 are bonded to each other.

  The LED die 20 is formed by epitaxially growing an n-type semiconductor layer 22, a light emitting layer 23, and a p-type semiconductor layer 24 in order on a growth substrate. The epitaxial step mainly includes a step of forming one or more n-type semiconductor layers 22 on the growth substrate, and a step of forming one or more light-emitting layers 23 in the active region on the n-type semiconductor layer 22. And a step of forming one or more p-type semiconductor layers 24 on the light emitting layer 23 by metal organic chemical vapor deposition (MOCVD) or MBE. An example of dopants used for the n-type semiconductor layer 22 and the p-type semiconductor layer 24 are Si and Mg, respectively. Contacts for electrical connection are formed in the region of the Si-doped n-type semiconductor layer 22 and the region of the Mg-doped p-type semiconductor layer 24, respectively. In order to minimize electrical and mechanical protection and spurious effects, a protective layer covering the exposed portions of the n-type semiconductor layer 22 and the p-type semiconductor layer 24 of the thin-film LED die 20 may be formed.

  One main surface 22 a of the n-type semiconductor layer 22 of the LED die 20 is an open surface from which the sapphire growth substrate is removed, while the opposite main surface is in contact with the light emitting layer 23. By removing the sapphire growth substrate and thinning the LED element, the optical characteristics of the LED can be improved, and electrical access to the LED layer can be facilitated. Further, the LED die 20 can be bonded at the wafer level, and the subsequent chip division can be easily performed.

  In the present embodiment, the open surface 22a of the n-type semiconductor layer 22 is preferably roughened. According to this configuration, the light emission efficiency of the LED can be improved. As a method for selectively etching the n-type semiconductor layer 22, a photoelectrochemical technique using potassium hydroxide (KOH) can be used. This method is also convenient as a method for making the n-type semiconductor layer 22 thinner in order to reduce light absorption. Instead of roughening the light emitting surface, it is possible to enhance the light emission by adopting a method of forming a dry etching pattern of micro or nano scale on the light emitting surface.

  4A and 4B are schematic plan views of the submount substrate 10, where FIG. 4A shows the upper surface side and FIG. 4B shows the bottom surface side.

  As shown in FIG. 4A, first and second contact pads 13a and 13b for electrically and mechanically connecting the LED die 20 are formed on the upper surface 10a of the submount substrate 10, respectively. Yes. When viewed from the upper surface 10a side of the submount substrate 10, the internal electrode layer 11 forms a striped pattern in which linear patterns extending in the Y direction are arranged at substantially equal intervals in the X direction.

  The positions and shapes of the contact pads 13a and 13b are set based on the positions and shapes of the electrodes on the LED die 20 side. In the present embodiment, the area of the second contact pad 13b is set larger than the area of the first contact pad 13a. The exposed end surface 11k on the upper surface side of the first internal electrode layer 11a is connected to a common contact pad 13a. The exposed end surface 11k on the upper surface side of the second internal electrode layer 11b is connected to a common contact pad 13b.

  On the other hand, as shown in FIG. 4B, the first and second external terminal electrodes 14a and 14b are formed on the bottom surface 10b of the submount substrate 10, respectively. The positions and shapes of the first and second external terminal electrodes 14a and 14b are preferably positions and shapes that can be easily solder-mounted as surface-mounted components. Has been. The exposed end surface 11k on the lower surface side of the first internal electrode layer 11a is connected to the common first external terminal electrode 14a. The exposed end surface 11k on the lower surface side of the second internal electrode layer 11b is commonly connected to a common second external terminal electrode 14b.

  5 (a) to 5 (c) are schematic plan views of the LED die 20, and particularly show an electrode pattern.

  In the LED die 20 shown in FIG. 5A, a light emitting layer 23 is provided over most of the surface of the n-type semiconductor layer 22, and a p-type semiconductor layer 24 is provided over substantially the entire surface of the light emitting layer 23. One large anode electrode 25 b is provided on the surface of the p-type semiconductor layer 24. This anode electrode 25 b covers substantially the entire surface of the p-type semiconductor layer 24. On the other hand, the cathode electrode 25 a is provided in a region not covered with the light emitting layer 23 and the p-type semiconductor layer 24, and forms an elongated strip pattern. As described above, the LED die 20 shown in FIG. 5A includes one cathode electrode 25a and one anode electrode 25b. The shape of the pair of contact pads shown in FIG. 4 (a) corresponds to the electrode shape of the LED die 20 shown in FIG. 5 (a).

  On the other hand, in the LED die 20 shown in FIGS. 5B and 5C, the formation region (active region) of the light-emitting layer 23 and the p-type semiconductor layer 24 on the n-type semiconductor layer 22 is divided into four parts. 23 and six circular cathode electrodes 25a are provided in a predetermined region where the p-type semiconductor layer 24 is not formed. An anode electrode 25 b is provided on the upper surfaces of the four p-type semiconductor layers 24. The difference between FIG. 5B and FIG. 5C is that in FIG. 5B, one large anode electrode 25b is provided on the upper surface of one p-type semiconductor layer 24, whereas FIG. ) In that two divided anode electrodes 25 b and 25 b are provided on the upper surface of one p-type semiconductor layer 24.

  As described above, the pattern layout of the LED die 20 is arbitrary, and the active region and the anode / cathode electrode 25a can be divided and provided. In this case, it is needless to say that the shape of the pair of contact pads shown in FIG. 4A needs to be matched with the electrode shape of FIGS. 5B and 5C.

  Next, the manufacturing method of the LED device 1 will be described in detail. The LED device 1 according to the present embodiment can be manufactured by bonding the LED die 20 and the submount substrate 10 at the wafer level.

  FIG. 6 is a schematic diagram illustrating the overall flow of the manufacturing process of the LED device 1.

  As shown in FIG. 6, in the manufacture of the LED device 1, first, a plurality of ceramic green sheets 30 are prepared (FIG. 6A), and an electrode pattern (internal electrode layer 11) is formed on the surface of each ceramic green sheet. Electrode pattern) 31 is formed (FIG. 6B). The ceramic green sheet can be formed by a doctor blade method using a slurry in which ZnO powder, a dopant, and an organic binder are mixed at an appropriate ratio. Although not particularly limited, the large-area ceramic green sheet on which the internal electrode pattern is printed is a square or a rectangle having a side of 2 to 4 inches, and has a thickness of 3 to 60 μm. The electrode pattern can be formed by screen printing of a metal paste. As the metal paste, a mixture of Pd, Ag, or an alloy thereof, an organic binder, and an organic solvent can be used.

  Next, a plurality of ceramic green sheets 31A on which the electrode pattern 31 is formed are laminated and bonded in order while being aligned (FIG. 6C), and then fired under predetermined temperature and pressure conditions to produce a multilayer ceramic A block 32 is produced (FIG. 6D). At this time, the ceramic green sheet on which the electrode pattern to be the first internal electrode layer 11a is formed and the ceramic green sheet on which the electrode pattern to be the second internal electrode layer 11b is formed are alternately stacked.

  Next, the multilayer ceramic block 32 is cut in parallel to the stacking direction, that is, perpendicularly to the stacking surface as indicated by the broken line in the drawing to obtain the submount wafer 33 (FIG. 6E). The thickness of the submount wafer 33 is preferably 20 to 1000 μm, and more preferably 30 to 100 μm.

  Next, the front and back surfaces of the submount wafer 33 are polished and flattened (FIG. 6F), and then the upper surface of the submount wafer 33 is metalized to be used for the first and second contact pads 13a and 13b. In addition to forming the electrode pattern 34, the bottom surface of the submount wafer 33 is also metallized to form electrode patterns for the first and second external terminal electrodes 14a and 14b (FIG. 6G). For metallization for forming the electrode pattern, for example, a multilayer film of Ti / Cu / Ni / Au or AlCu / Ni / Au can be used.

  Next, the processed LED wafer 35 is bonded to the submount wafer 33 while being aligned (FIG. 4 (h)), and then the LED wafer 35 is bonded (FIG. 4 (h)).

  FIG. 7 is a schematic cross-sectional view showing a state in which the LED wafer 35 is bonded to the submount wafer 33.

  As shown in FIG. 7, internal electrode layers 11 a and 11 b corresponding to individual submount substrates 10 are formed inside the submount wafer 33. The LED wafer 35 is formed with LED layers 35b corresponding to individual LED chips separately on a common sapphire growth substrate 35a. These are aligned with each other and connected by a metal bonding material (metal bond) 25m. The metal bonding material 25m functions as a cathode electrode 25a and an anode electrode 25b.

  FIG. 8 is a schematic cross-sectional view showing another example of the state in which the LED wafer 35 is bonded to the submount wafer 33.

  As shown in FIG. 8, an underfill 36 is provided between the submount wafer 33 and the LED wafer 35. The underfill 36 is filled before the LED wafer 33 is bonded to the submount wafer 33. An epoxy resin can be used as the material for the underfill 36. Thus, by providing the underfill 36 in advance, the mechanical strength of the LED wafer 33 can be ensured in the peeling process of the sapphire growth substrate 35a described later, and peeling of the metal bonding material can be prevented. .

  Next, the sapphire growth substrate 35a is peeled from the LED wafer 35 on the submount wafer 33 (FIG. 6 (j)). This peeling process can be realized by a laser irradiation technique called laser lift-off. Since the energy of the laser beam melts the gallium nitride material in contact with the sapphire growth substrate 35a, only the sapphire growth substrate 35a can be peeled off.

  Next, the surface of the LED wafer 35 on the submount wafer 33 from which the sapphire growth substrate 35a has been removed is roughened (FIG. 6 (k)). This process is performed to improve the light output characteristics of the LED. In addition, the roughening process here includes not only a normal roughening process in which irregular irregularities are formed, but also a patterning process in micro level or nano level in which regular irregularities are formed. It is.

  Next, the submount wafer 33 on which the LED wafer 35 is mounted is diced, and individual LED elements on the wafer are separated into individual pieces (FIG. 4L). Since the sapphire growth substrate 35a has already been removed, a general dicing saw can be used for dicing, and processing is ready. Thus, the LED device 1 as the chip device shown in FIG. 1 is completed. Such an LED device 1 may be directly solder-mounted on a printed board, may be mounted on a printed board via a normal surface-mount device or other connection means, and further connected to a light-molded component. May be.

  FIG. 9 is a schematic cross-sectional view for explaining a method for bonding an LED wafer.

  As shown in FIG. 9, the bonding of LED wafers can be connected by an alloy reaction of two different kinds of metals. That is, the bonding process at the wafer level between the submount wafer 33 and the LED wafer 35 is realized by TLP (Transient liquid phase) technology. As bonding materials for bonding, indium (In), palladium (Pd), gold (Au), silver (Ag), bismuth (Bi), tin (Sn), gallium (Ga), zinc (Zn), nickel A combination of at least two metals selected from (Ni), lead (Pb), and cadmium (Cd) can be used.

  The bonding material is formed as a thin film having a thickness in the range of 1 to 12 μm, and is formed on the LED wafer 35 and the submount wafer 33 by a vacuum method and / or a plating method. The bonding material may also be introduced as a fine powder in a form contained in a paste form printed at a desired location on the semiconductor layer or submount. In this case, it is preferable that the particles of the bonding material have a particle size in the range of several hundred nm to 20 μm.

  In the bonding according to the present embodiment, the first and second metals 41 and 42 are sequentially formed on the submount wafer 33 side, and the first metal 41 is formed on the LED wafer side. Then, after bringing the first metal 41 on the LED wafer 35 side into contact with the second metal 42 on the submount wafer 33 side, they are bonded together by heat treatment at a predetermined temperature T1. The metal component selected as the bonding material is raised to a temperature T1 during the bonding process and undergoes an alloy process, but the resulting alloy has a melting point at a temperature T2 higher than the temperature T1. .

  FIG. 10 is a schematic cross-sectional view showing another bonding method of the LED wafer.

  As shown in FIG. 10, this bonding method uses a paste of a mixed material of two kinds of metals. This bonding material 43 is introduced as a fine powder in a form contained in a paste form printed at a desired position on the semiconductor layer or submount. In this case, it is preferable that the particles of the bonding material have a particle size in the range of several hundred nm to 20 μm.

  In the bonding according to the present embodiment, the bonding material 43 is formed on the submount wafer 33 side, and the bonding material 43 is not formed on the LED wafer side. At this time, the anode / cathode electrode 25a can be omitted. Then, the bonding material 43 on the submount substrate 10 side is brought into direct contact with the semiconductor layer on the LED wafer 20 side, and then the two are bonded by heat treatment at a predetermined temperature T1. The metal component selected as the bonding material is raised to a predetermined temperature T1 during the bonding process and undergoes an alloy process, but the resulting alloy has a melting point of temperature T2 higher than the temperature T1. ing.

  As described above, in the LED device 1 according to the present embodiment, the electrode pattern is formed on the surface of the single insulating layer 12, a plurality of the insulating layers 12 are prepared, the insulating layers 12 are bonded together, and then the substrate surface The submount substrate 10 is formed by cutting the substrate vertically, and the electrode pattern provided in advance becomes a conductive line between the upper and lower sides of the substrate, so that it is not necessary to form individual conductive lines such as through holes. . Accordingly, it is possible to provide an LED device 1 that has fewer man-hours, can easily form a conductive line, can avoid damage to the ceramic substrate due to the formation of a through hole, and has excellent electrical and thermal characteristics. Can do.

  FIG. 11 is a schematic diagram showing an overall flow of another manufacturing process of the LED device 1.

  As shown in FIG. 11, the manufacturing method according to the present embodiment is characterized by using a ceramic green sheet 30 in which a plurality of slits (or slots) are formed (FIG. 11A). At this time, each slit penetrates the sheet, and the formation position thereof coincides with the slice position indicated by the broken line in FIG. Since the subsequent steps are substantially the same as those in FIG. 6, detailed description thereof is omitted. When such a slit is provided, the thermal gradient of the ceramic sheet can be reduced, and uniform firing can be promoted over the entire surface of the sheet. That is, a more uniform distribution of the thermal profile can be provided, and the firing uniformity in the direction orthogonal to the laminated ceramic sheets can be improved during the firing process.

  12 is a schematic cross-sectional view for explaining an application example of the slit machining shown in FIG.

  As shown in FIG. 12, in the manufacturing method according to the present embodiment, a non-penetrating shallow groove 30g is formed on the ceramic green sheet 30, and an electrode pattern (internal electrode pattern) 31 to be the internal electrode layer 11 is formed thereon. (See FIGS. 11A and 11B). As described above, the electrode pattern 31 can be formed by screen printing of a metal paste, and since the inside of the shallow groove 30g is filled and the upper surface is flattened, the thickness of the electrode in the shallow groove portion is larger than the surrounding area. Become thicker. By producing the submount substrate 10 using such a ceramic green sheet, the DC resistance of the internal electrode layers 11a and 11b can be reduced, and the heat dissipation can be improved.

  FIG. 13 is a schematic plan view showing the configuration of an LED device 2 according to another preferred embodiment of the present invention, where (a) shows a state in which the LED die 20 is mounted, and (b) shows a state in which the LED die 20 is mounted. Each state is not shown.

  As shown in FIG. 13A, the LED device 2 is characterized in that four LED dies 20A to 20D are mounted on one submount substrate 10, and each LED die 20A to 20D is individually turned on. / Off controlled. In addition, a fluorescent material 29 is formed on one LED die 20B in order to convert emitted light to another wavelength. The fluorescent material 29 can be formed by screen printing or electrophoretic deposition.

  As shown in FIG. 13B, first to eighth contact pads 13 a to 13 h are formed on the upper surface 10 a of the submount substrate 10 used in the LED device 2. Further, the submount substrate 10 has first to eighth internal electrode layers 11a to 11h connected to the first to eighth contact pads 13a to 13h, respectively. The first and second internal electrode layers 11a and 11b are provided corresponding to the first LED die 20A, and the third and fourth internal electrode layers 11c and 11d correspond to the second LED die 20A. Is provided. The fifth and sixth internal electrode layers 11e and 11f are provided on the third LED die 20C, and the seventh and eighth internal electrode layers 11g and 11h correspond to the fourth LED die 20D. Is provided.

  The exposed end surface 11k on the upper surface side of the first internal electrode layer 11a is connected to the first contact pad 13a, and the exposed end surface 11k on the upper surface side of the second internal electrode layer 11b is connected to the second contact pad 13b. Has been. The exposed end surface 11k on the upper surface side of the third internal electrode layer 11c is connected to the third contact pad 13c, and the exposed end surface 11k on the upper surface side of the fourth internal electrode layer 11d is connected to the fourth contact pad 13d. It is connected to the. The same applies to the fifth to eighth internal electrode layers 11e to 11h.

  In the present embodiment, an unused dummy electrode layer 11i is provided between the fifth internal electrode layer 11d and the sixth internal electrode layer. Thus, the internal electrode layer that cannot be connected to the contact pad due to the layout of the plurality of LED dies can be the dummy electrode layer 11i.

  As described above, since the LED device 2 according to the present embodiment has a plurality of LED dies 20 mounted on one submount substrate 10, a very compact and highly functional LED package can be provided. .

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above-described embodiment, the case where an LED grown on a sapphire growth substrate is used has been described, but the material of the growth substrate is not limited to sapphire, and other materials may be used. Examples of other materials for the growth substrate include silicon carbide (SiC), zinc oxide (ZnO), and gallium nitride (GaN). When a material other than the sapphire substrate is used as the growth substrate, dry etching or mechanical polishing may be employed as a method for peeling the growth substrate from the LED layer.

  In the above embodiment, the submount substrate 10 has a sandwich structure in which the internal electrode layers 11 and the insulating layers 12 are alternately arranged along the first direction parallel to the first main surface. It is not always necessary to alternately arrange the entire direction, and the internal electrode layer 11 may be partially omitted. In other words, the insulating layer 12 may partially include a stacked structure.

10 Submount substrate 10a Upper surface (first main surface) of the submount substrate
10b Bottom surface of submount substrate (second main surface)
11, 11a-11h Internal electrode layer 11i Dummy electrode layer 11k Exposed end face 12 of internal electrode layer Insulating layers 13a-13h Contact pads 14a, 14b External terminal electrodes 14a, 14b Terminal electrodes 14b External terminal electrodes 20, 20A-20D LED die 21 LED layer 22 n-type semiconductor layer 22a One main surface (open surface) of n-type semiconductor layer
23 light emitting layer 24 p-type semiconductor layer 25a cathode electrode (n-side electrode)
25b Anode electrode (p-side electrode)
25m metal bonding material (metal bond)
29 Fluorescent material 30 Ceramic green sheet 30 g Shallow groove 31 Electrode pattern 31 A Ceramic green sheet 32 Multilayer ceramic block 33 Submount wafer 34 Electrode pattern 35 LED wafer 35 a Sapphire growth substrate 35 b LED layer 36 Underfill 41 to 43 Metal (bonding material)

Claims (15)

A submount substrate,
And at least one LED die mounted on the first main surface of the submount substrate,
The submount substrate includes a contact pad formed on the first main surface and a terminal electrode formed on a second main surface opposite to the first main surface,
The submount substrate includes a sandwich structure in which a plurality of internal electrode layers and a plurality of insulating layers are alternately arranged along a first direction parallel to the first main surface,
The internal electrode layer is a belt-like pattern extending in a second direction parallel to the first main surface and perpendicular to the first direction, and from the first main surface of the submount substrate to the first main surface. Through to the main surface of 2,
At least a part of the internal electrode layer on the first main surface side is exposed to the first main surface of the submount substrate and connected to the contact pad;
At least a part of the internal electrode layer on the second main surface side is exposed to the second main surface of the submount substrate and connected to the terminal electrode. The LED die includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer sandwiched between the n-type semiconductor layer and the p-type semiconductor layer,
The contact pad includes the first and second contact pads,
The plurality of internal electrode layers are connected to the first contact pad and insulated from the second contact pad, and are connected to the second contact pad and the first contact pad. A plurality of second internal electrode layers insulated from one contact pad;
The first internal electrode layers and the second internal electrode layers are alternately arranged along the first direction,
The n-type semiconductor layer of the LED die is connected in parallel to the plurality of first internal electrode layers via the first contact pad,
2. The LED device according to claim 1, wherein the p-type semiconductor layer of the LED die is connected in parallel to the plurality of second internal electrode layers via the second contact pad.   The LED device according to claim 1, wherein the insulating layer is a ceramic layer having nonlinear resistance characteristics, and the submount substrate functions as a varistor. The LED die is
A first electrode electrically connected to the n-type semiconductor layer;
A second electrode electrically connected to the p-type semiconductor layer,
The electrode surfaces of the first and second electrodes are formed on the same side of the LED die and face the same direction,
The first electrode is connected to the first contact pad;
The LED device according to claim 1, wherein the second electrode is connected to the second contact pad.   The first and second electrodes are made of an alloy material, the first electrode is directly connected to the n-type semiconductor layer, and the second electrode is directly connected to the p-type semiconductor layer. The LED device according to claim 4.   The first main surface of the n-type semiconductor layer of the LED die is an open surface from which the growth substrate of the n-type semiconductor layer has been removed, and the first main surface of the n-type semiconductor layer faces the first main surface of the n-type semiconductor layer. The LED device according to claim 1, wherein the main surface of 2 is in contact with the light emitting layer.   The LED device according to claim 6, wherein the open surface of the n-type semiconductor layer of the LED die is roughened.   The LED device according to any one of claims 1 to 7, wherein an underfill is filled between the submount substrate and the LED die. Forming a laminate formed by laminating a plurality of insulating sheets on which internal electrode patterns are formed;
A sub-structure having a sandwich structure in which a plurality of internal electrode patterns and a plurality of insulating sheets are alternately arranged along a first direction parallel to the stacking direction by slicing the stack in parallel with the stacking direction. A process for producing a mount wafer;
Forming a contact pad covering at least a part of the first end surface of the internal electrode pattern exposed on the first main surface of the submount wafer;
Forming a terminal electrode covering at least a part of the second end surface of the internal electrode pattern exposed on the second main surface of the submount wafer;
An LED wafer is prepared by laminating a growth substrate, an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer in this order, and the p-type semiconductor layer is directed to the submount wafer side to the submount wafer of the LED wafer. The pasting process,
And a step of dicing the submount wafer to divide the wafer into individual LED chips. The step of forming a laminate of insulating sheets includes:
A first insulating sheet on which a first internal electrode pattern is formed;
Including sequentially stacking a second insulating sheet on which a second internal electrode pattern different from the first internal electrode pattern is formed,
The step of forming the contact pad includes forming a first contact pad at an exposed position on the first main surface side of the first internal electrode pattern, and the first internal electrode pattern. Forming the second contact pad at an exposed position on the main surface side,
The step of forming the terminal electrode includes forming the first terminal electrode at an exposed position on the second main surface side of the first internal electrode pattern, and the second internal electrode pattern. The method for manufacturing the LED device according to claim 9, further comprising forming a second terminal electrode at an exposed position on the main surface side.   The step of bonding the LED wafer to the submount wafer includes a step of connecting the contact pad of the submount wafer and a semiconductor layer of the LED wafer by an alloy reaction of two kinds of metals. The manufacturing method of the LED device of Claim 9 or 10.   The method for manufacturing an LED device according to any one of claims 9 to 11, wherein a ceramic material having nonlinear resistance characteristics is used as a material of the insulating sheet.   13. The method according to claim 9, further comprising a step of peeling the growth substrate from the LED wafer on the submount wafer to open one main surface of the n-type semiconductor layer. The manufacturing method of the LED device of description.   The LED device according to claim 13, further comprising a step of roughening the one main surface of the n-type semiconductor layer of the LED wafer.   The LED device according to claim 13, further comprising a step of filling an underfill between the submount substrate and the LED wafer before the LED wafer is bonded to the submount wafer. .

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