JP2012108993A - Semiconductor memory device and method for testing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which shares a read/write amplifier among a plurality of banks and a method for testing the same, capable of improving test efficiency.SOLUTION: When an active command is inputted from the outside during testing of a wafer, an inner activation signal for individually activating each of banks is sequentially generated for each bank which does not share a read/write amplifier, and thus all banks are sequentially activated. When a read command or a write command is inputted from the outside, an individual column address selection signal is sequentially generated for each bank which allows data to be read from and written into the bank corresponding to the activated bank, and the data is read from a bank selected by the column address selection signal or written into the bank.

Description

  The present invention relates to a semiconductor memory device and a test method thereof.

  In general, in a semiconductor memory device such as a DRAM (Dynamic RAM), a known read / write amplifier for reading / writing data from / to a memory cell operates in a bank unit. It is configured. For example, as shown in FIG. 6, in the semiconductor memory device 100 that includes four memory cell units 110 and in which the banks (Bank 0 to 3) 111 are formed in units of the memory cell units 110, there are four corresponding to each memory cell unit 110. Two read / write amplifiers (RWAMP) 112 are provided.

  In such a semiconductor memory device 100, by providing the read / write amplifier 112 for each bank 111, all the banks 111 can be activated simultaneously and data can be read from each bank 111 as shown in FIG. it can. For example, the data read from each bank 111 is compared with an expected value stored in a register or the like in advance to determine whether or not it matches the expected value (expected value determination), and the determination result is converted into a serial signal. And output to the outside, and the quality of the semiconductor memory device 100 to be tested may be determined using a known tester or the like. The expected value determination may be executed in the read / write amplifier 112, for example. The expected value determination result for each bank 111 is converted into a serial signal by the determination result output control circuit 120 shown in FIG. As the determination result output control circuit 120, for example, a circuit shown in FIG. 8 can be used.

  For example, Patent Document 1 discloses a parallel test in which data is simultaneously read from a plurality of banks and compared with the expected value to determine whether the semiconductor memory device is good or bad.

  FIG. 8 is a circuit diagram showing a configuration example of a determination result output control circuit included in the semiconductor memory device shown in FIG.

As shown in FIG. 8, the determination result output control circuit 120 includes four latch circuits (LAT) 121 ₁ to 121 ₄ for latching the expected value determination result TDATA0~3 of each bank, the latch circuits 121 ₁ to 121 ₄ And a parallel-serial conversion circuit 122 for converting data output from the serial signal into a serial signal.

Expected value determination result TDATA0~3 output from each bank 111, are output is latched in synchronization with TLAT signal by the latch circuit 121 ₁ to 121 _4, the parallel - in synchronism with the TECLK signal by the serial conversion circuit 122 It is converted into a serial signal and output as a TOUTD signal (see FIG. 7). The TOUTD signal output from the parallel-serial conversion circuit 122 is output to the outside via a buffer circuit (not shown). The determination result output control circuit 120 shown in FIG. 8 is used only during the wafer test of the semiconductor memory device 100.

  By the way, in the case of producing a product in which the memory capacity of the semiconductor memory device 100 shown in FIG. 6 is halved, in order to reduce the chip area, the layout area, etc., as shown in FIG. In addition, the number of read / write amplifiers 12 may be halved. In that case, it is necessary to share one read / write amplifier 12 between the two banks 11. Further, there is a configuration in which one read / write amplifier 12 is shared by four banks 11 by reducing the number of read / write amplifiers 12 to ¼.

  In the semiconductor memory device 1 in which the read / write amplifier 12 is shared by a plurality of banks 11, an active (ACT) command, a read (READ) command, and a precharge (PRE) command are performed while complying with a predetermined tRCD during a wafer test. When reading data from each bank 11 by sequentially inputting, for example, in a configuration in which the read / write amplifier 12 is shared by the two banks 11, these banks 11 cannot be activated at the same time. Therefore, as shown in FIG. Data is read from the four banks (Bank 0 to 3) 11 by the operation. In a configuration in which one read / write amplifier 12 is shared by four banks 11, data is read from four banks (Banks 0 to 3) 11 by four read operations. Therefore, there is a problem that the time required for the wafer test is extended. Note that tRCD is an input of an active (ACT) command that is a command for activating the selected bank 11, and then a read (READ) command that is a command for reading data in the bank 11 or the bank 11 Indicates a time until a write command for writing data can be input.

JP 2000-11695 A

  As described above, in a semiconductor memory device in which one read / write amplifier is shared by a plurality of banks, the bank sharing the read / write amplifier cannot be activated at the same time during a wafer test. Data needs to be read. Therefore, there is a problem that the time required for the wafer test is extended.

A semiconductor memory device according to the present invention includes a read / write amplifier for reading / writing data to / from memory cells in the bank shared by a plurality of banks,
When an active command is input from the outside during wafer testing, an internal Activate signal for activating each bank individually is sequentially generated in units of banks that do not share the read / write amplifier, and an external read command or write command is generated. , An Active / YSW Bank activation control circuit that sequentially generates individual column address selection signals corresponding to the activated banks for each of the banks that permit data reading / writing to the banks; ,
Have

On the other hand, the test method for a semiconductor memory device according to the present invention is a test method for a semiconductor memory device having a read / write amplifier for reading / writing data to / from memory cells in the bank, which is shared by a plurality of banks. And
When an active command is input from the outside during wafer testing, an internal Activate signal for individually activating each bank is sequentially generated for each bank not sharing the read / write amplifier, and all banks are sequentially activated. ,
When a read command or a write command is input from the outside, individual column address selection signals are sequentially generated corresponding to the activated banks for each of the banks that permit reading / writing of data with respect to the banks,
In this method, data is read from or written to the bank selected by the column address selection signal.

  In the semiconductor memory device and method as described above, when an active command is input, an internal Activate signal is sequentially generated in units of banks that do not share the read / write amplifier, and all banks are sequentially activated to input a read command or a write command. At the same time, a single column address selection signal is generated for each bank corresponding to the activated bank, so that a single read operation is performed at the time of the wafer test as in the case of a semiconductor memory device having a read / write amplifier for each bank. Data can be read from each bank by operation, and data can be written to each bank by one write operation.

  According to the present invention, it is possible to improve the test efficiency of a semiconductor memory device in which a read / write amplifier is shared by a plurality of banks.

It is a block diagram which shows one structural example of the semiconductor memory device of this invention. FIG. 3 is a waveform diagram showing an operation example during a wafer test of the semiconductor memory device shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration example of an Active / YSW Bank activation control circuit shown in FIG. 1. FIG. 2 is a circuit diagram illustrating a configuration example of a determination result output control circuit illustrated in FIG. 1. It is a wave form diagram which shows the operation example at the time of the wafer test of the semiconductor memory device which shares one read / write amplifier by four banks. It is a block diagram which shows the example of 1 structure of the semiconductor memory device provided with the read-write amplifier for every bank. FIG. 7 is a waveform diagram showing an operation example during a wafer test of the semiconductor memory device shown in FIG. 6. FIG. 7 is a circuit diagram illustrating a configuration example of a determination result output control circuit included in the semiconductor memory device illustrated in FIG. 6. FIG. 7 is a block diagram illustrating a configuration example of a product in which the memory capacity of the semiconductor storage device illustrated in FIG. 6 is halved. FIG. 10 is a waveform diagram showing an example of operation of the background art during a wafer test of the semiconductor memory device shown in FIG. 9.

  Next, the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of the semiconductor memory device of the present invention, and FIG. 2 is a waveform diagram showing an operation example of the semiconductor memory device shown in FIG. 1 during a wafer test.

  As shown in FIG. 1, the semiconductor memory device of the present invention is configured by adding an Active / YSW Bank activation control circuit 30 to the semiconductor memory device 1 sharing the read / write amplifier 12 shown in FIG. It is. In FIG. 1, except for the Active / YSW Bank activation control circuit 30, the same reference numerals as those of the semiconductor memory device shown in FIG. 9 are given to the components of the semiconductor memory device 1.

  The semiconductor memory device 1 shown in FIG. 1 has a configuration in which one read / write amplifier 12 is shared by Banks 0 and 1 and one read / write amplifier 12 is shared by Banks 2 and 3. Therefore, Bank0 and Bank2 can be operated simultaneously, and Bank1 and Bank3 can be operated simultaneously.

  As shown in FIG. 2, when an ACT command is input from the outside during the wafer test of the semiconductor memory device 1, the Active / YSW Bank activation control circuit 30 first synchronizes with the rising edge of the clock CLK, and first Bank0 and Bnak2 The internal activate signal ACTn (n = 0, 2) is generated for activating the signal, and the internal activate signal ACTm (m = 1, m) for activating Bank1 and Bank3 in synchronization with the next rising edge of the clock CLK. 3) is generated.

  Subsequently, when a READ command is input from the outside, the Active / YSW Bank activation control circuit 30 synchronizes with the rising edge of the clock CLK, and a column address selection signal YSWn that permits reading / writing of data with respect to Bank0 and Bnak2. (n = 0, 2) is generated, and a column address selection signal YSWm (m = 1, 3) that permits reading / writing of data with respect to Bank 1 and Bank 3 is generated in synchronization with the next rising edge of the clock CLK.

  That is, when an ACT command is input from the outside during wafer testing, the Active / YSW Bank activation control circuit 30 uses an internal Activate signal for individually activating each bank 11 as a bank that does not share the read / write amplifier 12. When the READ command is input from the outside sequentially generated in units, an individual column address selection signal YSW is assigned to each bank 11 in a bank unit that does not share the read / write amplifier 12 corresponding to the activated bank 11 Generate sequentially.

  2 shows an example in which the Active / YSW Bank activation control circuit 30 generates the internal Activate signals ACTn and ACTm and the column address selection signals YSWn and YSWm in synchronization with the rising edge of the clock CLK supplied from the outside. However, the Active / YSW Bank activation control circuit 30 may generate these signals in synchronization with the falling edge of the clock CLK.

  FIG. 3 is a circuit diagram showing a configuration example of the Active / YSW Bank activation control circuit shown in FIG.

As shown in FIG. 3, the Active / YSW Bank activation control circuit 30 includes a plurality of latch circuits (LAT) 31 _{1 to} 31 ₆ , Philip flops (F / F) 32 _{1 to} 32 ₃ , SR-FFs 33 _{1 to} 33 _2. In this configuration, gate circuits (GATE) 34 _{1 to} 34 ₃ and YSW generation circuits 35 _{1 to} 35 ₂ are provided.

The latch circuit 31 ₁ is based on the ACT command is generated in the semiconductor memory device, a low active (Row Active) synchronization signal for the state RACTn the (n = 0, 2) the clock CLK Bank0,2 and latches and outputs, the latch circuit 31 _2, based on the ACT command is generated in the semiconductor memory device, the signal RACTm for causing the Bank1,3 the low active (row active) state (m = 1 , 3) are latched and output in synchronization with the clock CLK.

Latch circuit 31 ₃ is generated in the semiconductor memory device based on the PRE command latches synchronously precharge signal RPREn requesting precharged (n = 0, 2) the clock CLK to Bank0,2 output, the latch circuit 31 ₄ is generated in the semiconductor memory device based on the pRE command, synchronization precharge signal RPREm requesting precharged (m = 1, 3) to the clock CLK to Bank1,3 Latch and output. The latch circuit 31 _5, based on the READ command is generated in the semiconductor memory device, the signal COLn (n = 0,2) for indicating the column address of the uptake for Bank0,2 the latches in synchronism with the clock CLK output, the latch circuit 31 _6, based on the READ command is generated in the semiconductor memory device, and a synchronization signal indicating a column address of uptake COLm the (m = 1, 3) to the clock CLK for Bank1,3 Latch and output.

The Philip flop 32 ₁ outputs the signal RACTn (n = 0, 2) output from the latch circuit 31 ₁ after being delayed by one cycle of the clock CLK, and the Philip flop 32 ₂ is output from the latch circuit 31 ₃ . RPREn (n = 0, 2) and COLn (n = 0, 2) are delayed by one cycle of the clock CLK and output. Also, flip-flop 32 ₃ outputs signals outputted from the latch circuit 31 ₅ COLn the (n = 0, 2) is delayed by one cycle of the clock CLK.

The gate circuit 34 ₁ has a latch circuit 31 when the TPARA signal indicating that the wafer test is being performed (here, the parallel test is “H”) and the RACTn output from the Philip flop 32 ₁ is “H”. _The signal RACTm latched at ₂ is output. The gate circuit 34 ₂ has a latch circuit 31 when the TPARA signal indicating that the wafer test (here, the above parallel test) is “H” and the RPREn output from the Philip flop 32 ₂ is “H”. _The signal RPREm latched at ₄ is output. The gate circuit 34 ₃ latches when the TPARA signal indicating that the wafer test (here, the parallel test) is “H” and the COLn output from the Philip flop 32 ₃ is “H”. and it outputs a signal COLm latched by circuit 31 _6.

SR-FF 33 ₁ generates an internal Activate signal ACTn from the signal outputted from the latch circuit 31 ₁ RACTn (n = 0,2) and the latch circuit 31 ₃ output from the signal RPREn (n = 0,2). The SR-FF 33 ₂ generates an internal Activate signal ACTm from the signal RACTm (m = 1, 3) output from the gate circuit 34 ₁ and the signal RPREm (m = 1, 3) output from the gate circuit 34 _2. To do.

The internal activate signal ACTn is enabled when the signal RACTn output from the latch circuit 31 ₁ is latched by the SR-FF 33 _{1. When the} signal RPREn is output from the latch circuit 31 ₃ , the SR-FF 33 ₁ is reset (Reset). ) And becomes Disable.

Delayed from the operation by one cycle of the clock CLK, the internal Activate signal ACTm the signal RACTm output from the gate circuit 34 ₁ becomes Enable state by SR-FF 33 ₂ latches, the gate circuit 34 ₂ from the signal RPREm There the Disable state when output SR-FF 33 ₂ is reset (reset).

Column address select signal YSWn, when the signal COLn to the latch circuit 31 ₅ is input generated by YSW generating circuit 35 _1, delayed from the operation by one cycle of the clock CLK, the column address selection signal YSWm is YSW generating circuit 35 Generated by ₂ . At this time, if the period of the clock CLK is constant, the Banks 1 and 3 can be operated by the column address selection signal YSWm in a state where the specifications such as tRCD are satisfied.

  FIG. 4 is a circuit diagram showing a configuration example of the determination result output control circuit shown in FIG.

As shown in FIG. 4, the determination result output control circuit 20 of the present embodiment includes two latch circuits (LAT) 21 ₁ that latch the expected value determination result TDATA0 of Bank0, 2 and the expected value determination result TDATA1 of Bank1, _3. -21 ₂ and a parallel-serial conversion circuit 22 for converting data output from the latch circuits 21 ₁ -21 ₂ into serial signals.

The expected value determination results TDATA 0 and ₁ output from each bank 11 are latched and output in synchronization with the TLAT signal by the latch circuits 21 _{1 to} 21 _2, and are serialized by the parallel-serial conversion circuit 22 at the timing of the TECLK signal. It is converted into a signal and output as a TOUTD signal (see FIG. 2). The TOUTD signal output from the parallel-serial conversion circuit 22 is output to the outside through a buffer circuit (not shown), for example. The determination result output control circuit 20 shown in FIG. 4 is used only during the wafer test of the semiconductor memory device 1.

  FIG. 5 is a waveform diagram showing an operation example during a wafer test of a semiconductor memory device in which one read / write amplifier is shared by four banks. In this case, when an ACT command is input from the outside, the Active / YSW Bank activation control circuit 30 sequentially generates the internal Activate signals ACT0 to ACT3 in synchronization with the rising edge and the falling edge of the clock CLK, respectively. When the READ command is input, the column address selection signals YSW0 to YSW3 may be sequentially generated in synchronization with the rising edge and the falling edge of the clock CLK.

  By providing such an Active / YSW Bank activation control circuit 30, data can be read from each bank by a single read operation during a wafer test even in a configuration in which one read / write amplifier is shared by four banks.

  In the present embodiment, the configuration and operation of the semiconductor memory device including the Active / YSW Bank activation control circuit 30 has been described by taking the case of reading data from each bank as an example. However, when the WRITE command is input after the ACT command. If the column address selection signals YSWn and YSWm, or the column address selection signals YSW0 to YSW3 are sequentially generated by the Active / YSW Bank activation control circuit 30, even when data is written in the wafer test, each write operation is performed in each bank. On the other hand, data can be written sequentially.

  According to the semiconductor memory device of this embodiment, when an ACT command is input, an internal Activate signal is sequentially generated in units of banks that do not share the read / write amplifier to sequentially activate all banks, and an READ command or a WRITE command is input. At this time, the read / write amplifier 12 is shared by the plurality of banks 11 by providing the Active / YSW Bank activation control circuit 30 that sequentially generates individual column address selection signals for each bank corresponding to the activated banks. Even in the semiconductor memory device 1, data can be read from each bank 11 by a single read operation during wafer test, and data can be written to each bank 11 by a single write operation. Therefore, similarly to the semiconductor memory device shown in FIG. 6 having the read / write amplifier for each bank, data can be read / written from / to all the banks 11 by one read operation or write operation.

  Therefore, the test efficiency of the semiconductor memory device 1 in which the read / write amplifier 12 is shared by the plurality of banks 11 can be improved.

1 the semiconductor memory device 10 the memory cell portion 11 bank 12 read-write amplifier 20 determination result output control circuit 21 ₁ to 21 _2, 31 ₁ to 31 ₆ latch circuit 22 parallel - serial converting circuit 30 Active / YSW Bank starting control circuit 32 ₁ - 32 ₃ Philip flop 33 _{1 to} 33 ₂ SR-FF
34 _{1 to} 34 ₃ gate circuit 35 _{1 to} 35 ₂ YSW generation circuit

Claims (4)

A read / write amplifier for reading / writing data to / from memory cells in the bank shared by a plurality of banks;
When an active command is input from the outside during wafer testing, an internal Activate signal for activating each bank individually is sequentially generated in units of banks that do not share the read / write amplifier, and an external read command or write command is generated. , An Active / YSW Bank activation control circuit that sequentially generates individual column address selection signals corresponding to the activated banks for each of the banks that permit data reading / writing to the banks; ,
A semiconductor memory device. The read / write amplifier is
Compare the data read from the bank with a preset expected value, and output an expected value determination result as the comparison result,
2. The semiconductor memory device according to claim 1, further comprising a determination result output control circuit that converts the expected value determination result for each bank received from the read / write amplifier into a serial signal and outputs the serial signal to the outside. A test method of a semiconductor memory device having a read / write amplifier for reading / writing data to / from memory cells in a bank shared by a plurality of banks,
When an active command is input from the outside during wafer testing, an internal Activate signal for individually activating each bank is sequentially generated for each bank not sharing the read / write amplifier, and all banks are sequentially activated. ,
When a read command or a write command is input from the outside, individual column address selection signals are sequentially generated corresponding to the activated banks for each of the banks that permit reading / writing of data with respect to the banks,
A test method for a semiconductor memory device for reading data from a bank selected by the column address selection signal or writing data to the bank. When data is read by the read / write amplifier, the data read from the bank is compared with a preset expected value,
4. The test method for a semiconductor memory device according to claim 3, wherein an expected value determination result which is the comparison result for each bank is converted into a serial signal and output to the outside.

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