JP2012105049A - Phase/frequency comparison circuit and pll circuit - Google Patents

Abstract

A method of driving a logic circuit using a PLL that retains the frequency of an output clock even when the input clock is stopped is provided.
A phase frequency comparison circuit includes two modules, a PFD main part and a reference clock stop detection part 202B. The reference clock stop detection unit 202B outputs the reference data signal pfd_in_en to the RS-FF data terminal of the PFD main part. The reference data signal pfd_in_en is generated from the flip-flop 202B-1 in the reference clock stop detection unit 202B. The flip-flop 202B-1 is reset by the reference clock ref_clk with the overlap signal overlap indicating the end of the phase comparison operation as a timing. When the reference clock ref_clk stops, the reference data signal pfd_in_en remains “L”, and as a result, the operation of the main part of the PFD stops.
[Selection] Figure 4

Description

  The present invention relates to a PLL circuit related to ASK modulation, and more particularly to a phase frequency comparison circuit that can be controlled autonomously even when 100% ASK is input.

  Currently, NFC (Near Field Communication) functions are being installed in mobile phones mainly in Japan. Overseas, NFC-equipped mobile phone products are emerging.

  An NFC chip exists for mounting NFC in a mobile phone, but there is a problem in supplying a clock to a logic circuit.

  In a card mode in which the NFC chip operates as an IC card (UICC), an oscillation circuit using a crystal or a ceramic oscillator for supplying a clock to the chip is difficult to apply for the following reasons.

  Before operating in the card mode, there is a state in which no signal is input from the antenna and the RW is not operating. At that time, it operates as a carrier sense mode in which most circuits other than the circuit (carrier detector) for monitoring the input of the carrier signal from the antenna are stopped.

  When the carrier signal input from the antenna is detected in the carrier sense mode, the mode transitions to the card mode. The time from the input of a carrier signal to the completion of processing is determined by a standard (such as Felica). Here, when a crystal oscillation circuit is used, it takes time until the oscillation starts, and it becomes difficult to satisfy the standard.

  Therefore, in NFC, a reference clock is often extracted from a carrier signal and used.

  Japanese Patent Laying-Open No. 2006-195901 (Patent Document 1) discloses that either a VCO clock or a non-contact clock is selected as a clock and the clock is supplied to each module in the IC card.

JP 2006-195901 A

  However, problems also occur when using the carrier signal as a reference clock. There is a standard called Type A in the NFC standard. In Type A, 100% ASK (amplitude shift keying) is used for communication from the RW to the card. 100% ASK is a modulation method in which communication is performed using On / Off of a carrier signal, and there is a moment when a carrier signal is not input even if it is operating effectively. When the carrier signal is not input, the extracted reference clock is also stopped, which is a serious problem for the operation of the logic circuit.

  An object of the present invention is to provide a method of driving a logic circuit using a PLL that retains the frequency of an output clock even when a reference clock is stopped.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A phase frequency comparison circuit according to a representative embodiment of the present invention includes a PFD main unit that compares the phases of a reference clock and a feedback clock, and receives a reference clock and supplies a reference data signal to the PFD main unit. When the input of the reference clock is stopped, the reference clock stop detection unit changes the output waveform of the reference data signal supplied to the PFD main part.

  In this phase frequency comparison circuit, when the input of the reference clock is stopped, the reference clock stop detection unit may maintain the reference data signal at a low level.

  In these phase frequency comparison circuits, the PFD main part includes a first RS flip-flop that operates using the reference clock as a timing signal, and a second RS flip-flop that operates using the feedback clock as a timing signal, and the reference data signal May be a data signal of the first RS-flip-flop and the second RS-flip-flop.

  In these phase frequency comparison circuits, the PFD main part outputs an overlap signal whose state changes when the positive outputs of the first RS-flip-flop and the second RS-flip-flop are both at a high level. The stop detection unit may be operated by using the overlap signal as timing 1.

  In these phase frequency comparison circuits, the first RS-flip-flop and the second RS-flip-flop may be reset based on the overlap signal.

  A PLL circuit including these phase frequency comparison circuits is also included in the range of the present invention.

  In this PLL circuit, the PLL circuit may include a 90-degree phase delay circuit.

  Another PLL circuit according to the present invention includes a ring oscillator composed of a plurality of inverters and a 90-degree phase delay circuit, and includes a double number of inverters included in the ring oscillator. Is configured.

  By using the phase frequency comparison circuit and PLL circuit according to the present invention, when 100% ASK is input and the reference clock is stopped, the phase frequency comparison circuit autonomously switches the control ON / OFF, thereby stabilizing Can be obtained. In particular, it is possible to cope with the stoppage of the reference clock by slightly improving a normal PLL circuit, thereby minimizing the design cost.

It is a conceptual diagram which shows the structure of PLL generally used with an IC card. It is a conceptual diagram which shows the structure of PLL concerning the 1st Embodiment of this invention. It is a block diagram of the PFD main part. It is a block diagram of a reference clock stop detection unit. 3 is a timing chart showing a series of operations when a reference clock precedes in the first embodiment of the present invention. 4 is a timing chart showing a series of operations when a feedback clock precedes in the first embodiment of the present invention. FIG. 4 is a configuration diagram of the main part of the PFD in FIG. 3 represented by logic gates. It is a block diagram of VCO with a 90 degree | times delay circuit regarding the 2nd Embodiment of this invention. It is a conceptual diagram showing how PLL concerning the 2nd Embodiment of this invention is used with an NFC chip | tip. It is an internal block diagram of the non-contact type card built-in mobile phone.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, it is not irrelevant to one another, and one is related to some or all of the other, details, supplementary explanations, and the like. Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except for the specific number, the number may be more than or less than the specified number.

  Further, in the following embodiments, it is needless to say that the constituent elements are not necessarily essential unless particularly specified and apparently essential in principle. The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by an integrated circuit technology such as CMOS (complementary MOS transistor). Note that in the embodiment, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: abbreviated as a MOSFET transistor) does not exclude a non-oxide film as a gate insulating film.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Phenomenon that becomes an issue)
FIG. 1 is a conceptual diagram showing a configuration of a PLL (Phase Lock Loop) generally used in an IC card.

  The phase and frequency of the clock output from the voltage controlled oscillation circuit (Voltage Controlled Oscillator: VCO) 101 are compared with the reference clock ref_clk in the phase frequency comparison circuit (Phase Frequency Detector: PFD) 102.

  In the figure, the VCO 101 outputs a clock having two frequencies, but this can be generated by frequency division / multiplication. Therefore, it is assumed that the VCO 101 has a frequency divider / multiplier (not shown).

  The PFD 102 is a comparator that compares the phase of the clock extracted from the carrier signal input from the antenna and the clock output from the VCO 101.

  The PFD 102 outputs the down signal when the phase of the VCO 101 is ahead of the reference clock ref_clk, and outputs the up signal when the phase is behind.

  The up signal is a signal line on which a pulse having a width of the phase difference rides when the phase of the reference clock ref_clk is advanced compared to the phase of the feedback clock. On the other hand, the down signal is a signal line on which a pulse having a phase difference width is applied when the phase of the reference clock ref_clk is delayed compared to the phase of the feedback clock. The up signal raises the control potential Vcntrl of the VCO 101, and the down signal lowers the control potential Vcntrl of the VCO 101.

  The charge pump 103 is a circuit that raises and lowers the control potential Vcntrl of the VCO 101 based on the up signal and the down signal. Since the oscillation frequency of the VCO 101 is controlled by the control potential Vcntrl, the reference clock and the output of the VCO 101 are stabilized in a state where the phase and the frequency coincide with each other.

  The control potential Vcntrl is a signal that controls the output frequency of the VCO 101. When the control potential Vcntr rises, a low pass filter (LPF) 104 generates a DC component of the control potential Vcntrl from the up signal and the down signal. The LPF 104 determines the frequency characteristic of the control potential Vcntr, and thus the frequency characteristic of the entire PLL, and guarantees the stability of the PLL control.

  The problem when applying the above PLL to the NFC chip is the operation of the PLL when 100% ASK is input. When 100% ASK is input, the input signal amplitude may become almost zero. At this time, the reference clock stops.

  When the reference clock input to the PLL stops, the PLL control works in the direction of decreasing the oscillation frequency. When the input signal amplitude becomes a certain magnitude again and the reference clock operates, the PLL tries to lock to the input reference clock again. However, it takes time to relock the PLL due to the characteristics of the LPF.

  When 100% ASK is input in this way, the PLL frequency becomes unstable.

  To make matters worse, even if 100% ASK is input and the power input from the antenna becomes 0, the input amplitude remains for a while due to the Q of the antenna and the resonance circuit, and the frequency at that time is not necessarily the desired frequency. It is not.

  The frequency at this time is determined by the resonance frequency of a complicated circuit system such as an RW driver, an RW resonance circuit, an RW antenna, a coupling coefficient, an NFC antenna, an NFC resonance circuit, and an NFC load. Among these, the coupling coefficient changes every time communication occurs. Therefore, the frequency during the transition of the input signal from 100% to 0% cannot be guaranteed, and the frequency control of the PLL frequency is disturbed.

  In addition, although the word “100% ASK” is frequently used in the above, this indicates the following meaning.

The ASK modulation rate is as follows: A is the amplitude without modulation (large amplitude), and B is the amplitude during modulation (small amplitude).
((A−B) / (A + B)) × 100 (%)
It is prescribed by. At this time, when B = 0, the modulation rate is 100%. This signal is referred to as “100% ASK”.

(First embodiment)
FIG. 2 is a conceptual diagram showing the configuration of the PLL 100 according to the first embodiment of the present invention.

  The PFD 202 according to the present invention is arranged in a form that replaces the conventional PFD 102. The PFD 202 is roughly divided into a PFD main part 202A and a reference clock stop detection part 202B. FIG. 3 is a configuration diagram of the PFD main unit 202A, and FIG. 4 is a configuration diagram of the reference clock stop detection unit 202B.

  The PFD main part 202A is a module configured by a PFD that provides the original operation of the PFD. The PFD main part 202A includes two flip-flops 202A-1 that operate using the reference clock ref_clk as a timing and a flip-flop 202A-2 that operates using the feedback clock fb_clk that is the output of the VCO 101 as a timing.

  The reference clock ref_clk is input from the outside. Here, it is assumed that a clock extraction circuit (not shown) extracts a 13.56 MHz clock extracted from radio waves received by the antenna.

  As the feedback clock fb_clk, a clock output from the VCO 101 is assumed. In the figure, the VCO 101 outputs two clocks, but in the present embodiment, it is assumed that 13.56 MHz is fed back.

  The down signal that is the output of the flip-flop 202A-1 lowers the control potential Vcntrl to the VCO 101. The up signal output from the flip-flop 202A-2 raises the control potential Vcntrl to the VCO 101.

  Further, a PFD control signal pfd_in_en signal that is an output of the reference clock stop detection unit 202B is added as an input signal, and is connected to the data terminals of the two flip-flops. Only when the pfd_in_en signal is “H” (high level), the two flip-flops output “H” at the fall of the input clock.

  The outputs of these two flip-flops need to be appropriately lowered from “H” to “L” (low level). This is because a path from the voltage power source to the ground potential is generated in the charge pump and power consumption is increased. The NOR gate 202A-3 plays this role.

  The inverted output of the two flip-flops is input to the NOR gate 202A-3. When one of these input signals is “H” (= one of the outputs of the two flip-flops is “L”), the NOR gate 202A-3 outputs “L”. On the other hand, when both of the input signals of the NOR gate 202A-3 are “L” (= both outputs of the two flip-flops are “H”), the NOR gate 202A-3 outputs “H”.

  The output of the NOR gate 202A-3 is input to the reference clock stop detection unit 202B as an overlap signal overlap and is also input to the reset terminals of the flip-flops 202A-1 and 202A-2.

  The overlap signal overlap is a signal indicating that the positive outputs of the flip-flops 202A-1 and 202A-2 are "H", that is, both flip-flops are in the same "H" state. The overlap signal overlap is an asynchronous signal based on outputs from flip-flops operating at different clocks. When this signal rises, the end of phase comparison is transmitted.

  The overlap signal overlap is a signal indicating that the outputs of the flip-flop 202A-1 and the flip-flop 202A-2 are synchronized, and that the down signal and the up signal immediately after the synchronization are rising at the same time. When the overlap signal “overlap” rises, the flip-flop 202A-1 and the flip-flop 202A-2 are reset, and the down signal or the up signal changes from “H” to “L”.

  Note that the 3 ns delay circuit after the overlap signal adjusts the pulse width of the overlap signal.

  Next, the reference clock stop detection unit 202B will be described.

  The reference clock stop detection unit 202B includes three flip-flops 202B-1, 202B-2, and 202B-3. These are connected in series.

  The reference clock stop detection unit 202B receives an overlap signal overlap, a reference clock ref_clk, and a feedback clock fb_clk as input signals.

  First, the flip-flop 202B-1 will be described.

  The data terminal of this flip-flop is fixed to “H”. In addition, an overlap signal overlap is input as the timing of the flip-flop.

  The inverted output of the flip-flop 202B-1 is defined as an output signal pfd_en0. The output signal pfd_en0 becomes “L” at the rising edge of the overlap signal “overlap”, and becomes “H” at the rising edge of the reference clock ref_clk input to the reset terminal (inverted input in the figure). That is, the output signal pfd_en0 becomes “L” when the phase comparison is completed, and becomes “H” when the reference clock ref_clk rises.

  When the output signal pfd_en0 is “L”, the complement of the clock can be realized by stopping the operation of the PFD. However, if this signal itself is used for operation control of the PFD main part 202A, a metastable state may occur.

  Next, the flip-flop 202B-2 will be described. This flip-flop is for eliminating the metastable state of the flip-flop 202B-1.

  The inverted output signal pfd_en0 of the flip-flop 202B-1 is input to the data terminal and reset terminal of the flip-flop 202B-2. The feedback clock fb_clk is inverted and input to the timing terminal of the flip-flop 202B-2. Accordingly, the flip-flop 202B-2 operates so as to latch the inverted output signal pfd_en0 of the flip-flop 202B-1 when the feedback clock fb_clk falls.

  As a result, pfd_en1 does not fall unless pfd_en0 falls continuously. Therefore, it is difficult for pfd_en1 to be in a metastable state.

  The flip-flop 202B-2 is reset when pfd_en0 rises. This is because the PFD operation is restored at high speed.

  However, in the above, depending on the input timing of the inverted output signal pfd_en0 of the flip-flop 202B-1 and the feedback clock fb_clk, there is a possibility that “whisker” rides on the output signal of the flip-flop 202B-2. Therefore, the flip-flop 202B-3 is arranged.

  The positive output signal pfd_en1 of the flip-flop 202B-2 is input to the data terminal of the flip-flop 202B-3. This is because the purpose is to remove noise on the signal.

  The feedback clock fb_clk is input as it is to the timing terminal of the flip-flop 202B-3. As a result, the output of the flip-flop 202B-2 is delayed by a half clock of the feedback clock fb_clk, and the PFD control signal pfd_in_en signal is output.

  Conversely, the inverted output signal pfd_en0 of the flip-flop 202B-1 is input to the reset terminal of the flip-flop 202B-3. Thereby, the flip-flop 202B-3 and the flip-flop 202B-2 are reset at the same timing. This is because, like the flip-flop 202B-2, the PFD operation is restored at high speed.

  The PFD control signal pfd_in_en signal, which is the positive output of the flip-flop 202B-3, becomes a reference data signal input to the data terminals of the flip-flops 202A-1 and 202A-2 of the PFD main part 202A.

  As a result, the PFD main part 202A operates only during the period when the PFD control signal pfd_in_en signal is “H”.

  FIG. 5 is a timing chart showing a series of operations when the reference clock ref_clk precedes in the first embodiment of the present invention. FIG. 6 is a timing chart showing a series of operations when the feedback clock fb_clk is preceded in the first embodiment of the present invention.

  As can be seen from these figures, while the reference clock ref_clk input from the outside exists, the first flip-flop 202B-1 of the reference clock stop detection unit 202B operates. However, when the reference clock ref_clk is no longer detected, the PFD control signal pfd_in_en signal becomes Low after a certain period of time with respect to the feedback clock fb_clk. In this case, the down signal and the up signal that are the outputs of the flip-flop 202A-1 and the flip-flop 202A-2 of the PFD main part 202A are fixed to Low.

  In this way, it is possible to control the operation / stop of the PFD main part 202A with a digital signal. As a result, it is possible to stabilize the operation of the electronic device including the PLL.

  Note that the PFD in the above description uses two flip-flops. In addition, the same operation can be realized by using a PFD called a Motorola type PFD shown in FIG.

  In this way, the PFD main part 202A is composed of logic gates. It goes without saying that reproducing the NAND gate used here by using another logic gate is also included in the scope of the present invention.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.

  When performing wireless communication, transmission of one symbol and two symbols by an IQ detection method using a sine wave and a cosine wave is generally used. Typical examples of the IQ detection method include a method using a multiplication circuit such as a Gilbert cell, and a sampling detection method that samples two points that are 90 degrees out of phase with a carrier wave.

  At this time, in order to generate the IQ component, it is necessary to generate a clock whose phase is shifted by 90 degrees. Also, the one with the same frequency as the carrier wave is better. Generally, a method of taking a 90 degree phase by multiplying by 2 using a PLL or taking a 90 degree phase using a DLL (Delay-Locked Loop) is employed.

  However, the conventional system can be designed so that the PLL frequency hardly changes at the time of 100% ASK reception, but it is difficult to guarantee the phase.

  The second embodiment of the present invention relates to a method of generating two clocks that are 90 degrees out of phase.

  FIG. 8 is a configuration diagram of a VCO 500 with a 90-degree delay circuit according to the second embodiment of the present invention. The VCO 500 is used in the form of replacing the VCO 101 related to the first embodiment.

  The VCO 500 with a 90 degree delay circuit includes two modules, a VCO unit 501 and a 90 degree delay circuit 502.

  The VCO 500 is a ring oscillator type oscillation circuit using four stages of simple current control type inverters. There are two input signals of the VCO 500, a pbias signal and a pllen_t signal.

  The VCO 500 amplifies the input of the current control type inverter to Rail-Rail (amplitude from the ground voltage to the power supply voltage) by receiving the output of the current control type inverter with a normal passive inverter. By doing so, it is possible to ensure the accuracy of the 90-degree delay circuit.

  The pbias signal and the vco_iv_fb signal are control signals for controlling the oscillation frequency. The pbias signal is an input signal to the VCO 500, and the vco_iv_fb signal is an output signal from the VCO 500. Oscillation frequency substantially proportional to the input Vcntr potential is output to vcoout by negative feedback by the opAMP 500-1.

  The pbias signal is a bias signal generated from the control potential Vcntrl in FIG. When the control potential Vcntr rises, the oscillation frequency is adjusted by being controlled by the negative feedback of the opAMP 500-1.

  The pllen_t signal is a signal for operating the PLL. While this signal is “H”, the current control type inverter operates normally, and the entire PLL operates.

  The output vcoout of the VCO unit 501 is a reference frequency for the oscillation frequency of the VCO 500. As described below, an output clock (27.12 MHz) is obtained by dividing the output vcoout of the VCO unit 501 by 2, and an output clock (13.56 MHz) is obtained by further dividing the output vcoout by 2.

  In the present embodiment, it is assumed that when PLL is input and locked at 13.56 MHz, the output vcoout is four times 54.24 MHz. By dividing the output vcoout by 2, 27.12 MHz is obtained by dividing the output vcoout by 4, and 13.56 MHz is obtained. This is equal to the output of the VCO 101 represented in FIG.

  The 90-degree delay circuit 502 has a configuration in which two VCOs are connected in series and a loop is opened. Since the sign of the signal is reversed in the central NAND 502-1, the delay amount from 90 vcoin (same as the reference clock ref_clk in FIG. 1) to 90 vcoout as the output signal is one cycle of the output vcoout of the VCO unit 501. Equal to minutes. When the PLL is locked in, the frequency of the output vcoout of the VCO unit 501 is 54.24 MHz, and this period is 1/4 of 13.56 MHz which is the frequency of the output fed back to the PFD 202 of the VCO 101 in FIG. Hit the cycle. Therefore, when the PLL is locked in, 90 vcoin and 90 vcoout have a phase difference of 90 degrees.

  With such a configuration, it is possible to prepare a VCO that can reliably output two signals having a frequency that is 90 degrees out of phase and a PLL that uses the VCO. In a normal PLL, it is difficult to maintain the phase because the frequency deviation accumulates as a phase error, whereas in the present invention, a clock extracted from a carrier wave is used, and the 90-degree delay circuit 502 This is because the output has a constant phase difference from the carrier wave.

  FIG. 9 is a conceptual diagram showing how the PLL 100 according to this embodiment is used in the NFC chip 1001.

  When operating in the card mode, the clock extraction circuit 1001a extracts the operation clock from the signal received from the NFC antenna. The extracted operation clock is input to the receiving circuit 1001b and the PLL 100.

  The PLL 100 generates a signal (90 vcoout) that is 90 degrees out of phase, outputs the signal to the receiving circuit, and supplies an operation clock to the logic circuit 1001c.

  Next, how the NFC chip 1001 is used when mounted on a mobile phone will be described. FIG. 10 is an internal configuration diagram of a non-contact card built-in mobile phone.

  A normal mobile phone includes a main CPU (application CPU) 1002, a UIM card module 1003, a human interface (operation unit and display unit) 1004, and a mobile RF module 1005.

  In this configuration, the NFC chip 1001 is arranged so as to be connected to the main CPU (application CPU) 1002 and the UIM card module 1003. In the figure, the modules are directly connected by signal lines, but may be connected by using an internal bus.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The VCO and PLL according to the present invention can be used for a contactless card or a wireless communication device.

100 ... PLL, 101, 500 ... VCO, 102,202 ... PFD,
103 ... Charge pump, 104 ... LPF,
202A: PFD main part, 202B: reference clock stop detection part,
501 ... VCO section, 502 ... 90 degree delay circuit,
1001 ... NFC chip, 1002 ... Main CPU,
1003 ... UIM card module,
1004 ... Human interface, 1005 ... Portable RF module.

Claims (8)

A PFD main part that compares the phases of a reference clock and a feedback clock; and a reference clock stop detection part that receives the reference clock and supplies a reference data signal to the PFD main part.
When the input of the reference clock is stopped, the reference clock stop detection unit changes the output waveform of the reference data signal supplied to the PFD main unit.   2. The phase frequency comparison circuit according to claim 1, wherein the reference clock stop detection unit maintains the reference data signal at a low level when the input of the reference clock is stopped. 3. The phase frequency comparison circuit according to claim 2, wherein the PFD main part is a first RS flip-flop that operates using the reference clock as a timing signal, and a second RS flip-flop that operates using the feedback clock as a timing signal. Including
The phase frequency comparison circuit, wherein the reference data signal is a data signal of the first RS-flip-flop and the second RS-flip-flop.   4. The phase frequency comparison circuit according to claim 3, wherein the PFD main part is an overlap signal whose state changes when both the positive outputs of the first RS-flip flop and the second RS-flip flop are at a high level. And the reference clock stop detection unit operates with the overlap signal as timing 1.   5. The phase frequency comparison circuit according to claim 4, wherein the first RS-flip-flop and the second RS-flip-flop are reset based on the overlap signal.   A PLL circuit comprising the phase frequency comparison circuit according to claim 1.   7. The PLL circuit according to claim 6, wherein the PLL circuit includes a 90-degree phase delay circuit. A PLL circuit including a ring oscillator composed of a plurality of inverters and a 90-degree phase delay circuit,
A PLL circuit in which the 90-degree phase delay circuit is configured to include twice the number of inverters included in the ring oscillator.

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