JP2012199702A - Solid state image sensor, driving method thereof, and electronic information apparatus - Google Patents

Abstract

A drive method for improving the image quality of a horizontal division CCD, which efficiently drives charge transfer from the VCCD to the HCCD and prevents vertical lines in the still mode and the moving image mode, thereby improving the image quality. Get a picture.
SOLUTION: A vertical transfer gate 15 of a vertical register adjacent to the horizontal transfer gates H1 and H2 of the horizontal register is at a middle potential, and one of the vertical transfer gates 14A to 14C closest to the horizontal transfer gates H1 and H2 is low. The waiting time at the time of the potential is configured to be longer than the switching time t0 of the vertical transfer clocks of the other normal pixel portions.
[Selection] Figure 2

Description

  The present invention relates to a solid-state imaging device composed of a semiconductor element that photoelectrically converts and captures image light from a subject, a method for driving the solid-state imaging device, and, for example, a digital that uses this solid-state imaging device as an image input device in an imaging unit. The present invention relates to an electronic information device such as a digital camera such as a video camera and a digital still camera, an image input camera such as a surveillance camera, a scanner device, a facsimile device, a television phone device, and a camera-equipped mobile phone device.

  In recent years, the image quality of digital still cameras has been increasing rapidly, and solid-state imaging devices having a number of pixels of 1 million pixels or more, especially CCD image sensors, are widely used. In these CCD image sensors, a driving method (still mode) for obtaining a still image by independently reading out signal charges of all pixels and a driving method (monitoring mode) for displaying a moving image on a liquid crystal monitor or the like are switched. It is common to use.

  In order to achieve the function of the monitoring mode, a frame rate of about 30 frames per second is required. However, because the drive frequency characteristics of the CCD image sensor are limited or the power consumption is reduced, the drive frequency cannot be increased, and it is difficult to ensure the frame rate in the monitoring mode as the number of pixels of the CCD image sensor increases. It has become.

  On the other hand, in general, in a CCD image sensor having a number of pixels of 1 million pixels or more, the amount of data is reduced by reading out only the signal charges from some pixels in the vertical direction and thinning the number of lines. The frame rate can be improved by reducing the frame rate.

  There is also a method for improving the frame rate by reducing the data amount of pixels in the horizontal direction. As the simplest method for reducing the data amount of the pixel in the horizontal direction, there is a method of providing a discharge drain at the junction between the vertical CCD and the horizontal CCD corresponding to the portion where data is thinned out. In addition to this, FIG. 6 shows a method of thinning out charge data of a plurality of row lines arranged in the horizontal direction as a method of reducing the data amount in the vertical direction.

  FIG. 6 is a plan view schematically showing a transfer configuration example of a conventional solid-state imaging device.

  In FIG. 6, a conventional solid-state imaging device 100 is an interlaced CCD image sensor having a four-phase drive vertical transfer register. The CCD image sensor includes a photodiode 101 as a light receiving unit, a transfer gate 102, a vertical transfer register 103, a horizontal transfer register 104, a charge detection unit 105, an output amplifier 106, and a discharge drain 107.

  The photodiodes 101 are provided in a matrix on a semiconductor substrate, and RGB color filters are provided on the front surface thereof in a Bayer arrangement.

  The vertical transfer register 103 is provided adjacent to each column of the photodiodes 101 and is connected to the photodiodes 101 via the transfer gates 102. In each vertical transfer register 103, the signal charge read from the photodiode 101 is transferred in the vertical direction by four-phase driving of φV1 to φV4.

  The horizontal transfer register 104 is provided in a direction perpendicular to the plurality of vertical transfer registers 103. In the horizontal transfer register 104, the signal charges transferred by the vertical transfer registers 103 are transferred in the horizontal direction by two-phase driving of φH1 and φH2. The signal charge transferred by the horizontal transfer register 104 is detected by the charge detection unit 105 and converted into a voltage, and an amplified imaging signal is output from the output amplifier 106.

  The sweep-out drain 107 is provided adjacent to the lower part of the horizontal transfer register 104. In this CCD image sensor, unnecessary charge is swept out in units of rows and discharged to the drain 107, whereby the charge data of a plurality of row lines arranged in the horizontal direction can be thinned out.

  On the other hand, when all pixel signals in the horizontal direction are read out, the drains 107 of all the pixel columns are turned off, and when arbitrary pixel signals in the horizontal direction are thinned out, The sweep-out drain 107 is turned on. In the pixel column in which the discharge drain 107 is turned on, signal transfer from the vertical CCD to the horizontal CCD is not performed, and the signal charge flows to the discharge drain 107.

  As a result, it is possible to obtain a method of reading a signal of only a necessary vertical CCD column to the horizontal CCD. However, in such a method, since spatial information in the horizontal direction is thinned out, there are cases in which adverse effects (jaggies, false colors, cracks, etc.) due to this occur.

  As means for solving this, a method of adding a plurality of horizontal pixel signals has been proposed as a method of reducing the amount of horizontal pixel data without thinning out spatial information in the horizontal direction. However, the color filter array employed in the CCD image sensor is generally different for each pixel in the horizontal direction. Once signal charges are read from the vertical register to the horizontal register, signals of the same color are added. I can't. For this reason, in order to add signals of the same color, the signal reading from the vertical register to the horizontal register is divided into multiple times, the signal reading from the vertical register to the horizontal register, and the subsequent signal from the vertical register to the horizontal register. Prior to reading, it is necessary to repeatedly perform horizontal transfer for moving the read signal to a vertical column of the same color component.

  The gate layout for adding pixel signals of the same color in the horizontal direction and the driving method thereof have the following inventions. For example, a method of adding two pixels in the horizontal direction is shown in Patent Document 1, and the frame rate of the camera is improved by this method. Furthermore, when the number of pixels increases, in order to ensure the same frame rate, it is necessary to increase the number of added pixels to 3 pixels in the horizontal direction and 4 pixels in the horizontal direction.

  For example, as a method for adding three pixels in the horizontal direction, a method shown in FIG. This method has a three-column period configuration, each of which has a transfer portion having an independent transfer gate, and controls charge transfer in an arbitrary three-column period. As described above, Patent Documents 3 and 4 propose a method of reading signal charges from a vertical CCD to a horizontal CCD by dividing horizontal reading into three times.

  Such a pixel addition method is also called a horizontal three-division method, and in order to obtain a frame image, it is necessary to read out the pixel signal in the horizontal direction by dividing it into 1/3 times.

  FIG. 7 is a timing chart schematically showing a transfer driving example of a three-column cycle in a conventional solid-state imaging device. FIG. 8 is a waveform diagram of a transfer drive signal having a three-column period in the conventional solid-state imaging device of FIG.

  7 and 8, in the conventional solid-state imaging device 200 having a three-column period, four pixels of the optical black portion are provided below the pixels arranged in the vertical direction (column direction), and further horizontally below the pixels. The signal signal is read from the vertical CCD to the horizontal CCD by dividing the pixel signal in the direction by 1/3 three times. Each signal charge at the head in the vertical direction (column direction) is held at one end in lines 13A to 13C having a three-column period, and signal charges are read out to 15 lines by sequentially selecting the lines 14A to 14C. ing. In short, at the time t1 of the first field, after the signal charges at the head in the vertical direction (column direction) are once held in the lines 13A to 13C of the three-column period, the signal charges of 13C are transferred at the next time t2. Then, the signal charge of 14C is transferred to the next 15 at time t3, and the signal charge of 15 is transferred to the horizontal charge transfer path at time t4. The horizontal CCD is driven to the next addition point of the same color. The signal charge of 13B starts to be transferred to 14B at time t5 in the next second field, the signal charge of 13B is transferred to 14B at the next time t6, and further, the signal charge of 14B becomes 15 at time t7. Charge transfer is performed, and 15 signal charges are transferred to the horizontal charge transfer path at time t8. The horizontal CCD is driven to the next addition point of the same color. Further, the signal charge of 13A starts to be transferred to the signal charge of 14A at the time t9 in the third field, the signal charge of 13A is transferred to the charge of 14A at the next time t10, and further the signal charge of 14A at the time t11. Is transferred to 15 and at time t12, 15 signal charges are transferred to the horizontal charge transfer path. The horizontal CCD is driven to the next addition point of the same color.

  Finally, in Patent Document 5, by moving a gate having a large capacity in a slow time and moving a gate having a small capacity in an early time, the charge transfer of the signal charge is efficiently performed, and the charge transfer of the signal charge is performed as the charge remaining. It is described that it is performed smoothly.

JP 2005-39561 A JP 2006-310655 A JP 2000-115643 A Japanese Patent Laid-Open No. 11-54741 JP 2002-262183 A

  In the above-described conventional configuration, when signal charge is left behind in the charge transfer path, normally, in the pixel portion, the charge transfer leftover is carried over to the next signal charge every time as shown in FIG. Although there is no image degradation, if there is any signal charge left in the adder, the signal charge is left in the adjacent column as shown in FIG. 9B, and the signal charge is always mixed in the adjacent column. A line defect straddling two vertical lines will occur. As described above, the adding unit severely deteriorates the image quality even if a very small signal charge is left behind.

  In general, the drive timing for improving transfer efficiency extends the switching time of pulses applied to a terminal having a large gate load (Patent Document 5).

  However, since the load capacity of the adding unit gate is very small (for example, 1/1000) and the time constant is also small, transfer timing is not considered at all in the conventional driving of the adding unit gate (Patent Documents 1 to 5).

  The present invention solves the above-described conventional problems, and is a driving method for improving the image quality of a horizontal division CCD, which efficiently drives charge transfer from the VCCD to the HCCD, and in a still mode or a moving image mode. A solid-state imaging device capable of preventing a vertical line of the image and obtaining a high-quality image, a method for driving the solid-state imaging device, a mobile phone device with a camera using the solid-state imaging device as an image input device in an imaging unit, etc. The purpose is to provide electronic information equipment.

  The solid-state imaging device of the present invention is a horizontal division type solid-state imaging device that periodically reads out charge transfer from a vertical register to a horizontal register in a plurality of times, and the vertical register adjacent to the horizontal transfer gate of the horizontal register. The waiting time when the vertical transfer clock of the vertical transfer gate of the register is the middle potential and the vertical transfer clock of the second vertical transfer gate closest to the horizontal transfer gate is the low potential is the switching time of the vertical transfer clock of the normal pixel portion The object is achieved by that.

  Preferably, the waiting time in the solid-state imaging device of the present invention is maintained 1.1 to 5 times longer than the switching time of the vertical transfer clock of the normal pixel portion.

  Further preferably, the waiting time in the solid-state imaging device of the present invention is maintained 3 to 5 times longer than the switching time of the vertical transfer clock of the normal pixel portion.

  Furthermore, it is preferable that the waiting time in the solid-state imaging device of the present invention is longer than a period in which one field time is equally divided by each processing time, and is a period that can be set so that the entire one field time does not become longer.

  Further preferably, the waiting time in the solid-state imaging device of the present invention is a period in which the signal charges are completely transferred.

  More preferably, the waiting time in the solid-state imaging device of the present invention is such that the potential of the vertical transfer gate that is second closest to the horizontal transfer gate is set to a low potential, and the signal charge of the vertical transfer gate is transferred vertically to the middle potential. This is the period during which charges are transferred to the gate.

  Further preferably, in the solid-state imaging device of the present invention, a horizontal transfer clock to the horizontal transfer gate is set to a high level potential of +3 V, and a vertical transfer clock to a vertical transfer gate closest to the horizontal transfer gate is set to 0 V of a middle potential. The vertical transfer clock of the vertical transfer gate that is the second closest to the horizontal transfer gate is set to -7 V having a low potential.

  Further, preferably, the middle potential of 0 V in the solid-state imaging device of the present invention is increased to the + voltage side and is set to a voltage lower than the +3 V.

  Furthermore, preferably, for each vertical transfer gate in the solid-state imaging device of the present invention, a plurality of types of impurity concentration regions having a high concentration in the charge transfer direction are formed, and the vertical transfer gate is configured so that signal charges are smoothly transferred. The lower potential is sloped.

  Further preferably, in the horizontal division system in the solid-state imaging device of the present invention, horizontal 2 in which charge transfer reading from the vertical register to the horizontal register is periodically performed in any of 2 to 5 times. ~ 5 division method.

  Further preferably, each of the signal charges at the head in the column direction is held at one end by n vertical transfer gates of n (n is a plurality) column period third closest to the horizontal transfer gate in the solid-state imaging device of the present invention, By sequentially selecting n vertical transfer gates of the second closest n column period from the horizontal transfer gate, signal charges are sequentially read out from the horizontal transfer gate to the closest vertical transfer gate. Yes.

  The solid-state imaging device driving method according to the present invention is a solid-state imaging device driving method having a horizontal division method in which reading of charge transfer from a vertical register to a horizontal register is periodically performed in a plurality of times. The waiting time when the vertical transfer clock of the vertical transfer gate of the vertical register adjacent to the transfer gate is the middle potential and the vertical transfer clock of the vertical transfer gate closest to the horizontal transfer gate is the low potential is the normal pixel The switching time of the vertical transfer clock is longer than that, thereby achieving the above object.

  The electronic information device of the present invention uses the solid-state imaging device of the present invention as an image input device in an imaging unit, and thereby achieves the above object.

  With the above configuration, the operation of the present invention will be described below.

  In the present invention, in a horizontal division type solid-state imaging device that periodically reads out charge transfer from a vertical register to a horizontal register in a plurality of times, the vertical transfer gate of the vertical register adjacent to the horizontal transfer gate of the horizontal register The waiting time when the vertical transfer clock is the middle potential and the vertical transfer clock of the second vertical transfer gate closest to the horizontal transfer gate is the low potential is configured to be longer than the switching time of the normal pixel vertical transfer clock. Yes.

  As a result, it is possible to prevent signal charges from remaining from the vertical register to the horizontal register, drive charge transfer efficiently, and prevent vertical lines in the still mode and moving image mode. Can be obtained.

  As described above, according to the present invention, the waiting time when the vertical transfer gate adjacent to the horizontal transfer gate is at the middle potential and the second vertical transfer gate from the horizontal transfer gate is at the low potential is set to the other vertical transfer clock. Since it is longer than the switching time, it is possible to prevent signal charges from being left from the vertical register to the horizontal register. As a result, a CCD image in the still mode or moving image mode obtains a high-quality image without vertical lines. be able to.

It is a top view which shows typically the example of a transfer structure of the solid-state image sensor in Embodiment 1 of this invention. FIG. 2 is a waveform diagram of a transfer drive signal having a three-column period in the solid-state imaging device of FIG. 1. FIG. 5 is a potential diagram schematically showing a case where signal charges of a vertical transfer gate are set to a low potential and charges are transferred from a middle potential vertical transfer gate to a high level potential horizontal transfer gate. It is a principal part top view which shows typically the case where the potential under a vertical transfer gate is inclined so that a signal charge may be smoothly transferred using two types of impurity concentrations for each vertical transfer gate. It is a block diagram which shows the example of schematic structure of the electronic information device which used the solid-state image sensor of Embodiment 1 of this invention for the imaging part as Embodiment 2 of this invention. It is a top view which shows typically the transfer structural example of the conventional solid-state image sensor. It is a timing diagram which shows typically the example of transfer drive of the 3 column period in the conventional solid-state image sensor. It is a wave form diagram of the transfer drive signal of the 3 column period in the conventional solid-state image sensor of FIG. (A) is a schematic diagram for demonstrating the case where the signal charge is left behind in the charge transfer path, and (b) is a diagram for explaining the case where the signal charge is left behind in the addition unit. It is a schematic diagram.

  Hereinafter, Embodiment 1 of the solid-state imaging device and the driving method thereof according to the present invention and implementation of an electronic information device such as a mobile phone device with a camera using Embodiment 1 of the solid-state imaging device as an image input device in an imaging unit will be described below. Form 2 will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a plan view schematically showing a transfer configuration example of a solid-state imaging device in Embodiment 1 of the present invention.

  In FIG. 1, in the solid-state imaging device 1 according to the first embodiment, as a method for improving the frame rate by reducing the data amount of pixels in the horizontal direction without thinning out spatial information in the horizontal direction, a plurality of horizontal directions are used. In order to add signals of the same color, signal readout from the vertical register to the horizontal register is divided into multiple times, signal readout from the vertical register to the horizontal register, and subsequent vertical Prior to signal reading from the register to the horizontal register, it is necessary to repeatedly perform horizontal transfer in which the read signal is moved to a vertical column of the same color component. In the solid-state imaging device 1 of the first embodiment, the pixel addition method for reading the signal charge from the vertical register to the horizontal register by dividing the signal charge horizontal readout a plurality of times (here, three times) is a horizontal division method (here, horizontal 3). This is also called a division method, and each signal charge in the horizontal direction is read from the vertical register to the horizontal register in a period of three columns.

  In the solid-state imaging device 1, four pixels of the vertical transfer gate 2 of the optical black portion are provided at a position below each pixel in which a plurality of vertical transfer gates are arranged in the vertical direction (column direction), and further horizontally below that. The signal charge in the direction is read from the vertical register to the horizontal register at a period of three columns. The vertical transfer gates 13A to 13C having a period of three columns each hold one end of each signal charge in the vertical direction (column direction), and the vertical transfer gates 14A to 14C are sequentially selected by sequentially selecting the vertical transfer gates 14A to 14C. The signal charge is read out by a common gate at 14C.

  FIG. 2 is a waveform diagram of a transfer drive signal having a three-column period in the solid-state imaging device 1 of FIG.

  As shown in FIGS. 1 and 2, at the time t1 of the first field, after the signal charges at the beginning of each vertical direction (column direction) are held at one end by the vertical transfer gates 13A to 13C of the three column periods of the vertical register. At the next time t2, the signal charge of the vertical transfer gate 13C of the vertical register is transferred to the next vertical transfer gate 14C of the vertical register, and at the time t3, the signal charge of the vertical transfer gate 14C of the vertical register is transferred to the next vertical transfer. Charges are transferred to the vertical transfer gate 15 of the register. Further, at time t4, the signal charge of the vertical transfer gate 15 is transferred to the horizontal transfer gates H1 and H2 of the horizontal register. The horizontal transfer clock φH of the horizontal register is driven to the next addition position of the same color.

  At time t5 of the next second field, the signal charge of the vertical transfer gate 13B of the vertical register starts to be transferred to the vertical transfer gate 14B of the vertical register, and at the next time t6, the signal charge of the vertical transfer gate 13B of the vertical register. Is transferred to the vertical transfer gate 14B of the vertical register, and the signal charge of the vertical transfer gate 14B of the vertical register is transferred to the vertical transfer gate 15 of the vertical register at time t7. The signal charge of the transfer gate 15 is transferred to the horizontal transfer gates H1 and H2 of the horizontal register. The horizontal transfer clock φH of the horizontal register is driven to the next addition position of the same color.

  At time t9 in the next third field, the signal charge of the vertical transfer gate 13A of the vertical register starts to be transferred to the vertical transfer gate 14A of the vertical register, and at the next time t10, the signal charge of the vertical transfer gate 13A of the vertical register is changed. The charge is transferred to the vertical transfer gate 14A of the vertical register, and further, the signal charge of the vertical transfer gate 14A of the vertical register is transferred to the vertical transfer gate 15 of the vertical register at time t11, and the vertical transfer gate 15 of the vertical register is transferred at time t12. Are transferred to the horizontal transfer gates H1 and H2 of the horizontal register. The horizontal transfer clock φH of the horizontal register is driven to the next addition position of the same color.

  In this case, in the solid-state imaging device 1 according to the first embodiment, the vertical transfer gate 15 of the vertical register adjacent to the horizontal transfer gates H1 and H2 of the horizontal register is at the middle potential (intermediate potential M) and from the horizontal transfer gates H1 and H2. The waiting time when any of the second closest vertical transfer gates 14A to 14C is at the low potential (low potential L) is configured to be longer than the switching time t0 of the vertical transfer clocks of the other normal pixel portions (circle in FIG. 2). A portion of A to C surrounded by) prevents signal charges from being left behind.

  The load capacity of the vertical transfer gates 13A to 13C and 14A to 14C and the vertical transfer gate 15 which are adder gates is very small (for example, about 1/1000 compared to the vertical transfer gates of other normal pixels) and the time constant is also small. Conventionally, the driving timing of the adding unit gate is not configured to be long because it is light, but in the solid-state imaging device 1 of the first embodiment, the driving timing of the adding unit gate is configured to be long in time. In short, as shown in FIG. 3, the horizontal transfer clock to the horizontal transfer gates H1 and H2 is set to the high level potential H, and the vertical transfer clock V15 to the vertical transfer gate 15 closest to the horizontal transfer gates H1 and H2 is set to the intermediate potential M. The vertical transfer clock of the normal pixel portion is a state in which any one of the vertical transfer clocks V14A to V14C to any one of the vertical transfer gates 14A to 14C that is the second closest to the horizontal transfer gates H1 and H2 is set to the low potential L. The switching time t0 (charge transfer time) is exceeded, and it is maintained as long as 1.1 to 5 times (more preferably 3 to 5 times) as in the A to C portions. The standby time that is maintained about 3 to 5 times longer is the maximum time that can be taken by the horizontal division method. In short, one field time is determined by the number of frames per second, and each period of time t1 to t4 exists within the one field time, and the signal charge of the vertical transfer gate 14C is transferred to the next vertical transfer gate 15. The period of time t3 during which charges are transferred to is long. This period of time t3 (standby time) is a period longer than the period (approximately 20 clocks of the reference clock) obtained by equally dividing one field time by the times t1 to t4, so that the entire one field time does not become longer. Further, the period of time t3 (standby time) may be a period in which the signal charges are completely transferred. In any case, it is meaningless to extend the whole field time because the whole time becomes long, and the entire one field time is efficiently used to transfer the signal charge of the vertical transfer gate 14C to the next vertical transfer gate 15. The period of time t3 to take is long.

  The horizontal transfer clock to the horizontal transfer gates H1 and H2 is set to the high level potential H, for example, + 3V, the vertical transfer clock V15 to the vertical transfer gate 15 closest to the horizontal transfer gates H1 and H2 is set to 0V of the intermediate potential M, and the horizontal transfer gate A normal pixel portion in a standby state (standby time) in which one of the vertical transfer clocks V14A to V14C to any of the vertical transfer gates 14A to 14C that is the second closest to H1 and H2 is set to -7V of a low potential L. The vertical transfer clock V15 to the vertical transfer gate 15 is set to +1 V other than 0V of the intermediate potential M, for example, when the vertical transfer clock is maintained longer than the vertical transfer clock switching time t0 (charge transfer time), for example, about 3 to 5 times longer. The charge transfer efficiency is improved, but the power supply must have a potential of +1 V in addition to the ground potential (0 V). There is Tsu door. In any case, if 0V (ground potential) of the middle potential M increases to the + voltage side and a voltage lower than + 3V of the high level potential H is used, the charge transfer efficiency is improved.

  As shown in FIG. 4, when the charge transfer direction is the direction of the arrow, a plurality of types of impurity concentrations, for example, two types of impurity concentrations N + and N− are set for each vertical transfer gate. As a result, when a predetermined gate voltage is applied to the vertical transfer gate, the potential under the vertical transfer gate is inclined, and the signal charge can be smoothly transferred in the transfer direction. In this case, the remaining signal charge can be further reduced.

  As described above, according to the first embodiment, in the solid-state imaging device 1, the vertical transfer gate 15 of the vertical register adjacent to the horizontal transfer gates H1 and H2 of the horizontal register has the middle potential and is second from the horizontal transfer gates H1 and H2. The waiting time when any of the vertical transfer gates 14A to 14C close to is low is configured to be longer than the switching time t0 of the vertical transfer clocks of the other normal pixel portions.

  Thereby, it is possible to prevent the signal charges from being left from the vertical register (VCCD) to the horizontal register (HCCD). Since the charge transfer from the VCCD to the HCCD can be driven efficiently, vertical lines in the still mode and the moving image mode can be prevented, and a high-quality image can be obtained. Therefore, the CCD image can obtain a high-quality image without vertical lines.

(Embodiment 2)
FIG. 5 is a block diagram illustrating a schematic configuration example of an electronic information device using the solid-state imaging device 1 according to Embodiment 1 of the present invention as an imaging unit as Embodiment 2 of the present invention.

  In FIG. 5, an electronic information device 90 according to the second embodiment includes a solid-state image pickup device 91 that obtains a color image signal by performing predetermined signal processing on the image pickup signal from the solid-state image pickup device 1 according to the first embodiment. A memory unit 92 such as a recording medium capable of recording data after processing a color image signal from the solid-state imaging device 91 for recording, and a predetermined signal for displaying the color image signal from the solid-state imaging device 91 The display unit 93 such as a liquid crystal display device that can be displayed on a display screen such as a liquid crystal display screen after processing, and the color image signal from the solid-state imaging device 91 can be subjected to communication processing after predetermined signal processing for communication. A communication unit 94 such as a transmission / reception device, and a printer that can perform print processing after performing a predetermined print signal processing for color image signals from the solid-state imaging device 91 for printing. And an image output unit 95. The electronic information device 90 is not limited to this, but in addition to the solid-state imaging device 91, at least one of a memory unit 92, a display unit 93, a communication unit 94, and an image output unit 95 such as a printer. You may have.

  As described above, the electronic information device 90 includes, for example, a digital camera such as a digital video camera and a digital still camera, an in-vehicle camera such as a surveillance camera, a door phone camera, and an in-vehicle rear surveillance camera, and a video phone camera. An electronic device having an image input device such as an image input camera, a scanner device, a facsimile device, a camera-equipped mobile phone device, and a portable terminal device (PDA) is conceivable.

  Therefore, according to the third embodiment, based on the color image signal from the solid-state imaging device 91, it can be displayed on the display screen, or can be printed out on the paper by the image output unit 95. (Printing), communicating this as communication data in a wired or wireless manner, performing a predetermined data compression process in the memory unit 92 and storing it in a good manner, or performing various data processings satisfactorily Can do.

  In the first embodiment, the horizontal division method is described as the horizontal three division method. However, the present invention is not limited to this, and reading of charge transfer from the vertical register to the horizontal register is divided into two, four, or five times. Alternatively, the horizontal division method, the horizontal division method, the horizontal division method, or the horizontal division method may be used.

  That is, each of the three vertical transfer gates 13A to 13C having a period of three columns closest to the horizontal transfer gate holds one end of each signal charge in the column direction, and has a period of three columns closest to the horizontal transfer gate. Although the case where the signal charges are sequentially read from the horizontal transfer gate to the one vertical transfer gate 15 by sequentially selecting the three vertical transfer gates 14A to 14C has been described, the present invention is not limited thereto. First, each signal charge at the head in the column direction is held once by n vertical transfer gates of the n (n is a plurality) column period that is the third closest to the horizontal transfer gate, and the n columns that are the second closest to the horizontal transfer gate. This is the case where the signal charges are sequentially read out from the horizontal transfer gate to the one vertical transfer gate by sequentially selecting n vertical transfer gates with a period. The waiting time when the vertical transfer clock of the vertical transfer gate of the vertical register adjacent to the horizontal transfer gate of the horizontal register is at the middle potential and the vertical transfer clock of the second vertical transfer gate closest to the horizontal transfer gate is at the low potential. Is set longer than the switching time t0 of the vertical transfer clock of the normal pixel portion, and the present invention can be applied so that the signal charge is completely transferred.

  As mentioned above, although this invention was illustrated using preferable Embodiment 1, 2 of this invention, this invention should not be limited and limited to this Embodiment 1,2. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge, from the description of specific preferred embodiments 1 and 2 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a solid-state imaging device composed of a semiconductor element that photoelectrically converts and captures image light from a subject, a method for driving the solid-state imaging device, and, for example, a digital that uses this solid-state imaging device as an image input device in an imaging unit. In the field of digital information cameras such as video cameras and digital still cameras, image input cameras such as surveillance cameras, scanner devices, facsimile devices, television telephone devices, mobile phone devices with cameras, etc. This is a driving method for improving the image quality, which can efficiently drive the charge transfer from the VCCD to the HCCD and prevent vertical lines in the still mode and the moving image mode, thereby obtaining a high-quality image.

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 Vertical transfer gate of optical black part 13A-13C, 14A-14C, 15 Vertical transfer gate of addition part H1, H2 Horizontal transfer gate φH Horizontal transfer clock V13A-V13C, V14A-V14C, V15 Vertical transfer clock M Middle potential (intermediate potential)
L Low potential (low potential)
H High level potential

Claims (13)

In a horizontal division type solid-state imaging device that periodically reads out charge transfer from a vertical register to a horizontal register in multiple times,
The waiting period when the vertical transfer clock of the vertical transfer gate of the vertical register adjacent to the horizontal transfer gate of the horizontal register is at the middle potential and the vertical transfer clock of the vertical transfer gate closest to the horizontal transfer gate is at the low potential A solid-state imaging device in which the time is configured to be longer than the switching time of the vertical transfer clock of the normal pixel unit.   2. The solid-state imaging device according to claim 1, wherein the waiting time is maintained 1.1 to 5 times longer than a switching time of a vertical transfer clock of the normal pixel portion.   The solid-state imaging device according to claim 1, wherein the waiting time is maintained 3 to 5 times longer than a switching time of the vertical transfer clock of the normal pixel unit.   The solid-state imaging device according to claim 1, wherein the waiting time is longer than a period in which one field time is equally divided by each processing time, and is a period that can be set so that the entire one field time does not become longer.   The solid-state imaging device according to claim 1, wherein the waiting time is a period during which signal charges are completely transferred.   2. The waiting period is a period in which a potential of a vertical transfer gate that is second closest to the horizontal transfer gate is set to a low potential, and a signal charge of the vertical transfer gate is transferred to the vertical transfer gate of the middle potential. The solid-state image sensor in any one of -5.   The horizontal transfer clock to the horizontal transfer gate is set to a high level potential of +3 V, the vertical transfer clock to the vertical transfer gate closest to the horizontal transfer gate is set to 0 V of the middle potential, and the second closest to the horizontal transfer gate. The solid-state imaging device according to claim 1, wherein a vertical transfer clock of the vertical transfer gate is set to −7 V having a low potential.   The solid-state imaging device according to claim 7, wherein 0 V of the middle potential is increased to the + voltage side and is set to a voltage lower than the +3 V.   A plurality of types of impurity concentration regions having a high concentration in the charge transfer direction are formed for each of the vertical transfer gates, and the potential below the vertical transfer gate is inclined so that signal charges are smoothly transferred. The solid-state imaging device according to 1.   2. The horizontal division method is a horizontal 2 to 5 division method in which reading of charge transfer from the vertical register to the horizontal register is periodically divided into any of 2 to 5 times. Solid-state image sensor.   Each of the signal charges at the head in the column direction is held once by n vertical transfer gates of the n (n is a plurality) column period that is the third closest to the horizontal transfer gate, and the n columns that are the second closest to the horizontal transfer gate. 2. The solid-state imaging device according to claim 1, wherein signal charges are sequentially read out to one vertical transfer gate closest to the horizontal transfer gate by sequentially selecting n vertical transfer gates having a cycle. In a method for driving a solid-state imaging device having a horizontal division system that periodically reads out charge transfer from a vertical register to a horizontal register in a plurality of times,
The waiting period when the vertical transfer clock of the vertical transfer gate of the vertical register adjacent to the horizontal transfer gate of the horizontal register is at the middle potential and the vertical transfer clock of the vertical transfer gate closest to the horizontal transfer gate is at the low potential A method of driving a solid-state imaging device, wherein the time is longer than the switching time of the normal pixel vertical transfer clock.   The electronic information apparatus which used the solid-state image sensor in any one of Claims 1-11 as an image input device for the imaging part.