JP2012199468A - Method of manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device manufacturing method for manufacturing a low-resistance semiconductor device with good controllability is provided.
A method of manufacturing a semiconductor device according to an embodiment of the present invention includes an intermediate product 100A including a substrate 3, a plurality of gate electrodes 15 provided in a plurality of gate trenches 12, and an insulating film 7. A step of preparing, a step of forming the interlayer insulating film 16, a step of removing the insulating film 7, a step of forming the contact trench 17, a step of forming the first electrode 19, and a second electrode 20. Forming. The insulating film is provided on the first surface of the substrate sandwiched between adjacent gate trenches among the plurality of gate trenches, and has a side wall that is recessed from the side wall of the adjacent gate trench. The interlayer insulating film is formed so as to cover a portion of the first surface of the substrate extending from the side wall of the gate trench to the side wall of the insulating film and the gate electrode. The contact trench is formed by etching using an interlayer insulating film as a mask.
[Selection] Figure 7

Description

  Embodiments described herein relate generally to a method for manufacturing a trench gate type semiconductor device having a trench contact structure.

  Insulated gate power semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are required to have low loss and low price. In order to meet such demands, a trench type semiconductor device is used, and the gate electrode is more advantageous for miniaturization and higher density than a planar type semiconductor device. A trench contact structure is used to reduce the contact resistance between the source layer and the source electrode and the contact resistance between the base layer and the source electrode. However, when the miniaturization further proceeds, a mask alignment margin cannot be obtained in a lithography process for forming a trench having a trench contact structure. In forming a trench having a trench contact structure, a highly reliable process that does not require mask alignment is desired.

JP 7-115192 A

  Provided is a method for manufacturing a semiconductor device, which manufactures a low-resistance semiconductor device with good controllability.

  In a method for manufacturing a semiconductor device according to an embodiment of the present invention, a step of preparing an intermediate product having a substrate, a plurality of gate electrodes provided in a plurality of gate trenches, and an insulating film, A step of forming, a step of removing the insulating film, a step of forming a contact trench, a step of forming a first electrode, and a step of forming a second electrode. The substrate comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer of a first conductivity type provided on the first semiconductor layer and having an impurity concentration of the first conductivity type lower than that of the first semiconductor layer; A third semiconductor layer of a second conductivity type provided on a surface of the second semiconductor layer opposite to the first semiconductor layer. The plurality of gate trenches penetrates the third semiconductor layer from the first surface of the substrate opposite to the first semiconductor layer to reach the second semiconductor layer. The plurality of gate electrodes are provided in the plurality of gate trenches via the gate insulating film. The insulating film is provided on the first surface of the substrate sandwiched between adjacent gate trenches among the plurality of gate trenches, and has a side wall that is recessed from the side wall of the adjacent gate trench. In the step of forming the interlayer insulating film, an interlayer insulating film made of a silicon oxide film is formed so as to cover a portion of the first surface of the substrate extending from the sidewall of the gate trench to the sidewall of the insulating film and the gate electrode. Is done. In the step of removing the insulating film, the insulating film is removed so that the first surface of the substrate is exposed from the interlayer insulating film under the insulating film. In the step of forming the contact trench, the exposed portion of the first surface of the substrate is etched by the RIE method using the interlayer insulating film as a mask, so that the first surface of the substrate enters the third semiconductor layer. Leading contact trenches are formed. In the step of forming the first electrode, the first electrode electrically connected to the surface of the first semiconductor layer opposite to the second semiconductor layer is formed. In the step of forming the second electrode, a second electrode electrically connected to the third semiconductor layer is formed in the contact trench.

The figure which shows the flow of each process of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 6 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 3 is a cross-sectional view of a principal part of the semiconductor device obtained by the method for manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the method for manufacturing a semiconductor device according to Modification 1 of the first embodiment. The figure which shows the flow of each process of the manufacturing process of the manufacturing method of the semiconductor device which concerns on the modification 2 of 1st Embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the method for manufacturing a semiconductor device according to Modification 2 of the first embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the method for manufacturing a semiconductor device according to Modification 2 of the first embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to Modification 2 of the first embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the method for manufacturing a semiconductor device according to Modification 2 of the first embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to Modification 2 of the first embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the method for manufacturing a semiconductor device according to Modification 2 of the first embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to Modification 2 of the first embodiment. Sectional drawing of the principal part of the semiconductor device obtained by the manufacturing method of the semiconductor device which concerns on the modification 2 of 1st Embodiment. The figure which shows the flow of each process of the manufacturing process of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the second embodiment. FIG. 10 is a partial cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the second embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings used in the description in the embodiments are schematic for ease of description, and the shape, size, magnitude relationship, etc. of each element in the drawings are not necessarily shown in the drawings in actual implementation. The present invention is not limited to the above, and can be appropriately changed within a range in which the effect of the present invention can be obtained. The semiconductor material will be described using silicon as an example. The first conductivity type and the second conductivity type will be described for n-type and p-type, respectively. When n ^{− type} , n type, and n ^{+ type} are used, it is assumed that the impurity concentration has a relationship of n ⁻ <n <n ⁺ . p ^- forms, The same applies to p-type, and ^{p +} -type. Each embodiment will be described by taking a MOSFET as an example of a power semiconductor device, but these embodiments can be similarly applied to an IGBT and other insulated gate semiconductor devices.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing the flow of each process of the manufacturing method of the semiconductor device according to the first embodiment of the present invention. 1 to 14 are fragmentary cross-sectional views of a part of the manufacturing process of the semiconductor device manufacturing method according to the first embodiment. FIG. 15 is a fragmentary cross-sectional view of the semiconductor device obtained by the semiconductor device manufacturing method according to the first embodiment. The semiconductor device manufacturing method described in this embodiment is, for example, a method of manufacturing a MOSFET having a trench-type gate electrode and a source electrode electrically connected to the source layer and the base layer by a trench contact structure. It is.

As shown in FIG. 1, the method for manufacturing a semiconductor device according to the present embodiment includes a step of preparing an intermediate product (S100), a step of forming an interlayer insulating film (S200), and a step of removing the insulating film (S300). ), Forming a contact trench (S400), forming a p ^{+ -type} contact layer (S500), forming a drain electrode (first electrode) (S600), and a source electrode (second electrode). Forming a step (S700). Here, the step of preparing an intermediate product (S100) includes the step of forming an n ^{− type} semiconductor layer (second semiconductor layer) on the n ^{+ type} semiconductor layer (first semiconductor layer) (S10), n ^- p-type base layer to form the semiconductor layer surface to form a step (S20) of forming a (third semiconductor layer), n ⁺ -type source layer on the surface of the p-type base layer (a fourth semiconductor layer) (S30), a step of forming an insulating film having a pattern on the substrate surface (S40), a step of forming a sidewall on the side wall of the insulating film (S50), a step of forming a gate trench (S60), It includes a step of forming a gate insulating film (S70), a step of forming a gate electrode (S80), and a step of removing sidewalls (S90). In addition, although the flow of each process is shown in order by the arrow in FIG. 1, it means that the next process cannot be started unless the previous process is completed as indicated by the arrow. It is not a thing. Of course, there may be a step that can be performed in parallel with the step shown before the arrow even in the step shown after the arrow. Moreover, each process is not necessarily performed in the order according to the direction indicated by the arrow. Hereafter, each said process is demonstrated using FIGS.

As shown in FIG. 2, the step of forming an n ^{− type} semiconductor layer (second semiconductor layer) on the n ^{+ type} semiconductor layer (first semiconductor layer) (S10) results in an n ^{− type} semiconductor layer (first semiconductor layer). 2 semiconductor layer) 2 is formed on the n ^{+ -type} semiconductor layer (first semiconductor layer) 1 by, for example, epitaxial growth of silicon. Alternatively, the n ^{+ -type} semiconductor layer 1 can be formed by ion implantation and heat treatment of n-type impurities on the surface of the silicon n ⁻ -type semiconductor substrate 2. n ^- p-type base layer to form the semiconductor layer surface by forming a (third semiconductor layer) (S20), p type base layer 4 the n ^- and n + -type semiconductor layer 1 in the form semiconductor layer 2 on the opposite side Formed on the surface. The p-type base layer 4 can be obtained, for example, by performing ion implantation of p-type impurities (for example, boron) on the surface of the n ⁻ -type semiconductor layer 2 opposite to the n + -type semiconductor layer 1 and subsequent heat treatment. it can. The heat treatment does not need to be performed immediately after the ion implantation, but may be performed in combination with the heat treatment required after other steps or after ion implantation of other impurities for forming other diffusion layers. Is possible. That is, when the p-type base layer 4 is formed by impurity diffusion, the step of forming the p-type base layer 4 is performed by performing other processes between the ion implantation of the p-type impurity and the heat treatment necessary for this. May be included. Further, the necessary heat treatment may be replaced by another diffusion heat treatment or a high-temperature process of another step. The process for forming a diffusion layer such as a source layer or a contact layer by ion implantation and heat treatment, which will be described later, is considered in the same manner as described above.

Next, in the step (S30) of forming an n ^{+ -type} source layer (fourth semiconductor layer) on the surface of the p-type base layer 4 opposite to the n + -type semiconductor layer 1, the n ^{+ -type} source layer 5 is The p-type base layer 4 is formed on the surface opposite to the n + -type semiconductor layer 1. The n ^{+ -type} source layer 5 can be formed, for example, by performing heat treatment after ion-implanting an n-type impurity (such as arsenic or phosphorus) into the surface of the p-type base layer 4 as described above. .

Through the above steps, the substrate 3 having the n ^{+ -type} semiconductor layer 1, the n ⁻ -type semiconductor layer 2, the p-type base layer 4, and the n ^{+ -type} source layer 5 is formed.

Next, in the step (S40) of forming an insulating film having a pattern on the substrate surface, the pattern is formed on the first surface of the substrate 3 opposite to the n ^{+ -type} semiconductor layer 1 as shown in FIG. An insulating film 7 having the following is formed. In this step, the insulating film 7 is formed as follows, for example. A first oxide film 6 made of a silicon oxide film is formed on the first surface of the substrate 3, that is, on the surface of the n ^{+ -type} source layer 5 by a CVD (Chemical Vapor Deposition) method or thermal oxidation. Thereafter, an insulating film 7 made of a silicon nitride film is formed by CVD or the like. Thereafter, a second oxide film 8 made of a silicon oxide film is formed on the surface of the insulating film 7 by a CVD method or the like. Here, in the present embodiment, a SiO ₂ / SiN / SiO ₂ film (hereinafter referred to as an ONO film) is formed by the first oxide film 6, the insulating film 7, and the second oxide film 8. Alternatively, only the insulating film 7 may be used, and at least the insulating film 7 that is a silicon nitride film may be formed. In this embodiment, an ONO film is used, but this is preferable because impurity contamination and defect growth on the substrate 3 during the process can be prevented. Next, the ONO film is etched and removed by the RIE method using the resist 9 having a predetermined pattern formed as shown in FIG. 2 as a mask, and the first surface of the substrate 3 is exposed on the surface. By removing the resist 9, the insulating film 7 having a predetermined pattern is formed on the first surface of the substrate 3 as shown in FIG.

  Next, as shown in FIGS. 4 and 5, the sidewall 11 made of a silicon oxide film is formed on the sidewall of the insulating film 7 by the step of forming the sidewall on the sidewall of the insulating film (S 50). The sidewall 11 is formed as follows, for example. A silicon oxide film 10 is formed on the entire first surface of the substrate 3 so as to cover the insulating film 7 by CVD or the like. The silicon oxide film 10 is formed on the first surface of the substrate 3, on the surface of the insulating film 7, and on the sidewall of the insulating film 7 at substantially the same film formation rate. Therefore, the thickness of the silicon oxide film 10 in the vertical direction (stacking direction of the substrate 3) on the first surface of the substrate 3 and the thickness of the silicon oxide film 10 in the vertical direction on the surface of the insulating film 7 are substantially the same. The thickness of the silicon oxide film 10 formed on the side wall of the insulating film 7 in the direction perpendicular to the first surface of the substrate 3 is equal to the thickness of the insulating film 7 rather than these thicknesses. thick. In the RIE method, the etching is anisotropic etching. Therefore, by etching the entire surface of the silicon oxide film 10 by the RIE method, the silicon oxide film on the first surface of the substrate 3 and the surface of the insulating film 7 is etched. 10 is removed, and the silicon oxide film 10 remains only on the side wall portion of the insulating film 7, which becomes the side wall 11.

  Here, the thickness of the sidewall 11 in the direction parallel to the first surface of the substrate 3, that is, the direction perpendicular to the sidewall of the insulating film 7 can be adjusted by the deposition time of the silicon oxide film 10 by the CVD method or the like. is there. Therefore, since the gate trench 12 described later is etched using the sidewall 11 as a mask, the distance from the sidewall of the gate trench 12 to the sidewall of the insulating film 7 can be adjusted by the deposition time of the silicon oxide film 10. Become. In FIG. 5, the silicon oxide film remains on the surface of the insulating film 7. This is a case where etching by the RIE method is stopped when the second oxide film 8 of the above-mentioned ONO film is formed thick and the first surface of the substrate 3 is exposed. The silicon oxide film on the surface of the insulating film 7 may be removed by continuing etching for a while after the first surface of the substrate 3 is exposed. In this embodiment, the case where a silicon oxide film remains on the insulating film 7 will be described.

Next, as shown in FIG. 6, the step of forming a gate trench (S 60) penetrates the p-type base layer 4 from the first surface of the substrate 3, reaches the n ⁻ -type semiconductor layer 2, and reaches the substrate 3. the first and the adjacent n ⁺ -type source layer 5 at the surface (or penetrate the n ⁺ -type layer source layer 5) a plurality of gate trenches 12 are formed. The formation of the gate trench 12 is performed as follows, for example. Etching is performed by the RIE method using the sidewall 11 and the insulating film 7 as a mask, whereby the sidewall of the gate trench 12 is formed along the sidewall of the sidewall 11, and the gate trench 12 is an n ^{− type} semiconductor. When the layer 2 is reached, the etching is stopped.

  Next, the gate insulating film 13 is formed so as to cover the entire inner wall of the gate trench 12 by a step of forming a gate insulating film (S70). The gate insulating film 13 is formed by, for example, thermal oxidation, and the gate insulating film 13 is a silicon oxide film. The silicon oxide film can be formed by a CVD method. Further, the gate insulating film 13 is not limited to a silicon oxide film, but can be a laminated film of a silicon oxide film and a silicon nitride film, or another dielectric film.

Next, as shown in FIGS. 7 and 8, the gate electrode 15 is formed in the gate trench 12 via the gate insulating film 13 by the step of forming the gate electrode (S <b> 80). The gate electrode 15 is formed in the gate trench 12 such that the upper end portion of the gate electrode 15 recedes from the first surface of the substrate 3 toward the n ^{+ -type} semiconductor layer 1 side. The gate electrode 15 is formed as follows, for example. Polysilicon 14 is deposited by CVD on the entire first surface of substrate 3 with sidewall 11 and insulating film 7 so as to fill gate trench 12 with gate insulating film 13 interposed. . Thereafter, the entire surface of the polysilicon 14 is etched by, for example, CDE (Chemical Dry Etching) method, the polysilicon 14 on the first surface of the substrate 3 is removed, and the upper end of the polysilicon 14 in the gate trench 12 is the substrate. The etching of the polysilicon 14 is stopped when it reaches the n ^{+ -type} semiconductor layer 1 side from the first surface 3. As a result, the upper end of the gate electrode 15 recedes from the first surface of the substrate 3 toward the n ^{+ -type} semiconductor layer 1, and the gate electrode 15 is formed in the gate trench 12.

Next, as shown in FIG. 9, the gate insulating film formed on the sidewall of the gate trench 12 above the upper end of the sidewall 11 and the gate electrode 15 is removed by the step of removing the sidewall (S <b> 90). Thus, a portion from the side wall of gate trench 12 to the side wall of insulating film 7 is exposed on the first surface of substrate 3 (in the n ^{+ -type} source layer). The removal of the sidewall 11 can be performed, for example, by wet etching with an etchant containing hydrogen fluoride. Or it can implement also by the etching by RIE method.

In the present embodiment, as described above, the step of forming the n ^{+ -type} source layer on the surface of the p-type base layer shown in FIG. 2 (S30) is performed by using the insulating film having the pattern shown in FIG. By performing before the step (S40) of forming on the surface, the n ^{+ -type} source layer 5 is formed on the surface of the p-type base layer 4. However, after the step of removing the sidewall 11 shown in FIG. 9 (S90), as shown in FIG. 10, a step of forming an n ^{+ -type} source layer on the surface of the p-type base layer (S30) is performed. It is also possible. In this case, a portion from the side wall of the gate trench to the side wall of the insulating film 7 on the first surface (part of the p-type base layer 4) of the substrate 3 is exposed to the surface, and n-type impurities are ion-implanted into this part. Thus, the n ^{+ -type} source layer 5 is formed. Therefore, as shown in FIG. 10, under the condition that the diffusion of the n-type impurity is weak, the source layer 5 is not formed on the first surface of the substrate 3 immediately below the insulating film 7, and the p-type base layer 4 is formed. It becomes a formed state. Even in such a state, the semiconductor device can be manufactured by performing the subsequent steps of the present embodiment.

The step (S10) of forming the n ^{− type} semiconductor layer (second semiconductor layer) on the n ^{+ type} semiconductor layer (first semiconductor layer), and the p type base layer (on the surface of the n ^{− type} semiconductor layer). A step (S20) of forming a third semiconductor layer), a step (S30) of forming an n ^{+ -type} source layer (fourth semiconductor layer) on the surface of the p-type base layer, and an insulating film having a pattern as a substrate Forming on the surface (S40), forming a sidewall on the sidewall of the insulating film (S50), forming a gate trench (S60), forming a gate insulating film (S70), By performing a step (S100) of preparing an intermediate product having a step of forming a gate electrode (S80) and a step of removing a sidewall (S90), as shown in FIG. ⁺ -type semiconductor layer 1, n ^- type semiconductor layer , A substrate 3 having a p-type base layer 4, and the n ⁺ -type source layer 5, through the first p-type base layer 4 from the surface of the substrate 3 n ^- type semiconductor layer a plurality of gate trenches extending into 2 Are provided on the first surface of the substrate 3 sandwiched between the plurality of gate electrodes provided between the gate insulating films and the adjacent gate trenches 12 and receded from the side walls of the adjacent gate trenches 12. An intermediate product 100A having the insulating film 7 having the sidewalls is prepared.

Next, as shown in FIG. 11, from the side wall of the gate trench 12 in the n ^{+ -type} source layer 5 (first surface of the substrate 3) of the intermediate product 100A by the step of forming an interlayer insulating film (S200). An interlayer insulating film 16 is formed so as to cover the portion reaching the side wall of the insulating film 7 and the gate electrode. The interlayer insulating film 16 is a silicon oxide film, using the insulating film 7 as a mask, a portion from the side wall of the gate trench 12 to the side wall of the insulating film 7 in the n ^{+ -type} source layer 5 exposed from the insulating film 7, and It is formed by selectively thermally oxidizing the upper end portion of the gate electrode 15. This is a structure similar to a so-called LOCOS (Local Oxidation of Silicon) structure.

Next, as shown in FIG. 12, in the step of removing the insulating film (S300), the insulating film 7 is removed by etching, for example, by the CDE method, and the first main surface (n ^{+ type)} of the substrate 3 is removed. The surface of the semiconductor layer 5 is exposed immediately below the insulating film 7 (not shown). First, since it is considered that an oxide film is attached to the surface of the insulating film 7 during the formation of the interlayer insulating film 16 or in another process, the insulating film 7 is removed before the insulating film 7 is removed. It is preferable that the surface is etched with an etching solution containing hydrogen fluoride as a pretreatment. Thereby, the surface of the insulating film 7 is cleaned. The insulating film 7 can be removed by wet etching or the like, but here is etched by the CDE method as an example. When the insulating film 7 is removed, as shown in FIG. 12, the underlying first oxide film 6 is exposed. Since the first oxide film 6 is formed extremely thin compared to the thickness of the interlayer insulating film 16, the entire first surface of the substrate 3 is etched by anisotropic etching such as RIE. The first insulating film 6 can be removed while leaving the interlayer insulating film 16 (details not shown). As a result, the first surface of the substrate 3 (the surface of the n ^{+ -type} source layer 5) is exposed immediately below the insulating film 7 (not shown). As described above, when the insulating film 7 is formed on the first surface of the substrate 3 without the first oxide film, the insulating film 7 is simply removed and the substrate 3 1 surface (the surface of the n ^{+ -type} source layer 5) is exposed immediately below the insulating film 7.

As described above, in the present embodiment, the step of forming the n + type source layer on the surface of the p-type base layer (S30), the step of forming the p-type base layer on the surface of the n− type semiconductor layer (S20), It has already been carried out between the step (S40) of forming an insulating film having a pattern on the substrate surface. However, a step (S30) of forming an n + -type source layer on the surface of the p-type base layer is implemented partly or immediately after the last step of the step (S300) of removing the insulating film shown in FIG. May be. That is, in the state where the insulating film 7 of FIG. 11 is removed and the first oxide film 6 immediately below the insulating film 7 is exposed, or the first oxide film 6 is further removed and the first surface of the substrate 3 is removed. With the (insulating surface of the p-type base layer 4) exposed, an n-type impurity such as arsenic or phosphorus is ion-implanted and the subsequent heat treatment is performed using the interlayer insulating film 16 as a mask. The n ^{+ -type} source layer 5 may be formed as shown in FIG. 12 as another high-temperature process may be performed instead.

Next, as shown in FIG. 13, in the step of forming a contact trench (S 400), the contact trench 17 is directly below the first surface (n ^{+ -type} source) of the substrate 3 where the insulating film 7 was present. It is formed so as to extend into the p-type base layer 4 from the surface of the layer 5. The contact trench 17 performs anisotropic etching such as RIE on the first surface (surface of the n ^{+ -type} source layer 5) of the substrate 3 exposed from the interlayer insulating film 16 using the interlayer insulating film 16 as a mask. Thus, the p-type base layer 4 is formed by extending along the side wall of the interlayer insulating film 16. The n ^{+ -type} source layer 5 is exposed on the side wall of the contact trench 17, and the p-type base layer is exposed on the bottom of the contact trench 17.

Next, as shown in FIG. 14, the p ^{+ -type} contact layer 18 is formed adjacent to the bottom of the contact trench 17 by the step of forming a p ^{+ -type} contact layer (S 500). The p ^{+ -type} contact layer 18 has a higher p-type impurity concentration than the p-type base layer 4. For example, a p-type impurity such as boron is exposed in or adjacent to the bottom of the contact trench 17. It is formed by ion implantation followed by heat treatment. The p ^{+ -type} contact layer 18 may be connected to the n ^{+ -type} source layer 5 at the top, but is formed so as not to be joined to the n ⁻ -type semiconductor layer 2 in the stacking direction of the gate trench 12 and the substrate 3 in the horizontal direction. Is done.

Next, as shown in FIG. 15, the drain electrode 19 is electrically connected to the surface of the n ^{+ -type} semiconductor layer 1 opposite to the p-type base layer 4 by the step of forming a drain electrode (S600). Formed. Further, in the step of forming the source electrode (S700), the source electrode 20 is formed so as to be embedded in the contact trench 17 and cover the interlayer insulating film 16. The source electrode 20 is electrically connected to the n ^{+ -type} source layer 5 at the sidewall of the contact trench 17 and the p ^{+ -type} contact layer 4 at the bottom of the contact trench 17. The p-type base layer 4 is electrically connected to the source electrode via the p ^{+ -type} contact layer 18. The source electrode 20 and the drain electrode 19 can be formed of, for example, gold, copper, or aluminum.

  Through the above manufacturing steps, the semiconductor device is provided by the semiconductor device manufacturing method according to the present embodiment. According to the semiconductor device manufacturing method of the present embodiment, the following effects can be obtained.

When a positive voltage (gate voltage) exceeding a threshold value is applied to the gate electrode 15 with respect to the source electrode 20 in a state where a positive voltage is applied to the drain electrode 19 with respect to the source electrode 20, the inversion distribution layer becomes a p-type base. It is formed at the interface between the layer 4 and the gate insulating film 13. As a result, the semiconductor device is turned on, and current flows from the drain electrode 19 to the source electrode 20. The semiconductor device has a contact trench structure in order to improve the electrical connection between the source electrode 19 and the n ^{+ -type} source layer 5 and the electrical connection between the source electrode 19 and the p-type base layer 4. In the contact trench structure, as described above, the source electrode 20 is electrically connected to the n ^{+ -type} source layer 5 at the sidewall of the contact trench 17 and the p ^{+ -type} contact layer 5 at the bottom of the contact trench 17. . If the p ^{+ -type} contact layer 18 is too close to the side wall of the gate trench 12, the formation of the inversion distribution layer is suppressed at the interface between the gate insulating film 13 and the p-type base layer 4, and the threshold voltage of the gate voltage of the semiconductor device Rises and the on-resistance between the drain electrode 19 and the source electrode 20 increases. When the miniaturization is further advanced in order to reduce the on-resistance of the semiconductor device, the above problem becomes obvious.

In the manufacturing method of the semiconductor device according to the present embodiment, by performing the step (S100) of preparing an intermediate product, as shown in FIG. 9, the n ^{+ type} semiconductor layer 1 and the n ^{− type} semiconductor layer 2 , P-type base layer 4, and n ^{+ -type} source layer 5, and a plurality of gate trenches extending from the first surface of substrate 3 through p-type base layer 4 and into n ⁻ -type semiconductor layer 2. Are provided on the first surface of the substrate 3 sandwiched between the plurality of gate electrodes 15 provided between the gate insulating films and the adjacent gate trenches 12, and from the side walls of the adjacent gate trenches 12. An intermediate product 100A having an insulating film 7 having a recessed side wall is prepared. As described above, the step of forming the n + type source layer on the surface of the p-type base layer (S30) is not necessarily included in the step of preparing the intermediate product. The n ^{+ -type} source layer 5 is not necessarily formed in the intermediate product 100A at this time, and is formed in a part of the subsequent step (S300) for removing the insulating film or immediately after this step. May be. By using the intermediate product 100A to form an interlayer insulating film (S200), the sidewall of the gate trench 12 in the n ^{+ -type} source layer 5 (in other words, the first surface of the substrate 3) of the intermediate product 100A An interlayer insulating film 16 is formed so as to cover a portion extending from to the side wall of the insulating film 7 and the gate electrode. That is, the interlayer insulating film 16 is a portion that covers a portion from the side wall of the gate trench 12 to the side wall of the insulating film 7 in the n ^{+ -type} source layer 5 (or the first surface of the substrate 3) And a portion covering the gate electrode (hereinafter referred to as a gate electrode portion). Then, in the step of forming a contact trench (S400), the contact trench 17 is etched from the first surface of the substrate 3 (the surface of the n ^{+ -type} source layer 4) by etching using the interlayer insulating film 16 as a mask. It is formed so as to extend into the p-type base layer 4.

  As described above, since the contact trench 17 is formed between the adjacent gate trenches 12, mask alignment for forming the contact trench 17 is not necessary, so that the characteristic failure of the semiconductor device due to the mask alignment failure is suppressed. can do. In addition, since the interlayer insulating film 16 used for the mask has the above-described ridge portion, the distance between the contact trench 17 and the gate trench 12 can be secured with good controllability, so that the on-resistance of the semiconductor device can be reduced with good controllability. That is, according to the method for manufacturing a semiconductor device of this embodiment, a mask alignment defect for forming a contact trench is reduced, and a semiconductor device with low on-resistance is provided with good controllability.

  Furthermore, in the manufacturing method of the semiconductor device of this embodiment, the interlayer insulating film 16 has a flange portion, and the width of this flange portion determines the interval between the gate trench 12 and the contact trench 17. The width of the flange portion is determined by the width of the side wall 11 as shown in FIG. 8, and the width of the side wall is perpendicular to the side wall of the insulating film 7 as described in the step of forming the side wall (S50). The thickness can be controlled in accordance with the film formation time of the silicon oxide film 10 covering the insulating film 7. Therefore, mask alignment for determining the distance between the gate trench 12 and the contact trench 17 is not necessary, and the gate trench 12 and the contact are formed in the time for forming the silicon oxide film 10 in the side wall forming step (S50). The distance from the trench 17 can be controlled.

  Next, a method for manufacturing a semiconductor device according to the first modification of the present embodiment will be described with reference to FIGS. Note that the same reference numerals or symbols are used for portions having the same configurations as those described in the first embodiment, and description thereof is omitted. Differences from the first embodiment will be mainly described.

FIG. 16 is a fragmentary cross-sectional view of a part of the manufacturing process of the semiconductor device manufacturing method according to the first modification of the first embodiment. The method for manufacturing a semiconductor device according to the first modification of the present embodiment is the same as the method for manufacturing a semiconductor device according to the present embodiment, after the step of forming the contact trench (S400) shown in FIG. This is different from the method for manufacturing the semiconductor device according to the present embodiment in that it further includes a step of retracting the side wall of the film 16 from the side wall of the contact trench 17, but the other points are the same. In the method of manufacturing the semiconductor device according to the modification of the present embodiment, the interlayer insulating film 16 is formed in such a range that the heel portion of the interlayer insulating film 16 is not lost by the step of retracting the sidewall of the interlayer insulating film 16 from the sidewall of the contact trench 17. The side wall is retracted from the side wall of the contact trench 17. This can be performed, for example, by isotropic etching such as CDE, but other methods may be used. As described above, the surface of the n ^{+ -type} source layer 5 is exposed from the interlayer insulating film 16 by retreating the ridge portion of the interlayer insulating film 16 from the side wall of the contact trench 17, so that the semiconductor device according to the present embodiment described above is exposed. Compared with the manufacturing method, the contact resistance between the n ^{+ -type} source layer 5 and the source electrode 20 can be further reduced. The other effects are the same as the effects of the method for manufacturing the semiconductor device according to the present embodiment. This modification can also be applied to other modifications and other embodiments described later.

  Next, a method for manufacturing a semiconductor device according to the second modification of the present embodiment will be described with reference to FIGS. FIG. 17 is a diagram illustrating the flow of each process of the manufacturing process of the semiconductor device manufacturing method according to the second modification of the first embodiment. 18 to 24 are fragmentary cross-sectional views of a part of the manufacturing process of the semiconductor device manufacturing method according to the second modification of the first embodiment. FIG. 25 is a fragmentary cross-sectional view of a semiconductor device obtained by a method for manufacturing a semiconductor device according to Modification 2 of the first embodiment.

  As shown in FIG. 17, the step (S101) of preparing the intermediate product of the method for manufacturing a semiconductor device according to the second modification of the present embodiment is an intermediate of the method for manufacturing the semiconductor device according to the present embodiment in FIG. Including a step (S81) of forming a gate electrode in a gate trench different from the step (S80) of forming a gate electrode in the gate trench included in the step of preparing a product (S100), and removing the sidewalls. It is different from the step (S100) of preparing the intermediate product according to the present embodiment in that the step (S90) is not included. Other than this, there is no difference between the two. Hereinafter, this difference will be described. In addition, in FIG. 17, although the flow of each process is shown in order by the arrow, it does not necessarily mean that the next process cannot be started unless the previous process is completed as shown by the arrow. It is not a thing. Of course, there may be a step that can be performed in parallel with the step shown before the arrow even in the step shown after the arrow. Moreover, each process is not necessarily performed in the order according to the direction indicated by the arrow.

In the method of manufacturing a semiconductor device according to the second modification of the present embodiment, as in the present embodiment, as shown in FIGS. 2 to 6, n in the step of preparing an intermediate product (S101) ^The process from the step (S10) of forming the n ^{− type} semiconductor layer on the ^{+ type} semiconductor layer to the step (S70) of forming the gate insulating film is performed.

  Next, in the step of forming a gate electrode in the gate trench (S81), the upper end of the gate electrode 15 is located between the first surface of the substrate 3 and the surface of the sidewall 11 or the surface of the sidewall 11 A gate electrode 15 is formed in the gate trench 12 so as to be located in the same plane. For example, the gate electrode 15 is formed as follows. As shown in FIG. 7, the sidewalls 11 and the insulating film 7 are formed over the first surface of the substrate 3 so that the polysilicon 14 fills the gate trench 12 via the gate insulating film 13 by the CVD method. The film is formed via Thereafter, as shown in FIG. 18, the entire surface of the polysilicon 14 is etched by, for example, a CDE (Chemical Dry Etching) method, and the polysilicon 14 on the first surface of the substrate 3 is removed, and the inside of the gate trench 12 is removed. Etching is performed when the upper end of the polysilicon 14 reaches the lower side than the surface of the sidewall 11 above the first surface of the substrate 3 or reaches the same plane as the surface of the sidewall 11. Stopped. As a result, the gate electrode 15 is formed.

In the second modification, an example in which the upper end portion of the gate electrode 15 is slightly retracted from the surface of the sidewall 11 toward the n ^{+ -type} semiconductor layer 1 will be described. The step (S101) of preparing an intermediate product of the method for manufacturing a semiconductor device according to Modification 2 of the present embodiment is a step of preparing an intermediate product of the method of manufacturing a semiconductor device according to the present embodiment (S100). ) Is different. In the step of forming a gate electrode in the gate trench (S80) included in the step of preparing an intermediate product of the method for manufacturing a semiconductor device according to the present embodiment (S100), the upper end portion of the gate electrode 15 is formed on the substrate 3. It is formed closer to the n ^{+ -type} semiconductor layer 1 than the first surface. The removal of the polysilicon 14 is not limited to the etching by the CDE method but can be performed by the etching by the RIE method, the polishing by the CMP (Chemical Mechanical Polishing) method, or a combination thereof.

  Further, in the step of preparing the intermediate product according to the second modification (S101), the step of removing the sidewall 11 (S90) is unnecessary, and also in this respect, the intermediate product according to the present embodiment is prepared. This is different from the step (S100). In the step of preparing the intermediate product according to the second modified example, the sidewall 11 is used for the flange portion of the interlayer insulating film 16 as described later.

As described above, the step (S101) of preparing the intermediate product according to the second modification is performed, and the n ^{+ -type} semiconductor layer 1, the n ⁻ -type semiconductor layer 2, and the p-type base shown in FIG. A gate insulation in a plurality of gate trenches extending from the first surface of the substrate 3 through the p-type base layer 4 into the n ⁻ -type semiconductor layer 2, with the substrate 4 having a layer 4 and an n ^{+ -type} source layer 5 A plurality of gate electrodes 15 provided via the film 13 and a first surface of the substrate 3 sandwiched between the adjacent gate trenches 12, and side walls retreated from the side walls of the adjacent gate trenches. An intermediate product 101A having an insulating film 7 is prepared. As will be described below, the subsequent steps (S200 to S700) are performed in the same manner as in the semiconductor device manufacturing method according to the present embodiment.

Next, as shown in FIG. 19, the side wall of the gate trench 12 in the n ^{+ -type} source layer 5 (or the first surface of the substrate 3) of the intermediate product 101A is formed by the step of forming an interlayer insulating film (S200). An interlayer insulating film 16 is formed so as to cover the portion from the first to the insulating film 7 and the gate electrode. That is, the interlayer insulating film 16 is a silicon oxide film, and covers a portion (庇) of the n ^{+ -type} source layer 5 (or the first surface of the substrate 3) that extends from the side wall of the gate trench 12 to the side wall of the insulating film 7. Part) and a part (gate electrode part) covering the gate electrode. For example, the interlayer insulating film 16 is formed by thermally oxidizing the upper end portion of the gate electrode 15 exposed from the sidewall 11 using the insulating film 7 and the sidewall 11 as a mask. The thermal oxide film on the upper end portion of the gate electrode 15 becomes a gate electrode portion of the interlayer insulating film 16 and is integrally formed by being joined to the sidewall 11 which becomes a flange portion.

  Next, as shown in FIG. 20, the second oxide film 8 on the insulating film 7 is removed by etching from the first surface side of the substrate 3 by, for example, the RIE method. As a result, the surface of the insulating film 7 is exposed from the interlayer insulating film 16. By etching the surface of the interlayer insulating film 16, the surface of the interlayer insulating film 16 recedes from the insulating film 7 toward the substrate 3.

Next, as shown in FIG. 21, in the step of removing the insulating film (S300), the insulating film 7 is removed by etching, for example, by the CDE method, and the first main surface (n ^{+ type)} of the substrate 3 is removed. The surface of the source layer 5) is exposed immediately below the insulating film 7. Since the method for removing the insulating film 7 is the same as the method for manufacturing the semiconductor device according to the above-described embodiment, detailed description thereof is omitted.

  In the present embodiment, as described above, the step (S30) of forming the n + -type source layer on the surface of the p-type base layer shown in FIG. 2 uses the insulating film having the pattern shown in FIG. The n + -type source layer 5 is formed on the surface of the p-type base layer 4 by being performed before the step (S40) of forming on the top. However, the step (S30) of forming the n + -type source layer on the surface of the p-type base layer may be performed immediately after the step (S300) of removing the insulating film. That is, as shown in FIG. 22, after the insulating film 7 is removed and the first surface (p-type base layer 4) of the substrate 3 immediately below the insulating film 7 is exposed, the interlayer insulating film 16 is formed. By using ion implantation of n-type impurities and heat treatment using the mask, the n + -type source layer 5 can be formed as shown in FIG.

  Alternatively, by removing the insulating film 7 and leaving the first oxide film 6 thereunder, using the interlayer insulating film 16 as a mask, ion implantation of n-type impurities and heat treatment are performed, whereby an n + type source is obtained. Layer 5 can be formed. Since the first oxide film 6 is thinner than the interlayer insulating film 16, impurity ions are selectively implanted immediately below the first oxide film 6 (immediately below where the insulating film 7 exists), and then diffused by heat treatment. N + type source layer 5 is formed. After the n + type source layer 5 is formed, the first oxide film 6 is removed as shown in FIG.

  As described above, the step (S30) of forming the n + -type source layer on the surface of the p-type base layer can be performed immediately after or in the step of removing the insulating film (S300). . Needless to say, the heat treatment after the ion implantation can be performed somewhere in a later process.

Next, as shown in FIG. 23, in the step of forming a contact trench (S400), the contact trench 17 is directly below the first surface (n ^{+ -type} source) of the substrate 3 where the insulating film 7 was present. It is formed so as to extend into the p-type base layer 4 from the surface of the layer 5. Since the method for forming the contact trench 17 is the same as the method for manufacturing the semiconductor device according to the above-described embodiment, detailed description thereof is omitted.

Next, as shown in FIG. 24, the p ^{+ -type} contact layer 18 is formed adjacent to the bottom of the contact trench 17 by the step of forming a p ^{+ -type} contact layer (S500). Since this step is also the same as the semiconductor device manufacturing method according to the above-described embodiment, detailed description thereof is omitted.

Next, as shown in FIG. 25, the drain electrode 19 is electrically connected to the surface of the n ^{+ -type} semiconductor layer 1 opposite to the p-type base layer 4 by the step of forming the drain electrode (S600). Formed. Further, in the step of forming the source electrode (S700), the source electrode 20 is formed so as to fill the contact trench 17 and cover the interlayer insulating film 16. Since both of these steps are the same as the method for manufacturing the semiconductor device according to the above-described embodiment, detailed description thereof is omitted.

  Through the above manufacturing steps, the semiconductor device is provided by the method for manufacturing a semiconductor device according to the second modification of the present embodiment. According to the method for manufacturing a semiconductor device according to this modification, the same effects as those of the method for manufacturing a semiconductor device according to the present embodiment can be obtained. Furthermore, in the method for manufacturing a semiconductor device according to this modification, since the sidewall 11 is used for the flange portion of the interlayer insulating film 11, the step of removing the sidewall 11 (S90) becomes unnecessary, and the manufacturing process is reduced. It has further.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. FIG. 26 is a diagram illustrating a flow of each process of the manufacturing method of the semiconductor device according to the second embodiment. 27 to 32 are partial cross-sectional views of part of the manufacturing process of the semiconductor device manufacturing method according to the second embodiment. Note that the same reference numerals or symbols are used for portions having the same configurations as those described in the first embodiment, and description thereof is omitted. Differences from the semiconductor device manufacturing method according to the first embodiment will be mainly described.

  The method for manufacturing a semiconductor device according to the present embodiment includes a manufacturing process as shown in FIG. 26 and includes a process of preparing an intermediate product (S102). The step of preparing the intermediate product according to the present embodiment (S102) is performed in place of the step of forming the gate trench (S60) in the step of preparing the intermediate product according to the first embodiment (S100). It includes a step of forming a trench (S61) and a step of retracting the insulating film from the trench sidewall (S62), and does not include a step of forming a sidewall (S50) and a step of removing the sidewall (S90). In this respect, the method for manufacturing the semiconductor device according to the present embodiment is different from the method for manufacturing the semiconductor device according to the first embodiment. In other respects, both have the same manufacturing process. Hereinafter, the steps different from each other will be mainly described. In FIG. 26, the flow of each process is shown in order by arrows, but as indicated by the arrows, it means that the next process cannot be started unless the previous process is completed. It is not a thing. Of course, there may be a step that can be performed in parallel with the step shown before the arrow even in the step shown after the arrow. Moreover, each process is not necessarily performed in the order according to the direction indicated by the arrow.

In the step of preparing an intermediate product according to the present embodiment (S102), an n ^{− type} semiconductor layer is formed on the n ^{+ type} semiconductor layer in the step of preparing the intermediate product according to the first embodiment (S100). A step (S40) of forming an insulating film having a pattern on the substrate surface from the forming step (S10) is performed. Thereafter, as shown in FIG. 27, in the step of forming a gate trench (S61), the p-type base layer 4 is penetrated from the first surface of the substrate 3 to reach the n ⁻ -type semiconductor layer 2, and the substrate 3 the first and the adjacent n ⁺ -type source layer 5 at the surface (or penetrate the n ⁺ -type layer source layer 5) a plurality of gate trenches 12 are formed. The formation of the gate trench 12 is performed as follows, for example. Etching is performed by the RIE method using the patterned insulating film 7 formed in the process shown in FIGS. 2 and 3 of the first embodiment as a mask, along the side wall of the insulating film 7. A sidewall of the gate trench 12 is formed. The etching is stopped when the bottom of the gate trench 12 reaches the n ⁻ -type semiconductor layer 2.

  Next, as shown in FIG. 28, as in the first embodiment, the gate insulating film 13 is formed so as to cover the entire inner wall of the gate trench 12 by the step of forming the gate insulating film (S70). The The gate insulating film 13 is a silicon oxide film formed by thermal oxidation, and can also be formed by a CVD method. The gate insulating film 13 is connected to the first oxide film 6 at the upper end of the side wall of the gate trench 12 and is formed so as to cover the side wall and the bottom of the gate trench 12.

  Next, as shown in FIGS. 29 and 30, the gate electrode 15 is formed in the gate trench 12 through the gate insulating film 13 by the step of forming the gate electrode (S80), as in the first embodiment. Formed. As described in the first embodiment, the gate electrode 15 is formed as follows. Polysilicon 14 is formed on the entire first surface of the substrate 3 through the insulating film 7 so as to fill the gate trench 12 through the gate insulating film 13 by CVD. Thereafter, the entire surface of the polysilicon 14 is etched by, for example, the CDE method, the polysilicon 14 on the first surface of the substrate 3 is removed, and the upper end of the polysilicon 14 in the gate trench 12 is the first of the substrate 3. Etching is stopped when reaching the n + type semiconductor layer 1 side from the surface. As a result, the upper end of the gate electrode 15 recedes from the first surface of the substrate 3 toward the n + -type semiconductor layer 1, and the gate electrode 15 is formed in the gate trench 12. Here, when the polysilicon 14 is etched by the CDE method and the upper end portion of the gate electrode 15 recedes from the second oxide film 8 toward the n + -type semiconductor layer 1, the sidewall of the insulating film 7 begins to be exposed. Since the insulating film 7 is etched by the CDE method, the insulating film 7 is side-etched. By this side etching, the side wall of the insulating film 7 recedes from the side wall of the gate trench 12 toward the inside of the insulating film 7. That is, in the step of forming the gate electrode (S80), the step of retreating the insulating film from the trench sidewall (S62) is performed.

  The distance that the side wall of the insulating film 7 recedes from the side wall of the gate trench 12 determines the length of the flange portion of an interlayer insulating film 16 to be described later in the direction perpendicular to the side wall of the insulating film 7. The length of the ridge portion of the interlayer insulating film 16 determines the distance that the contact trench 17 is separated from the gate trench 12. Accordingly, when it is desired to further increase the length of the ridge portion of the interlayer insulating film 16, the insulating film is retracted from the sidewall of the trench after the gate electrode forming step is finished (after the polysilicon 14 is etched by the CDE method). In the step (S62), side etching of the insulating film 7 may be further added. As an additional side etching of the insulating film 7, the gate electrode 15 can be masked with a resist or the like, and etching by CDE method or wet etching or the like can be performed. Alternatively, an etching method in which the insulating film 7 is selectively etched without etching polysilicon is possible.

  After the step (S62) of retracting the insulating film from the sidewall of the trench is completed, the second oxide film 8 on the insulating film 7 is removed by, for example, wet etching using an etching solution containing hydrogen fluoride. In the removal of the second oxide film, a portion of the gate insulating film 13 exposed above the upper end of the gate electrode 15, a side wall of the gate trench 12 and a side wall of the insulating film 7 of the first oxide film The portion exposed between the two is removed simultaneously with the second oxide film 8. As a result, as shown in FIG. 31, a portion from the side wall of the gate trench 12 to the side wall of the insulating film 7 in the n + -type source layer 5 (first surface of the substrate 3) is exposed on the surface.

  In the present embodiment, as described above, the step (S30) of forming the n + -type source layer on the surface of the p-type base layer shown in FIG. 2 is performed using the insulating film having the pattern shown in FIG. The n + -type source layer 5 is formed on the surface of the p-type base layer 4 by being performed before the step (S40) of forming on the substrate surface. However, as shown in FIG. 32, a step (S30) of forming an n + type source layer on the surface of the p-type base layer may be performed after the step (S62) of retracting the insulating film from the sidewall of the trench. Is possible. In this case, an n-type impurity is ion-implanted into the portion of the p-type source layer 4 (first surface of the substrate 3) exposed from the side surface of the gate trench 12 to the side wall of the insulating film 7 to expose the n + -type source. Layer 5 is formed. Similar to the first embodiment, under the condition that the diffusion of the n-type impurity is weak, the source layer 5 is not formed on the first surface of the substrate 3 immediately below the insulating film 7, but the p-type base layer 4 is formed. It will be in the state. Even in such a state, it is possible to manufacture a semiconductor device by performing the subsequent steps of the present embodiment.

By performing the step of preparing an intermediate product (S102) having the above steps, the n ^{+ -type} semiconductor layer 1, the n ⁻ -type semiconductor layer 2, the p-type base layer 4 shown in FIG. A substrate 3 having an n ^{+ -type} source layer 5 and a plurality of gate trenches extending from the first surface of the substrate 3 through the p-type base layer 4 and into the n ⁻ -type semiconductor layer 2 via a gate insulating film A plurality of gate electrodes 15 provided, and an insulating film 7 provided on the first surface of the substrate 3 sandwiched between adjacent gate trenches 12 and having sidewalls recessed from the sidewalls of the adjacent gate trenches; , An intermediate product 102A is prepared.

Thereafter, as in the first embodiment, as shown in FIGS. 11 to 15, a step of forming an interlayer insulating film (S200), a step of removing the insulating film (S300), and a step of forming a contact trench (S400), a step of forming a p ^{+ -type} contact layer (S500), a step of forming a drain electrode (S600), and a step of forming a source electrode (S700) are performed to manufacture a semiconductor device. In this embodiment, as described above, the step of forming the n + type source layer on the surface of the p-type base layer (S30) and the step of forming the p-type base layer on the surface of the n− type semiconductor layer (S20). ) And a step (S40) of forming an insulating film having a pattern on the substrate surface. However, as in the first embodiment, the n + type source layer is formed on the surface of the p type base layer immediately after a part of the last step (S300) of removing the insulating film shown in FIG. The step of forming (S30) may be performed. That is, in the state where the insulating film 7 of FIG. 11 is removed and the first oxide film 6 immediately below the insulating film 7 is exposed, or the first oxide film 6 is further removed and the first surface of the substrate 3 is removed. With the (insulating surface of p-type base layer 4) exposed, ion implantation of n-type impurities such as arsenic or phosphorus and subsequent heat treatment are performed using interlayer insulating film 16 as a mask (heat treatment is performed thereafter). The n ^{+ -type} source layer 5 may be formed as shown in FIG. 11 by performing other high temperature processes instead).

In the method for manufacturing the semiconductor device according to the present embodiment, as shown in FIG. 31, the step of preparing an intermediate product (S102) is performed as in the method for manufacturing the semiconductor device according to the first embodiment. As described above, the substrate 3 having the n ^{+ -type} semiconductor layer 1, the n ⁻ -type semiconductor layer 2, the p-type base layer 4, and the n ^{+ -type} source layer 5, and the p-type base layer 4 from the first surface of the substrate 3. Of the substrate 3 sandwiched between the plurality of gate electrodes 15 provided through the gate insulating film 13 and the adjacent gate trenches 12 in the plurality of gate trenches extending through the n ^{− type} semiconductor layer 2. An intermediate product 102 </ b> A having an insulating film 7 provided on the first surface and having a side wall recessed from the side wall of the adjacent gate trench 12 is prepared. By using the intermediate product 102A to form an interlayer insulating film (S200), on the portion from the side wall of the gate trench 12 to the side wall of the insulating film 7 in the n ^{+ -type} source layer 5 of the intermediate product 102A, An interlayer insulating film 16 is formed so as to cover the gate electrode. That is, the interlayer insulating film 16 includes a portion (a ridge portion) covering a portion from the sidewall of the gate trench 12 to a sidewall of the insulating film 7 in the n ^{+ -type} source layer 5 and a portion covering the gate electrode (gate electrode portion). And having. Then, in the step of forming a contact trench (S400), the contact trench 17 is etched from the first surface of the substrate 3 (the surface of the n ^{+ -type} source layer 4) by etching using the interlayer insulating film 16 as a mask. It is formed so as to extend into the p-type base layer 4.

  As described above, since the contact trench 17 is formed between the adjacent gate trenches 12, mask alignment for forming the contact trench 17 is not necessary, so that the characteristic failure of the semiconductor device due to the mask alignment failure is suppressed. can do. In addition, since the interlayer insulating film 16 used for the mask has the above-described ridge portion, the distance between the contact trench 17 and the gate trench 12 can be secured with good controllability, so that the on-resistance of the semiconductor device can be reduced with good controllability. That is, according to the method for manufacturing a semiconductor device of the present embodiment, a mask alignment defect in contact trench formation is reduced, and a semiconductor device with low on-resistance is provided with good controllability.

  Furthermore, in the manufacturing method of the semiconductor device of this embodiment, the interlayer insulating film 16 has a flange portion, and the width of this flange portion determines the interval between the gate trench 12 and the contact trench 17. As described above with reference to FIG. 25, the width of the flange portion is determined by the distance by which the side wall of the insulating film 7 recedes from the side wall of the gate trench 12. This distance can be controlled by the etching time for side etching the insulating film 7. Therefore, it is not necessary to align the mask for determining the distance between the gate trench 12 and the contact trench 17, and the distance between the gate trench 12 and the contact trench 17 can be controlled by the side etching time of the insulating film 7. Become.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 n ^{+ type} semiconductor layer 2 n ^{− type} epitaxial layer 3 substrate 4 p type base layer 5 n ^{+ type} source layers 6, 8, 10 silicon oxide film 7 insulating film 9 resist mask 11 sidewall 12 gate trench 13 gate insulating film 14 Polysilicon 15 Gate electrode 16 Interlayer insulating film 17 Contact trench 18 p ^{+ type} contact layer 19 Drain electrode 20 Source electrodes 100A, 101A, 102A Intermediate product

Claims (10)

A second semiconductor layer of the first conductivity type having a lower impurity concentration of the first conductivity type than the first semiconductor layer is provided on the first type semiconductor layer of the first conductivity type, and the second semiconductor A substrate provided with a third semiconductor layer of the second conductivity type on the surface of the layer opposite to the first semiconductor layer;
A gate insulating film is formed in a plurality of gate trenches extending from the first surface of the substrate opposite to the first semiconductor layer to the third semiconductor layer and into the second semiconductor layer. A plurality of gate electrodes provided via,
An insulating film provided on a first surface of the substrate sandwiched between adjacent gate trenches among the plurality of gate trenches, and having a side wall recessed from a side wall of the adjacent gate trench;
Providing an intermediate product having:
Using the insulating film as a mask, the portion exposed from the insulating film is thermally oxidized, so that at least the upper end portion of the gate electrode is thermally oxidized, and from the side wall of the gate trench on the first surface of the substrate Forming an interlayer insulating film made of a silicon oxide film so as to cover the portion of the insulating film reaching the side wall and the gate electrode;
Removing the insulating film under the insulating film so as to expose the first surface of the substrate from the interlayer insulating film;
A contact trench extending from the first surface of the substrate into the third semiconductor layer by anisotropically etching the exposed portion of the first surface of the substrate using the interlayer insulating film as a mask Forming a step;
Forming a first electrode electrically connected to a surface of the first semiconductor layer opposite to the second semiconductor layer;
Forming a second electrode electrically connected to the third semiconductor layer in the contact trench;
A method for manufacturing a semiconductor device, comprising: The step of preparing the intermediate product comprises:
Forming the second semiconductor layer on the first semiconductor layer;
Forming the third semiconductor layer on the surface of the second semiconductor layer;
Forming the insulating film on the first surface of the substrate;
Forming a sidewall on the sidewall of the insulating film;
Forming the gate trench by RIE using the insulating film and the sidewall as a mask;
Forming a gate insulating film on the inner wall in the gate trench;
Forming a gate electrode made of polysilicon through the gate insulating film in the gate trench;
The method of manufacturing a semiconductor device according to claim 1, wherein:   The step of forming the gate electrode includes a step of filling the gate trench and forming polysilicon on the entire first surface of the substrate, and a step of etching the polysilicon. 3. The semiconductor according to claim 2, wherein an upper end portion of the gate electrode recedes from the first surface of the substrate toward the first semiconductor layer to form the gate electrode in the gate trench. Device manufacturing method.   The step of preparing the intermediate product further includes the step of removing the sidewall, and the step of removing the sidewall causes the insulation from the sidewall of the gate trench on the first surface of the substrate. The portion of the film reaching the sidewall is exposed, and the step of forming the interlayer insulating film covers the gate electrode and the exposed portion of the first surface of the substrate so as to cover the interlayer insulation. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a film is formed.   The step of forming the gate electrode includes a step of filling the gate trench and forming polysilicon on the entire first surface of the substrate, and a step of etching the polysilicon. The gate electrode is formed in the gate trench so that an upper end portion of the gate electrode is located between the first surface of the substrate and an upper end of the sidewall. The manufacturing method of the semiconductor device of description.   In the step of forming the interlayer insulating film, the upper end portion of the gate electrode and the sidewall are integrated by thermally oxidizing the upper end portion of the gate electrode. The method of manufacturing a semiconductor device according to claim 5, wherein: is formed. The step of preparing the intermediate product comprises:
Forming the second semiconductor layer on the first semiconductor layer;
Forming the third semiconductor layer on the surface of the second semiconductor layer;
Forming the insulating film on the first surface of the substrate;
Forming the gate trench by anisotropic etching using the insulating film as a mask;
Forming a gate insulating film on the inner wall in the gate trench;
Forming a gate electrode made of polysilicon through the gate insulating film in the gate trench;
Retreating the side wall of the insulating film from the side wall of the gate trench by etching;
The method of manufacturing a semiconductor device according to claim 1, wherein:   The step of forming the gate electrode includes a step of filling the gate trench and forming polysilicon on the entire first surface of the substrate, and a step of etching the polysilicon. The semiconductor device according to claim 7, wherein an upper end portion of the gate electrode recedes from the first surface of the substrate toward the first semiconductor layer, and the gate electrode is formed in the gate trench. Device manufacturing method. In the step of preparing the intermediate product,
The substrate is provided on a surface of the third semiconductor layer opposite to the first semiconductor layer, and has an impurity of a first conductivity type higher than an impurity concentration of the first conductivity type of the second semiconductor layer. A fourth semiconductor layer having a concentration;
The plurality of gate trenches adjacent to the fourth semiconductor layer on the first surface of the substrate;
In the step of forming the contact trench,
The contact trench is adjacent to the fourth semiconductor layer on the first surface of the substrate;
In the step of forming the second electrode in the contact trench,
The second electrode is further electrically connected to the fourth semiconductor layer.
The method for manufacturing a semiconductor device according to claim 1, wherein: In the step of preparing the intermediate product,
The substrate is provided on a surface of the third semiconductor layer opposite to the first semiconductor layer, and has an impurity of a first conductivity type higher than an impurity concentration of the first conductivity type of the second semiconductor layer. A fourth semiconductor layer having a concentration;
The plurality of gate trenches adjacent to the fourth semiconductor layer on the first surface of the substrate;
In the step of forming the contact trench,
The contact trench is adjacent to the fourth semiconductor layer on the first surface of the substrate;
In the step of forming the second electrode in the contact trench,
The second electrode is further electrically connected to the fourth semiconductor layer,
The step of preparing the intermediate product further includes a step of forming the fourth semiconductor layer on a surface of the third semiconductor layer.
A method for manufacturing a semiconductor device according to claim 2, wherein:

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