JP2012186329A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

A semiconductor device with improved connection reliability and a method for manufacturing the semiconductor device are provided.
A semiconductor device according to the present invention includes a semiconductor substrate having a first surface, a first electrode formed on the first surface of the semiconductor substrate, and the first electrode of the semiconductor substrate. An opening formed on the surface and positioned on the first electrode; and a surface opposite to the surface on the first surface side, the circular first at a position separated from the opening. An insulating film having a second surface having one region; a first resin portion formed so as to surround the first region of the second surface; and the first region of the second surface. A second resin portion having a third surface formed on the surface opposite to the surface on the second surface side and having a curved surface convex in a direction toward the second surface; A first portion connected to the first electrode, formed on the third surface of the second resin portion, and extending from the first portion to the first electrode; Has a wire having a second portion, and a second electrode formed on said first portion.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  For example, a semiconductor device that employs a package technology called WCSP (wafer level chip size package) that forms wiring and external terminals on a resin layer formed on a semiconductor substrate is known (Patent Document 1).

  Patent Document 1 discloses a semiconductor device that employs WCSP, and in order to improve connection reliability, a resin part having an elastic modulus lower than that of the surrounding resin is supported by supporting an end part avoiding the center part of the land. A semiconductor device including a resin layer is disclosed.

  In such a semiconductor device, it is desired to further improve the connection reliability of the semiconductor device by further relaxing the stress applied to the external terminal due to demands for increasing the chip size and increasing the density of the external terminal. Yes.

JP-A-2005-340453

  The present invention has been made in view of the above problems, and according to some aspects of the present invention, a semiconductor device with high connection reliability and a method for manufacturing the semiconductor device can be provided. .

  (1) A semiconductor device according to this embodiment includes a semiconductor substrate having a first surface, a first electrode formed on the first surface of the semiconductor substrate, and the first surface of the semiconductor substrate. An opening located on the first electrode and a surface opposite to the surface on the first surface side, and is a circular first at a position spaced from the opening. A second surface having a region; an insulating film having a first surface; a first resin portion formed so as to surround the first region of the second surface; and the first surface of the second surface. A second resin portion having a third surface which is a surface opposite to the surface on the second surface side and is a curved surface convex in a direction toward the second surface; A first portion connected to one electrode and formed on the third surface of the second resin portion; and a second portion extending from the first portion to the first electrode. Has a portion, a wire having a first electrode, and a second electrode formed on said first portion.

  According to the present invention, the second electrode is formed above the third surface, which is a curved surface convex in the direction toward the second surface of the second resin portion, via the wiring. According to this, the stress applied to the second electrode can be more relaxed than when the third surface is a flat surface. Therefore, a semiconductor device with high connection reliability can be provided.

  In the description according to the present invention, the word “above” is used to form, for example, “above” a “specific thing” (hereinafter referred to as “A”) and another specific thing (hereinafter referred to as “B”). And so on. In the description according to the present invention, in the case of this example, the case where B is directly formed on A and the case where B is formed on A via another are included. , The word “above” is used. Similarly, the term “under” includes a case where B is directly formed under A and a case where B is formed under A via another.

  (2) In the semiconductor device according to this embodiment, the first resin portion may have a ring shape.

  (3) In the semiconductor device according to the present embodiment, the first resin portion may be formed of a plurality of third resin portions that are spaced apart from each other so as to surround the first region.

  (4) In the semiconductor device according to this embodiment, the first resin portion may have a smaller elastic modulus than the second resin portion.

  (5) A method for manufacturing a semiconductor device according to this embodiment includes a semiconductor substrate having a first surface, a first electrode formed on the first surface of the semiconductor substrate, and the first electrode of the semiconductor substrate. An opening formed on the first surface and positioned on the first electrode, and a surface opposite to the first surface side, and is circular at a position separated from the opening. Preparing a structure having an insulating film having a second surface having the first region, and forming a first resin portion so as to surround the first region of the second surface And on the first region of the second surface, a surface that is opposite to the surface on the second surface side and is a curved surface that is convex in the direction toward the second surface. Forming a second resin portion having a first surface, and a first resin connected to the first electrode and formed on the third surface of the second resin portion. Min, a second portion extending from said first portion to said first electrode, forming a wiring having, and forming a second electrode on the first portion.

  According to the present invention, the second electrode is formed above the third surface, which is a curved surface convex in the direction toward the second surface of the second resin portion, via the wiring. According to this, the stress applied to the second electrode can be more relaxed than when the third surface is a flat surface. Therefore, a method for manufacturing a semiconductor device with high connection reliability can be provided.

  (6) In the method of manufacturing a semiconductor device according to this embodiment, the first resin portion may be formed in a ring shape.

  (7) In the method of manufacturing a semiconductor device according to the present embodiment, the first resin portion is formed by forming a plurality of third resin portions that are spaced apart from each other and are disposed so as to surround the first region. May be.

  (8) In the method of manufacturing a semiconductor device according to this embodiment, the viscosity of the resin material used in the step of forming the second resin portion may be 1 Pa · s or more.

  (9) In the method of manufacturing a semiconductor device according to this embodiment, the elastic modulus of the resin material used in the step of forming the first resin portion is higher than the elastic modulus of the resin material used in the step of forming the second resin portion. It may be small.

FIG. 3 is a plan view schematically showing the semiconductor device according to the embodiment. 2A is a cross-sectional view schematically showing the main part of the semiconductor device taken along the line IIA-IIA in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line IIB-IIB in the semiconductor device shown in FIG. Sectional drawing which shows the principal part typically. Sectional drawing which shows typically the semiconductor device which concerns on the modification 1 of this embodiment. Sectional drawing which shows typically the semiconductor device which concerns on the modification 2 of this embodiment. Sectional drawing which illustrates typically the 1st resin part of the semiconductor device which concerns on the modification 3 of this embodiment. FIG. 6A is a plan view schematically illustrating the first resin portion of the semiconductor device according to the present embodiment, and FIGS. 6B and 6C are related to Modification 4 of the present embodiment. The top view which illustrates typically the 1st resin part of a semiconductor device. Sectional drawing which shows typically the semiconductor device which concerns on the modification 5 of this embodiment. The figure which shows typically the circuit board with which the semiconductor device which concerns on this embodiment was mounted. FIG. 6 is a diagram schematically illustrating an electronic apparatus including the semiconductor device according to the embodiment. FIG. 6 is a diagram schematically illustrating an electronic apparatus including the semiconductor device according to the embodiment. FIG. 11A and FIG. 11B are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to this embodiment. 12A to 12D are cross-sectional views schematically showing a method for manufacturing a semiconductor device according to this embodiment. Sectional drawing which shows typically the manufacturing method of the semiconductor device which concerns on the modification of this embodiment.

  An example of an embodiment to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited only to the following embodiments. The present invention includes any combination of the following embodiments and modifications thereof.

1. Semiconductor Device Hereinafter, the semiconductor device according to the present embodiment will be described with reference to the drawings.

  FIG. 1 is a plan view schematically showing a semiconductor device 100 according to the present embodiment. 2A is a cross-sectional view schematically showing a part of a cross section taken along line IIA-IIA of the semiconductor device 100 shown in FIG. 1, and FIG. 2B is a cross-sectional view of the semiconductor device 100 shown in FIG. It is sectional drawing which shows typically a part of cross section in the IIB-IIB line.

  In the description of this embodiment, the term “plan view” is used to mean a plan view when the semiconductor device 100 is viewed from a normal direction of a first surface 11 described later of the semiconductor device 100. The term “plan view” is also used to mean a plan view when the semiconductor device 100 is viewed from the normal direction of the first surface 11.

  As shown in FIGS. 1 and 2A, the semiconductor device according to the present embodiment includes a semiconductor substrate 10. The semiconductor substrate 10 may have a chip shape as shown in FIG. That is, the semiconductor substrate 10 may be a semiconductor chip. Alternatively, the semiconductor substrate 10 may have a wafer shape including a plurality of semiconductor substrates 10 (not shown). For example, the conductive substrate 10 may be a silicon substrate.

  As shown in FIGS. 2A and 2B, the integrated circuit 1 is formed over the semiconductor substrate 10. The integrated circuit 1 is formed on the surface layer of one surface of the semiconductor substrate 10. The configuration of the integrated circuit 1 is not particularly limited. For example, the integrated circuit 1 may include an active element such as a transistor and a passive element such as a resistor, a coil, and a capacitor.

  As shown in FIGS. 1 and 2A, the semiconductor substrate 10 has a first surface 11. As shown in FIGS. 1 and 2A, the first surface 11 is a surface on which a first electrode 14 and an insulating film 16 described later are formed.

  As shown in FIGS. 1 and 2A, the semiconductor device according to the present embodiment includes a first electrode 14 formed on a first surface 11 of a semiconductor substrate 10. The first electrode 14 may be electrically connected to the integrated circuit 1 formed inside the semiconductor substrate 10 by an internal wiring (not shown). The first electrode 14 may be a part of the internal wiring of the semiconductor substrate 10. The first electrode 14 may be formed outside the region where the integrated circuit 1 is formed, or may be formed above the region where the integrated circuit 1 is formed. As shown in FIG. 1, a plurality of first electrodes 14 may be formed. The first electrode 14 may be disposed along the outer periphery of the semiconductor substrate 10. Further, the first electrode 14 may be formed in the central portion of the semiconductor substrate 10.

  The material of the first electrode 14 is not particularly limited as long as it has conductivity. For example, the first electrode 14 may be formed of a metal such as aluminum (Al) or copper (Cu). The first electrode 14 may be a single conductive layer, or may include a plurality of barrier layers formed of a metal such as titanium (Ti) or titanium tungsten (TiW) that prevents metal diffusion such as aluminum. A laminate of conductive layers may be used.

  As shown in FIGS. 1 to 2B, the semiconductor device according to this embodiment includes an insulating layer 16. The insulating layer 16 may be a passivation film. On the first surface 11, the insulating layer 16 is formed so as to expose at least a part of the first electrode 14. That is, the insulating layer 16 has an opening 16 a located on the first electrode 14.

  As shown in FIGS. 1 to 2B, the insulating layer 16 has a second surface 16b opposite to the surface on the first surface side. As shown in FIGS. 1 and 2A, the second surface 16b has a circular (including substantially circular) first region 16c at a position separated from the opening 16a.

  The first area 16 is an area in which the second electrode 60 serving as an external terminal is disposed above, and is a virtual area provided by design. The center position of the second electrode 60 in plan view coincides with the center of the first region 16c. The magnitude | size of the 1st area | region 16 is not specifically limited, It is a matter determined suitably in consideration of the shape of the 1st resin part 20 and the 2nd resin part 30 mentioned later. Details will be described later. As shown in FIG. 1, a plurality of first regions 16c may be provided corresponding to the number of second electrodes 60 to be formed.

The material of the insulating layer 16 is not particularly limited as long as it has electrical insulation. For example, the insulating layer 16 may be an inorganic insulating layer such as SiO ₂ or SiN. Alternatively, the insulating layer 16 may be an organic insulating layer such as a polyimide resin.

  As shown in FIGS. 1 to 2B, the semiconductor device according to the present embodiment includes a first resin portion 20. The first resin portion 20 is formed so as to surround the first region 16c of the second surface 16b. As shown in FIG. 2B, the first resin portion 20 has an upper surface 21 that is the surface opposite to the surface on the second surface 16b side, and a tapered surface that extends from the upper surface 21 to the second surface 16b. And certain side surfaces 22 and 23. Therefore, the shape of the first resin portion 20 in the cross-sectional view (for example, the cross-sectional view taken along the line IIA-IIA in FIG. 2A) is a trapezoid. As shown in FIG. 2B, the side surface 22 is a surface facing outward, and the side surface 23 is a surface facing inward (center side of the first resin portion 20). The shape of the first resin portion 20 in plan view is not particularly limited as long as it is formed so as to surround the first region 16c. For example, as shown in FIG. A shape continuously surrounding the first region 16c).

  As shown in FIG. 2B, a region inside the side surface 23 (inside the first resin portion 20) (a region sandwiched between the opposing side surfaces 23) is the first region 16c.

  As shown in FIG. 2B, the interval (width) between the corner formed by the upper surface 21 and the side surface 23 and the corner facing the corner at the farthest position is W.

  As shown in FIG. 2 (B), when the maximum diameter of the second electrode 60 (solder ball 60) described later is d, the distance W is the same as the diameter d of the second electrode 60. The first region 16c and the first resin portion 20 may be formed.

  The 1st resin part 20 is formed from resin which has a stress relaxation function. The first resin portion 20 may be formed of, for example, a polyimide resin, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. .

  Moreover, the 1st resin part 20 may be formed so that an elasticity modulus may become lower than the 2nd resin part 30 mentioned later. In other words, the first resin part 20 is formed softer than the second resin part 30. That is, the first resin part 20 can be elastically deformed with a smaller force when compared with the second resin part 30. By forming the first resin part 20 and the second resin part 30 with different materials, a difference may be provided in the elastic modulus of both. When the second resin portion 30 is formed of a polyimide resin, the first resin portion 20 is formed of a silicone-modified polyimide resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. A difference may be provided in the elastic modulus. Moreover, when the 2nd resin part 30 is formed with an epoxy resin, you may provide a difference in both elastic modulus by forming the 1st resin part 20 with a polyimide resin.

  As shown in FIGS. 1 to 2B, the semiconductor device according to the present embodiment has a second resin portion 30. As shown in FIG. 1, the second resin layer 30 may be formed in the central portion avoiding the end portion of the semiconductor substrate 10.

  As shown in FIGS. 2A and 2B, the second resin portion 30 is formed at least on the first region 16c of the second surface 16b. The second resin part 30 may be formed so as to fill the inside of the first resin part 20. The second resin portion 30 is a surface opposite to the surface on the second surface 16b side, and is a third surface 30a (curved surface convex in a direction toward the second surface 16b (semiconductor substrate 10). Top surface). The planar shape of the third surface 30a is not particularly limited as long as it is a curved surface having no flat surface. In other words, the third surface 30a is formed with a curved depression that is convex in the direction toward the second surface 16b.

  As shown in FIG. 2A, the second resin portion 30 is formed so as not to cover the entire first electrode 14. As shown in FIG. 2A, the second resin portion 30 may have an opening 30 b located on the first electrode 14. As shown in FIG. 2A, the second resin portion 30 may be formed so as to cover the first resin portion 20.

  The second resin portion 30 is formed from a resin having a stress relaxation function. The second resin portion 30 may be formed of, for example, a polyimide resin, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. .

  Here, the resin material for forming the second resin portion 30 is selected from materials having a high viscosity. For example, the absolute viscosity of the resin material of the second resin portion 30 may be 1 Pa · s or more and 10 Pa · s or less. According to this, in the manufacturing process of the 2nd resin part 30, the planar shape of the 3rd surface 30a can be made into a desired curved surface comparatively simply. For example, when the second resin portion 30 is formed of a polyimide resin, for example, by selecting a resin material having a molecular weight of 10,000 or more and 700,000 or less, the absolute viscosity is set to 1 Pa · s or more, for example. It can be 10 Pa · s or less. Moreover, the resin material may contain the well-known regulator which adjusts the viscosity of the resin material.

  As shown in FIGS. 1 to 2B, the semiconductor device according to this embodiment includes a wiring 40. The wiring 40 is connected to the first electrode 14 as shown in FIG. 1 and FIG. As shown in FIG. 2A, the wiring 40 includes a first portion 41 (land portion 41) formed on the third surface 30a of the second resin portion 30 and a first portion 41 to a first portion. And a second portion 42 (line portion 42) extending to one electrode 14. The second portion 42 is formed on the second resin portion 30 and on the first electrode 14.

  Since the first portion 41 (land portion 41) is a wiring formed on the third surface 30a, the planar shape thereof corresponds to the shape of the third surface 30a. Therefore, the first portion 41 (land portion 41) is a curved surface that is convex in the direction toward the second surface 16b. The first portion 41 and the second portion 42 may be integrally formed. At this time, the first portion 41 and the second portion 42 may be collectively referred to as a wiring pattern 40.

  The wiring 40 may be a single conductive layer or a stacked body of a plurality of conductive layers. For example, as shown in FIG. 2A, a first wiring 40a and a second wiring 40b may be included. The first wiring 40 a is a layer formed on the second resin layer 30 and may be a lower layer of the wiring 40. The second wiring 40b is a layer formed on the first wiring 40a and may be an upper layer of the wiring 40.

  The material of the wiring 40 is not particularly limited as long as it has conductivity. For example, the first wiring 40a may be a single-layer body including any one of copper (Cu), titanium (Ti), titanium tungsten (TiW), and chromium (Cr). Alternatively, the first wiring 40a may be a stacked body including at least one of copper (Cu), titanium (Ti), titanium tungsten (TiW), and chromium (Cr). The material of the second wiring 40b is not particularly limited as long as it has higher corrosion resistance than the conductive material of the first wiring 40a. For example, the second wiring 40b may be a single layer body including any one of gold (Au) and nickel (Ni). Further, for example, the second wiring 40b may be a stacked body including gold (Au) and nickel (Ni).

  The semiconductor device according to the present embodiment may have a resist layer 50 as shown in FIGS. The resist layer 50 covers at least a part of the wiring 40. By covering all the portions of the wiring 40 except the first portion 41 with the resist layer 50, the wiring 40 can be prevented from being oxidized and corroded, and an electrical failure can be prevented. As shown in FIGS. 2A and 2B, the resist layer 50 has an opening 51 above the first portion 41 of the wiring 40. Although not shown, the resist layer 50 may cover the peripheral edge of the first portion 41.

  The material of the resist layer 50 is not particularly limited as long as it has insulating properties and a part of the wiring 40 can be sealed. For example, the resist layer 50 may be a known resin. For example, the resist layer 50 may be a known solder resist. Specifically, the resist layer 50 is a resin such as a polyimide resin, a silicone-modified polyimide resin, an epoxy resin, a silicone-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or a phenol resin. It may be formed.

  The semiconductor device according to the present embodiment includes the second electrode 60 as shown in FIGS. The second electrode 60 is an external terminal that is electrically connected to an external electronic member. As shown in FIGS. 1 to 2B, the second electrode 60 is a spherical solder ball (solder bump, solder ball) having a maximum diameter d. The second electrode 60 is formed on the first portion 41. The second electrode 60 is electrically connected to the first electrode 14 via the wiring 40. The material of the second electrode 60 may be a metal (for example, an alloy) that is melted to achieve electrical connection (for example, solder). The second electrode 60 may be formed of either soft solder or hard solder.

  The semiconductor device 100 according to the present embodiment may be configured as described above.

  The semiconductor device 100 according to the present embodiment has the following features, for example.

  According to the semiconductor device 100, the second electrode 60 that is an external terminal is formed on the third surface 30 a that is a curved surface convex in the direction toward the second surface 16 b via the wiring 40.

  In general, after mounting a semiconductor device on a mother board or the like, stresses in various directions may be generated on bumps that are external terminals due to a difference in thermal expansion coefficient between the semiconductor chip and the mother board. is there. When the bump is formed on a flat surface, the stress generated at the interface between the bump and the land portion is not easily relaxed by the resin member below the land portion.

  On the other hand, according to the semiconductor device 100, since the second electrode 60 that is an external terminal of the semiconductor device 100 is formed on the land portion 41 (first portion 41) that is a curved surface, the bumps are flat. The stress generated at the interface between the second electrode 60 and the first portion 41 can be relaxed and reduced as compared with the case where it is formed on the surface.

  Further, according to the semiconductor device 100, the stress generated in the direction from the second electrode 60 toward the semiconductor substrate 10 (direction perpendicular to the first surface 11) is applied to the semiconductor substrate 10 (second surface 16b). It can be mitigated by the third surface 30a, which is a curved surface convex in the direction toward. Compared with the case of a flat surface, the stress can be more effectively dispersed by relaxing by the third surface 30a which is a curved surface.

  Further, according to the semiconductor device 100, when the first resin portion 20 is formed to be softer than the second resin portion 30, the curved peripheral portion (first portion 41) of the curved first portion 41 (land portion 41). The portion closer to one resin portion 20) is more easily deformed and absorbs stress, so that the stress generated at the interface between the second electrode 60 and the first portion 41 can be further relaxed.

  Even when the first resin portion 20 is elastically deformed, the second resin portion 30 has a higher elastic modulus than the first resin portion 20, and therefore prevents the first resin portion 20 from being deformed excessively. Can do.

  As described above, the semiconductor device 100 with high reliability against stress can be provided.

  Note that the structure of the semiconductor device 100 according to the present embodiment is not limited to that described above. Hereinafter, a semiconductor device 100 according to a modification of the present embodiment will be described with reference to the drawings.

  3 and 4 are cross-sectional views according to Modifications 1 and 2 of the semiconductor device 100. FIG. FIG. 5 is a cross-sectional view schematically illustrating only the first resin portion 20 and the second electrode 60, for explaining a third modification of the semiconductor device 100. FIGS. 6A to 6C are diagrams for explaining the fourth modification of the semiconductor device 100 and are plan views schematically showing only the first resin portion 20. FIG. 7 is a cross-sectional view according to Modification 5 of the semiconductor device 100.

(Modification 1)
For example, as shown in FIG. 3, the first resin portion 20 may be arranged so that the interval W is larger than the maximum diameter d of the second electrode 60 (solder ball 60). Here, for example, as shown in FIG. 3, the first resin portion 20 may be arranged so that the diameter of the first region 16 c is the same as the diameter d of the second electrode 60. Although not shown, the first resin portion 20 may be arranged so that the diameter of the first region 16 c is larger than the diameter d of the second electrode 60. At this time, the first resin portion 20 may be arranged so that the first region 16c surrounds the second electrode 60 in plan view.

  According to this modification, the curved surface of the third surface 30a can be made smoother. Therefore, the stress in the direction perpendicular to the first surface 11 can be further relaxed.

(Modification 2)
For example, as shown in FIG. 4, the first resin portion 20 may be arranged so that the interval W is smaller than the maximum diameter d of the second electrode 60 (solder ball 60). Here, for example, as shown in FIG. 4, the first resin portion 20 may be arranged such that all the upper surfaces 21 of the first resin portion 20 are located below the second electrode 60. Although not shown, the first resin portion 20 may be disposed so that all of the first resin portion 20 (upper surface 21, side surfaces 22, 23) overlap the second electrode 60 in plan view.

  According to this modification, the plurality of external terminals 60 can be arranged in a smaller space, so that the connection reliability of the external terminals of the semiconductor device 100 can be improved and the density of the external terminals can be increased. it can.

(Modification 3)
Further, for example, as shown in FIG. 5, the distance W is geometrically determined from the radius d of the second electrode 60 so that the third surface 30 a becomes a curved surface more approximate to the spherical surface of the second electrode 60. You may decide. For example, as shown in FIG. 5, when the center of the spherical second electrode 60 is the center point c, the perpendicular from the center point c to the first surface 11 and the upper surface of the first resin portion 20 from the center point c. Let α be the angle formed by the straight line to the corner of 21 and the side surface 23. The interval W is determined by the following formula 1 from a trigonometric function.

W = {d / 2 × (sin α)} × 2 (Expression 1)
The angle α at which the second electrode 60 is stably formed in the first portion 41 that is the land portion is 30 ° or more and 60 ° or less, and more preferably, the angle α is 45 °. . Therefore, the range of the distance W in which the first resin portion 20 and the second electrode 60 have such a positional relationship is d / 2 (when α = 30 °) ≦ W ≦ √3d / 2 (α = 60). °). More preferably, W = d / √2 (when α = 45 °). Therefore, you may arrange | position so that the space | interval W of the 1st resin part 20 may satisfy | fill d / 2 <= W <= 3d / 2.

  According to this modification, the first resin portion 20 is arranged such that the third surface 30a is a curved surface that is more approximate to the spherical surface of the second electrode 60, and the angle α is not less than 30 ° and not more than 60 °. Can do. Therefore, since the second electrode 60 can be supported more stably, connection reliability can be improved.

(Modification 4)
Further, for example, as shown in FIGS. 6B and 6C, the first resin portions 20 are separated from each other, and a plurality of third resin portions 20b are arranged so as to surround the first region 16c. 20c. FIG. 6A schematically illustrates the first resin portion 20 of the semiconductor device according to this embodiment described above. As shown in FIG. 6A, the first resin portion 20 is formed in a ring shape. On the other hand, for example, as shown in FIG. 6B, the first resin portion 20 may have a ring shape cut at two locations. At this time, the first resin portion 20 is formed of two third resin portions 20b. Although not shown here, the first resin portion 20 may have a ring shape that is cut at two or more locations.

  Further, for example, as shown in FIG. 6C, a third resin portion 20c, which is a post-shaped (columnar or conical) resin protrusion, may be arranged so as to surround the first region 16c. In the illustrated example, the four third resin portions 20c are arranged point-symmetrically at the center point of the first region 16c. Here, as shown in FIG. 6C, the plurality of third resin portions 20c are arranged such that the first region 16c is an inscribed circle. Although not shown, the first resin portion 20 may be formed by three third resin portions 20c, or the first resin portion 20 may be formed by four or more third resin portions 20c. Good.

  According to this modification, the entire outer periphery of the first region 16 c is not surrounded by the first resin portion 20. Therefore, in the manufacturing process, voids are not easily formed, and when the second resin portion 30 is formed above the first region 16c, the inside of the first resin portion 20 can be more reliably filled. Reliability can be improved.

(Modification 5)
For example, as illustrated in FIG. 7, the upper surface 21 of the first resin portion 20 may not be covered with the second resin portion 30. In other words, the second resin portion 30 is formed so as to cover only the side surfaces 22 and 23 of the first resin portion 20.

  According to this modification, the stress relaxation effect of the first resin part 20 that is lower in elasticity and easier to deform than the second resin part 30 can be further increased, and the stress can be further relaxed.

  In these modified examples, the same contents as those of the above-described embodiment can be applied to the points other than the contents specifically described, and the same effects can be achieved. Further, the semiconductor device 100 may be configured by combining the contents described so far.

  Note that the semiconductor device 100 according to this embodiment and the semiconductor devices 100 according to the first to fifth modifications described above have a package size substantially equal to that of a semiconductor chip, and can be classified as CSP. Alternatively, it can be said that the semiconductor device 100 is a flip chip having a stress relaxation function. FIG. 8 shows a circuit board 1000 on which the semiconductor device 100 is mounted. FIG. 9 shows a notebook personal computer 2000 and FIG. 10 shows a mobile phone 3000 as electronic devices having a semiconductor device according to an embodiment to which the present invention is applied.

2. Semiconductor Device Manufacturing Method Hereinafter, an example of a semiconductor device manufacturing method according to the present embodiment will be described with reference to the drawings. Therefore, the manufacturing method of the semiconductor device according to the present embodiment is not limited to the following.

  FIG. 11A to FIG. 12D are cross-sectional views of main parts schematically illustrating an example of a method for manufacturing a semiconductor device according to the present embodiment.

  The method for manufacturing a semiconductor device according to the present embodiment includes a semiconductor substrate 10 having a first surface 11, a first electrode 14 formed on the first surface 11 of the semiconductor substrate 10, and the semiconductor substrate 10. The opening 16a formed on the first surface 11 and located on the first electrode 14 is a surface opposite to the surface on the first surface 11 side, and is separated from the opening 16a. A step (S1) of preparing a structure having an insulating film 16 having a second surface 16b having a circular first region 16c at a position, and surrounding the first region 16c of the second surface 16b. Forming the first resin portion 20 on the second region 16c on the first region 16c of the second surface 16b, the surface opposite to the surface on the second surface 16b side; A process for forming the second resin portion 30 having the third surface 30a which is a curved surface convex in the direction toward the surface 16b. (S3), a first portion 41 connected to the first electrode 14 and formed on the third surface 30a of the second resin portion 30, and a first portion 41 extending from the first portion 41 to the first electrode 14. A step (S4) of forming the wiring 40 having the second portion 42, and a step (S5) of forming the second electrode 60 on the first portion 41.

  The step (S1) of preparing the structure includes preparing a semiconductor substrate 200 as shown in FIGS. 11 (A) and 11 (B). Note that FIG. 11A is a diagram illustrating the entire shape of the semiconductor substrate 200, and FIG. 11B is a cross-sectional view of the semiconductor substrate 200. The semiconductor substrate 200 may be a semiconductor wafer as shown in FIG. As shown in FIG. 11A, the semiconductor substrate 200 includes a region 201 to be a plurality of semiconductor devices. As shown in FIG. 11B, a plurality of integrated circuits 1 are formed on the semiconductor substrate 200. The integrated circuit 1 may be formed for each region 201 to be a semiconductor device. The semiconductor substrate 200 includes a plurality of electrodes 14 as illustrated in FIG.

  As shown in FIG. 12A, in each region 201, the semiconductor substrate 10 having the first surface 11, the first electrode 14 provided on the first surface 11 of the semiconductor substrate 10, A structure having an insulating layer 16 having an opening 16a located on one electrode 14 is provided. In addition, the description which concerns on the semiconductor substrate 10, the 1st electrode 14, and the insulating layer 16 applies the description mentioned above, and abbreviate | omits.

  Next, as shown in FIG. 12B, the first resin portion 20 is formed (S2). In addition, the description which concerns on the 1st resin part 20 applies the description mentioned above, and abbreviate | omits. The first resin portion 20 is formed by a known method. The step of forming the first resin portion 20 includes, for example, a step of forming a resin layer 29 by forming a photosensitive resin material by a known film formation technique such as a spin coating method, and a known photolithography technique. You may have the process of exposing, the process of patterning the resin layer 29, and the process of heat-processing and hardening.

  Here, the elastic modulus of the resin material used in the step of forming the first resin portion 20 may be smaller than the elastic modulus of the resin material used in the step of forming the second resin portion 30.

  Next, as shown in FIG. 12C, the second resin portion 30 is formed (S3). The step of forming the second resin portion 30 may be the same as the step of forming the first resin portion 20 described above. The viscosity of the resin material used in the step of forming the second resin portion 30 is 1 Pa · s or more. Thereby, when the resin material is formed by spin coating or the like, the third surface 30c having a curved surface can be easily formed above the first region 16c.

  Next, as shown in FIG. 12D, the wiring 40 is formed (S4). In addition, the description which concerns on the wiring 40 applies the description mentioned above, and abbreviate | omits. The manufacturing method of the wiring 40 is not particularly limited, and is formed using a known film forming technique. The step (S4) of forming the wiring 40 includes, for example, a step of forming a first conductive film made of copper (Cu) by a sputtering method, and a step of forming a resist so that the wiring 40 has a desired wiring pattern. And a step of forming a second conductive layer such as gold (Au) on the first conductive layer exposed from the resist by plating and growing by an electroplating method. Next, the resist is removed, etching is performed using the second conductive layer as a mask, and the first conductive layer is patterned. As described above, the wiring 40 can be patterned into a desired shape.

  Next, a resist layer 50 is formed (see FIG. 2A). The description of the second insulating layer 40 is omitted by applying the above description. The resist layer 50 is formed by any known method. For example, after forming a photosensitive resin layer on the second resin portion 30 and the wiring 40, the resist layer 50 is exposed to light by a known photolithography technique and patterned into a desired shape (not shown). .

  Next, the second electrode 60 is formed on the first portion 41 (S5) (see FIG. 2A). External terminals 50 are formed on the first portions 41 in the openings 51 of the resist layer 50 (see FIG. 2A). The external terminal 50 is not particularly limited as long as it is a conductive material, and may be, for example, a solder bump (solder ball) formed from a solder paste.

  Furthermore, the semiconductor device 100 may be manufactured through a process of cutting the semiconductor substrate 200, an inspection process, and the like (see FIGS. 1, 2A, and 2B).

  The semiconductor device manufacturing method according to the present embodiment can take any of the above-described configurations.

  According to the method for manufacturing a semiconductor device according to this embodiment, a method for manufacturing a semiconductor device with high connection reliability can be provided.

Note that the semiconductor device manufacturing method according to the present embodiment is not limited to the one described above. FIG. 13 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a modification of the present embodiment. For example, as shown in FIG. 13, in the step (S3) of forming the second resin portion 30, the top surface of the first resin portion 20 is formed by, for example, dry etching after the step of forming the resin material or the step of patterning. The process of exposing 21 may be included. For dry etching, a known technique can be used. For example, O ₂ plasma etching can be applied. According to this, the manufacturing method of the semiconductor device 100 which concerns on the modification 5 can be provided.

  As described above, the embodiments of the present invention have been described in detail. However, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. . Accordingly, all such modifications are intended to be included in the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Integrated circuit, 10 Semiconductor substrate, 11 1st surface, 14 1st electrode, 16 Insulating layer,
16a opening, 16b 2nd surface, 16c 1st field, 20 1st resin part,
21 upper surface, 22 side surface, 23 side surface, 30 2nd resin part, 30a 3rd surface,
30b opening, 40 wiring, 40a first wiring, 40b second wiring,
41 first part, 42 second part, 50 resist layer, 51 opening,
60 second electrode, 100 semiconductor device, 200 semiconductor substrate, 201 region.

Claims (9)

A semiconductor substrate having a first surface;
A first electrode formed on the first surface of the semiconductor substrate;
An opening formed on the first surface of the semiconductor substrate and positioned on the first electrode, and a surface opposite to the surface on the first surface side, the opening An insulating film having a second surface having a circular first region at a spaced position;
A first resin portion formed so as to surround the first region of the second surface;
A third surface formed on the first region of the second surface and opposite to the surface on the second surface side is a curved surface convex in the direction toward the second surface. A second resin part having a surface of
A first portion connected to the first electrode and formed on the third surface of the second resin portion; and a second portion extending from the first portion to the first electrode. Having wiring;
A second electrode formed on the first portion;
A semiconductor device. In claim 1,
The first resin portion is a semiconductor device having a ring shape. In claim 1,
The first resin part is formed of a plurality of third resin parts arranged so as to be separated from each other and surround the first region. In any one of Claim 1 to 3,
The semiconductor device, wherein the first resin portion has a smaller elastic modulus than the second resin portion. A semiconductor substrate having a first surface; a first electrode formed on the first surface of the semiconductor substrate; and a first electrode formed on the first surface of the semiconductor substrate; An opening located above, and a second surface having a circular first region in a position opposite to the surface on the first surface side and spaced from the opening. A step of preparing a structure having an insulating film;
Forming a first resin portion so as to surround the first region of the second surface;
A third surface on the first region of the second surface that is a surface opposite to the surface on the second surface side and is convex in a direction toward the second surface. Forming a second resin part having:
A first portion connected to the first electrode and formed on the third surface of the second resin portion; and a second portion extending from the first portion to the first electrode. Forming a wiring having:
Forming a second electrode on the first portion;
A method for manufacturing a semiconductor device comprising: In claim 5,
A method of manufacturing a semiconductor device, wherein the first resin portion is formed in a ring shape. In claim 5,
The method of manufacturing a semiconductor device, wherein the first resin portion is formed by forming a plurality of third resin portions that are spaced apart from each other and are disposed so as to surround the first region. In any one of Claims 5-7,
The method of manufacturing a semiconductor device, wherein the resin material used in the step of forming the second resin portion has a viscosity of 1 Pa · s or more. In any one of Claims 5 to 8,
A method of manufacturing a semiconductor device, wherein an elastic modulus of a resin material used in the step of forming the first resin portion is smaller than an elastic modulus of a resin material used in the step of forming the second resin portion.

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