JP2012185884A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory array structure with resistance between memory cells reduced for a laminate-type semiconductor memory device that stores information by means of variation in resistance value.SOLUTION: The semiconductor memory device according to the present invention has a laminate with a second semiconductor layer being disposed between an upper first semiconductor layer and a lower first semiconductor layer. A potential for putting the second semiconductor layer into a conduction state is applied in both states in which a potential for putting the first semiconductor layer into a conduction state is applied and in which the potential is not applied.

Description

  The present invention relates to a semiconductor memory device.

  In a semiconductor memory device including a phase change memory, a storage element uses a Ge—Sb—Te-based chalcogenide material (or phase change material) containing at least antimony (Sb) and tellurium (Te) as a material for a recording layer. The element for selecting a memory cell is configured using a vertical MOS transistor.

  Patent Document 1 below describes an array configuration in which phase change memory cells using a chalcogenide material and a vertical MOS transistor are stacked. According to FIG. 3 of the document, four memory cells and a vertical transistor TR5 are formed at the intersections of the word line WL, the bit line BL, and the source line SL. Each of the four memory cells has a configuration in which a phase change element and a vertical transistor are connected in parallel. These four memory cells are connected in series to the vertical transistor TR5. A word line WL is connected to the gate electrode of the vertical transistor TR5.

JP 2008-160004 A

  Prior to the present application, the inventors of the present application have examined the high integration of the phase change memory and found the following problems.

  In the memory array described in Patent Document 1, memory cells are connected in series in a direction perpendicular to the semiconductor substrate. Therefore, Joule heat generated when memory information is written in the selected cell passes through the silicon film serving as the channel of the vertical transistor for selecting the memory cell, and the memory cells positioned below and above the selected cell (hereinafter referred to as non-selected cells). , The stored information of the non-selected cell is inverted, and erroneous writing may occur. Therefore, in Patent Document 1, in order to avoid the erroneous writing as described above, it is necessary to increase the interval between the memory cells so that Joule heat does not reach the non-selected cells.

  However, when the non-selected cell is moved away from the selected cell, the region that does not face the side surface of the gate electrode of the vertical transistor increases. This region corresponds to a source / drain region when compared to a conventional MOS transistor formed on a silicon substrate, and its resistance value is higher than that of a region facing the side surface of the gate electrode of the vertical transistor. Therefore, there is a side effect that the resistance in this region increases as a resistance component of the current path including the selected cell. As a result, the resistance between the memory cells increases, and there is a possibility that the operating voltage increases or the read time becomes long.

  As a method for solving such a problem, in a conventional MOS transistor formed on a silicon substrate, a method is known in which the impurity concentration added to silicon in the source / drain region is increased and the resistance value is decreased. However, in the memory array configuration described in Patent Document 1, a patterning process is performed by laminating a semiconductor layer or the like on the sidewall of a hole having a large aspect ratio (hereinafter referred to as “connection hole” in this specification). A plurality of memory cells are formed without any problem. In the course of this manufacturing process, it is extremely difficult to locally add a desired amount of impurities only to a silicon region of a vertical transistor included in a specific memory cell, that is, to a specific portion in a stacked structure. Have difficulty. Therefore, it is desired to reduce the resistance value between the memory cells without adjusting the impurity concentration.

  The present invention has been made to solve the above-described problems, and provides a memory array structure in which resistance between memory cells is suppressed in a stacked semiconductor memory device that stores information by changing a resistance value. The purpose is to do.

  A semiconductor memory device according to the present invention includes a stacked body in which a second semiconductor layer is stacked between an upper first semiconductor layer and a lower first semiconductor layer, and the first semiconductor layer is made conductive. In both the state where the potential is applied to the first semiconductor layer and the state where the potential is not applied, the potential that makes the second semiconductor layer conductive is applied.

  According to the semiconductor memory device of the present invention, a highly integrated, highly reliable, and high performance semiconductor memory device can be realized.

2 is a diagram showing a configuration example of a cell array and its direct peripheral circuit in the semiconductor memory device according to the first embodiment. FIG. It is a diagram showing a configuration example of a memory block MB00 formed at an intersection of a word line WL0 and a bit line BL0. 3 is a cross-sectional view of a memory array MA in an interlayer insulating film 123. FIG. 4 is a cross-sectional view of memory blocks MB00 and MB10 connected to a bit line BL0. FIG. FIG. 4 is a cross-sectional view of memory blocks MB11 and MB10 connected to a word line WL1. It is a figure which shows the relationship of the drive voltage in the word line WL, the bit line BL, and the source line SL. FIG. 10 is a diagram illustrating a drive voltage of each selection gate control line when information is written to the memory cell MC1. It is a figure which shows the drive voltage of each auxiliary gate control line at the time of writing information in memory cell MC1. FIG. 6 is a diagram showing a memory array MA and a memory array driving circuit group in the second embodiment. FIG. 10 is a diagram showing details of a circuit configuration at an intersection of an anode line ANL0 and a bit line BL0 in the memory array shown in FIG. FIG. 10 is a bird's eye view particularly showing a part of the memory array MA extracted from FIG. 9. FIG. 12 is a cross-sectional view showing the overall structure of the memory array MA including the AA ′ cross section shown in FIG. 11. FIG. 5 is a view of the arrangement relationship of m anode lines ANL0 to ANL (m−1) as viewed from the bit line 3 side. It is the figure which looked at the arrangement | positioning relationship of the cell selection gate lines CGL00-CGLm0 from the bit line 3 side similarly. FIG. 5 is a diagram of the arrangement relationship of cell chain selection lines CSL0 to CSLm as viewed from the bit line 3 side. It is a figure which shows the relationship of the drive voltage in the word line WL, the bit line BL, and the source line SL. It is a figure which shows the drive voltage of the cell chain selection line CSL. It is a figure which shows the drive voltage of the cell selection gate line CGL. It is a figure which shows the drive voltage of the cell selection gate line CGL. It is a figure which shows the drive voltage of the cell selection gate line CGL. It is a figure which shows the drive voltage of the cell selection gate line CGL. FIG. 11 is a cross-sectional view of a memory block MB00 corresponding to the circuit configuration shown in FIG. 10.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. The circuit elements constituting each functional block of the embodiment are not particularly limited, but are formed on a semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as a CMOS (complementary MOS transistor).

<Embodiment 1>
In Embodiment 1 of the present invention, a memory array structure using a phase change memory using a chalcogenide material as a storage element will be described. In this memory array, in a memory block in which a plurality of memory cells are connected in series, an auxiliary transistor is provided between the memory cells, and all the auxiliary transistors are always kept in a conductive state, thereby reducing the additional resistance between the memory cells. There is a feature in the point.

<Embodiment 1: Configuration of Memory Array>
FIG. 1 is a diagram showing a configuration example of a cell array and its direct peripheral circuit in the semiconductor memory device according to the first embodiment. In FIG. 1, as an example, (m × n) memories arranged at intersections of m word lines WL0 to WL (m−1) and n bit lines BL0 to BL (n−1). A memory array MA composed of blocks MB00 to MB (m−1) (n−1) is shown. As will be described later, memory blocks MB00 to MB (m−1) (n−1) have a plurality of memory cells. The source lines SL0 to SL (n-1) are arranged to be paired with the bit lines BL0 to BL (n-1).

  The sense amplifier SA, the write circuit WC, the bit line selection circuit BSLC, the word driver group WDBK, the selection transistor drive circuit group TRDBK, and the auxiliary transistor drive circuit group ATRDBK arranged around the memory array MA are necessary for the read / write operation with respect to the memory cell. This is a direct peripheral circuit. These circuits and a driver group to be described later correspond to a “potential application circuit” in the first embodiment.

  The sense amplifier SA and the write circuit WC are connected to an arbitrary bit line in the bit lines BL0 to BL (n−1) via the common data line CDL and the bit line selection circuit BSLC. The bit line selection circuit BSLC further has a function of driving a source line paired with the selected bit line.

  The word driver group WDBK is a circuit block for activating any one of the word lines WL0 to WL (m−1).

  The selection transistor drive circuit group TRDBK and the auxiliary transistor drive circuit group ATRDBK are drivers common to m × n memory blocks MB00 to MB (m−1) (n−1). Select transistor drive circuit group TRDBK is connected to memory array MA via select gate signal line group MGSIG. The auxiliary transistor drive circuit group ATRDBK is connected to the memory array MA through the auxiliary gate signal line group MASIG.

  FIG. 2 is a diagram showing a configuration example of the memory block MB00 formed at the intersection of the word line WL0 and the bit line BL0. The memory block MB00 includes a block selection transistor BTR, four memory cells MC1 to MC4, and three auxiliary transistors ATRa to ATRc.

  The block selection transistor BTR has a source electrode connected to the source line SL0, a drain electrode connected to the memory cell MC1, and a gate electrode connected to the word line WL0. The “first selection line” in the first embodiment corresponds to the word line WL. The “select element” corresponds to the block select transistor BTR. The “second selection line” corresponds to the bit line BL.

  The memory cell MC1 is composed of a variable resistor HRa and a select transistor TRa formed of a chalcogenide material. The memory cell MC2 includes a variable resistor HRb formed of a chalcogenide material and a selection transistor TRb. The memory cell MC3 includes a variable resistor HRc formed of a chalcogenide material and a selection transistor TRc. The memory cell MC4 includes a variable resistor HRd made of a chalcogenide material and a selection transistor TRd. The memory cell MC4 is directly connected to the bit line BL0.

  The gate electrode of the selection transistor TRa is selected by the selection gate control line G1, the gate electrode of the selection transistor TRb is selected by the selection gate control line G2, the gate electrode of the selection transistor TRc is selected by the selection gate control line G3, and the gate electrode of the selection transistor TRd is selected. Each is connected to a gate control line G4. The selection gate control lines G1 to G4 are constituent elements of the selection gate control line group MGSIG shown in FIG. The selection transistor drive circuit group TRDBK drives the selection gate control lines G1 to G4 according to the read / write operation with respect to the memory cell.

  The auxiliary transistor ATRa is inserted between the memory cells MC1 and MC2. The gate electrode of the auxiliary transistor ATRa is connected to the auxiliary gate control line A1. As will be described later, the variable resistors included in each memory cell have a structure that is continuously connected in the memory block. Therefore, the variable resistor AHRa is formed on the side surface of the auxiliary transistor ATRa, and these are connected in parallel. Yes.

  Similarly, the auxiliary transistor ATRb is inserted between the memory cells MC2 and MC3, and the gate electrode is connected to the auxiliary gate control line A2. The variable resistor AHRb is formed on the side surface of the auxiliary transistor ATRb, and these are connected in parallel. The auxiliary transistor ATRc is inserted between the memory cells MC3 and MC4, and the gate electrode is connected to the auxiliary gate control line A3. The variable resistor AHRc is formed on the side surface of the auxiliary transistor ATRc, and these are connected in parallel.

  The auxiliary gate control lines A1 to A3 are components of the auxiliary gate control line group MASIG shown in FIG. The voltage level is a fixed value such that the auxiliary transistors ATRa to ATRc are always in a conductive state, and the resistance value of each auxiliary transistor ATR in that state is lower than the variable resistors AHRa to AHRc. Therefore, most of the current applied to the memory block MB00 flows through each auxiliary transistor.

  A region that does not face the side surface of the gate electrode of each transistor exists between the selection transistor and the auxiliary transistor described above. RSI0 to RSI5 in FIG. 2 are resistors formed of silicon of the same material as the channel of each transistor in this region.

  The silicon resistor RSI0 is an additional resistor formed between the selection transistor TRa and the auxiliary transistor ATRa in the memory cell MC1. As will be described later, the variable resistors included in each memory cell have a structure that is continuously connected in the memory block. Therefore, the variable resistor RF0 is formed on the side surface of the silicon resistor RSI0, and these are connected in parallel. .

  Similarly, the silicon resistor RSI1 is an additional resistor formed between the auxiliary transistor ATRa and the select transistor TRb in the memory cell MC2, and the variable resistor RF1 is formed on the side surface of the silicon resistor RSI1, and these are connected in parallel. ing. The silicon resistor RSI2 is an additional resistor formed between the selection transistor TRb and the auxiliary transistor ATRb in the memory cell MC2. A variable resistor RF2 is formed on the side surface of the silicon resistor RSI2, and these are connected in parallel. The silicon resistor RSI3 is an additional resistor formed between the auxiliary transistor ATRb and the select transistor TRc in the memory cell MC3, and a variable resistor RF3 is formed on the side surface of the silicon resistor RSI3, and these are connected in parallel. The silicon resistor RSI4 is an additional resistor formed between the selection transistor TRc and the auxiliary transistor ATRc in the memory cell MC3, and a variable resistor RF4 is formed on the side surface of the silicon resistor RSI4, and these are connected in parallel. The silicon resistor RSI5 is an additional resistor formed between the auxiliary transistor ATRc and the select transistor TRd in the memory cell MC4, and a variable resistor RF5 is formed on the side surface of the silicon resistor RSI5, and these are connected in parallel.

  The resistance values of the additional resistors RSI0 to RSI5 are designed to be lower than the variable resistors RF0 to RF5. Therefore, most of the current applied to the memory block MB00 flows through the additional resistor.

  When selecting any one of the memory cells MC1 to MC4 in FIG. 2, the block selection transistor BTR is turned on by turning on the word line WL0 in a state where there is a potential difference between the bit line BL0 and the source line SL0. The selection gate control lines G1 to G4 and the auxiliary gate control lines A1 to A3 are driven ON / OFF.

<Embodiment 1: Structure of memory array>
Next, a structure example of the cell array in the semiconductor memory device according to the first embodiment will be described with reference to FIGS.

  FIG. 3 is a cross-sectional view of the memory array MA in the interlayer insulating film 123. The interlayer insulating film 123 (see FIGS. 4 and 5 described later) is a film that separates the selection transistor TRc of the memory cell MC3 from the auxiliary transistor ATRc inserted between the memory cell MC3 and the memory cell MC4. . In FIG. 3, a cross-sectional view of four memory blocks MB00 to MB11 is shown for simplicity of description. The interlayer insulating film 123 corresponds to the “inter-gate insulating layer” in the first embodiment.

  The silicon film 132 becomes a channel of a vertical transistor for memory cell selection. The reaction preventing film 133 suppresses the reaction between silicon and the chalcogenide material. The phase change film 134 becomes a variable resistance using a chalcogenide material. The insulating film 135 is a film provided for insulation. The heat dissipation film 136 is a metallic film provided to radiate heat generated in the phase change film 134 and disperse the heat.

  FIG. 4 is a cross-sectional view of memory blocks MB00 and MB10 connected to bit line BL0. FIG. 5 is a cross-sectional view of memory blocks MB11 and MB10 connected to word line WL1. An interlayer insulating film 102 made of silicon oxide is formed on the semiconductor substrate 101, and a metal wiring layer 103 to be the source line SL0 is further formed thereon.

  A block selection transistor BTR is first formed on the metal wiring layer 103. Reference numeral 105 denotes an interlayer insulating film made of a silicon nitride film. Reference numerals 106 and 108 denote interlayer insulating films made of silicon oxide. Reference numeral 107 denotes a silicon film to which an N-type impurity is added, which becomes the word line WL1. Reference numeral 109 denotes a gate insulating film of the block selection transistor BTR. Reference numeral 110 denotes a silicon film, which becomes a channel of the block selection transistor BTR. Reference numeral 111 denotes an interlayer insulating film made of silicon oxide, which is present to isolate the block selection transistor.

  Memory cells MC1 to MC4 are formed on the block selection transistor BTR. Reference numeral 112 denotes a silicon nitride film. Reference numerals 113, 115, 117, 119, 121, 123, 125, 127, and 137 are interlayer insulating films made of silicon oxide. 114, 118, 122, and 126 are silicon films to which an N-type impurity is added, and serve as select gate control lines G1, G2, G3, and G4. Reference numerals 116, 120, and 124 denote silicon films to which N-type impurities are added, which serve as auxiliary gate control lines A1, A2, and A3. Reference numeral 128 denotes a metal wiring layer that becomes the bit line BL0. 131 is a gate insulating layer of the auxiliary transistor ATRb inserted between the memory cell MC2 and the memory cell MC3. Although omitted in FIGS. 4 and 5 for the sake of simplicity, similar gate insulating layers are also formed in the select transistors TRa to TRd and the auxiliary transistors ATRa and ATRc in the memory cells MC1 to MC4.

  The “first semiconductor layer” in the first embodiment corresponds to the silicon films 114, 118, 122, and 126 that become the selection gate control lines G1, G2, G3, and G4. The “second semiconductor layer” corresponds to the silicon films 116, 120, and 124 to be the auxiliary gate control lines A1, A2, and A3. The “first stacked body” corresponds to a structure formed by stacking these silicon films.

<Embodiment 1: Operation of Memory Array>
Next, an example of cell array operation in the semiconductor memory device according to the first embodiment will be described with reference to FIGS. Hereinafter, as an example, a case where the memory cell MC0 in the memory block MB00 is selected is shown.

  FIG. 6 is a diagram showing the relationship of driving voltages in the word line WL, the bit line BL, and the source line SL. Although not shown in the figure, during standby, each of the word lines WL0 to WL (m−1), the bit lines BL0 to BL (n−1), and the source lines SL0 to SL (n−1) It is driven to 0V. The selection gate control lines G1 to G4 are held at 5V. The auxiliary gate control lines A1 to A3 are fixed at 5V.

  The bit line selection circuit BSLC drives the selected bit line BL0 to a voltage corresponding to the operation to generate a potential difference in the memory block MB00. That is, the voltage of the bit line BL0 in the reset operation is 5V, 4V in the set operation, and 2V in the read operation.

  FIG. 7 is a diagram showing the drive voltage of each select gate control line when writing information to the memory cell MC1. The select transistor drive circuit group TRDBK drives the select gate control line G1 held at 5V to the ground voltage 0V to select the select transistor of the memory cell MC1 in the memory blocks MB00 to MB (m−1) (n−1). Cut off TRa. As a result, no current flows through the selection transistor TRa, and a current flows through the variable resistor HRa so that information can be written.

  Next, the selection transistor drive circuit group TRDBK drives the word line WL0 having the ground voltage of 0V to 5V, and turns on the block selection transistor BTR in the memory block MB00. As a result, a current corresponding to the read / write operation is applied to the variable resistor HRa of the memory cell MC0 in the memory block MB00, and information is written.

  FIG. 8 is a diagram showing the driving voltage of each auxiliary gate control line when writing information to the memory cell MC1. The auxiliary transistor drive circuit group ATRDBK applies a voltage of 5 V to the gate electrode of each auxiliary transistor, regardless of whether the select transistor drive circuit group TRDBK drives the select transistor or not, and always keeps the conductive state.

  When each auxiliary transistor ATR is in a conductive state, the resistance value of each auxiliary transistor ATR is smaller than the resistance value of the opposing variable resistor AHR. Thereby, the resistance value between each selection transistor ATR can be suppressed small.

<Embodiment 1: Summary>
As described above, the semiconductor memory device according to the first embodiment includes the auxiliary transistor ATR between the memory cells MC, and keeps the auxiliary transistor ATR in a conductive state at all times. Thereby, the additional resistance between the memory cells MC can be reduced. More specifically, in the write operation (for example, the reset operation or the set operation), the interval between the memory cells MC is set to such an extent that the stored information of the memory cells MC adjacent above and below is not inverted by Joule heat generated in the selected cell. Even if it is expanded, the resistance between the memory cells can be reduced by the auxiliary transistor ATR arranged between the memory cells MC. Thereby, the operating voltage and the read operation time can be suppressed.

  In the semiconductor memory device according to the first embodiment, the auxiliary transistor ATR is formed by stacking a semiconductor layer on the side surface of the connection hole, like the selection transistor TR. For this reason, it is not necessary to perform local special processing in order to reduce the resistance value between the select transistors, and a high-performance semiconductor memory device can be obtained under the same manufacturing process as the conventional one.

  The portion of the silicon channel in the auxiliary transistor ATR where the resistance value is effectively reduced is a gate oxide film in which charged particles induced by the voltage applied to the gate electrode of the auxiliary transistor ATR are concentrated. It is limited to the vicinity of the interface with the channel. Since this region occupies a small ratio with respect to the channel cross-sectional area, even if the current resistance value of the auxiliary transistor as a whole decreases, the decrease in thermal resistance is kept small, and the amount of heat propagation does not increase so much. Accordingly, the diffusion of Joule heat generated in the selected cell is suppressed, and the additional resistance between the selection transistors is suppressed, so that a low-voltage and high-speed phase change memory can be realized while being highly integrated and highly reliable.

<Embodiment 2>
In the second embodiment of the present invention, another configuration example of the memory array MA will be described. In the second embodiment, two memory cell chains having the same structure as in the first embodiment are configured in pairs, and the number of bits that can be stored in one connection hole is doubled.

<Embodiment 2: Memory Array and Memory Array Drive Circuit Configuration>
FIG. 9 is a diagram showing a memory array MA and a memory array driving circuit group (hereinafter referred to as a memory array driving circuit) in the second embodiment. The configuration of the memory array MA will be described below.

  First, a matrix of m rows and n columns is constituted by m anode lines ANL0 to ANL (m−1) and n bit lines BL0 to BL (n−1) (m and n are natural numbers). Then, memory cell groups MB00 to MB (m−1) (n−1) are arranged at each intersection of the m × n matrix (this memory cell group MB is hereinafter referred to as “memory block”).

  Each memory block MB includes a pair of cell chains. The cell chain will be described later. In FIG. 9, each of the two ellipses provided at each intersection of the anode line ANL and the bit line BL corresponds to one cell chain, and the memory block MB is a set of two ellipses. In FIG. 9, the memory block MB00 provided at the intersection of the anode line ANL0 and the bit line BL0 is clearly shown as a representative example.

  Details of each memory block MB will be described. First, a diode PD is connected to each of the m anode lines (see FIG. 10 described later). A pair of cell chains are connected in series with the diode PD.

  In the second embodiment, the cell chain means that k memory cells MC0 to MC (k-1) and (k-1) auxiliary cells AC0 to AC (k-2) are alternately connected in series in the z-axis direction. Refers to the structure connected to The z-axis direction is a height direction with respect to the substrate and is a direction perpendicular to both the anode line ANL and the bit line BL. Therefore, in each of the m × n memory blocks MB, k × 2 memory cells and (k−1) × 2 auxiliary cells corresponding to a pair of cell chains are connected to the diode PD described above. It will be connected in series. As a result, the memory array MA according to the second embodiment has m × n × k × 2 memory cells.

  A bit line selection circuit BSLC and an unselected bit line voltage power supply circuit USBVS are connected to both ends of the bit lines BL0 to BL (n−1), respectively. The bit line selection circuit BSLC selects any one of the bit lines BL0 to BL (n-1) and electrically connects it to the common data line CBL. The common data line CDL is connected to a rewrite circuit WC and a sense amplifier SA for rewriting information of a memory cell selected from the memory array MA and reading the information. The unselected bit line voltage power supply circuit USBVS supplies unselected voltages to all the bit lines in the standby state and (n−1) bit lines excluding the selected bit line in the read / write operation. Details will be described when the operation of the memory array is described. By this power supply mechanism, erroneous writing to other than the selected cell chain can be avoided. These circuits and a driver group described later correspond to a “potential application circuit” in the second embodiment.

<Embodiment 2: Circuit configuration of cell chain>
FIG. 10 is a diagram showing details of the circuit configuration at the intersection of the anode line ANL0 and the bit line BL0 in the memory array shown in FIG. This circuit configuration is a configuration in which two cell chains CCE and CCO arranged in parallel are connected in series to a polysilicon diode PD connected to the anode line ANL0. In order to simplify the drawing, the silicon resistances RSI0 to RSI5 and the additional resistance components corresponding to the variable resistances RF1 to RF5 shown in FIG. 2 are omitted.

  The cell chains CCE and CCO have a configuration in which k memory cells MC0 to MC (k−1), (k−1) auxiliary cells AC0 to AC (k−2), and a cell chain selection transistor CCG are connected in series. Have Memory cells MC and auxiliary cells AC are alternately connected in series.

  The memory cells MC0 to MC (k-1) are composed of a MOS transistor TG serving as a transmission gate and a variable resistance storage element STD. In each memory cell MC, the source-drain path of the MOS transistor TG and the storage element STD are connected in parallel to each other. One of the cell selection gate line groups MCGL is connected to the gate electrode of the MOS transistor TG serving as the transmission gate of these memory cells MC.

  The auxiliary cells AC0 to AC (k-2) are configured by a MOS transistor ATG serving as a transmission gate and a resistance element FTD formed of the same material as the variable resistance type storage element STD. In each auxiliary cell AC, the source-drain path of the MOS transistor ATG and the resistance element FTD are connected in parallel to each other. One of the auxiliary gate line groups MAGL is connected to the gate electrode of the MOS transistor ATG serving as the transmission gate of the auxiliary cell AC. Further, a cell chain selection line CSL is connected to the cell chain selection transistor CCG.

  In the cell chain CCE, the memory cells MC0 to MC (k−1) are driven and controlled by cell selection gate lines CGL00 to CGL0 (k−1) which are constituent elements of the cell selection gate line group MCGL0. The auxiliary cells AC0 to AC (k−2) are driven and controlled by auxiliary gate lines AGL00 to AGL0 (k−2) which are components of the auxiliary gate line group MAGL0. The cell chain selection MOS transistor CCG is driven and controlled by a cell chain selection line CSL0.

  Similarly, in the cell chain CCO, the memory cells MC0 to MC (k−1) are driven and controlled by cell selection gate lines CGL10 to CGL1 (k−1) which are components of the cell selection gate line group MCGL1. The auxiliary cells AC0 to AC (k−2) are driven and controlled by auxiliary gate lines AGL10 to AGL1 (k−2) that are components of the auxiliary gate line group MAGL1. The cell chain selection MOS transistor CCG is driven and controlled by a cell chain selection line CSL1.

  Next, the cell chain selection line CSL, the cell selection gate line group MCGL, and the auxiliary gate line group MAGL will be described. As described above, since the memory array MA in the second embodiment has a pair of cell chains (that is, 2k memory cells) in each of the m rows and n columns matrix, only m rows and n columns are specified. Then, selection / non-selection of the memory cell MC cannot be specified. A wiring group for specifying this is the cell chain selection line CSL and the selected cell gate line group MCGL.

  First, one of a pair of cell chains is selected by the cell chain selection line CSL. In FIG. 9, an arrow is shown for one of the two ellipses from each of the cell chain selection lines CSL. This arrow indicates that one of the pair of cell chains is selected.

  In FIG. 9, the cell chain selection line CSL is commonly connected to two adjacent cell chains. For example, the x-th cell chain selection line CSLx selects both the cell chain connected to the anode line ANL (x−1) and the cell chain connected to the anode line ANLx. That is, the cell chain selection line CSLx includes the cell chain selection transistor CCG included in the cell chain CCO connected to the anode line ANL (x−1) and the cell chain selection included in the cell chain CCE connected to the anode line ANLx. Both transistors CCG are connected (x is an integer satisfying 1 ≦ x ≦ (m−1)).

  Similarly, the cell selection gate line group MCGLx is included in the gate of the transistor TG of the memory cell MC included in the cell chain CCO connected to the anode line ANL (x−1) and in the cell chain CCE connected to the anode line ANLx. Connected to both gates of the transistor TG of the memory cell MC to be connected (x is an integer satisfying 1 ≦ x ≦ (m−1)).

  Similarly, the auxiliary gate line group MAGLy is included in the gate of the transistor ATG of the auxiliary cell AC included in the cell chain CCO connected to the anode line ANL (x−1) and in the cell chain CCE connected to the anode line ANLx. It is connected to both gates of the transistor ATG of the auxiliary cell AC (x is an integer satisfying 1 ≦ x ≦ (m−1)).

  Even if one of the pair of cell chains is selected, since the cell chain further includes k memory cells MC, it is necessary to characterize which memory cell MC is selected. Therefore, the selected cell gate line group MCGL specifies which memory cell is selected from the k memory cells included in the cell chain. In FIG. 9, each of the selected cell gate line groups MCGL is represented as one wiring CGL. However, this is a notation for simplification, and in actuality, as shown in FIG. 10, there are k wiring groups. A memory cell can be selected / unselected by applying a selection or non-selection voltage to each of the k wirings.

  In FIG. 9, an arrow is shown for each of the two ellipses from each selected cell gate line group MCGL. This arrow indicates which of the k memory cells in the cell chain is selected / unselected. It shows what to do.

  The anode lines ANL0 to ANL (m−1) are driven by the anode driver group ANDBK. Cell selection gate line groups MCGL0 to MCGLm are driven by cell selection MOS transistor driver group MCGDBK. The auxiliary gate line groups MAGL0 to MAGLm are driven by an auxiliary MOS transistor driver MAGD. Cell chain selection lines CSL0 to CSLm are driven by a cell chain selection driver group CSDBK.

  Different anode drivers AND are connected to each anode line ANL. The same applies to the cell chain selection line CSL and the cell selection gate line group MCGL. Similarly, different auxiliary transistor drivers can be connected to each auxiliary gate line MAGL. However, since a fixed voltage is applied to the auxiliary gate line MAGL as described later, a common auxiliary MOS transistor driver MAGD can be connected to the auxiliary gate line groups MAGL0 to MAGLm as shown in FIG. With such a circuit configuration, the circuit area can be suppressed.

  Although details will be described later, the anode lines ANL0 to ANL (m−1), the cell selection gate line groups MCGL0 to MCGLm, the auxiliary gate line groups MAGL0 to MAGLm, and the cell chain selection lines CSL0 to CSLm have a width of the minimum processing dimension F. It has a wiring structure patterned into a shape having an interval. On the silicon substrate, anode lines ANL0 to ANL (m−1), cell selection gate line groups MCGL0 to MCGLm, auxiliary gate line groups MAGL0 to MAGLm, and cell chain selection lines CSL0 to CSLm are formed in this order. The cell selection gate line groups MCGL0 to MCGLm and the auxiliary gate line groups MAGL0 to MAGLm are alternately formed.

<Embodiment 2: Structure of memory array>
FIG. 11 is a bird's-eye view particularly showing a part of the memory array MA extracted from FIG. 9 described above. In FIG. 11, polysilicon diodes PD are periodically formed in the extending direction of the anode line 2 on the plurality of anode lines 2 formed by patterning a metal film at a pitch twice the minimum processing dimension F. Yes. Here, although omitted in the figure, the metal film forming the anode line 2 is formed on the insulating film deposited on the silicon substrate. The polysilicon diode PD has a structure in which a polysilicon layer 4p doped with p-type impurities, a polysilicon layer 5p doped with low-concentration impurities, and a polysilicon layer 6p doped with n-type impurities are stacked.

  The stacked films of the gate polysilicon layers 21p, 22p, 23p, 24p, 41p, 42p, 43p, 61p and the insulating film layers 11, 12, 13, 14, 15, 16, 17, 18, 71 2 is patterned in a stripe shape in a direction parallel to 2. Stripe lines of the stacked films of the gate polysilicon layers 21p, 22p, 23p, 24p, 41p, 42p, 43p, 61p and the stacked films of the insulating film layers 11, 12, 13, 14, 15, 16, 17, 18, 71 A portion is arranged immediately above the space between the anode lines 2. Stripe spaces for the stacked films of the gate polysilicon layers 21p, 22p, 23p, 24p, 41p, 42p, 43p, 61p and the stacked films of the insulating film layers 11, 12, 13, 14, 15, 16, 17, 18, 71 A portion is formed immediately above the anode line 2.

  The bit line 3 has a stripe shape formed by patterning a metal film at a pitch twice the minimum processing dimension F and extending in a direction perpendicular to the anode line 2. Arranged via silicon 38p.

  In the space portion of the laminated film of the gate polysilicon layers 21p, 22p, 23p, 24p, 41p, 42p, 43p, 61p and the laminated film of the insulating film layers 11, 12, 13, 14, 15, 16, 17, 18, 71 Below the bit line 3, sidewalls of gate polysilicon layers 21p, 22p, 23p, 24p, 41p, 42p, and 43p are stacked. On the side walls of the insulating film layers 11, 12, 13, 14, 15, 16, and 17 and on the lower side of the side wall of the insulating film 18, the gate insulating film 9, the channel polysilicon layer 8 p, the diffusion prevention film 10, and the phase change material layer 7 Are stacked in this order.

  Diffusion prevention film 10 is a layer for preventing diffusion between phase change material layer 7 and channel polysilicon layer 8p. An insulating film layer 91 is embedded between the facing phase change material layers 7. A gate insulating film layer 9 and a channel polysilicon layer 8p are laminated on the upper side wall of the insulating film layer 18 and the lower side walls of the gate polysilicon layer 61p and the insulating film layer 71, respectively. An insulating film layer 92 is buried between the opposing channel polysilicon layers 8p. On the insulating film layer 71, a gate insulating film layer 9 and a polysilicon layer 38p are stacked.

  In the space portion of the laminated film of the gate polysilicon layers 21p, 22p, 23p, 24p, 41p, 42p, 43p, 61p and the laminated film of the insulating film layers 11, 12, 13, 14, 15, 16, 17, 18, 71 At the bottom below the bit line 3, the upper surface of the polysilicon layer 6p and the channel polysilicon layer 8p are in contact with each other.

  The metal wiring layer 3 to be the bit line 3 and the polysilicon diode PD have gate polysilicon layers 21p, 22p, 23p, 24p, 41p, 42p, 43p, 61p and insulating film layers 11, 12, 13, 14, 15, 16 17, 17, 18, 71 are connected to each other through a polysilicon layer 38 p and a channel polysilicon layer 8 p formed on opposite side surfaces of the laminated film pair.

  A space portion of a laminated film of gate polysilicon layers 21p, 22p, 23p, 24p, 41p, 42p, 43p, 61p and a laminated film of insulating film layers 11, 12, 13, 14, 15, 16, 17, 18, 71, Further, the channel polysilicon layer 8p, the polysilicon layer 38p, the phase change material layer 7, and the diffusion prevention film 10 are removed under the space portion of the metal wiring 3 that becomes the bit line 3. This space portion is a space portion of the polysilicon diode PD on the metal wiring layer 2 to be the anode line 2. An insulating film 33 is embedded in this space portion. That is, the polysilicon layers 8p and 38p, the phase change material layer 7 and the diffusion prevention film 10 are the laminated films of the gate polysilicon layers 21p, 22p, 23p, 24p, 41p, 42p, 43p and 61p, and the insulating film layers 11 and 12. , 13, 14, 15, 16, 17, 18, 71, and the region surrounded by the insulating layer 33, that is, the side surface of the connection hole.

  Under the structure as described above, a device group formed on one side wall of the connection hole corresponds to the cell chain CCE or CCO shown in FIG. That is, the gate electrodes of the MOS transistors TG serving as the transmission gates of the memory cells MC0 to MC (k−1) (here, k = 4) are the gate polysilicon layers 21p, 22p, 23p, and 24p shown in FIG. Respectively. Therefore, the memory cells MC0 to MC (k−1) are formed on the sidewalls of these gate polysilicon layers 21p, 22p, 23p, and 24p.

  More specifically, it is deposited on the side walls of the gate polysilicon layers 21p, 22p, 23p, 24p, the side walls of the insulating film layers 11, 12, 13, 14, 15, 16, 17 and the lower side of the side walls of the insulating film 18. The gate insulating film 9 and the channel polysilicon layer 8p form a MOS transistor TG serving as a transmission gate. At the same height as the gate polysilicon layers 21p, 22p, 23p, and 24p, the channel polysilicon layer 8p serves as a channel of the MOS transistor TG that serves as a transmission gate in the memory cells MC0 to MC (k-1). . Further, at the same height as the side walls of the insulating film layers 11, 12, 13, 14, 15, 16 and 17 and the lower part of the side walls of the insulating film 18, the channel polysilicon layer 8 p is connected to the drain electrode of each MOS transistor TG. Or it becomes a source electrode.

  If the position corresponding to the position where the MOS transistor TG is formed, the position where the memory element STD is formed can be easily understood. That is, the storage elements STD of the memory cells MC0 to MCk are formed by the diffusion prevention film 10 and the phase change material layer 7 in regions corresponding to the same height as the gate polysilicon layers 21p, 22p, 23p, and 24p. Accordingly, the portion functioning as the storage element STD is a region having the same height as the gate polysilicon layers 21p, 22p, 23p, and 24p. Therefore, the current path flowing through the memory element STD is in the order of the diffusion prevention film 10 → the phase change material layer 7 → the diffusion prevention film 10 between the drain electrode and the source electrode of the MOS transistor TG.

  Similarly, the gate electrodes of the MOS transistors ATG of the auxiliary cells AC0 to AC (k−2) (here, k = 4) are formed by the gate polysilicon layers 41p, 42p, and 43p shown in FIG. Therefore, the auxiliary cells AC0 to AC (k−2) are formed on the side walls of the gate polysilicon layers 41p, 42p, and 43p.

  More specifically, the gate insulating film 9 and the channel polysilicon layer 8p deposited on the side walls of the gate polysilicon layers 41p, 42p, and 43p and the side walls of the insulating film layers 12, 13, 14, 15, and 16 provide the MOS. A transistor ATG is formed. The channel polysilicon layer 8p serves as the channel of the MOS transistor ATG in the auxiliary cells AC0 to AC (k−2) at the same height as the gate polysilicon layers 41p, 42p, and 43p. Further, the channel polysilicon layer 8p serves as a drain electrode or a source electrode of each MOS transistor ATG at the same height as the side walls of the insulating film layers 12, 13, 14, 15, 16, and 17.

  If the position corresponding to the position where the MOS transistor ATG is formed, the position where the resistance element FTD is formed can be easily understood. That is, the resistance element FTD of the auxiliary cells AC0 to AC (k−2) is formed by the diffusion preventing film 10 and the phase change material layer 7 in the region corresponding to the same height as the gate polysilicon layers 41p, 42p, and 43p. Is done. Therefore, the portion functioning as the resistance element FTD is a region having the same height as the gate polysilicon layers 41p, 42p, and 43p. However, since the resistance value of resistance element FTD is formed higher than the resistance value of MOS transistor ATG in the conductive state, most of the current applied to auxiliary cell AC flows through MOS transistor ATG.

  The gate electrode of the cell chain selection MOS transistor CCG is formed by the gate polysilicon layer 61p shown in FIG. Therefore, the cell chain selection MOS transistor CCG is formed on the side wall of the gate polysilicon layer 61p. More specifically, the channel polysilicon layer 8p becomes a channel of the cell chain selection MOS transistor CCG at the same height as the gate polysilicon layer 61p. Further, the channel polysilicon layer 8p serves as a source electrode or a drain electrode of the cell chain selection MOS transistor CCG at the same height as the side wall of the insulating film layer 71 and the upper part of the side wall of the insulating film 18.

  The polysilicon layer 38p serving as the source electrode exhibits n-type conductivity by diffusing impurities such as phosphorus in order to suppress contact resistance with the metal film 3 serving as the bit line 3. Composed.

  FIG. 12 is a cross-sectional view showing the overall structure of the memory array MA including the AA ′ cross section shown in FIG. 11. The feature of this structure is that the memory array MA shown in FIG. 11 is stacked on a MOS transistor formed on the semiconductor substrate 1. This transistor is used to connect the metal wiring layer 3 serving as the bit line 3 and the common data line CDL in the memory array MA.

  FIG. 12 shows an element isolation trench STI, a transistor gate GATE, a gate insulating film GOX, and a diffusion layer DIF regarding the MOS transistor. In addition, as a structure for connecting the transistor and the metal wiring layer 3 to be the bit line 3, interlayer insulating films ILD1, ILD2, ILD3, ILD4, ILD5, wiring layers M1, M2, and devices on the semiconductor substrate and M1 are provided. Contact holes C1, M1 and M2 to be connected, a contact hole BLC to connect the metal wiring layer 3 to be the bit line 3 and a MOS transistor formed on the semiconductor substrate 1, and a polysilicon diode PD An embedded interlayer insulating film 31 is shown.

With the above configuration, assuming that the minimum processing dimension is F, two phase change cell chains arranged opposite to each other are formed on the side wall of the connection hole formed in the cross-sectional area of 4F ² (= 2F × 2F). . Therefore, the cross-sectional area required to form the phase change cell chain can be 2F ² . Accordingly, the bottom area necessary for forming one memory cell is smaller than that of the conventional case, and can be 1 / k of 2F ² . Here, the value of k is the same as the number of stacked memory cells, and in the case of FIG. 11, k = 4.

<Embodiment 2: Wiring structure of memory array>
Next, the wiring structure of the memory array MA will be described. Referring to FIGS. 9 to 12, the anode lines ANL0 to ANL (m−1) and the bit lines BL0 to BL (n−1) are arranged to cross each other. Here, paying attention to one memory block MB00, the gate electrode of each MOS transistor TG in the memory cells MC0 to MC (k−1) (here, k = 4) constituting the cell chains CCE and CCO is an anode line. The gate polysilicon layers 21p, 22p, 23p, and 24p are individually deposited in a stripe shape in the direction in which 2 extends.

  FIG. 13 is a view of the arrangement relationship of the m anode lines ANL0 to ANL (m−1) as viewed from the bit line 3 side. FIG. 14 is a view of the arrangement relationship of the cell selection gate lines CGL00 to CGLm0 as seen from the bit line 3 side.

  When the direction in which the m anode lines ANL0 to ANL (m-1) extend is the Y direction and the direction in which the bit line 3 extends is the X direction, the gate electrode of the MOS transistor TG in the first-layer memory cell MC0 is connected. The (m + 1) cell selection gate lines CGL00 to CGLm0 are extended in the Y direction as shown in FIG. In addition, cell selection gate lines CGL01 to CGLm1, CGL02 to CGLm2 to which the gate electrodes of the MOS transistors TG in the second to fourth layer memory cells MC1 to MC (k−1) (here, k = 4) are connected. , CGL03 to CGLm3 also have the same wiring structure as FIG.

  Similarly, the gate electrodes of the MOS transistors ATG in the auxiliary cells AC0 to AC (k−2) (here, k = 4) are individually formed in a stripe pattern in the direction in which the anode line 2 extends. The silicon layers 41p, 42p and 43p are formed. The auxiliary gate lines AGL00 to AGLm0, AGL01 to AGLm1, and AGL02 to which the gate electrodes of the MOS transistors ATG in the first to third auxiliary cells AC1 to AC (k-2) (here, k = 4) are connected. AGLm2 also has the same wiring structure as FIG.

  FIG. 15 is a view of the arrangement relationship of the cell chain selection lines CSL0 to CSLm as viewed from the bit line 3 side. The gate electrode of the cell chain selection MOS transistor CCG is also formed by the gate polysilicon layer 61p deposited individually in a stripe shape in the direction in which the anode line 2 extends. That is, (m + 1) cell chain selection lines CSL0 to CSLm to which the gate electrode of the cell chain selection MOS transistor CCG is connected are extended in the Y direction as shown in FIG.

  As described above, the cell selection gate lines CGL0 (k-1) to CGLm (k-1) (here, k = 1 to 4), the auxiliary gate lines AGL0 (j-1) to AGLm (j-1). (Here, j = 1 to 3), and the cell chain selection lines CSL0 to CSLm have the same wiring pattern, whereby the connection holes described in FIGS. 11 to 12 can be formed in a single etching process. The polysilicon layer 8p, the phase change material layer 7, the insulating layer 9, and the diffusion prevention film 10 in the connection hole are each formed in a single step. That is, a plurality of memory cells MC and auxiliary cells (here, eight memory cells and six auxiliary cells) AC can be formed in the connection hole at a time. Therefore, a three-dimensional stacked semiconductor memory device can be realized with fewer processes or manufacturing costs than before, and the cost per bit can be reduced.

  The relationship between the number of memory blocks MB and the number of cell chains in the memory array MA and the number of wirings is as follows. When m memory blocks MB are arranged in the direction in which the bit line 3 extends (that is, the X direction) (where m is an integer equal to or greater than 1), as shown in FIG. 13, m anode lines ANL0 A wiring pattern of the metal layer 2 to be -ANL (m-1) is required. Since one memory block MB has two cell chains, cell chains CCE and CCO are formed immediately above each anode line 2.

  However, the cell selection gate lines CGL1 (k-1) to CGL (m-1) (k-1) (where k = 1 to 4) and the cell chain selection lines CSL1 to CSL (m-1) are bits. Since it is connected to two memory blocks MB adjacent in the direction along the line 3, every other cell chain CCE and CCO is arranged. For example, as shown in FIGS. 13 to 15, when attention is paid to bit line 3 in the y-th column, cell chains CCO of memory blocks MB0y and MB1y are arranged adjacent to each other, and cell chains CCE of memory blocks MB1y and MB2y are arranged adjacent to each other Be placed.

  Cell selection gate lines CGL0 (k-1) to CGLm (k-1) (k = 1 to 4), auxiliary gate lines AGL0 (j-1) to AGLm (j-1) (j =) connected to the cell chain 1-3) and (m + 1) cell chain selection lines CSL0-CSLm are required as shown in FIGS. This is because the polysilicons 21p, 22p, 23p, and 24p that become the cell selection gate lines CGL0 (k-1) to CGLm (k-1) (where k = 1 to 4), the auxiliary gate line AGL0 (j-1). ) To AGLm (j-1) (where j = 1 to 3), polysilicon 41p, 42p, 43p, and polysilicon 61p serving as the cell chain selection lines CSL0 to CSLm have been described with reference to FIGS. Thus, it is because it is formed immediately above the space part of the wiring pattern of the metal layer 2 used as the anode lines ANL0 to ANL (m-1).

  Memory cells MC are formed on the side walls of the polysilicons 21p, 22p, 23p, and 24p serving as the cell selection gate lines CGL0 (k-1) to CGLm (k-1) (where k = 1 to 4). Is done. Among these, cell selection gate lines CGL0 (k−1) and CGLm (k−1) (where k = 1 to 4) formed on the outer periphery of the memory array MA are as shown in FIG. The memory cell MC formed on the inner side wall of the memory array MA is used. These memory cells MC are constituent elements of the cell chain CCE in the memory blocks MB0y and MB (m−1) y when attention is paid to the bit line in the y-th column as shown in FIG. 14, for example. For the other cell selection gate lines CGL1 (k-1) to CGL (m-1) (k-1) (where k = 1 to 4), the memory cells MC formed on both side walls are memory cells. It is used as a constituent element of the cell chain CCO in the blocks MB0y and MB (m-1) y or the cell chains CCE and CCO in the memory blocks MB1y and MB (m-2) y.

  An auxiliary cell AC is formed on both side walls of the polysilicons 41p, 42p, and 43p serving as the auxiliary gate lines CGL0 (k-1) to CGLm (k-1) (where k = 1 to 3). Of these, auxiliary gate lines AGL0 (j−1) and AGLm (j−1) (where j = 1 to 3) formed on the outer periphery of the memory array MA are shown in FIG. An auxiliary cell AC formed on the inner side wall of the array MA is used. These auxiliary cells AC are constituent elements of the cell chain CCE in the memory blocks MB0y and MB (m−1) y when attention is paid to the bit line in the y-th column as shown in FIG. 14, for example. For other auxiliary gate lines AGL1 (j-1) to AGL (m-1) (j-1) (where j = 1 to 3), the memory cells MC formed on both side walls are memory blocks. It is used as a component of cell chain CCO in MB0y and MB (m-1) y or cell chain CCE and CCO in memory blocks MB1y and MB (m-2) y. The auxiliary gate lines AGL0 (k-1) to AGLm (k-1) are short-circuited at the outer periphery of the memory array MA as shown in FIG. 9 and connected to the common auxiliary MOS transistor driver MAGD.

  Cell chain selection MOS transistors CCG are formed on both sidewalls of polysilicon 61p serving as cell chain selection lines CSL0 to CSLm. Among these, for the cell chain selection lines CSL0 and CGLm formed on the outer periphery of the memory array MA, MOS transistors formed on the inner sidewalls of the memory array MA are used as shown in FIG. These MOS transistors are, for example, cell chain selection MOS transistors CCG of the cell chain CCE in the memory blocks MB0y and MB (m−1) y when attention is paid to the bit line in the y-th column as shown in FIG. For the other cell chain select lines CSL1 to CSL (m−1), the MOS transistors formed on both side walls are the cell chains CCO in the memory blocks MB0y and MB (m−1) y, or the memory blocks MB1y and MB. (M-2) Cell chain CCE at y, used as cell chain selection MOS transistor CCG of CCO.

  As described above, the memory array MA according to the second embodiment has four systems of control lines extending in the Y direction. In order to distinguish these control lines from the viewpoint of function, anode lines ANL0 to ANL (m−1), cell selection gate line groups MCGL0 to MCGLm, auxiliary gate line groups MAGL0 to MAGLm, cell chain selection lines CSL0 to CSLm Called. These control lines are orthogonal to the bit line 3. Therefore, in particular, any one of the anode lines ANL0 to ANL (m-1), the cell selection gate line groups MCGL0 to MCGLm, and the cell chain selection lines CSL0 to CSLm may be called a word line as in the conventional memory. .

<Embodiment 2: Operation of Memory Array>
As shown in FIG. 9, the memory array MA according to the second embodiment includes memory blocks MB formed at intersections of a plurality of bit lines 3 and a plurality of anode lines 2. Hereinafter, assuming that the lowermost memory cell MC0 in the cell chain CCE of the memory block MB00 is selected, a reset operation, a set operation, and a read operation of the memory array MA will be described with reference to FIGS.

  FIG. 16 is a diagram illustrating a relationship of driving voltages in the word line WL, the bit line BL, and the source line SL. First, auxiliary gate lines AGL00 to AGL (j-1) 0, AGL01 to AGL (j-1) 1, AGL02 to AGL (j-1) 2,..., AGL (m-1) 0 to AGL (m -1) (j-1) (where j = 3) is held at 5V. Then, as shown in FIG. 16, the bit line BL0 to be selected and the anode lines ANL1 to ANL (m−1) held in the non-selected state are set to 0 V in any operation. Further, the anode line ANL0 to be selected and the bit lines BL1 to BL (n−1) held in the non-selected state are driven to 5V during the reset operation, 4V during the set operation, and 2V during the read operation. .

  In such a voltage application state, paying attention to the potential difference between the anode line 2 and the bit line 3 with respect to the diode PD in the memory block MB, the anode line ANL0 is driven to a positive voltage, and the bit line BL0 is held at the ground voltage. As a result, only the memory block MB00 is in the forward bias state. That is, the memory block MB00 is selected.

  The memory blocks MB10 to MB (m−1) 0 in which both the anode lines ANL1 to ANL (m−1) and the bit line BL0 are held at the ground voltage (0V) have a potential difference of zero. Therefore, the non-selected state is maintained.

  The memory blocks MB01 to MB0 (n−1) in which both the anode line ANL0 and the bit lines BL1 to BL (n−1) are driven to the same positive voltage have zero potential difference. Therefore, the non-selected state is maintained.

  Anode lines ANL1 to ANL (m-1) are held at the ground voltage, and bit lines BL1 to BL (n-1) are driven to a positive voltage. Memory blocks MB11 to MB (m-1) (n-1) Is in a reverse bias state. The breakdown voltage of the polysilicon diode PD can be greater than 5V. Therefore, even if any of the cell chains is conducted, the current flowing through the diode PD is suppressed. Therefore, these memory blocks MB11 to MB (m−1) (n−1) are also kept in a non-selected state.

  FIG. 17 is a diagram showing a drive voltage of the cell chain selection line CSL. The cell chain CCE in the memory block MB00 can be selected by driving the cell chain selection line CSL0 to 5V and the other cell chain selection lines CSL1 to CSLm to 0V.

  18 to 21 are diagrams showing drive voltages of the cell selection gate line CGL. The cell selection gate line CGL00 is set to 0V, the other cell selection gate lines CGL10 to CGL (k-1) 0, CGL01 to CGL (k-1) 1, CGL02 to CGL (k-1) 2, ..., GL0m to By driving CGL (k−1) m (here, k = 4) to 5V, only the lowermost memory cell MC0 in the cell chain CCE of the memory block MB00 can be selected.

  FIG. 22 is a cross-sectional view of memory block MB00 corresponding to the circuit configuration shown in FIG. Hereinafter, the state of each element in the selected memory block MB00 will be described in detail with reference to FIG. FIG. 22 shows the operating voltage of each terminal in the order of the reset operation, the set operation, and the read operation based on FIGS. The insulating film layer 32 is an insulating film embedded between adjacent polysilicon diodes PD, although omitted for simplification in FIGS.

  First, 0V is applied to the bit line BL0, and 5V, 4V, and 2V are applied to the anode line ANL0 during a reset operation, a set operation, and a read operation, respectively.

  In the cell chain CCE, 0 V is applied to the cell selection gate line CGL00 to which the memory cell MC0 to be selected is connected, and the transistor having the polysilicon layer 8p as a channel is cut off. 5 V is applied to the cell selection gate lines CGL01 to CGL0 (k-1) (here, k = 4) to which the other memory cells MC1 to MC (k-1) (here, k = 4) are connected. Then, the transistor is turned on. 5 V is applied to the auxiliary gate lines AGL00 to AGL0 (j−1) (here j = 3) to which the auxiliary cells AC0 to AC (j−1) (here j = 3) are connected, Is turned on. 5V is applied to the polysilicon 61p serving as the cell chain selection line CSL0, and the cell chain selection gate CCG is turned on.

  By such control, in the cell chain CCE, the MOS transistors TG serving as transmission gates in the memory cells MC1 to MC (k−1) (here, k = 4) in the non-selected state, and the auxiliary cells AC0 to AC ( j-1) The MOS transistor ATG serving as a transmission gate in j-1 (here, j = 3) becomes conductive, and the resistance of the channel is lowered. Further, since the cell chain selection MOS transistor CCG is also turned on, the resistance of the polysilicon layer 8p in the MOS transistor is also low. Therefore, in the memory cells MC1 to MC (k−1) (here, k = 4), it is possible to cause substantially the same current to flow through the MOS transistor TG regardless of the state of the phase change material layer 7. it can. Similarly, in the auxiliary cells AC0 to AC (j−1) (here, j = 3), substantially the same current can flow through the MOS transistor ATG.

  In the memory cell MC0 in the selected state, the MOS transistor TG is cut off, so that a current flows through the phase change material layer 7. That is, during the reset operation and the set operation, information can be written by changing the resistance value of the phase change material 7 using Joule heat generated by the current flowing through the phase change material layer 7 itself. During the read operation, the current value flowing through the phase change material layer 7 is measured to separate the stored information.

  In the cell chain CCO, cell selection gate lines CGL10 to CGL1 (k−1) (here, k = 4) to which the memory cells MC0 to MC (k−1) (here, k = 4) are connected are included in the cell chain CCO. 5V is applied to make the transistor conductive. 5V is applied to the auxiliary gate lines AGL10 to AGL1 (j-1) (here j = 3) to which the auxiliary cells AC0 to AC (j-1) (here j = 3) are connected. Is turned on. Further, the polysilicon 61p serving as the cell chain selection line CSL1 is held at the ground voltage 0V, and the cell chain selection MOS transistor CCG is kept in the cut-off state.

  By such control, in the cell chain CCO, the MOS transistors TG and the auxiliary cells AC0 to AC (j−1) in the memory cells MC0 to MC (k−1) (here, k = 4) in the non-selected state. Although the MOS transistor ATG at (here j = 3) is in a conducting state, no current flows because the cell chain selection MOS transistor CCG is cut off.

  Through the control as described above, information can be written by selectively applying a current to the phase change material layer 7 of the memory cell MC0 in the cell chain CCE in the memory block MB00.

<Embodiment 2: Summary>
As described above, the semiconductor memory device according to the second embodiment can halve the effective memory cell area as compared with the memory cell described in the first embodiment. That is, one of the characteristics of the structure of the memory block MB in the memory array MA according to the second embodiment is that the insulating layer 91 formed inside the connection hole as shown in FIGS. 11 to 12 and FIG. The polysilicon layer 8p and the phase change material layer 7 are separated into a first region included in the cell chain CCE and a second region included in the other cell chain CCO facing each other. Further, a switch (here, a cell chain selection MOS transistor CCG) for independently controlling the current flowing through these layers is provided on each current path. With such a configuration, when the MOS transistor TG in the memory cell MC formed on one side wall of the connection hole is cut off, a current is passed through the phase change material layer 7 in the region to which the memory cell MC belongs. Thus, it is possible to prevent a current from flowing through the phase change material layer 7 in the other region facing each other. Therefore, twice as much information as in the first embodiment can be stored in one connection hole.

  In the semiconductor memory device according to the second embodiment, as in the first embodiment, the auxiliary transistor AC is provided between the memory cells MC, and the auxiliary transistor AC is always kept in a conductive state. As a result, it is possible to reduce the additional resistance between the memory cells MC formed with an interval that can avoid erroneous writing to the non-selected cells. Therefore, a synergistic effect with the above effect can realize a low-voltage and high-speed phase change memory while being highly integrated and highly reliable.

  Further, in place of the block selection transistor BTR in the first embodiment, the polysilicon diode PD in the second embodiment can be provided. If the polysilicon diode PD is used, the mounting area can be reduced as compared with the block selection transistor BTR.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

MA: Memory arrays MB00 to MB (m-1) (n-1): Memory blocks CCE, CCO: Cell chains BL0 to BL (n-1): Bit lines ANL0 to ANL (m-1): Anode lines CGL0k to CGL (m−1) k, k = 0 to 3: cell selection gate lines MCGL0 to MCGL (m−1): cell selection gate line groups MAGL0 to MAGL (m−1): auxiliary gate line groups CSL0 to CSL (m -1), k = 0 to 3: cell chain selection lines G1, G2, G3, G4: selection gate control lines A1, A2, A3: auxiliary gate control line CDL: common data line MCk (k = 0 to 3): Memory cells ACj (j = 0 to 2): auxiliary cells TRa, TRb, TRc, TRd, ATRa, ATRb, ATRc, TG, ATG: MOS transistors HRa, HRb, HRc, HRd, ST : Memory elements RF0, RF1, RF2, RF3, RF4, RF5: variable resistances AHRa, AHRb, AHRc, FTD: resistance elements BTR: block selection transistors RSI0, RSI2, RSI3, RSI4, RSI5: silicon resistance CCG: cell chain selection MOS Transistor PD: Polysilicon diode SA: Sense amplifier WC: Rewrite circuit ANDBK: Ano driver group MCGDBK: Cell selection MOS transistor driver group MAGD: Auxiliary MOS transistor driver CSDBK: Cell chain selection driver group TRDBK: Selection transistor drive circuit group ATRDBK: Auxiliary Transistor drive circuit group BSLC: bit line selection circuit USBVS: unselected bit line voltage power supply circuit 131: gate insulating layer 132: silicon film 133: reaction prevention film 34: phase change film 135: insulating film 136: heat dissipation film 101: semiconductor substrate 103, 128: metal wiring layers 105, 112: interlayer insulating films 102, 106, 108, 111, 113, 115, 117 made of silicon nitride film, 119, 121, 123, 125, 127, 137: interlayer insulating films 107, 110, 116, 120, 124 made of silicon oxide: silicon film doped with N-type impurities 109: gate insulating film 128: bit line BL0 Metal wiring layers 2, 3: Metal wiring layer 4a: Amorphous silicon layer 5a doped with p-type impurities: Amorphous silicon layer 6a doped with low-concentration impurities: Amorphous silicon layer 4p doped with n-type impurities: Polysilicon layer 5p doped with p-type impurities: Polysilicon doped with low-concentration impurities N layer 6p: polysilicon layer doped with n-type impurities 7: phase change material layer 8a: amorphous silicon layer 8p: channel polysilicon layer 9: gate insulating film 10: diffusion barrier films 11, 12, 13, 14, 15 : Insulating films 21p, 22p, 23p, 24p, 41p, 42p, 43p: polysilicon layers 31, 32, 33: insulating film 38p: polysilicon layer doped with n-type impurities 61p: polysilicon layer 71: insulating film 91 92: Insulating film STI: Element isolation trench GATE: Transistor gate GOX: Gate insulating film DIF: Diffusion layers ILD1, ILD2, ILD3, ILD4, ILD5: Interlayer insulating films M1, M2: wiring layers C1, C2, BLC: contacts Hole

Claims (16)

A substrate on which a semiconductor element is formed;
A first selection line provided above the substrate;
A selection element provided on the first selection line, wherein a drain-source current flows perpendicularly to the substrate;
A first stacked body having a structure in which a second semiconductor layer is stacked between an upper first semiconductor layer and a lower first semiconductor layer, and provided above the selection element;
A second selection line disposed in a direction crossing the first selection line and provided above the first stacked body;
A gate insulating layer provided along a side surface of the first stacked body;
A channel layer provided along a side surface of the gate insulating layer;
A variable resistance material layer including a variable resistance material that is provided along a side surface of the channel layer and has a resistance value that varies depending on a current;
With
The channel layer, the variable resistance material layer, and the selection element are provided in a region where the first selection line and the second selection line intersect,
The second semiconductor layer includes
The potential for making the second semiconductor layer conductive is applied in both the state where the potential for making the first semiconductor layer conductive is applied to the first semiconductor layer and the state where the potential is not applied to the first semiconductor layer. A semiconductor memory device characterized by being configured. In claim 1,
A potential applying circuit for applying a potential for making the first semiconductor layer conductive to the first semiconductor layer and applying a potential for making the second semiconductor layer conductive to the second semiconductor layer;
The potential application circuit includes:
Applying a potential for making the second semiconductor layer conductive to the second semiconductor layer both when the potential for making the first semiconductor layer conductive is applied to the first semiconductor layer and when not applied to the first semiconductor layer. A semiconductor memory device. In claim 1,
An inter-gate insulating layer is formed between the first semiconductor layer and the second semiconductor layer;
The first semiconductor layer includes
A gate electrode of a second transistor configured using the gate insulating layer, the channel layer, and the first semiconductor layer;
The second semiconductor layer includes
A semiconductor memory device comprising: a gate electrode of a third transistor configured using the gate insulating layer, the channel layer, and the second semiconductor layer. In claim 3,
The variable resistance material layer includes:
It is configured as a memory cell that stores information by a change in resistance value,
The second transistor is
When the first potential is applied to the gate electrode and becomes conductive, the resistance value of the second transistor is lower than the resistance value of the variable resistance material layer,
When the second potential is applied to the gate electrode to be in a non-conducting state, the resistance value of the variable resistance material layer is lower than the resistance value of the second transistor,
The potential application circuit includes:
When information is not written to the memory cell, a first potential is applied to the gate electrode of the second transistor to make it conductive.
When writing information in the memory cell, a second potential is applied to the gate electrode of the second transistor to make it non-conductive. The semiconductor memory device according to claim 1, wherein the variable resistance material is a chalcogenide material. In claim 1,
A second stacked body in which a second semiconductor layer is stacked between an upper first semiconductor layer and a lower first semiconductor layer, and is provided above the selection element;
A cell chain selection switch for selecting which of the first stacked body and the second stacked body to write information to,
With
The gate insulating layer, the channel layer, and the variable resistance material layer are:
Each of them is formed along a side surface of the first stacked body and a side surface of the second stacked body, and is separated by an insulating layer into the first stacked body side and the second stacked body side. Semiconductor memory device. In claim 1,
A semiconductor memory device comprising a transistor as the selection element. In claim 1,
A semiconductor memory device comprising a diode in which a P-type impurity semiconductor and an N-type impurity semiconductor are stacked as the selection element. A substrate on which a semiconductor element is formed;
A first selection line provided above the substrate;
A selection element provided on the first selection line, wherein a drain-source current flows perpendicularly to the substrate;
A first stacked body having a structure in which a second semiconductor layer is stacked between an upper first semiconductor layer and a lower first semiconductor layer, and provided above the selection element;
A second selection line disposed in a direction crossing the first selection line and provided above the first stacked body;
A gate insulating layer provided along a side surface of the first stacked body;
A channel layer provided along a side surface of the gate insulating layer;
A variable resistance material layer including a variable resistance material that is provided along a side surface of the channel layer and has a resistance value that varies depending on a current;
With
The channel layer, the variable resistance material layer, and the selection element are provided in a region where the first selection line and the second selection line intersect,
The resistance value of the portion of the channel layer disposed on the side surface of the second semiconductor layer is:
In both the case where the resistance value of the portion arranged on the side surface of the first semiconductor layer in the variable resistance material layer changes and the case where the resistance value does not change, the side surface of the second semiconductor layer in the variable resistance material layer A semiconductor memory device, wherein the semiconductor memory device is configured to be lower than a resistance value of a portion where it is disposed. In claim 9,
A potential applying circuit for applying a potential for making the first semiconductor layer conductive to the first semiconductor layer and applying a potential for making the second semiconductor layer conductive to the second semiconductor layer;
The potential application circuit includes:
In both the case where the potential for making the first semiconductor layer conductive is applied to the first semiconductor layer and the case where it is not applied,
The resistance change material layer disposed on a side surface of the second semiconductor layer by applying a potential to bring the second semiconductor layer into a conductive state to the second semiconductor layer, thereby causing the resistance value of the second semiconductor layer to be disposed on a side surface of the second semiconductor layer. A semiconductor memory device characterized by having a resistance value lower than that of the semiconductor memory device. In claim 9,
An inter-gate insulating layer is formed between the first semiconductor layer and the second semiconductor layer;
The first semiconductor layer includes
A gate electrode of a second transistor configured using the gate insulating layer, the channel layer, and the first semiconductor layer;
The second semiconductor layer includes
A semiconductor memory device comprising: a gate electrode of a third transistor configured using the gate insulating layer, the channel layer, and the second semiconductor layer. In claim 11,
The variable resistance material layer includes:
It is configured as a memory cell that stores information by a change in resistance value,
The second transistor is
When the first potential is applied to the gate electrode and becomes conductive, the resistance value of the second transistor is lower than the resistance value of the variable resistance material layer,
When the second potential is applied to the gate electrode to be in a non-conducting state, the resistance value of the variable resistance material layer is lower than the resistance value of the second transistor,
The potential application circuit includes:
When information is not written to the memory cell, a first potential is applied to the gate electrode of the second transistor to make it conductive.
When writing information in the memory cell, a second potential is applied to the gate electrode of the second transistor to make it non-conductive. The semiconductor memory device according to claim 9, wherein the variable resistance material is a chalcogenide material. In claim 9,
A second stacked body in which a second semiconductor layer is stacked between an upper first semiconductor layer and a lower first semiconductor layer, and is provided above the selection element;
A cell chain selection switch for selecting which of the first stacked body and the second stacked body to write information to,
With
The gate insulating layer, the channel layer, and the variable resistance material layer are:
Each of them is formed along a side surface of the first stacked body and a side surface of the second stacked body, and is separated by an insulating layer into the first stacked body side and the second stacked body side. Semiconductor memory device. In claim 9,
A semiconductor memory device comprising a transistor as the selection element. In claim 9,
A semiconductor memory device comprising a diode in which a P-type impurity semiconductor and an N-type impurity semiconductor are stacked as the selection element.

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