JP2012182240A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a trench gate, which achieves reduction in wiring resistance of the gate and a higher working speed.SOLUTION: In a trench MOSFET provided with a bridge electrode 33B orthogonal to striped trenches T, source pads 35s included in a first external lead out electrode are integrally formed. The source pads 35s have a narrowed part k, and a gate pad 35g as a second external lead out electrode is extended and formed in the narrowed part k. At least a part of a surface of the bridge electrode includes an aluminum layer which is the same metal layer as the source pad 35s.

Description

  The present invention relates to a semiconductor device, and more particularly to a trench gate extraction structure such as a layout of a gate extraction electrode and a source extraction electrode of a MOSFET having a trench structure.

  In recent years, with the reduction in power consumption, higher functionality, and higher speed in electronic devices such as mobile phones, semiconductor devices mounted on the electronic devices have been required to have lower power consumption and higher speed. Transistors generally used in load switches and DC-DC converters for electronic devices are also required to have low on-resistance in order to cope with them. In order to reduce the on-resistance of a transistor, one method is to miniaturize each device and increase the density of the transistors arranged per unit area. Specifically, for example, in a vertical MOSFET in which a gate electrode is formed in a trench, the trenches in which the transistors are formed are arranged in a stripe shape to reduce the width of the trench and to increase the pitch between adjacent trenches. The transistor density can be increased by reducing the transistor density. In this structure, the area of the gate oxide film per cell area is simply reduced as compared with the structure in which the trenches are provided in a lattice shape, so that the parasitic capacitance between the gate and drain can be reduced.

As an example, as shown in FIGS. 13 and 14, a plurality of trenches T having a depth T _h and a width T _W are provided in a semiconductor substrate 1, and MOSFETs are provided in the trenches T ( For example, Patent Document 1). In this structure, a gate pad 35g is formed on a part of the surface of the semiconductor substrate, and a gate electrode (polycrystalline silicon gate) 33 formed by filling the trench T with polycrystalline silicon extends along the periphery of the semiconductor substrate. The gate pad 35g is connected by a current collecting layer 35gl including a gate peripheral wiring to be formed. Here, a base wiring 33gl made of polycrystalline silicon is formed under the current collecting layer 35gl which is a gate peripheral wiring.

In this semiconductor device, as shown in FIGS. 14A and 14B, a plurality of trench lines are formed on the semiconductor layer, and the terminal portion of the gate electrode 33 made of polycrystalline silicon filled therein is formed on the semiconductor substrate. It is directly connected to the current collecting ring electrode gl formed on the peripheral edge. The current collecting ring electrode gl is composed of a base layer 33gl made of a polycrystalline silicon layer and a current collecting layer 35gl made of an aluminum layer. N-type diffusion regions constituting the source region 32s are formed in the epitaxial layers at both ends so as to be in contact with the trench line. In addition, an opening end of a region where the N-type diffusion layer constituting the source region 32s and the metal wiring constituting the source electrode (pad) 35s are electrically connected, that is, a source contact opening is provided on the trench line. Yes.
Then, the gate resistance Rg at the intersecting portion can be reduced by providing the gate lead-out bridging electrode 33B orthogonal to the stripe-shaped gate electrode.

  Further, a gate electrode 33 made of polycrystalline silicon is led out to the element surface, and a gate wiring extending in parallel with the source wiring and the drain wiring is provided. A method of reducing the gate resistance by electrically connecting a backing wiring made of a conductive material such as aluminum having a lower heavy resistance than that of polycrystalline silicon to the gate wiring has been proposed (Patent Document 2).

  Furthermore, a method for improving the on / off characteristics of each transistor by optimizing the connection position between the source wiring and the source electrode has been proposed (Patent Document 3).

  In addition, when mounting a semiconductor chip on a package, a reduction in capacitance is a major issue. Of the semiconductor device manufacturing processes, an example of a mounting process is as follows. First, a semiconductor chip cut out from a wafer in which a desired element region and wiring are formed is formed by processing a plate-shaped body mainly composed of copper, and an island portion (semiconductor element mounting portion) and the island portion are formed. The lead frame is mounted on an island portion of a lead frame having a lead portion formed of a lead terminal formed so that the tip is close to the lead portion. Next, the element electrode formed on the surface of the semiconductor chip is electrically connected to a lead terminal provided in the vicinity of the periphery of the island portion using a connecting conductor such as a gold wire or an aluminum wire. Thereafter, the semiconductor chip and the lead frame are packaged by being sealed with a resin or the like, leaving a part of the tip of the lead terminal, thereby forming a semiconductor device. Here, the package means a combination of a lead frame including leads and a sealing resin.

  Here, when a connecting conductor such as a gold wire or an aluminum wire called a bonding wire is used for connection between the semiconductor chip and the lead, the wire diameter per one is about several tens to several hundreds μm. In order to reduce the on-resistance, it is necessary to use several tens to several hundreds of gold wires, aluminum wires, and the like, which increases the cost and complicates the assembly process.

  Therefore, in Patent Document 4, as shown in a cross-sectional view in FIG. 15 and a perspective view in FIG. 16, the semiconductor chip 1 and the lead frame 30 are electrically connected using a plate-like connecting conductor 15 made of aluminum. It describes how to connect. The source pad 36 connected to the source electrode 35 s and the lead frame 30 are electrically connected by the connecting conductor 15. Here, the gate pad 35 g connected to the gate electrode 33 made of the polycrystalline silicon film is connected to the lead terminal via the bonding wire 16. 34 is an interlayer insulating film, 36 is a nickel layer constituting a source pad, and 37 is a solder layer. Reference numeral 20 denotes a resin package. Direct ultrasonic connection is also possible without using a solder layer.

  Thus, by using a plate-like connecting conductor made of copper (for soldering connection) or aluminum (for ultrasonic connection), the on-resistance occupied by the package can be reduced, and a resistance of 1 milliohm or less is achieved. realizable. Furthermore, from the viewpoint of heat dissipation, the thermal conductivity is higher than that of a gold wire or aluminum wire. Therefore, heat dissipation from the semiconductor chip to the lead frame is improved, and a higher current capacity can be realized.

JP 2004-31386 A Japanese Patent Laid-Open No. 2005-12019 JP 2009-141007 A JP2002-314018 (page 16, FIG. 2)

In Patent Document 1, when the bridging electrode is polycrystalline silicon, there is a limit to lowering the gate resistance because the sheet resistance of polycrystalline silicon is large.
FIG. 17 shows the finger length dependency of the gate resistance. In the figure, the vertical axis represents the gate resistance, and the horizontal axis represents the finger length (μm). In the figure, a solid line a indicates a case where the bridging electrode is polycrystalline silicon, and a solid line b indicates a case where the bridging electrode is aluminum.

  As is apparent from this figure, when the bridging electrode is polycrystalline silicon, the sheet resistance is higher than that of aluminum, the bridging effect is reduced, and the gate resistance is increased. Therefore, it can be seen that it is desirable to use an aluminum layer having a low sheet resistance as the bridging electrode in order to reduce the gate resistance.

  However, when the aluminum layer is used as a bridging electrode, the aluminum layer is also used as the source electrode 35s, as shown in the plan views of the polycrystalline silicon layer and the aluminum layer in FIGS. 18 (a) and (b). The source electrode is divided.

  For this reason, in order to assemble a MOSFET in which the source electrode is divided, it is necessary to connect all of the divided source electrodes, and thus there is a problem that the assembly is restricted.

  The present invention has been made in view of the above circumstances, and aims to reduce the wiring resistance of the gate and increase the operation speed of a semiconductor device having a trench gate while suppressing an increase in source resistance. It is.

  In order to solve the above object, the present invention provides a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, and a first substrate formed on the first main surface. One semiconductor region, a plurality of trenches formed in the first main surface, a gate electrode made of a polycrystalline silicon layer filled in the trench, and formed in a direction orthogonal to the trench, A bridging electrode made of a polycrystalline silicon layer that connects the electrodes, a current collecting ring electrode that is formed along the periphery of the semiconductor substrate and is connected to the gate electrode and the bridging electrode, and formed on the first main surface A first electrode in contact with the first semiconductor region, and a first metal layer, a first external extraction electrode connected to the first electrode, and a second metal layer, A second outside connected to the gate electrode; The extraction electrode is a semiconductor device juxtaposed on the first main surface, the first external extraction electrode is integrally formed, and at least a part of the surface of the bridging electrode is the first It is characterized by comprising two metal layers.

  Further, the present invention is the semiconductor device, wherein the trench is formed in a stripe shape, the bridging electrode is provided so as to be orthogonal to the trench, and the first external extraction electrode is It includes a constricted portion, and the constricted portion is formed with the second external extraction electrode.

  The present invention is also the semiconductor device, wherein all of the trenches intersect the second external extraction electrode made of the second metal layer at at least one point of the intermediate portion excluding the end portion of the semiconductor device. Includes those configured to conduct.

  Also, the present invention is the semiconductor device, wherein the second external extraction electrode is an intermediate portion excluding an end portion of the semiconductor device, has a component parallel to the trench, and constitutes a relay point. Includes configured ones.

  The present invention also includes the semiconductor device, wherein the first and second metal layers are made of the same metal material.

  Further, the present invention is the semiconductor device, wherein the second external extraction electrode includes a parallel component formed in parallel to the trench and a vertical component orthogonal to the parallel component at the tip of the parallel component. Including a T-shaped electrode.

  The present invention is also the semiconductor device, wherein the first semiconductor region is a source region, the first external extraction electrode is a source pad, and the second external extraction electrode is a gate pad. including.

  Further, the present invention includes the semiconductor device, wherein the first external extraction electrode is formed so as to be symmetric.

  The present invention is also the semiconductor device, wherein the first electrode is made of a material containing aluminum as a main component.

  As described above, according to the semiconductor device of the present invention, since at least a part of the bridging electrode is composed of the second metal layer, it is possible to reduce the lead-out resistance of the trench gate. Moreover, since the 1st external extraction electrode connected to the 1st electrode is also formed integrally, without dividing, it is low resistance. Further, it is easy to connect the first external extraction electrode and the connection conductor, that is, the connection conductor, and it is possible to reduce the external extraction resistance (gate resistance) of the gate electrode while reducing the external extraction resistance of the first electrode. it can.

The figure which shows the semiconductor device which concerns on Embodiment 1 of this invention, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device (C) is a figure which shows only a 1st metal layer. A-A cross-sectional view of FIG. The figure which shows the mounting structure of the semiconductor device of Embodiment 1 of this invention BB sectional view of FIG. The figure which shows the connection conductor in this Embodiment 1, (a) is a top view, (b) is sectional drawing. The figure which shows the state before cutting | disconnection of the connection conductor The figure which shows the semiconductor device which concerns on Embodiment 2 of this invention, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device (C) is a figure which shows only a 1st metal layer. The figure which shows the semiconductor device which concerns on Embodiment 3 of this invention, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device (C) is a figure which shows only a 1st metal layer. The figure which shows the semiconductor device which concerns on Embodiment 4 of this invention, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device (C) is a figure which shows only a 1st metal layer. The figure which shows the mounting state of the semiconductor device which concerns on Embodiment 5 of this invention. The figure which shows the connection conductor of the semiconductor device which concerns on Embodiment 5 of this invention, (a) is a top view, (b) is sectional drawing. Sectional drawing of the semiconductor device which concerns on Embodiment 5 of this invention. The figure which shows the semiconductor device of a prior art example (A) And (b) is a figure which shows the semiconductor device of a prior art example The figure which shows the semiconductor device of a prior art example The figure which shows the semiconductor device of a prior art example Characteristic diagram showing the relationship between the finger length and gate resistance of polycrystalline silicon and aluminum The figure which shows the semiconductor device of a prior art example, (a) is a figure which shows the layout of the polycrystalline-silicon layer on the surface of a semiconductor device, (b) is the figure which shows the layout of the aluminum layer on the surface of the semiconductor device

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1A is a diagram showing a layout of a polycrystalline silicon layer on the surface of a semiconductor device in Embodiment 1 of the present invention, and FIG. 1B is a first metal layer and a second metal layer on the surface of the semiconductor device. It is a figure which shows the layout of an aluminum layer. FIG. 1C shows only the second metal layer. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a diagram showing a mounting structure of the semiconductor device. 4 is a cross-sectional view taken along line BB in FIG. FIG. 5 is a view showing the connecting conductor in the first embodiment, and FIG. 6 is a view showing a state before the connecting conductor is cut.

This semiconductor device constitutes a trench MOSFET provided with a bridging electrode 33B so as to be orthogonal to the stripe-shaped trench T, and a source pad 36 constituting a first external extraction electrode is formed integrally. The source electrode 35s has a constricted portion k and is formed by extending a gate pad 35g as a second external extraction electrode in the constricted portion k, and at least a part of the surface of the bridging electrode 33B is formed. The aluminum layer is the same metal layer as the source electrode 35s. That is, the gate current collecting electrode 35T, which is an extended portion of the gate pad 35g made of an aluminum layer, is laminated on the surface of the bridging electrode 33B. All of the trenches intersect with the second external extraction electrode constituting the gate pad 35g at at least one point of the intermediate portion excluding the end of the trench MOSFET chip, and the second external extraction electrode of the gate electrode 33g. that is, the length F _c of the region exposed from the second metal layer so as not to exceed three times the finger length F _0, to reduce the distance between the gate collecting electrode 35T or gate pad 35 g, gate resistor It is intended to reduce this. Here, the finger length refers to the gate electrode length between the bridging electrodes 33B. The source pad 35s is formed to be almost symmetrical. In the present embodiment, the finger length F _c between the gate collector electrodes 35T, that is, the maximum length F _cmax of the bridging electrode 33B of the single polycrystalline silicon layer is 1.37 mm. Here, the finger length between the gate electrodes 33g is 0.45 mm.

  That is, the semiconductor device includes a plurality of trenches T formed in the first main surface S1 of the semiconductor substrate, a gate electrode 33 made of a polycrystalline silicon layer filled in the trench T, and the trench T. It is formed in a direction orthogonal to the trench T so as to be connected, and is formed along the peripheral edge of the semiconductor substrate, and is connected to the gate electrode 33 and the bridge electrode 33B. A current collecting ring electrode gl (a base layer 33gl made of a polycrystalline silicon layer and a current collecting layer 35gl made of an aluminum layer) and a contact with a source region 32s as a first semiconductor region formed on the first main surface S1. And a source electrode 35s made of aluminum as a first electrode. Further, a source pad 36 connected to the source electrode 35s as the first electrode and a gate pad as the second external extraction electrode are juxtaposed on the first main surface S1. At least a part of the bridging electrode 33B is composed of the second metal layer, and all of the trenches T are configured to cross and conduct with the second metal layer at least at one point. Here, the first metal layer and the second metal layer are composed of the same metal layer, which is an aluminum layer here.

Next, the mounting structure of the semiconductor device will be described. In this semiconductor device, as shown in FIG. 4, the trench MOSFET is electrically connected to one end of a lead terminal 30 </ b> R of the lead frame 30 via a connecting conductor 15. FIG. 5A shows a top view of the connecting conductor, and FIG. 5B shows a cross-sectional view. This connecting conductor is composed of a plate-like body made of copper (Cu foil), and is in contact with the main body portion 15M, the lead terminal 30R, connected to the lead terminal 30R, and the trench MOSFET (chip). It is comprised by the finger part 15F which contact | abuts a source pad, and the connection part 15B which integrates the front-end | tip of the finger part 15F in a space part.
The trench MOSFET is formed on a semiconductor element mounting portion 30 s that is an island-shaped electrode of the lead frame 30. The finger portion 15F of the connecting conductor 15 is fused to the source pad 36, and the lead connection portion 15R is electrically connected to one end of the lead terminal 30 terminal R of the lead frame 30. The gate pad 35g is connected to the lead terminal 30P by the bonding wire 16. The trench MOSFET and the semiconductor element mounting portion 30s are electrically connected via a solder layer. The package 20 is then sealed with a sealing resin made of an epoxy resin. Since the sealing resin is originally opaque, the inside is not actually seen, but in this example, the inside is made visible for explanation.

  FIG. 6 is a view showing a connecting conductor before mounting, and a large number of connecting conductors are connected in a strip shape in the longitudinal direction. In manufacturing the connection conductor, a plate-like body such as a copper plate is formed by punching, and then fused to the connection portion between the lead and the semiconductor substrate, and then bent and cut. As described above, since the connecting conductor material is formed in a continuous form, it has good workability and high reliability in mounting. Due to the presence of the connecting portion 15B, it is possible to form a connecting conductor that is not continuously displaced.

  Here, since the source electrode 35s is made of aluminum, it can be electrically connected to the lead terminal 30R by ultrasonic connection. The connecting conductor 15 has two functions, that is, a function of high conductivity and thermal conductivity and a function of simplifying electrical connection. Therefore, the on-resistance occupied by the package when the trench MOSFET operates can be reduced, and the heat generated in the trench MOSFET can be efficiently discharged to the outside. In addition, when the connecting conductor 15 is made of aluminum instead of copper, when the source electrode 35s and the lead connecting portion 15R are electrically connected by the connecting conductor 15, it can be easily joined by ultrasonic joining. The construction method can be simplified as compared with the case of using.

The trench MOSFET had a gate resistance of 2.0Ω and an on-resistance of 3.7 mΩ when the gate width was 5 m. As described above, according to the trench MOSFET of the present embodiment, the gate resistance can be reduced while the on-resistance is kept low.
Here, the source wiring resistance was 0.3 mΩ, the device resistance was 3 mΩ, and the connection conductor resistance was 0.4 mΩ.

According to the present embodiment, in the semiconductor device in which the first external extraction electrode constituting the source electrode and the second external extraction electrode connected to the gate electrode are juxtaposed on the first main surface S1. The source pad as the first external extraction electrode is integrally formed, and at least a part of the surface of the bridging electrode is composed of the second metal layer. However, any part is shorter than the conventional example, and the gate resistance can be reduced. Therefore, it is possible to increase the speed.
Further, since the source pad has a constricted portion, and the gate current collecting electrode as the second external extraction electrode is formed in the constricted portion, the gate extraction resistance can be reduced to the maximum.

  Furthermore, the connecting conductor used for connecting the lead and the semiconductor chip here is connected to the main body 15M connected to the lead for external connection and the main body 15M, and is divided into a plurality of regions, each of which is a semiconductor. Since the finger portion 15F connected to the electrode pad of the substrate and the connecting portion 15B connected to the tip of the finger portion 15F and integrating the tip of the finger portion 15F are provided, the source pad is divided into a plurality of regions. It is possible to satisfactorily achieve electrical and physical contact even in the case where the contact point is formed or a deformation region is formed.

  Further, according to the present invention, if the connecting conductor is continuously used as the strip material connected in the vertical direction, the mounting workability becomes easy.

  In the above embodiment, the connecting conductor is made of copper foil, but is not limited to copper foil. For example, this connecting conductor is formed by joining an aluminum foil having a thickness of about 0.05 mm to a copper plate having a two-layer structure and having a thickness of about 0.1 mm, and cutting it into a desired shape. Aluminum is easy to ultrasonically bond and has good workability. Copper is characterized by high electrical conductivity and high mechanical strength.

  As the connecting conductor, an aluminum thin film as the second conductor may be formed on the copper plate as the first conductor by forming a thin film using sputtering, CVD, or the like, or by using a plating method. Also good.

  Although the semiconductor device according to the first embodiment of the present invention has been described above, the present invention is not limited to this embodiment.

  For example, although the aluminum layers are used as the first and second metal layers in the first embodiment, metals such as silver, gold, nickel, and titanium may be used. As the first and second metal layers, those having a low melting point and easy ultrasonic bonding are preferable. However, the first and second metal layers are not necessarily the same material as long as the materials have good adhesion to the lead terminal 30R or the source electrode 35s. May be. Moreover, you may make it interpose a solder as needed.

  Moreover, in the said embodiment, although the connection conductor was bent and comprised so that a level | step difference might be made, you may comprise so that a curved shape may be made. For example, when the semiconductor element mounting portion 30s is disposed at a position lower than the end face of the lead terminal 30R and the element electrode to be connected and the lead frame have the same lead height, the connecting conductor does not form a curved surface. It may be a flat surface.

(Embodiment 2)
FIG. 7A shows a layout of the polycrystalline silicon layer on the surface of the semiconductor device according to the second embodiment of the present invention, and FIG. 7B shows the first and second metal layers on the surface of the semiconductor device. It is a figure which shows the layout of an aluminum layer. FIG. 7C shows only the second metal layer.

In this semiconductor device, as shown in FIG. 7C, the tip of the gate current collecting electrode 35T is an intermediate portion excluding the end portion of the semiconductor device, and has a component parallel to the trench T to form a relay point. Configured as follows.
That is, the gate collecting electrode 35T, which is the second external extraction electrode, includes a parallel component formed in parallel to the trench and a vertical component orthogonal to the parallel component at the tip of the parallel component. Configure. Further, as in the first embodiment, this semiconductor device constitutes a trench MOSFET provided with a bridging electrode 33B so as to be orthogonal to the stripe-shaped trench T, and constitutes a first external extraction electrode. The source pad 36 is integrally formed, and the source electrode 35s is formed by extending a gate pad 35g as a second external extraction electrode at the constricted portion k and having the constricted portion k. At least a part of the surface is composed of an aluminum layer that is the same metal layer as the source electrode 35s.
As is clear from FIG. 7C, according to the present embodiment, the gate current collecting electrode 35T is formed symmetrically in the vertical and horizontal directions of the chip except for the gate pad. The length F _c , that is, the maximum length F _cmax of the bridging electrode 33B of the single polycrystalline silicon layer is 1.83 mm. Again, the finger length F ₀ between the gate electrodes 33g is 0.45 mm.

The trench MOSFET had a gate resistance of 1.5Ω and an on-resistance of 3.5 mΩ when the gate width was 5 m. As described above, according to the trench MOSFET of the present embodiment, the gate resistance can be reduced while the on-resistance is kept low. Here, the source wiring resistance was 0.1 mΩ, the device resistance was 3 mΩ, and the connection conductor resistance was 0.4 mΩ.
Since other configurations are the same as those of the above-described embodiment, description thereof is omitted here.
The mounting is the same as in the first embodiment.
According to the above configuration, it is possible to reduce the extraction resistance, and it is possible to provide a high-speed and highly reliable semiconductor device.

(Embodiment 3)
FIG. 8A shows a layout of the polycrystalline silicon layer on the surface of the semiconductor device according to the third embodiment of the present invention, and FIG. 8B shows the first and second metal layers on the surface of the semiconductor device. It is a figure which shows the layout of an aluminum layer. FIG. 8C shows only the second metal layer.

In this semiconductor device, as shown in FIG. 8C, the gate current collecting electrode 35T is basically the same as in the first embodiment, in which all of the trenches are at least one point in the intermediate portion excluding the end portion of the semiconductor device. In the same manner as in the second embodiment, the tip of the gate current collecting electrode 35T is an intermediate portion excluding the end portion of the semiconductor device and parallel to the trench. It has such a component and is configured to constitute a relay point.
That is, the second external extraction electrode includes a parallel component formed in parallel with the trench and a vertical component orthogonal to the parallel component at the tip of the parallel component, and constitutes a T-shaped electrode. Here again, the source pad has a constricted portion k, and the gate current collecting electrode extends in the constricted portion k. Other parts are the same as those in the first and second embodiments, and the description thereof is omitted here.
In this way, according to the present embodiment, the gate current collecting electrode 35T is formed to be substantially point-symmetric, and the finger length F _c between the gate current collecting electrodes, that is, the bridging electrode of a single polycrystalline silicon layer The maximum length F _cmax of 33B is 1.37 mm. Here, the finger length F ₀ between the gate electrodes 33g is 0.45 mm.

The trench MOSFET had a gate resistance of 1.2Ω and an on-resistance of 3.6 mΩ when the gate width was 5 m. As described above, according to the trench MOSFET of the present embodiment, the gate resistance can be reduced while the on-resistance is kept low.
Here, the source wiring resistance was 0.2 mΩ, the device resistance was 3 mΩ, and the connection conductor resistance was 0.4 mΩ.
Since other configurations are the same as those of the above-described embodiment, description thereof is omitted here.
The mounting is the same as in the first embodiment.
Thus, by forming a relay point as the gate current collecting electrode, it is possible to further increase the current collecting performance and reduce the gate extraction resistance while suppressing an increase in the source resistance.

(Embodiment 4)
FIG. 9A shows a layout of the polycrystalline silicon layer on the surface of the semiconductor device according to the fourth embodiment of the present invention, and FIG. 9B shows the first and second metal layers on the surface of the semiconductor device. It is a figure which shows the layout of an aluminum layer. FIG. 9C shows only the second metal layer.

In this semiconductor device, as shown in FIG. 9C, the gate current collecting electrode 35T has only a component orthogonal to the gate electrode 33g, and the constricted portion k of the source electrode 35s is suppressed as much as possible.
That is, the second external extraction electrode includes a parallel component formed in parallel with the trench and a vertical component orthogonal to the parallel component at the tip of the parallel component, and constitutes a T-shaped electrode. Again, the source pad has a constricted portion k, and the gate collecting electrode 35T is configured to extend to the constricted portion k.
In this manner, according to the present embodiment, the gate current collecting electrode 35T is formed substantially vertically and horizontally symmetrical except for the gate pad, and the finger length F _c between the gate current collecting electrodes, that is, polycrystalline silicon. The maximum length F _cmax of the single-layer bridging electrode 33B is 1.83 mm. Again, the finger length F _o between the gate electrodes 33g is 0.45 mm.

The trench MOSFET had a gate resistance of 3.5Ω and an on-resistance of 3.5 mΩ when the gate width was 5 m. As described above, according to the trench MOSFET of the present embodiment, the gate resistance can be slightly reduced while maintaining the on-resistance low. Here, the source wiring resistance was 0.1 mΩ, the device resistance was 3 mΩ, and the connection conductor resistance was 0.4 mΩ.
Since other configurations are the same as those of the above-described embodiment, description thereof is omitted here.
The mounting is the same as in the first embodiment.
As described above, according to the above configuration, the gate collecting electrode is formed with a T-shaped relay point having a component parallel to the finger and a component perpendicular to the finger, thereby suppressing an increase in source resistance and further collecting current. It is possible to increase the electrical property and reduce the gate extraction resistance.

(Embodiment 5)
Next, a modified example of the mounting structure of the semiconductor device will be described. In this semiconductor device, as shown in FIG. 10, the trench MOSFET is electrically connected to one end of a lead terminal 30 </ b> R of the lead frame 30 via a connecting conductor 15. FIG. 11A shows a top view of the connecting conductor, and FIG. 11B shows a cross-sectional view. FIG. 12 is a view showing a cross section of the semiconductor chip including the connecting conductor 15. Compared with the connection conductor of the first embodiment shown in FIGS. 5 and 6 (a) and 6 (b), this connection conductor has no connection portion 15B that integrates the tips of the finger portions 15F in the space portion. The only difference from Embodiment 1 is that the tip of the finger portion 15F is in a free state, and the others can be modified as appropriate. That is, the connecting conductor is formed of a plate-shaped body made of copper (Cu foil), and is in contact with the main body portion 15M, the lead terminal 30R and connected to the lead terminal 30R, and a trench MOSFET (chip). The finger portion 15F is in contact with the source pad.
The trench MOSFET is formed on a semiconductor element mounting portion 30 s that is an island-shaped electrode of the lead frame 30. The finger portion 15F of the connecting conductor 15 is fused to the source pad 36, and the lead connection portion 15R is electrically connected to one end of the lead terminal 30R of the lead frame 30. The gate pad 35g is connected to the lead terminal 30P by the bonding wire 16. The trench MOSFET and the semiconductor element mounting portion 30s are electrically connected via a solder layer. The package 20 is then sealed with a sealing resin made of an epoxy resin. Since the sealing resin is inherently opaque, the inside is not actually seen, but in this example, the inside is made visible for explanation.

  According to this configuration, since the rigidity of the connecting conductor is low, workability is slightly reduced in the joining step, but the same effect as in the first embodiment is also achieved in this embodiment. Also in the present embodiment, for example, since the source electrode 35s is made of aluminum, it can be electrically connected to the lead terminal 30R by solder connection. Here, solder connection is made through a source pad 36 made of a nickel layer. The connecting conductor 15 has two functions, that is, a function of high conductivity and thermal conductivity and a function of simplifying electrical connection. Therefore, the on-resistance occupied by the package when the trench MOSFET operates can be reduced, and the heat generated in the trench MOSFET can be efficiently discharged to the outside. Further, when the source pad 35s and the lead connection portion 15R are electrically connected by the connecting conductor 15, the connecting conductor 15 can be easily bonded by ultrasonic bonding by using an aluminum ribbon instead of copper. The construction method can be simplified as compared with the case where solder bonding is used.

For the semiconductor chip, any of the first to fourth embodiments may be used.
Needless to say, the connecting conductor used in the conventional semiconductor device shown in FIG. 16 may be used for mounting.
Further, although the vertical trench MOSFET has been described in the above embodiment, any vertical semiconductor device having a trench gate such as an IGBT can be applied.

  As described above, according to the present invention, since the gate resistance can be reduced while suppressing the source resistance, a high-speed semiconductor device with low power consumption can be provided. It can be applied to small electronic devices including secondary battery charge control circuits.

S1 1st main surface S2 2nd main surface 15 Connection conductor 15R Lead connection part 15M Connection conductor main-body part 15F Finger part 15B Connection part 30 Lead frame 30R Lead terminal 30s Semiconductor element mounting part 33B Bridging electrode k Constriction part 35g Gate pad 35s Source electrode 35T Gate current collecting electrode 36 Source pad

Claims (9)

A semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
A first semiconductor region formed on the first main surface;
A plurality of trenches formed in the first main surface; and a gate electrode made of a polycrystalline silicon layer filled in the trenches;
A bridging electrode made of a polycrystalline silicon layer formed in a direction perpendicular to the trench and connecting the trenches;
A current collecting ring electrode formed along the periphery of the semiconductor substrate and connected to the gate electrode and the bridging electrode;
A first electrode formed on the first main surface and in contact with the first semiconductor region;
A first external extraction electrode made of a first metal layer and connected to the first electrode, and a second external extraction electrode made of a second metal layer and connected to the gate electrode, A semiconductor device juxtaposed on the first main surface,
The first external extraction electrode is integrally formed;
A semiconductor device in which at least a part of a surface of the bridging electrode is constituted by the second metal layer. The semiconductor device according to claim 1,
The trench is formed in a stripe shape,
The bridging electrode is provided to be orthogonal to the trench,
The first external extraction electrode has a constricted portion,
A semiconductor device in which the second external extraction electrode is formed in the constricted portion. The semiconductor device according to claim 1, wherein
A semiconductor device configured such that all of the trenches cross and conduct with the second external extraction electrode made of the second metal layer at at least one point of an intermediate portion excluding an end portion of the semiconductor device. The semiconductor device according to claim 1, wherein
The second external extraction electrode is a semiconductor device configured to have a component parallel to the trench at an intermediate portion excluding an end portion of the semiconductor device and to constitute a relay point. 5. The semiconductor device according to claim 1, wherein:
The first and second metal layers are semiconductor devices made of the same metal material. The semiconductor device according to claim 5,
The second external extraction electrode includes a parallel component formed in parallel to the trench and a vertical component orthogonal to the parallel component at a tip of the parallel component, and constitutes a T-shaped electrode. The semiconductor device according to claim 5, wherein:
The first semiconductor region is a source region;
The first external extraction electrode is a source pad;
The semiconductor device, wherein the second external extraction electrode is a gate pad. A semiconductor device according to any one of claims 1 to 7,
The first external extraction electrode is a semiconductor device formed to be symmetrical. A semiconductor device according to any one of claims 1 to 8,
The first electrode is a semiconductor device made of a material whose main component is aluminum.

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