JP2012169841A - Timing control circuit, timing control method and system - Google Patents

Abstract

To suppress a decrease in timing margin.
A control circuit formed in a system device controls a capacitance value of a variable capacitor and causes a training circuit to execute timing training. The training circuit 45 outputs the maximum value and the minimum value of the set values with which the memory 12 can write normal data based on the data DQ. The control circuit 36 calculates the window width of the data DQ based on the maximum value and the minimum value, and sets a capacitance value corresponding to a larger window width in the variable capacitor 35.
[Selection] Figure 3

Description

  The present invention relates to a timing control circuit, a timing control method, and a system.

  Conventionally, a system includes a system device (for example, SoC: System on Chip) and a memory accessed by the system device. The system device and the memory are mounted on a board (for example, a printed circuit board (PCB)) and are connected to each other via wiring formed on the board. In a semiconductor device such as a system device or a memory, a chip (or die) is accommodated in a package. The chip is connected to the wiring of the substrate via a conductor of the package (a lead frame, wiring formed on the interposer, etc.).

  The memory is, for example, an SDRAM (Synchronous Dynamic Random Access Memory). The SDRAM inputs and outputs data in synchronization with a clock signal. Double data rate SDRAMs that input and output data at both rising and falling timings of clock signals are called DDR-SDRAMs (Double Data Rate SDRAMs), DDR2-SDRAMs, and DDR3-SDRAMs. Corresponding to the high speed.

  When reading data from the DDR-SDRAM (memory), the system device supplies a read command to the DDR-SDRAM. In response to the read command, the DDR-SDRAM outputs a data strobe signal DQS (clock signal) and data DQ synchronized with the data strobe signal DQS. The receiving circuit provided in the system apparatus adjusts the timing of the data strobe signal DQS and takes in the data DQ based on the adjusted data strobe signal.

  A circuit provided in the system apparatus operates with a power supply voltage supplied via a power supply wiring. The power supply voltage fluctuates due to circuit operations such as simultaneous bus switching and device activation, and noise (power supply noise) is generated due to fluctuations in the power supply voltage. Therefore, two power supply wirings (a wiring for supplying a high potential side voltage and a wiring for supplying a low potential side voltage) included in a system device package (PKG) and a wiring board (PCB: Printed Circuit Board) A capacitor (decoupling capacitor) that suppresses fluctuations in the power supply voltage is connected between them (see, for example, Patent Document 1 and Patent Document 2). This capacitance value (capacitance value) is determined so as to reduce the impedance of the power supply path such as the power supply wiring in the design of the system device, and the power supply noise amount is verified by the power supply noise simulation.

JP 2008-085321 A JP 2006-173369 A

  By the way, the shape of the system device, for example, the shape of the wiring board or package, may be changed after the above-described power supply noise simulation, for example, due to a change in user specifications. In this case, since the value of the capacitance between the power supply wirings necessary for reducing the power supply noise is different from the design value, resonance occurs at an unexpected frequency.

  The resonance generated in this way affects the edge (transition timing) of the data strobe signal DQS and data DQ, that is, the transition timing may be changed. For example, when the edge of the data DQ advances and the edge of the data strobe signal DQS delays, the period during which the data DQ is valid (data valid window) with respect to the data strobe signal DQS is effectively narrowed. Then, the timing margin of the data DQ with respect to the data strobe signal DQS becomes small, and the data DQ may not be correctly captured.

  According to one aspect of the present invention, a first output circuit that is connected between a first power supply line and a second power supply line and outputs a first signal is provided between the first power supply line and the second power supply line. A second output circuit that outputs a second signal, a variable capacitor connected between the first power supply line and the second power supply line, and a phase difference between the first signal and the second signal A delay circuit that adjusts the capacitance value of the variable capacitor, and data based on the first signal is stored in the memory for each of a plurality of phase differences in the first signal and the second signal that are adjusted by the delay circuit. A control circuit that determines whether or not writing is possible, measures the window width of the first signal, and sets a capacitance value corresponding to a larger window width to the variable capacitance.

  According to one aspect of the present invention, a decrease in timing margin can be suppressed.

1 is a schematic configuration diagram of a system. 1 is a schematic block diagram of a system. It is a block diagram which shows the principal part circuit of a system. It is explanatory drawing of a training circuit. It is explanatory drawing of a training circuit. It is a block diagram of a variable capacity. (A) (b) is explanatory drawing of a variable capacity | capacitance. It is a circuit diagram of an I / O circuit. It is a block diagram of a training control circuit. It is a block diagram of a timing margin determination circuit. It is explanatory drawing of the result of timing training. It is a flowchart of an adjustment process. It is a flowchart of a training process. It is a flowchart of a timing margin determination process. It is a flowchart of a test access process. It is explanatory drawing of control of various settings. (A) (b) is explanatory drawing of control of various settings.

Hereinafter, an embodiment will be described with reference to the accompanying drawings.
As shown in FIG. 1, a plurality of semiconductor devices 11 to 13 are mounted on a system board (for example, a printed circuit board (PCB) 10). The semiconductor devices 11 to 13 are connected to each other via wiring (not shown) formed on the substrate 10. For example, the semiconductor device 11 is the system device shown in FIG. 2, and the semiconductor device 12 is the memory shown in FIG. In addition, a decoupling capacitor 14 is mounted on the substrate 10, and the decoupling capacitor 14 reduces fluctuations in the power supply voltage supplied to the semiconductor devices 11 to 13. In FIG. 1, one decoupling capacitor 14 is shown. However, depending on the configuration of the system, a plurality of decoupling capacitors or one or more modules including a plurality of decoupling capacitors are provided on the substrate 10. It is mounted on. The capacitance value of the decoupling capacitor 14 is set on the substrate 10 so as to reduce the impedance of the power supply path when the substrate 10 is designed.

  A system device 21 is mounted on the package 20 of the semiconductor device 11. The system device 21 is a semiconductor chip (die). The package 20 of the semiconductor device 11 is equipped with a decoupling capacitor 22 for reducing fluctuations in the power supply voltage supplied to the system device 21. The decoupling capacitor 22 is a variable capacitance element configured such that a capacitance value can be changed by an adjustment circuit formed in the system device 21. Chips 12 a and 13 a are included in packages of the semiconductor devices 12 and 13, respectively.

  As shown in FIG. 2, the system device 21 includes a core circuit 31, a memory controller 32, an interface circuit (denoted as I / F circuit) 33, and an input / output circuit (denoted as I / O circuit) 34. . The memory 12 is a synchronous semiconductor memory device, for example, a double-rate dynamic random access memory (DDR-SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory).

  The core circuit 31 outputs a read request for reading data in the memory 12 and an address at which the data is stored to the memory controller 32 in accordance with processing to be executed. The core circuit 31 outputs a write request for writing data to the memory 12 and an address for storing the data to the memory controller 32. The core circuit 31 is, for example, a central processing unit (CPU).

  The memory controller 32 supplies the internal clock signal of the memory controller 32 to the input / output circuit 34 via the interface circuit 33. The input / output circuit 34 supplies complementary clock signals CK and XCK generated according to the internal clock signal to the memory 12.

The memory controller 32 accesses the memory 12 via the interface circuit 33 in response to a request from the core circuit 31.
When the request from the core circuit 31 is a read request, the memory controller 32 supplies a read command and an address to the memory 12 via the interface circuit 33 and the input / output circuit 34. Then, in response to the read command, the memory 12 outputs the data DQ read from the corresponding address and the data strobe signal DQS synchronized with the data DQ. At this time, the memory 12 bursts out the data DQ in synchronization with the complementary clock signals CK and XCK, that is, bursts out the data DQ at a frequency twice that of the internal clock signal of the memory controller 32.

  When the request from the core circuit 31 is a write request, the memory controller 32 stores the address for writing the write command, the data DQ, the data strobe signal DQS, and the data DQ via the interface circuit 33 and the input / output circuit 34. To supply. The input / output circuit 34 supplies the memory 12 with complementary data strobe signals DQS and XDQS generated according to the data strobe signal DQS supplied from the interface circuit 33. The memory 12 stores data DQ at a corresponding address.

  Data DQ is exchanged between the memory 12 and the interface circuit 33 by a data strobe signal DQS. That is, the interface circuit 33 adjusts the timing of the data strobe signal DQS received from the memory 12 via the input / output circuit 34 during the read operation, takes in the data DQ in synchronization with the data strobe signal DQS adjusted in timing, The fetched data DQ is output to the memory controller 32. Further, the interface circuit 33 outputs the data DQ and the data strobe signal DQS received from the memory controller 32 to the memory 12 via the input / output circuit 34 during the write operation.

  As shown in FIG. 3, a high potential voltage VDD and a low potential voltage VSS are supplied to the system device 21 from, for example, a power supply module (VRM) 13 outside the package 20. The high potential voltage VDD and the low potential voltage VSS are examples of operating voltages of the system device 21. The high potential voltage VDD and the low potential voltage VSS are supplied to the system device 21 via the power supply lines 10 a and 10 b formed on the substrate (PCB) 10 and the power supply lines 20 a and 20 b formed on the package 20.

  The power supply lines 10 a and 10 b are conductors that form a power supply path between the power supply module 13 and the package 20, and include a wiring pattern formed on the substrate 10. A decoupling capacitor 14 shown in FIG. 1 is connected between the power supply lines 10a and 10b. The power supply lines 20 a and 20 b include a conductor that forms a power supply path in the package 20, for example, a wiring pattern formed in the package 20. A variable capacitor 22 is connected between the power supply lines 20a and 20b.

  The system device 21 (die) is formed with a first power supply line 21a for transmitting the high potential voltage VDD and a second power supply line 21b for transmitting the low potential voltage VSS. These power supply lines 21a and 21b are wiring patterns such as copper formed in a predetermined layer of the die.

  A first I / O circuit 34a and a second I / O circuit 34b are connected between the first power supply line 21a and the second power supply line 21b. The first I / O circuit 34a operates using the high potential voltage VDD supplied via the first power supply line 21a and the low potential voltage VSS supplied via the second power supply line 21b as drive voltages. The data strobe signal DQS is output based on the signal output from the I / F circuit 33. The signal DQS is supplied to the memory 12 via the wiring 20 c of the package 20 and the wiring 10 c of the substrate 10. The data strobe signal DQS output from the memory 12 is supplied to the I / O circuit 34a via the wirings 10c and 20c.

  Similarly, the second I / O circuit 34b drives the high potential voltage VDD supplied via the first power supply line 21a and the low potential voltage VSS supplied via the second power supply line 21b. It operates as a voltage and outputs data DQ based on a signal output from the I / F circuit 33. Data DQ is supplied to the memory 12 via the wiring 20 d of the package 20 and the wiring 10 d of the substrate 10. Data DQ output from the memory 12 is supplied to the I / O circuit 34b via the wirings 20d and 10d.

  A variable capacitor 35 is connected between the first power supply line 21a and the second power supply line 21b. The variable capacitance 35 is a variable capacitance element configured such that the capacitance value can be changed by an adjustment circuit formed in the system device 21, similarly to the variable capacitance 22 provided in the package 20. The variable capacitor 35 reduces fluctuations in the power supply voltage based on the operations of the I / O circuits 34a and 34b.

  The I / F circuit 33 includes a data strobe (DQS) signal generation circuit 41 and a delay locked loop (DLL (Delay Locked Loop) circuit) 42. The DQS signal generation circuit 41 outputs, for example, a pulse signal having a frequency twice that of the internal clock signal based on the internal clock signal. The DLL circuit 42 outputs a signal obtained by delaying the output signal of the DQS signal generation circuit 41. The DLL circuit 42 is an example of a delay circuit.

  The I / F circuit 33 includes a DQ signal generation circuit 43 and a delay locked loop circuit (DLL circuit) 44 that delays the output signal of the DQ signal generation circuit 43. The DQ signal generation circuit 43 outputs a signal corresponding to data written to the memory 12 by the core circuit 31 shown in FIG. For example, the DQ signal generation circuit 43 serially outputs a plurality of bits of parallel data output from the core circuit 31 in synchronization with a pulse signal having a frequency twice that of the internal clock signal. The DLL circuit 44 outputs a signal obtained by delaying the output signal of the DQ signal generation circuit 43. The DLL circuit 44 is an example of a delay circuit.

  The DLL circuits 42 and 44 are provided for adjusting the phase difference between the data strobe signal DQS and the data DQ. The DQS signal generation circuit 41 and the DQ signal generation circuit 43 each output a signal in synchronization with the internal clock signal. Data strobe signals DQS and XDQS are output to the memory 12 based on the output signal of the DQS signal generation circuit 41, and data DQ is output to the memory 12 based on the output signal of the DQ signal generation circuit 43. The memory 12 is a DDR3-SDRAM, for example, and takes in the data DQ at the edge timing of the data strobe signals DQS and XDQS. Therefore, the system device 21 outputs the phase difference between the data DQ and the data strobe signal DQS with a predetermined value (90 degrees) shifted. Therefore, the DLL circuits 42 and 44 are a signal output in response (delay) to the output signal of the DQS signal generation circuit 41 and a signal output in response (delay) to the output signal of the DQ signal generation circuit 43. The phase difference is set to a predetermined value (90 degrees).

  The I / F circuit 33 includes a training circuit 45 that adjusts the timing of the data strobe signal DQS and the data DQ. The training circuit 45 provides a timing training function for adjusting the timing at which the data strobe signal DQS and data DQ output from the I / F circuit 33 reach the memory 12.

Timing control by the training circuit 45 will be described.
As shown in FIG. 4, the delay circuit 37 of the system device 21 outputs the internal clock signal with a predetermined time delay. The I / O circuit (driver circuit) 34 c outputs complementary clock signals CK and XCK based on the output signal of the delay circuit 37. The DLL circuit 42 delays and outputs the signal output from the DQS signal generation circuit 41 shown in FIG. Based on the output signal of the DLL circuit 42, the I / O circuit (driver circuit) 34a outputs the data strobe signal DQS and the inverted data strobe signal XDQS complementary to the data strobe signal DQS. The I / O circuit 34a is an example of a first output circuit. The DLL circuit 42 delays and outputs the signal output from the DQ signal generation circuit 43 shown in FIG. The I / O circuit (driver circuit) 34 b outputs a data signal DQ based on the output signal of the DLL circuit 42. The I / O circuit 34b is an example of a second output circuit.

  Various signals output from the system device 21 reach the memory 12 after elapse of time corresponding to the signal transmission path between the system device 21 and the memory 12. The period from the output time of the system device 21 until the signal reaches the memory 12 is a wiring delay in various signals and may vary depending on the wiring path.

  FIG. 5 shows timings of various signals between the system device 21 and the memory 12 shown in FIG. The upper part of FIG. 5 shows the output timing in the system device 21, and the lower part of FIG. 5 shows the input timing in the memory 12.

  For example, the clock signals CK and XCK output from the I / O circuit 34c are input to the memory 12 after the elapse of the delay time DL1 due to the wiring delay, as shown in FIG. Similarly, the data strobe signals DQS and XDQS output from the I / O circuit 34a shown in FIG. 4 are input to the memory 12 after the delay time DL2 has elapsed from the output time. The data DQ output from the I / O circuit 34b shown in FIG. 4 is input to the memory 12 after the delay time DL3 has elapsed from the output time.

  As described above, the memory 12 is a DDR-SDRAM. Such a memory 12 captures various control signals (commands) in synchronization with the clock signals CK and XCK. The memory 12 takes in the data DQ in synchronization with the edges of the data strobe signals DQS and XDQS. Therefore, as shown in the lower part of FIG. 5, the difference (timing deviation) between the timing of the clock signals CK and XCK and the timing of the data strobe signals DQS and XDQS is in a range according to the specification (spec) of the memory 12. Must be in. Further, the edge timing of the data strobe signals DQS and XDQS needs to be set so as to satisfy the hold time (Hold Time) and the setup time (Setup Time) with respect to the valid period of the data DQ. For example, the edge timings of the data strobe signals DQS and XDQS are adjusted so that there is a margin with respect to each of the hold time and the setup time in the valid period of the data DQ, for example, near the center. Need to be done. The valid period (data valid window) of the data DQ is a period during which data equal to the data on the driver side can be sampled on the receiver side.

  The training circuit 45 outputs the test signal to the memory 12 while shifting the timing of the output signal. Based on the reception result of the test signal output from the memory 12, the training circuit 45 outputs each signal, that is, the level of the data strobe signal DQS and the data DQ so that the memory 12 can receive correct data. The phase difference, that is, the delay amount in the DLL circuits 42 and 44 is adjusted.

  For example, in the case of data strobe signals DQS and XDQS, a delay time DL2 occurs in the signal transmission path as shown in FIG. Therefore, the training circuit 45 adjusts the DLL circuit 42 so that the data strobe signals DQS and XDQS are output after the delay time DS1 has elapsed with respect to the clock signals CK and XCK. Similarly, the training circuit 45 adjusts the DLL circuit 44 with respect to the clock signals CK and XCK so that the time after the delay time DS2 elapses is near the center of the data valid window of the data DQ.

  As shown in FIG. 3, the system device 21 includes a control circuit 36 that controls the capacitance value of the variable capacitor 35. The control circuit 36 controls the slew rate of the I / O circuits 34a and 34b. The control circuit 36 has a function of controlling the capacitance value of the variable capacitor 22 included in the package 20.

The control circuit 36 includes a training control circuit 51 and a timing margin determination circuit (hereinafter referred to as TM determination circuit, hereinafter referred to as TM determination circuit) 52.
The training control circuit 51 outputs an initialization signal to the TM determination circuit 52, and the TM determination circuit 52 initializes a register that holds a set value in response to the initialization signal. Further, the training control circuit 51 outputs a start signal to the training circuit 45, and the training circuit 45 executes timing training with the memory 12 in response to the start signal, and the maximum value of the set value for the DLL circuit 44 and Get the minimum value. Then, the training circuit 45 outputs the maximum setting value and the minimum setting value obtained by the timing training to the TM determination circuit 52.

  Based on the maximum setting value and the minimum setting value, the TM determination circuit 52 determines whether or not the size of the effective window of the data DQ at that time is maximum, and sets the setting value when the effective window is maximum. Store in register. Then, the set values (maximum value and minimum value) held in the TM determination circuit 52 register are output to the training control circuit 51.

  The training control circuit 51 controls the control signal SC1 for controlling the capacitance value of the variable capacitor 35 and the slew rate of the I / O circuits 34a and 34b based on the set value output from the TM determination circuit 52. The control signal SC3 and the control signal SC3 for controlling the capacitance value of the variable capacitor 22 are output.

A configuration example of the variable capacitor 35 will be described.
As shown in FIG. 6, the variable capacitor 35 includes a plurality (three in the figure) of power switches 61a to 61c. The first terminals of the power switches 61a to 61c are connected to a power line 21a to which a high potential voltage VDD is supplied. The second terminal of the power switch 61a is connected to the first terminals of a plurality of (four in the figure) capacity cells 62a, and the second terminal of each capacity cell 62a is a power line 21b to which the low potential voltage VSS is supplied. It is connected to the. Similarly, the first terminal of a plurality of (four in the figure) capacity cells 62b is connected to the second terminal of the power switch 61b, and the low potential voltage VSS is supplied to the second terminal of each capacity cell 62b. It is connected to the power line 21b. The second terminal of the power switch 61c is connected to the first terminals of a plurality (four in the figure) of the capacity cells 62a, and the second terminal of each capacity cell 62c is a power source to which the low potential voltage VSS is supplied. It is connected to the line 21b. The number of capacity cells 62a to 62c connected to the power switches 61a to 61c may be different.

  The power switches 61a to 61c operate independently of each other based on the control signal SC1. For example, the control signal SC1 is a 3-bit signal (SC1a to SC1c) corresponding to the number of power switches included in the variable capacitor 35. The power switches 61a to 61c are turned on and off in response to the control signals SC1a to SC1c, respectively. Accordingly, the number of capacity cells corresponding to the turned on power switch are connected in parallel to each other and connected between the two power supply lines 21a and 21b. That is, the capacitance value between the two power supply lines 21a and 21b can be adjusted by changing the number of power switches.

Next, a configuration example of the variable capacitor 22 will be described.
As shown in FIG. 7A, the high potential voltage VDD is supplied to the power supply terminal 71a of the variable capacitor 22, and the low potential voltage VSS is supplied to the power supply terminal 71b. A control signal SC3 is supplied to a plurality (three in the figure) of control terminals 72a to 72c. For example, the control signal SC3 is a 3-bit signal. The number of bits of the control signal SC3 corresponds to the number of power switches included in the variable capacitor 35. Signals supplied to the terminals 72a to 72c are SC3a to SC3c, respectively. A power line 73a is connected to the power terminal 71a, and a power line 73b is connected to the power terminal 71b. First terminals of a plurality (three in the figure) of power switches 74a to 74c are connected to the power line 73a.

  A first terminal of a plurality of (four in the figure) capacity cells 75a is connected to the second terminal of the power switch 74a, and the second terminal of each capacity cell 75a is a power line 73b to which a low potential voltage VSS is supplied. It is connected to the. Similarly, the first terminal of a plurality of (four in the figure) capacity cells 75b is connected to the second terminal of the power switch 74b, and the low potential voltage VSS is supplied to the second terminal of each capacity cell 75b. It is connected to the power line 73b. The second terminal of the power switch 74c is connected to the first terminals of a plurality (four in the figure) of the capacity cells 75a, and the second terminal of each capacity cell 75c is supplied with a low potential voltage VSS. It is connected to the line 73b. The number of capacity cells 75a to 75c connected to each power switch 74a to 74c may be different.

  The plurality of control terminals 72a to 72c are connected to the input terminals of the buffer circuits 76a to 76c, respectively. The output signals of the buffer circuits 76a to 76c are supplied to the power switches 74a to 74c. Accordingly, the power switches 74a to 74c operate independently of each other based on the control signals SC3a to SC3c. The power switches 74a to 74c are turned on and off in response to the control signals SC3a to DC3c, respectively. Accordingly, the number of capacity cells corresponding to the power switches that are turned on are connected in parallel to each other and connected between the two power supply lines 73a and 73b. That is, the capacitance value between the two power lines 73a and 73b can be adjusted by changing the number of power switches.

  The variable capacitor 22 may be directly connected to the system device (die) 21 as shown in FIG. Such a configuration makes it possible to reduce the package size of the system device 21.

Next, a configuration example of the I / O circuit 34b will be described.
As shown in FIG. 8, the signal Sin output from the DLL circuit 42 shown in FIG. 3 is supplied to a plurality (four in the figure) of NAND circuits 81a to 81d. The signal Sin is supplied to a plurality of inverter circuits 82a to 82d. A control signal SC2 is supplied to each of the NAND circuits 81a to 81d. In this example, the control signal SC2 is a 4-bit signal corresponding to the configuration of the I / O circuit 34a. These signals are referred to as SC2a to SC2d. Control signals SC2a to SC2d are supplied to the NAND circuits 81a to 81d, respectively. Output signals of the inverter circuits 82a to 82d are supplied to AND circuits 83a to 83d. Control signals SC2a to SC2d are supplied to the AND circuits 83a to 83d, respectively.

  Output signals of NAND circuits 81a-81d are supplied to the gates of P-channel MOS transistors 84a-84d, respectively. Similarly, output signals of AND circuits 83a to 83d are supplied to gates of N channel MOS transistors 85a to 85d.

  The sources of the transistors 84 a to 84 d are connected to the power supply line 21 a to which the high potential voltage VDD is supplied, and the drains of the transistors 84 a to 84 d are connected to the output node 86. The output node 86 is connected to the drains of the transistors 85a to 85d, and the sources of the transistors 85a to 85d are connected to the power supply line 21b to which the low potential voltage VSS is supplied.

  In accordance with signal Sin, I / O circuit 34b configured as described above includes a P-channel MOS transistor between output node 86 and power supply line 21a, and an N channel between output node 86 and power supply line 21b. The MOS transistor is turned on and off in a complementary manner. The number of transistors that are turned on corresponds to the control signal SC2. The P-channel MOS transistor raises the potential of the output node 86, that is, the wiring 20d shown in FIG. 3, from the low potential voltage VSS level to the high potential voltage VDD level. The time taken to increase the potential, that is, the slew rate, corresponds to the amount of current flowing from the power supply line 21a to which the high potential voltage VDD is supplied toward the output node 86. That is, as the number of P-channel MOS transistors that are turned on increases, the amount of current flowing from the power supply line 21a toward the output node 86 increases, and the potential of the output node 86 (wiring 20d) increases faster, that is, the slew rate increases. Become. Conversely, the smaller the number of transistors that are simultaneously turned on, the lower the slew rate.

  As the slew rate is set higher, the level of the output signal changes in a shorter time. That is, since the current change becomes steep, noise generated in the power supply voltage increases. For this reason, from the viewpoint of noise generated in the power supply voltage, it is preferable to set the slew rate small. On the other hand, the signal output from the I / O circuit with a low slew rate has a longer period during which the level changes between the high potential voltage VDD level and the low potential voltage VSS level, that is, a transition period. The period during which the level is stabilized, that is, the effective period (effective window) is shortened. For this reason, it is preferable to set a large slew rate from the viewpoint of a timing margin for taking in a signal. Therefore, in the I / O circuit, it is preferable to set the slew rate so that the noise generated in the power supply voltage is small and the effective window is large.

Next, a configuration example of the training control circuit 51 will be described.
As shown in FIG. 9, when receiving an automatic adjustment execution command signal from a circuit in the system device 21, for example, the memory controller 32, the training command transmission circuit 91 first initializes the registers 92 to 94 and the TM determination circuit 52. The signal SIT is output.

  The register 92 stores an initial value for adjusting the slew rate of the I / O circuits 34a and 34b in response to the initialization signal SIT. The initial value stored in the register 92 is supplied to the I / O circuits 34a and 34b, and the I / O circuits 34a and 34b are set to operate at a slew rate corresponding to the initial value. The register 93 stores an initial value for adjusting the capacitance value of the variable capacitor 35 in the system device 21 in response to the initialization signal SIT. The initial value stored in the register 93 is supplied to the variable capacitor 35, and the variable capacitor 35 is set to a capacitance value corresponding to the initial value. The register 94 stores an initial value for adjusting the capacitance value of the variable capacitor 22 in the package 11 in response to the initialization signal SIT. The initial value stored in the register 94 is supplied to the variable capacitor 22, and the variable capacitor 22 is set to a capacitance value corresponding to the initial value. The TM determination circuit 52 stores an initial value in response to the initialization signal SIT.

  Next, the training command transmission circuit 91 outputs a process execution signal to the output control circuit 95, the capacity control circuits 96 and 97, and the training circuit 45 at predetermined timings. Each control circuit 95, 96, 97 is supplied with a counter end setting signal from a circuit in the system device 21, for example, the memory controller 32. The counter end setting signal is a signal for setting the number of times each control circuit 95 to 97 executes processing. That is, each of the control circuits 95 to 97 has a count function and counts up the count value every time one process is executed. Each control circuit 95 to 97 ends the processing when the count value becomes equal to the counter end setting signal.

  In response to the processing execution signal, the output control circuit 95 outputs the control signal SC2 whose set value has been changed to the I / O circuits 34a and 34b, and performs control to change the slew rate of the I / O circuits 34a and 34b. The signal SC2 is output. In response to the processing execution signal, the capacity control circuit 96 outputs the control signal SC1 whose setting value has been changed to the variable capacity 35, and changes the capacity value of the variable capacity 35. In response to the processing execution signal, the capacity control circuit 97 outputs the control signal SC3 whose setting value has been changed to the variable capacity 35, and changes the capacity value of the variable capacity 22. Each control circuit 95 to 97 outputs the set value to the register update circuit 98.

The training circuit 45 executes timing training for the memory 12 shown in FIG. 3 in response to the processing execution signal.
The training command transmission circuit 91 operates the control circuits 95 to 97 to sequentially change the slew rate of the I / O circuits 34a and 34b and the capacitance values of the variable capacitors 35 and 22. Further, the training command transmission circuit 91 operates the training circuit 45 so that the training circuit 45 acquires the maximum value and the minimum value set in the DLL circuit 44 in each setting, and the control circuits 95 to 97 and the training circuit. 45 is controlled.

The training circuit 45 outputs the acquired maximum value and minimum value to the TM determination circuit 52.
The TM determination circuit 52 determines a timing margin based on the maximum value and the minimum value input from the training circuit 45, and outputs an update signal SUP to the register update circuit 98 according to the determination result. Specifically, the TM determination circuit 52 calculates a timing margin based on the maximum value and the minimum value supplied from the training circuit 45. For example, the TM determination circuit 52 subtracts the minimum value from the maximum value to calculate the timing margin. Then, the TM determination circuit 52 compares the calculated timing margin with the held value. When the calculated timing margin is larger than the hold value, the TM determination circuit 52 holds a value equal to the timing margin and outputs the update signal SUP. On the other hand, the TM determination circuit 52 does not output the update signal SUP when the calculated timing margin is equal to or smaller than the hold value.

  The register update circuit 98 updates the values of the registers 92 to 94 in response to the update signal SUP. That is, the register update circuit 98 outputs the set values output from the control circuits 95 to 97 to the corresponding registers 92 to 94 in response to the update signal SUP, and the registers 92 to 94 are input. The set value is held as a new set value. As a result, the setting values of the control circuits 95 to 97 when the timing margin is maximized are held in the registers 92 to 94, respectively.

Next, a configuration example of the TM determination circuit 52 will be described.
As shown in FIG. 10, the TM determination circuit 52 includes a setting holding register 101, a result holding register 102, and a comparison circuit 103. The setting holding register 101 stores a setting value set in the DLL circuit 44 shown in FIG. The setting holding register 101 initializes the stored value in response to the initialization signal SIT supplied from the training control circuit 51.

  The result holding register 102 stores the maximum value and the minimum value supplied from the training circuit 45. Each time the training circuit 45 changes the set value of the DLL circuit 44 to the memory 12 shown in FIG. 3, the training circuit 45 performs test access to the memory 12 and stores the result. For example, the training circuit 45 determines whether or not the memory 12 has normally received the test data. When the test data is normally received, the training circuit 45 is “1”, and when the test data is not normally received. Stores “0”. The data DQ is a signal of a plurality of bits (for example, 8 bits). The training circuit 45 performs this process for each bit of the data DQ. An example of the result is shown in FIG. FIG. 11 shows the result of increasing the set value of each DLL circuit 44 toward the right side.

  Then, the training circuit 45 obtains the minimum value and the maximum value of the set values when the memory 12 normally receives all the bits DQ [0] to DQ [7]. For example, the training circuit 45 performs an AND operation (AND) on each bit DQ [0] to DQ [7]. In the calculation result, the training circuit 45 obtains the minimum setting value (minimum value) and the maximum setting value (maximum value) among the setting values whose result is “1”. Then, the training circuit 45 supplies these maximum and minimum values to the result holding register 102.

  As illustrated in FIG. 10, the setting holding register 101 outputs the held setting values (minimum value (Min) and maximum value (Max)) to the comparison circuit 103. Similarly, the result holding register 102 outputs the held result values (minimum value (Min), maximum value (Max)) to the comparison circuit 103.

  The comparison circuit 103 calculates the window width of the set value by subtracting the minimum value of the set value from the maximum value of the set value. Similarly, the comparison circuit 103 calculates the window width of the result value by subtracting the minimum value of the result value from the maximum value of the result value. Then, the comparison circuit 103 compares the window width of the set value with the window width of the result value.

  When the window width of the result value is larger than the window width of the setting value, the comparison circuit 103 outputs the maximum value and the minimum value of the result value to the setting holding register 101, and the window width of the result value is the window width of the setting value. The result value is not output in the following cases. The setting holding register 101 stores the value supplied from the comparison circuit 103, that is, the maximum value and the minimum value of the result value. Therefore, the setting holding register stores the maximum value and the minimum value of the result value when the window width is maximum.

  The comparison circuit 103 outputs an update signal SUP when the window width of the result value is larger than the window width of the set value. This update signal SUP is supplied to the register update circuit 98 shown in FIG. In response to the update signal SUP, the register update circuit 98 outputs the set values supplied from the control circuits 95 to 97 to the registers 92 to 94, respectively, and the registers 92 to 94 store the supplied set values. To do. Accordingly, each of the registers 92 to 94 stores a set value when the window width is maximum.

  The control circuit 36 shown in FIG. 3 sets each set value in a corresponding circuit, and ends the adjustment process. That is, the control circuit 36 sets the setting value held in the register 92 in the I / O circuits 34a and 34b. Similarly, the control circuit 36 sets the set values held in the registers 93 and 94 in the variable capacitors 35 and 22. Further, the control circuit 36 sets the delay amount of the DLL circuit 44 shown in FIG. 3 based on the maximum value and the minimum value held in the setting holding register 101 shown in FIG. For example, the control circuit 36 calculates an intermediate value (= (maximum value + minimum value) / 2) between the maximum value and the minimum value, and sets this intermediate value in each DLL circuit 44 as a delay value.

Next, the flow of processing related to the control circuit 36 in the above system will be described.
As shown in FIG. 12, first, an initial value of the variable capacitor 22 of the package (PKG) 20 shown in FIG. 3 is set (step 201). Next, an initial value of the variable capacitor 35 of the system device (DIE) 21 is set (step 202). Next, initial values of the I / O circuits 34a and 34b are set (step 203).

Next, timing training is executed by the training circuit 45 shown in FIG. 3 (step 204).
Next, the timing margin is determined (step 205). Based on the determination result, it is determined whether or not the set value of the DLL circuit 44 has been updated (step 206). When the set value is updated (determination: YES), each set value is held in the register (step 207). On the other hand, if the set value has not been updated (determination: NO), the next step 207 is skipped.

  Next, it is determined whether or not all output settings have been completed for the I / O circuits 34a and 34b (step 208). If the setting has not been completed (determination: NO), the setting for the I / O circuits 34a and 34b is changed (step 209), and the process proceeds to step 204. On the other hand, when the setting is completed (determination: YES), the process proceeds to step 210.

  Next, it is determined whether or not all the capacity settings have been completed for the variable capacity 35 in the system device 21 (DIE) (step 210). If the setting has not been completed (determination: NO), the setting for the variable capacitor 35 is changed (step 211), and the process proceeds to step 204. On the other hand, when the setting is completed (determination: YES), the process proceeds to step 212.

  Next, it is determined whether or not all the capacity settings for the variable capacity 22 in the package 20 have been completed (step 212). If the setting has not been completed (determination: NO), the setting for the variable capacitor 22 is changed (step 213), and the process proceeds to step 204. On the other hand, when the setting is completed (determination: YES), the process proceeds to step 214.

Then, each set value held in the register is finally set in the corresponding circuit (step 214), and the process is terminated.
Next, timing training processing will be described.

  As shown in FIG. 13, first, initial values for the DLL circuit 44 shown in FIG. 3 are set (step 221). Next, test access is made to the memory 12 shown in FIG. 3 (step 222), and the set value set in the DLL circuit 44 when the memory 12 is normally accessed is held (step 223).

  Next, it is determined whether or not all setting values for the DLL circuit 44 have been set (step 224). If the setting is not completed (determination: NO), the setting for the DLL circuit 44 is changed (step 225), and the process proceeds to step 222. On the other hand, when the setting is completed (determination: YES), the process proceeds to step 226.

  Next, among the setting values held in step 223, that is, among the setting values set in the DLL circuit 44 when the memory 12 is normally accessed, the maximum setting value (maximum value) and the minimum setting value (minimum value) are TM. The data is transmitted to the determination circuit 52 (step 226).

Next, based on the maximum value and the minimum value, for example, an intermediate value between the maximum value and the minimum value is set in the DLL circuit 44 (step 227), and the process ends.
Next, the test access process will be described.

  As shown in FIG. 15, first, initial values (for example, “0”) are written in all the memory cells of the memory 12 shown in FIG. 3 (step 231). At this time, in order to reliably write the initial value, writing is performed over a plurality of cycles.

  Next, a first expected value (for example, “1”) different from the initial value is written in the memory 12 (step 232). At this time, an expected value is written in the first cycle in order to test data writing at the maximum speed operation. Next, data is read from the address where the first expected value is written (step 233), and the read data (read data) is compared with the expected value (step 234). If the read data does not match the first expected value (determination: NO), a value (eg, “0”) indicating that the result storage area (eg, register) could not be accessed normally is stored (step 0 235), the process is terminated. On the other hand, if the read data matches the first expected value (determination: YES), a value (eg, “1”) indicating that the result has been successfully accessed is stored (step 236).

  Next, similarly to step 232, a second expected value (for example, “0”) different from the first expected value is written to the address where the first expected value is written (step 237). Next, data is read from the address where the second expected value is written (step 238), and the read data (read data) is compared with the expected value (step 239). If the read data does not match the first expected value (determination: NO), a value (eg, “0”) indicating that the result storage area (eg, register) could not be accessed normally is stored (step 0 240), the process is terminated. On the other hand, if the read data matches the first expected value (determination: YES), a value (for example, “1”) indicating that the result has been successfully accessed is stored (step 241), and the process ends. .

  Therefore, when data writing with the value “1” and data writing with the value “0” are normally performed in the memory 12, the first result value (for example, “1”) is stored as a result. The On the other hand, if at least one of the data write with the value “1” and the data write with the value “0” is not normally performed, a second result value different from the first result value (for example, “ 0 ") is stored as a result.

Next, timing margin determination processing will be described.
As shown in FIG. 14, first, the window width of the setting value calculated from the maximum value and the minimum value of the held setting value, and the minimum value and the minimum value of the setting value when the memory 12 shown in FIG. The window width of the result value calculated by the above is compared, and it is determined whether or not the window width of the result value is larger than the window width of the set value (step 251). If the window width of the result value is equal to or smaller than the window width of the set value (determination: NO), the process ends. On the other hand, when the window width of the result value is larger than the window width of the set value (determination: YES), the holding value is updated with the maximum value and the minimum value of the result value (step 252), and the process is terminated.

Next, an example of changing each set value will be described.
Now, assume that the set values for the I / O circuits 34a and 34b shown in FIG. 3 are “0” to “2”. Similarly, set values for the variable capacitors 35 and 22 are “0” to “15”.

  As shown in FIG. 16, first, initial values for the setting elements (I / O circuits 34a and 34b, variable capacitors 35 and 22) are set to “0”, “0”, and “0”. At this time, the window width of the result value calculated by the timing margin determination is “10”.

  Next, the set value of the variable capacitor 22 of the package 20 (PKG) is changed from “0” to “1”. At this time, the window width of the result value calculated by the timing margin determination is “15”. Therefore, this window width “15” is stored.

  Similarly, the set value of the variable capacitor 22 of the package 20 (PKG) is changed by “1” to “15”. Then, the determination result of the timing margin at each setting stage is compared with the hold value, and the hold value is updated.

  When the timing margin at the maximum setting value “15” is determined for the variable capacitor 22, the setting value of the variable capacitor 35 of the system device 21 (DIE) is changed to “1”, and the variable of the package 20 (PKG) is changed. The setting value of the capacity 22 is changed by changing “1” from “0” to “15”.

  When the timing margin at the maximum setting value “15” is determined for the variable capacitor 35, the setting value for the I / O circuits 34a and 34b is changed from “0” to “1”. Then, similarly to the above, the set values for the variable capacitor 22 and the variable capacitor 35 are changed.

Similarly, all of the setting values for each setting element are set.
As shown in FIG. 16, “40” is the maximum value of the window width of the result value in the timing margin determination. Accordingly, the setting values “0”, “4”, and “7” at this time are held in the registers 92 to 94 shown in FIG. Thus, by changing each set value by “1”, the optimum set value can be obtained with certainty.

Next, another example of changing each set value will be described.
The setting values for the I / O circuits 34a and 34b shown in FIG. 3 are “0” to “2”. Similarly, set values for the variable capacitors 35 and 22 are “0” to “15”.

  First, as shown in FIG. 17A, the set values for the variable capacitors 35 and 22 are changed every predetermined step (for example, 4 steps). That is, the set value is changed in the order of “0”, “4”, “8”, “12”. When changed in this way, the maximum value of the window width is “36”. The set values at this time are “0”, “4”, and “8”.

A range including each set value obtained in the first stage is set, and a set value within the range is set in each setting element.
From the result shown in FIG. 17A, the set value for the I / O circuits 34a and 34b is determined to be “0”. Then, the set value for the variable capacitor 35 is set to a range “1” to “7” centering on “4”. Similarly, the set value for the variable capacitor 22 is set to a range “5” to “11” centering on “8”.

Then, as shown in FIG. 17B, the set values for the variable capacitors 35 and 22 are changed in the minimum step (“1”).
In this way, by changing the step of changing the set value, the number of times that the timing training is performed becomes smaller than when the set value is changed by “1”, and the time required for the adjustment process can be shortened. it can.

As described above, according to the present embodiment, the following effects can be obtained.
(1) The chip (die) on which the core circuit 31 that accesses the memory 12 is mounted includes an I / O circuit 34a that outputs a data strobe signal DQS to the memory 12 and an I / O circuit 34b that outputs data DQ. Is formed. Each I / O circuit 34a, 34b is connected between a power supply line 21a for supplying a high potential voltage VDD and a power supply line 21b for supplying a low potential voltage VSS. A variable capacitor 35 is connected between the power supply lines 21a and 21b, and the variable capacitor 35 suppresses voltage fluctuations of the high potential voltage VDD and the low potential voltage VSS.

  The I / F circuit 33 that outputs a signal to each of the I / O circuits 34a and 34b includes a DLL circuit 42 and 44 for adjusting the phase difference between the data strobe signal DQS and the data DQ, and setting of both DLL circuits 42 and 44. A training circuit 45 that controls the value (delay time) and adjusts the timing at which the data strobe signal DQS and the data DQ reach the memory 12 is provided.

  The control circuit 36 formed in the system device 21 controls the capacitance value of the variable capacitor 35 and causes the training circuit 45 to execute timing training. The training circuit 45 outputs the maximum value and the minimum value of the set values with which the memory 12 can write normal data based on the data DQ. The control circuit 36 calculates the window width of the data DQ based on the maximum value and the minimum value, and sets a capacitance value corresponding to a larger window width in the variable capacitor 35.

  As a result, the variable capacitor 35 reduces noise generated in the power supply voltage due to the operations of the I / O circuit 34a that outputs the data strobe signal DQS and the I / O circuit 34b that outputs the data DQ, and the window width of the data DQ. And a decrease in the timing margin for taking in the data DQ based on the data strobe signal DQS can be suppressed.

  (2) The control circuit 36 controls the drive capability of the I / O circuit 34a that outputs the data strobe signal DQS and the I / O circuit 34b that outputs the data DQ. The drive capability of each I / O circuit 34a, 34b corresponds to the slew rate of the signal output from each I / O circuit 34a, 34b. The larger the slew rate, the larger the current change and the greater the noise generated in the power supply voltage. Therefore, by reducing the data DQ window width and reducing the data DQ slew rate, noise generated in the power supply voltage can be reduced, and a decrease in timing margin can be suppressed.

  (3) The variable capacitor 22 is connected between the power supply lines 20 a and 20 b of the package 20 on which the system device 21 is mounted, and the control circuit 36 is similar to the variable capacitor 35 of the system device 21. A capacity value of 22 is set. Accordingly, even when the shape or the like of the package 20 is changed, the capacitance value of the variable capacitor 22 is set in accordance with the change, so that the package can be easily changed. In addition, the design time can be shortened because the effort for redesigning the power supply design and re-execution of the power supply simulation is reduced when the package is changed.

In addition, you may implement each said embodiment in the following aspects.
The variable capacity 22 of the package may be omitted.
The adjustment process for the variable capacity 22 of the package may be omitted.

  FIG. 1 shows three semiconductor devices 11 to 13, but two or four or more semiconductor devices may be mounted. 1 shows one decoupling capacitor 14, a plurality of decoupling capacitors or one or a plurality of modules including a plurality of decoupling capacitors may be mounted. Further, other members such as resistors and connectors may be mounted on the substrate 10.

  The package of the semiconductor devices 11 to 13 illustrated in FIG. 1 is an example, and the shape of the package may be changed. For example, in the semiconductor device 11, a bonding wire may be used for electrical connection between the package 20 and the substrate 10. Further, the semiconductor device 13 may be a chip size package (CSP), for example.

  The intermediate value between the maximum value and the minimum value obtained by timing training is set for the DLL circuit 44 shown in FIG. The value set in each DLL circuit 44 may be changed as appropriate. For example, you may set based on the maximum value and minimum value obtained by timing training, and a predetermined value (for example, setup time, hold time). For example, a value obtained by adding the setup time to the minimum value may be used as the set value. A value obtained by subtracting the hold time from the maximum value may be set as the set value. An intermediate value between a value obtained by adding the setup time to the minimum value and a value obtained by subtracting the hold time from the maximum value may be set as the set value. In addition, a ratio for dividing a range of values (window width) between the minimum value and the maximum value may be stored, and the value of the division point may be set as a setting value.

  -You may change the structure of each circuit suitably. For example, the training circuit 45 illustrated in FIG. 3 may be included in the control circuit 36.

21a, 21b Power line 22 Variable capacitance 34a, 34b I / O circuit (output circuit)
35 variable capacity 36 control circuit 42, 44 delay locked loop circuit (DLL circuit)
45 Training circuit 51 Training control circuit 52 Timing margin judgment circuit VDD High potential voltage VSS Low potential voltage

Claims (8)

A first output circuit connected between the first power supply line and the second power supply line and outputting a first signal;
A second output circuit connected between the first power supply line and the second power supply line and outputting a second signal;
A variable capacitor connected between the first power line and the second power line;
A delay circuit for adjusting a phase difference between the first signal and the second signal;
The capacitance value of the variable capacitor is controlled, and it is determined whether data based on the first signal can be written to the memory for each of a plurality of phase differences in the first signal and the second signal adjusted by the delay circuit. A control circuit for measuring a window width of the first signal and setting a capacitance value corresponding to a larger window width in the variable capacitor;
A timing control circuit comprising:   2. The timing according to claim 1, wherein the control circuit controls a driving capability of the first output circuit and sets a driving capability corresponding to a larger window width in the first output circuit. 3. Control circuit.   The control circuit changes a setting value for the delay circuit to adjust the phase difference, determines whether the memory can write the data for each setting value, and determines that the data can be written to the memory The timing control circuit according to claim 1, further comprising a training circuit that obtains a maximum value among a plurality of set values as a minimum value.   The timing control circuit according to claim 3, wherein the training circuit determines whether or not data can be written to the memory for each bit of the data, and measures the window width based on all the bits of the data. The control circuit includes:
The maximum value and the minimum value of the setting value obtained by the training circuit are held in the first register, and the maximum value and the minimum value obtained by the training circuit based on the setting value changed for the delay circuit. Value is held in the second register, the first window width is calculated from the maximum value and the minimum value held in the first register, and based on the maximum value and the minimum value held in the second register A second window width is calculated, the first window width is compared with the second window width, and when the second window width is larger than the first window width, the second register 5. The timing control circuit according to claim 3, further comprising a timing margin determination circuit that holds the maximum value and the minimum value held in the first register in the first register. The variable capacity is
A first variable capacitor formed on a chip on which a circuit for accessing the memory is mounted;
A second variable capacitor mounted on a package including a power line for supplying an operating voltage to the chip,
The timing control circuit according to claim 1, wherein the control circuit controls a capacitance value of the first variable capacitor and a capacitance value of the second variable capacitor. Controlling the capacitance value of the variable capacitor connected between the first power supply line and the second power supply line;
A first signal output from a first output circuit connected between the first power supply line and the second power supply line, and a second output connected between the first power supply line and the second power supply line Adjust the phase difference with the second signal output from the circuit,
It is determined whether or not data based on the first signal can be written in a memory for each of a plurality of phase differences in the first signal and the second signal to be adjusted, and the window width of the first signal is measured. A capacity value corresponding to the window width is set to the variable capacity;
The timing control method characterized by the above-mentioned. A system device for outputting data and a data strobe signal;
A memory for capturing the data based on the data strobe signal;
Including
The system device includes:
A first output circuit connected between the first power supply line and the second power supply line and outputting a first signal;
A second output circuit connected between the first power supply line and the second power supply line and outputting a second signal;
A variable capacitor connected between the first power line and the second power line;
A delay circuit for adjusting a phase difference between the first signal and the second signal;
The capacitance value of the variable capacitor is controlled, and it is determined whether data based on the first signal can be written to the memory for each of a plurality of phase differences in the first signal and the second signal adjusted by the delay circuit. A control circuit for measuring a window width of the first signal and setting a capacitance value corresponding to a larger window width in the variable capacitor;
Having a system.

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