JP2012169551A - Trench-gate type semiconductor device - Google Patents

Abstract

An object of the present invention is to provide a trench gate type semiconductor device capable of improving avalanche resistance and main breakdown voltage.
A trench gate type semiconductor device according to the present invention comprises a substrate, a first conductivity type epitaxial growth layer on the substrate, a second conductivity type diffusion layer on the epitaxial growth layer, and the diffusion layer. A trench gate that penetrates and has a tip reaching the epitaxial growth layer, and a low carrier concentration portion of the first conductivity type formed in the epitaxial growth layer so as to be in contact with the tip of the trench gate and having a carrier concentration lower than that of the epitaxial growth layer And.
[Selection] Figure 1

Description

  The present invention relates to a trench gate type semiconductor device in which a trench gate extends to an epitaxial growth layer.

  Patent Document 1 discloses a semiconductor device having a trench gate. In this semiconductor device, the depth of the trench gate is reduced to reduce the gate capacitance.

JP 2009-105268 A JP 2010-135526 A JP 2006-080177 A JP-A-2005-252204 JP 10-022462 A

  The semiconductor device disclosed in Patent Document 1 cannot improve the avalanche resistance because the depth of the trench gate is reduced. Further, when the trench gate is deepened to improve the avalanche resistance of the semiconductor device, the main breakdown voltage is deteriorated.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a trench gate type semiconductor device capable of improving the avalanche resistance and the main breakdown voltage.

  A trench gate type semiconductor device according to the invention of the present application includes a substrate, a first conductivity type epitaxial growth layer on the substrate, a second conductivity type diffusion layer on the epitaxial growth layer, and the diffusion layer. A trench gate reaching the epitaxial growth layer, and a low carrier concentration portion of a first conductivity type formed in the epitaxial growth layer so as to be in contact with the tip of the trench gate and having a carrier concentration lower than that of the epitaxial growth layer. It is characterized by that.

  According to the present invention, since the trench gate is formed deeply and the low carrier concentration portion is formed at the tip of the trench gate, the avalanche resistance and main breakdown voltage of the trench gate type semiconductor device can be improved.

1 is a cross-sectional view of a trench gate type semiconductor device according to a first embodiment of the present invention. It is sectional drawing of the outermost periphery part of the trench gate type semiconductor device which concerns on Embodiment 1 of this invention, and its vicinity. It is a figure which shows how the depletion layer extends just under a trench gate at the time of turn-off of a trench gate type semiconductor device. It is sectional drawing of the trench gate type semiconductor device which concerns on Embodiment 2 of this invention.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of a trench gate type semiconductor device according to Embodiment 1 of the present invention. The trench gate type semiconductor device 10 includes a substrate 12. An n-type (hereinafter referred to as first conductivity type) epitaxial growth layer 14 is formed on the substrate 12. The layer thickness (indicated by L in FIG. 1) of the epitaxial growth layer 14 is 10 μm. Note that the value of L varies depending on the breakdown voltage of the trench gate type semiconductor device. In the first embodiment of the present invention, the value of L is set to 10 μm in order to set the breakdown voltage of the trench gate type semiconductor device 10 to 75V.

  A p-type (hereinafter referred to as second conductivity type) diffusion layer 16 is formed on the epitaxial growth layer 14. Then, a trench gate 18 is formed so as to penetrate the diffusion layer 16 and the tip reaches the epitaxial growth layer 14. The tip of the trench gate 18 is on the 3.5 μm epitaxial growth layer 14 side from the interface between the epitaxial growth layer 14 and the diffusion layer 16. The length of the trench gate extending from the interface between the epitaxial growth layer 14 and the diffusion layer 16 toward the epitaxial growth layer 14 may be referred to as “the depth of the trench gate”.

A first carrier type low carrier concentration portion 20 having a carrier concentration lower than the carrier concentration of the epitaxial growth layer 14 (referred to as the carrier concentration of majority carriers, hereinafter the same) is formed in contact with the tip of the trench gate 18. The low carrier concentration portion 20 is formed in the epitaxial growth layer 14. The low carrier concentration portion 20 is a first conductivity type portion in which the carrier concentration is reduced to 1.0 × 10 ¹¹ cm ⁻³ by counterdose boron, which is an ion having a conductivity type opposite to that of the epitaxial growth layer 14. . The counter dose of boron is performed by ion implantation using a mask used in the process of forming the trench gate 18. In the ion implantation, boron is implanted while controlling the dose so that the low carrier concentration portion 20 can maintain the n-type (first conductivity type).

  A source 22 of the first conductivity type is formed in contact with the trench gate 18. A diffusion layer 24 of the second conductivity type is formed between the source 22 and another source 22. Further, a gate wiring 26 is formed in contact with the trench gate 18. Further, a source electrode 30 is formed in contact with the source 22. The source electrode 30 is in contact with the gate wiring 26 through the interlayer film 28. The structure on the front surface side of the substrate 12 has been described so far, but the collector electrode 32 is formed on the back surface of the substrate 12.

  FIG. 2 is a cross-sectional view of the outermost periphery of the trench gate type semiconductor device 10 according to the first embodiment of the present invention and its vicinity. The trench gate type semiconductor device 10 includes a second conductivity type diffusion layer 40 on the outermost periphery. The diffusion layer 40 is formed so as to be in contact with the epitaxial growth layer 14 and is provided in order to improve the avalanche resistance when the trench gate type semiconductor device 10 is turned off.

  According to the trench gate type semiconductor device 10 according to the first embodiment of the present invention, the tip of the trench gate 18 is on the 3.5 μm epitaxial growth layer 14 side from the interface between the epitaxial growth layer 14 and the diffusion layer 16. That is, the trench gate 18 is formed deep. Therefore, electric field concentration occurs not only in the diffusion layer 40 but also in the trench gate 18 when the trench gate type semiconductor device is turned off. Thus, the energy at turn-off is distributed throughout the chip.

  Here, how the depletion layer extends just below the trench gate 18 at the time of turn-off will be described with reference to FIG. FIG. 3 is a diagram illustrating how the depletion layer extends just below the trench gate 18 when the trench gate type semiconductor device is turned off. Since the equipotential line 50 extends along the shape of the trench gate 18 at the time of turn-off, the depletion layer reaches the back surface of the substrate 12 quickly due to the deep depth of the trench gate 18. Accordingly, it is possible to prevent excessive electric field concentration from occurring in the diffusion layer 40 at the time of turn-off and improve the avalanche resistance.

  Here, when the depth of the trench gate 18 is increased, the distance between the tip of the trench gate 18 and the substrate 12 is shortened, and there is a concern that the main breakdown voltage of the trench gate type semiconductor device 10 is lowered. However, according to the trench gate type semiconductor device 10 according to the first embodiment of the present invention, the low carrier concentration portion 20 is formed at the tip of the trench gate 18 and the specific resistance immediately below the tip of the trench gate 18 becomes high. As a result, the thickness of the depletion layer immediately below the tip of the trench gate 18 increases, so that the main breakdown voltage can be improved.

  Various modifications can be made to the trench gate type semiconductor device 10 according to the first embodiment of the present invention. For example, although the depth of the trench gate 18 is 3.5 μm, as long as the tip of the trench gate 18 reaches the epitaxial growth layer 14, the avalanche resistance can be improved by burdening the trench gate 18 with electric field concentration at the time of turn-off. Therefore, the depth of the trench gate 18 is not limited to 3.5 μm. In order to sufficiently improve the avalanche resistance, the depth of the trench gate 18 is preferably 3.5 μm or more.

  The layer thickness of the epitaxial growth layer 14 is not limited to 10 μm. The optimum layer thickness (L) of the epitaxial growth layer varies depending on the breakdown voltage class of the trench gate type semiconductor device. For example, when the withstand voltage is 100V class, L is preferably 11.5 μm, and when the withstand voltage is 150 V class, L is preferably 16 μm.

Although the carrier concentration of the low carrier concentration portion 20 is 1.0 × 10 ¹¹ cm ⁻³ , the present invention is not limited to this. In order to improve the main breakdown voltage of the trench gate type semiconductor device, it is necessary to form a portion with a high specific resistance between the tip of the trench gate and the substrate, so the carrier concentration of the low carrier concentration portion is 1.0 × 10 ¹¹ to A value of 1.0 × 10 ¹⁴ cm ⁻³ is desirable.

  In the trench gate type semiconductor device 10 according to the first embodiment of the present invention, the depth of the trench gate is increased in order to improve the avalanche resistance, but the present invention is not limited to this. That is, since the avalanche resistance can be improved by reducing the distance between the tip of the trench gate and the substrate, the same effect as increasing the depth of the trench gate can be obtained even if the thickness of the epitaxial growth layer is reduced.

  In Embodiment 1 of the present invention, the first conductivity type is n-type and the second conductivity type is p-type, but the conductivity type may be reversed. Further, the trench gate type semiconductor device 10 may be formed of a wide band gap semiconductor having a larger band gap than silicon. Since the wide band gap semiconductor is excellent in voltage resistance, the trench gate type semiconductor device can be downsized. Examples of the wide band gap semiconductor include silicon carbide, a gallium nitride-based material, and diamond.

Embodiment 2. FIG.
FIG. 4 is a cross-sectional view of the trench gate type semiconductor device according to the second embodiment of the present invention. The trench gate type semiconductor device according to the second embodiment of the present invention includes a cobalt silicide film (CoSi film) 60 on the trench gate 18 made of polysilicon. The cobalt silicide film 60 is formed by reacting cobalt formed by sputtering with the trench gate 18. In the trench gate type semiconductor device of FIG. 4, the same reference numerals are given to the portions common to the trench gate type semiconductor device of the first embodiment of the present invention, and the description thereof is omitted.

  According to the trench gate type semiconductor device according to the second embodiment of the present invention, the gate resistance is lowered by the cobalt silicide film 60 while obtaining the effect of the trench gate type semiconductor device according to the first embodiment of the present invention. The on-resistance can be reduced.

  10 trench gate type semiconductor device, 12 substrate, 14 epitaxial growth layer, 16 diffusion layer, 18 trench gate, 20 low carrier concentration part

Claims (6)

A substrate,
An epitaxial growth layer of a first conductivity type on the substrate;
A second conductivity type diffusion layer on the epitaxial growth layer;
A trench gate penetrating the diffusion layer and having a tip reaching the epitaxial growth layer;
A trench gate type semiconductor comprising: a first carrier type low carrier concentration portion formed in the epitaxial growth layer so as to be in contact with a front end of the trench gate and having a carrier concentration lower than that of the epitaxial growth layer. apparatus.   2. The trench gate type semiconductor device according to claim 1, wherein a tip of the trench gate is located on the epitaxial growth layer side by 3.5 μm or more from an interface between the epitaxial growth layer and the diffusion layer. 3. The trench gate type semiconductor device according to claim 1, wherein a carrier concentration of the low carrier concentration portion is a value of 1.0 × 10 ^{11 to} 1.0 × 10 ¹⁴ cm ^−3. .   The trench gate type semiconductor device according to claim 1, further comprising a cobalt silicide film formed on the trench gate.   The trench gate type semiconductor device according to any one of claims 1 to 4, wherein the trench gate type semiconductor device is formed of a wide band gap semiconductor.   6. The trench gate type semiconductor device according to claim 5, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

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