JP2012169027A - Nonvolatile memory device - Google Patents

Abstract

Provided is a non-volatile memory device capable of preventing a drop in reliability due to a decrease in a read margin by providing a drive signal having a constant rising slope to a memory cell array.
A nonvolatile memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells stacked in a direction orthogonal to a substrate, a row selection circuit connected to the memory cell array through word lines, A voltage generation circuit for generating a voltage provided to the word line, and the voltage generation circuit generates the voltage in a stepwise manner up to a target voltage level. The nonvolatile memory device according to the embodiment of the present invention can provide a drive signal having a constant rising slope to the memory cell array. Therefore, a drop in reliability due to a decrease in read margin can be prevented.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device.

  Semiconductor memory devices use semiconductors such as silicon (Si), germanium (Ge), gallium arsenide, indium phosphide (InP), and the like. This is a storage device embodied. Semiconductor memory devices are broadly classified into volatile memory devices and non-volatile memory devices.

  A volatile memory device is a memory device in which stored data is lost when power supply is cut off. Volatile memory devices include SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous DRAM), and the like. A non-volatile memory device is a memory device that maintains stored data even when power supply is interrupted. Non-volatile memory devices include ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), Flash Memory Device, RAM (PRAM), PRAM (PRAM) RAM), RRAM (registered trademark) (Resistive RAM), FRAM (registered trademark) (Ferroelectric RAM), and the like. Flash memory devices are roughly classified into a NOR type and a NAND type.

  Recently, a semiconductor memory device having a three-dimensional array structure has been studied in order to improve the degree of integration of the semiconductor memory device.

Japanese Patent Publication No. 2010-00102755

  An object of the present invention is to provide a non-volatile memory device that provides a drive signal having a constant rising slope to a memory cell array and a memory system including the same.

  A nonvolatile memory device according to an embodiment of the present invention provides a memory cell array including a plurality of memory cells stacked in a direction orthogonal to a substrate, a row selection circuit connected to the memory cell array through a word line, and a word line. A voltage generating circuit for generating a voltage to be generated, the voltage generating circuit generating the voltage in a stepwise manner up to a target voltage level.

  In one embodiment, the voltage generating circuit generates a voltage signal that increases stepwise up to a pass voltage level during a program operation.

  In one embodiment, the voltage generating circuit generates a first voltage signal that increases stepwise up to a program voltage level and a second voltage signal that increases stepwise up to a pass voltage level. A voltage generator.

  In one embodiment, the row selection circuit provides the second voltage signal as a driving signal to a non-selected word line among the word lines, and the driving signals provided to the non-selected word lines are the same. Has an ascending slope.

  As an embodiment, the voltage generation circuit generates a voltage signal that increases stepwise to a non-selected read voltage level during a read operation.

  As an embodiment, the voltage generation circuit generates a first voltage signal that generates a first voltage signal that increases stepwise to a selected read voltage level, and a second voltage signal that increases stepwise to an unselected read voltage level. A second voltage generator.

  In one embodiment, the row selection circuit provides the second voltage signal as a driving signal to a non-selected word line among the word lines, and the driving signals provided to the non-selected word lines are the same. Has an ascending slope.

  In one embodiment, the voltage generating circuit generates a first voltage signal that increases stepwise up to a program voltage level and a second voltage signal that increases stepwise up to a pass voltage level. A voltage generator; a third voltage generator for generating a third voltage signal that increases stepwise to a selected read voltage level; and a fourth voltage for generating a fourth voltage signal that increases stepwise to an unselected read voltage level. And a generator.

  The embodiment further includes ramping logic for controlling the voltage generating circuit to have different ramping step sizes depending on a target voltage level of the voltage.

  As an embodiment, memory cells on a plane parallel to the substrate share the same word line.

  The nonvolatile memory device according to the embodiment of the present invention can provide a driving signal having a certain rising slope to the memory cell array. Therefore, a drop in reliability due to a decrease in read margin can be prevented.

1 is a block diagram illustrating a non-volatile memory device according to an embodiment of the present invention. FIG. 2 is a block diagram showing the memory cell array of FIG. 1. FIG. 3 is a perspective view showing one first embodiment in the memory block of FIG. 2. FIG. 4 is a cross-sectional view taken along line I-I ′ of the memory block of FIG. 3. FIG. 5 is a cross-sectional view illustrating the transistor structure of FIG. 4. FIG. 6 is a circuit diagram illustrating an equivalent circuit according to the first embodiment of the memory block described with reference to FIGS. 3 to 5; 6 is a diagram illustrating a rising slope of a drive signal in a general case. FIG. 2 is a block diagram illustrating the high voltage generation circuit and the ramping logic of FIG. 1 in more detail. 9 is a diagram illustrating a first voltage signal generated by the first voltage generator of FIG. 8. 10 is a diagram illustrating a second voltage signal generated by the second voltage generator of FIG. 8. FIG. 2 is a block diagram showing the row selection circuit of FIG. 1 in more detail. 12 is a diagram for explaining the driving block of FIG. 11 in more detail. 2 is a diagram illustrating a rising slope of a driving signal when a voltage signal generated by the high voltage generating circuit of FIG. 1 is provided as a driving signal to a word line. 2 is a diagram illustrating a rising slope of a driving signal when a voltage signal generated by the high voltage generating circuit of FIG. 1 is provided as a driving signal to a word line. FIG. 6 is a block diagram illustrating a nonvolatile memory device according to another embodiment of the present invention. 6 is a diagram for explaining readout disturbance due to drive signals having different rising slopes. 6 is a diagram for explaining readout disturbance due to drive signals having different rising slopes. 6 is a diagram for explaining readout disturbance due to drive signals having different rising slopes. FIG. 2 is a block diagram illustrating an embodiment of the high voltage generation circuit and ramping logic of FIG. 1. FIG. 3 is a block diagram illustrating another embodiment of the high voltage generation circuit and ramping logic of FIG. 1. FIG. 6 is a circuit diagram illustrating an equivalent circuit BLKi_2 according to the second embodiment of the memory block BLKi described with reference to FIGS. 3 to 5; FIG. 6 is a circuit diagram illustrating an equivalent circuit according to a third embodiment of the memory block described with reference to FIGS. 3 to 5; FIG. 6 is a circuit diagram illustrating an equivalent circuit according to a fourth embodiment of the memory block described with reference to FIGS. 3 to 5; FIG. 6 is a circuit diagram illustrating an equivalent circuit according to a fifth embodiment of the memory block described with reference to FIGS. 3 to 5; FIG. 3 is a perspective view showing one second embodiment in the memory block of FIG. 2. FIG. 26 is a perspective view showing a modification of the memory block of FIG. 25. FIG. 4 is a perspective view showing one third embodiment in the memory block of FIG. 3. FIG. 28 is a cross-sectional view taken along line III-III ′ of the memory block of FIG. 27. FIG. 28 is a perspective view showing a modification of the memory block of FIG. 27. FIG. 30 is a cross-sectional view taken along line IV-IV ′ of the memory block of FIG. 29. FIG. 4 is a perspective view showing one fourth embodiment in the memory block of FIG. 3. FIG. 32 is a cross-sectional view taken along line V-V ′ of the memory block of FIG. 31. FIG. 32 is a perspective view showing a modification of the memory block of FIG. 31. FIG. 34 is a cross-sectional view taken along line VI-VI ′ of the memory block of FIG. 33. FIG. 6 is a perspective view showing one fifth embodiment in the memory block of FIG. 2. FIG. 36 is a cross-sectional view taken along line VII-VII ′ of the memory block of FIG. 35. FIG. 15 is a block diagram illustrating a memory system including the nonvolatile memory device of FIG. 1 or FIG. 14. FIG. 38 is a block diagram illustrating an application example of the memory system of FIG. 37. FIG. 39 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 38.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily implement the technical idea of the present invention. I will explain. For convenience of explanation, the same components are referred to using the same reference numerals. Similar components are cited using similar reference numbers.

  A nonvolatile memory device including a memory block having a three-dimensional structure may have different rising slopes of driving signals provided to word lines depending on process factors. Such a difference in the rising slope may cause a read fail due to a decrease in the read margin. The non-volatile memory device according to an embodiment of the present invention maintains a rising slope of a driving signal using a ramping technique. Thus, read margin reduction can be minimized. Hereinafter, for convenience of explanation, embodiments of the present invention will be described with a focus on program operations. However, the technical idea of the present invention can also be applied to a read operation and an erase operation.

  FIG. 1 is a block diagram illustrating a non-volatile memory device according to an embodiment of the present invention. Referring to FIG. 1, the nonvolatile memory device 100 includes a memory cell array 110, a high voltage generation circuit 120, a row selection circuit 130, a read / write circuit 140, a data input / output circuit 150, a control logic 160, and a ramping logic 170. .

  The memory cell array 110 is connected to the row selection circuit 130 through a plurality of word lines WL, and is connected to the read / write circuit 140 through a bit line BL. The memory cell array 110 includes memory blocks having a three-dimensional structure, and each memory block includes a plurality of memory cells. Illustratively, each memory block of the memory cell array 110 is composed of a plurality of memory cells that can store one or more bits per cell.

  The high voltage generation circuit 120 generates the first voltage signal VS_1 and the second voltage signal VS_2 in response to the control of the ramping logic 170. Here, the first voltage signal VS_1 is a voltage signal whose target voltage is a program voltage Vpgm, and the second voltage signal VS_2 is a voltage signal whose target voltage is a pass voltage.

  During the program operation, the high voltage generation circuit 120 increases the voltage level of the first voltage signal VS_1 to the program voltage Vpgm in a constant ramping step in response to the control of the ramping logic 170. The first voltage signal VS_1 is provided to the selected word line through the row selection circuit 130. That is, the selected word line is provided with the first voltage signal VS_1 that gradually increases to the program voltage Vpgm.

  Similarly, in response to the control of the ramping logic 170, the high voltage generation circuit 120 increases the voltage level of the second voltage signal VS_2 to the pass voltage Vpass in a certain ramping step unit. The second voltage signal VS_2 is provided to the selected word line through the row selection circuit 130.

  The row selection circuit 130 receives the first voltage signal VS_1 and the second voltage signal VS_2 from the high voltage generation circuit 120. During a program operation, the row selection circuit 130 provides a first voltage signal VS_1 to a selected word line and a second voltage signal VS_2 to a non-selected word line. The row selection circuit 130 includes a word line driver 131 and a row decoder 133.

  The word line driver 131 receives the first voltage signal VS_1 and the second voltage signal VS_2 from the high voltage generation circuit 120. The word line driver 131 provides the first voltage signal VS_1 or the second voltage signal VS_2 to each signal line SL in response to some addresses RAi in the row address RA.

  For example, during the program operation, the word line driver 131 provides the first voltage signal VS_1 as the drive signal DS to the signal line corresponding to the selected word line. The word line driver 131 provides the second voltage signal VS_2 as the drive signal DS to the signal line corresponding to the non-selected word line.

  The row decoder 133 receives the drive signal DS from the word line driver 131. The row decoder 133 selects the word line WL to which the driving signal DS is provided in response to the remaining address RAj among the row addresses RA.

  For example, the address RAj provided to the row decoder 133 may be an address for selecting a memory block. In this case, the row decoder 133 selects a memory block in response to the address RAj, and transmits the drive signal DS to each word line of the selected memory block. Accordingly, the first voltage signal VS_1 is provided as the driving signal DS to the selected word line, and the second voltage signal VS_2 is provided as the driving signal DS to each non-selected word line.

  The read / write circuit 140 is connected to the memory cell array 110 through the bit line BL, and is connected to the data input / output circuit 150 through the data line DL. The read / write circuit 140 receives data from the data input / output circuit 150 and writes the received data to the memory cell array 110. The read / write circuit 140 reads data from the memory cell array 110 and transmits the read data to the data input / output circuit 150. For example, the read / write circuit 140 may include components such as a page buffer (or page register) for reading and writing data, a column selection circuit for selecting the bit line BL, and the like.

  The data input / output circuit 150 is connected to the read / write circuit 140 through the data line DL. The data input / output circuit 150 operates in response to the control of the control logic 160. The data input / output circuit 150 is configured to exchange data DATA with the outside. The data input / output circuit 150 transmits data DATA transmitted from the outside to the read / write circuit 140 through the data line DL. The data input / output circuit 150 outputs the data DATA transmitted from the read / write circuit 140 through the data line DL to the outside. For example, the data input / output circuit 150 may include a component such as a data buffer.

  The control logic 160 controls various operations of the nonvolatile memory device 100. The control logic 160 is configured to control the high voltage generation circuit 120, the row selection circuit 130, the read / write circuit 140, and the data input / output circuit 150. Referring to FIG. 1, the control logic 160 includes ramping logic 170.

  The ramping logic 170 controls the high voltage generation circuit 120 so that the first and second voltage signals VS_1 and VS_2 that increase stepwise are generated. That is, during the program operation, the ramping logic 170 controls the high voltage generation circuit 120 to generate the first voltage signal VS_1 that increases stepwise up to the program voltage Vpgm. The ramping logic 170 also controls the high voltage generation circuit 120 to generate the second voltage signal VS_2 that increases stepwise up to the pass voltage Vpass.

  As described above, the non-volatile memory device 100 according to the embodiment of the present invention generates the first and second voltage signals VS_1 and VS_2 that increase stepwise up to the target voltage (that is, in units of ramping steps). The drive signal DS is provided to the word line.

  Since the voltage levels of the first and second voltage signals VS_1 and VS_2 increase step by step, the driving signal provided to the word line maintains a constant rising slope regardless of the resistance difference of each word line. can do. Therefore, the nonvolatile memory device 100 can prevent a read margin from being reduced due to a difference in program speed. Hereinafter, the structure of the memory cell array 110 according to the embodiment of the present invention will be described in more detail.

  FIG. 2 is a block diagram showing the memory cell array of FIG. Referring to FIG. 2, the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block BLK has a three-dimensional structure (or vertical structure). For example, each memory block BLK includes a structure extended along first to third directions. For example, each memory block BLK includes a plurality of NAND strings NS extended along the second direction. For example, a plurality of NAND strings NS are provided along the first and third directions.

  Each NAND string NS is connected to a bit line BL, a string selection line SSL, a ground selection line GSL, a word line WL, and a common source line CSL. That is, each memory block is connected to a plurality of bit lines BL, a plurality of string selection lines SSL, a plurality of ground selection lines GSL, a plurality of word lines WL, and a common source line CSL. The memory blocks BLK1 to BLKz will be described in more detail with reference to FIG.

  For example, the memory blocks BLK1 to BLKz are selected by the row selection circuit 130 illustrated in FIG. For example, the row selection circuit 130 selects the memory block BLK corresponding to the decoded row address among the memory blocks BLK1 to BLKz.

  FIG. 3 is a perspective view showing a first embodiment of one BLKi among the memory blocks BLK1 to BLKz of FIG. FIG. 4 is a cross-sectional view taken along line I-I ′ of the memory block BLKi in FIG. 3. Referring to FIGS. 3 and 4, the memory block BLKi includes a structure extended along first to third directions.

  First, a substrate 111 is provided. Illustratively, the substrate 111 is a well having a first type. For example, the substrate 111 is a p-well formed by implanting a group 5 element such as boron B (Boron). For example, the substrate 111 is a pocket p-well provided in an n-well. In the following, it is assumed that the substrate 111 is a p-well. However, the substrate 111 is not limited to a p-well.

  A plurality of doping regions 311 to 314 extended along the first direction is provided on the substrate 111. For example, the plurality of doping regions 311 to 314 have a second type different from the substrate 111. For example, the plurality of doping regions 311 to 314 have n type. Hereinafter, it is assumed that the first to fourth doping regions 311 to 314 have n type. However, the first to fourth doping regions 311 to 314 are not limited to having the n type.

  A plurality of insulating materials 112 extended along the first direction are sequentially provided on the region of the substrate 111 between the first and second doping regions 311 and 312 along the second direction. For example, the plurality of insulating materials 112 are provided separated by a specific distance along the second direction. For example, the insulating material 112 may include an insulating material such as silicon oxide.

  A plurality of pillars 113 sequentially disposed along the first direction on the substrate 111 between the first and second doping regions 311 and 312 and penetrating the insulating material 112 along the second direction are provided. Provided. For example, the plurality of pillars 113 may be connected to the substrate 111 through the insulating material 112.

  For example, each pillar 113 is composed of a plurality of substances. For example, the surface layer 114 of each pillar 113 includes a silicon material having a first type. For example, the surface layer 114 of each pillar 113 includes a silicon material having the same type as the substrate 111. Hereinafter, it is assumed that the surface layer 114 of each pillar 113 includes p-type silicon. However, the surface layer 114 of each pillar 113 is not limited to containing p-type silicon.

  The inner layer 115 of each pillar 113 is made of an insulating material. For example, the inner layer 115 of each pillar 113 includes an insulating material such as silicon oxide. For example, the inner layer 115 of each pillar 113 may include an air gap.

  An insulating film 116 is provided along the exposed surface of the insulating material 112, the pillar 113, and the substrate 111 in a region between the first and second doping regions 311 and 312. For example, the insulating film 116 provided on the exposed surface on the second direction side of the last insulating material 112 provided along the second direction may be removed.

  For example, the thickness of the insulating film 116 is less than ½ of the distance between the plurality of insulating materials 112. That is, between the insulating film 116 provided on the lower surface of the first insulating material among the plurality of insulating materials 112 and the insulating film 116 provided on the upper surface of the second insulating material below the first insulating material, A region where a material other than the insulating material 112 and the insulating film 116 can be disposed is provided.

  First conductive materials 211 to 291 are provided on the exposed surface of the insulating film 116 in a region between the first and second doping regions 311 and 312. For example, a first conductive material 211 that extends along a first direction between the insulating material 112 adjacent to the substrate 111 and the substrate 111 is provided. More specifically, a first conductive material 211 extending in the first direction is provided between the insulating film 116 on the lower surface of the insulating material 112 adjacent to the substrate 111 and the substrate 111.

  Hereinafter, the heights of the first conductive materials 211 to 291, 212 to 292, and 213 to 293 are defined. The first conductive materials 211 to 291, 212 to 292, and 213 to 293 are defined to have first to ninth heights sequentially from the substrate 111. That is, the first conductive materials 211 to 213 adjacent to the substrate 111 have a first height. The first conductive materials 291 to 293 adjacent to the second conductive materials 331 to 333 have a ninth height. As the distance between the first conductive material and the substrate 111 increases, the height of the first conductive material increases.

  In the insulating material 112, a first layer extending in a first direction extends between the insulating film 116 on the upper surface of the specific insulating material and the insulating film 116 on the lower surface of the insulating material disposed on the specific insulating material. A conductive material is provided. For example, a plurality of first conductive materials 221 to 281 extending in a first direction are provided between the plurality of insulating materials 112. For example, the first conductive materials 211 to 291 are metal materials. For example, the first conductive materials 211 to 291 are conductive materials such as polysilicon.

  In the region between the second and third doping regions 312, 313, a structure identical to the structure above the first and second doping regions 311, 312 is provided. Exemplarily, in the region between the second and third doping regions 312, 313, a plurality of insulating materials 112 extended in the first direction are sequentially disposed along the first direction and along the third direction. A plurality of pillars 113 penetrating through the plurality of insulating materials 112, a plurality of insulating materials 112 and an insulating film 116 provided on exposed surfaces of the plurality of pillars 113, and a plurality of first layers extended along the first direction. One conductive material 212-292 is provided.

  In the region between the third and fourth doping regions 313 and 314, a structure identical to the structure above the first and second doping regions 311 and 312 is provided. Exemplarily, in the region between the third and fourth doping regions 312, 313, a plurality of insulating materials 112 extended in the first direction are sequentially disposed along the first direction and along the third direction. A plurality of pillars 113 penetrating through the plurality of insulating materials 112, a plurality of insulating materials 112 and an insulating film 116 provided on exposed surfaces of the plurality of pillars 113, and a plurality of first layers extended along the first direction. One conductive material 213-293 is provided.

  A drain 320 is provided on each of the plurality of pillars 113. Illustratively, the drain 320 is a second type of doped silicon material. For example, the drain 320 is an n-type doped silicon material. In the following, it is assumed that the drain 320 includes n-type silicon. However, the drain 320 is not limited to including n-type silicon. Illustratively, the width of each drain 320 is greater than the width of the corresponding pillar 113. For example, each drain 320 is provided in the form of a pad on the upper surface of the corresponding pillar 113.

  Second conductive materials 331 to 333 extended in the third direction are provided on the drain 320. The second conductive materials 331 to 333 are sequentially disposed along the first direction. Each of the second conductive materials 331 to 333 is connected to the drain 320 of the corresponding region. For example, the drain 320 and the second conductive material 333 extended in the third direction are each connected through a contact plug. For example, the second conductive materials 331 to 333 are metal materials. For example, the second conductive materials 331 to 333 are conductive materials such as polysilicon.

  3 and 4, each pillar 113 forms a string together with an adjacent region of the insulating film 116 and an adjacent region among the plurality of first conductive lines 211 to 291, 212 to 292, and 213 to 293. For example, each pillar 113 forms a NAND string NS together with an adjacent region of the insulating film 116 and an adjacent region among the first conductive lines 211 to 291, 212 to 292, and 213 to 293. The NAND string NS includes a plurality of transistor structures TS. The transistor structure TS will be described in more detail with reference to FIG.

  FIG. 5 is a cross-sectional view showing the transistor structure of FIG. 3 to 5, the insulating film 116 includes first to third sub-insulating films 117, 118, and 119.

  The surface layer 114 including the p-type silicon of the pillar 113 operates as a body. The first sub-insulating film 117 adjacent to the pillar 113 operates as a tunneling insulating film. For example, the first sub-insulating film 117 adjacent to the pillar 113 includes a thermal oxide film.

  The second sub-insulating film 118 operates as a charge storage film. For example, the second sub insulating film 118 operates as a charge trap layer. For example, the second sub-insulating film 118 includes a nitride film or a metal oxide film (for example, an aluminum oxide film, a hafnium oxide film, etc.).

  The third sub-insulating film 119 adjacent to the first conductive material 233 operates as a blocking insulating film. For example, the third sub-insulating layer 119 adjacent to the first conductive material 233 extended in the first direction may be formed in a single layer or multiple layers. The third sub-insulating film 119 may be a high dielectric film (eg, an aluminum oxide film, a hafnium oxide film, etc.) having a higher dielectric constant than the first and second sub-insulating films 117 and 118.

  The first conductive material 233 operates as a gate (or control gate). That is, the first conductive material 233 that operates as a gate (or control gate), the third sub-insulating film 119 that operates as a blocking insulating film, the second sub-insulating film 118 that operates as a charge storage film, and the tunneling insulating film. The first sub-insulating film 117 and the surface layer 114 including p-type silicon that operates as a body form a transistor (or a memory cell transistor structure). For example, the first to third sub-insulating films 117 to 119 constitute an ONO (oxide-nitride-oxide). Hereinafter, the surface layer 114 including the p-type silicon of the pillar 113 is defined as operating as a body in the second direction.

  The memory block BLKi includes a plurality of pillars 113. That is, the memory block BLKi includes a plurality of NAND strings NS. More specifically, the memory block BLKi includes a plurality of NAND strings NS extended in the second direction (or a direction perpendicular to the substrate).

  Each NAND string NS includes a plurality of transistor structures TS arranged along the second direction. At least one of the plurality of transistor structures TS of each NAND string NS operates as a string selection transistor SST. At least one of the plurality of transistor structures TS of each NAND string NS operates as a ground selection transistor GST.

  The gate (or control gate) corresponds to the first conductive materials 211 to 291, 212 to 292, and 213 to 293 extended in the first direction. That is, the gate (or control gate) is extended in the first direction to form a word line and at least two selection lines (eg, at least one string selection line SSL and at least one ground selection line GSL).

  The second conductive materials 331 to 333 extended in the third direction are connected to one end of the NAND string NS. For example, the second conductive materials 331 to 333 extended in the third direction operate as the bit line BL. That is, a plurality of NAND strings are connected to one bit line BL in one memory block BLKi.

  Second type doping regions 311 to 314 extended in the first direction are provided at the other end of the NAND string. The second type doping regions 311 to 314 extended in the first direction operate as a common source line CSL.

  In summary, the memory block BLKi includes a plurality of NAND strings extended in a direction perpendicular to the substrate 111 (second direction), and a plurality of NAND strings NS are connected to one bit line BL. (For example, charge trapping type).

  3 to 5, the first conductive lines 211 to 291, 212 to 292, and 213 to 293 have been described as being provided in nine layers. However, the first conductive lines 211 to 291, 212 to 292, and 213 to 293 are not limited to being provided in nine layers. For example, the first conductive line can be provided in at least eight layers forming a memory cell and in at least two layers forming a select transistor. The first conductive line may be provided in at least 16 layers constituting the memory cell charge and in at least two layers forming a select transistor. The first conductive line may be provided in a plurality of layers forming a memory cell and in at least two layers forming a selection transistor. For example, the first conductive line can be provided in a layer forming a dummy memory cell.

  In FIG. 3 to FIG. 5, it has been described that three NAND strings NS are connected to one bit line BL. However, the present invention is not limited to three NAND strings NS connected to one bit line BL. For example, in the memory block BLKi, m NAND strings NS may be connected to one bit line BL. At this time, the number of first conductive materials 211 to 291, 212 to 292, and 213 to 293 that extend in the first direction and the number of NAND strings NS connected to one bit line BL and the common source line CSL operate. The number of doping regions 311 to 314 to be adjusted is also adjusted.

  In FIG. 3 to FIG. 5, the three NAND strings NS are connected to one first conductive material extended in the first direction. However, the present invention is not limited to three NAND strings NS connected to one first conductive material. For example, n NAND strings NS may be connected to one first conductive material. At this time, the number of bit lines 331 to 333 may be adjusted as much as the number of NAND strings NS connected to one first conductive material.

  As described with reference to FIGS. 3 to 5, the cross-sectional area of the pillar 113 along the first and third directions can be reduced as it approaches the substrate 111. For example, the cross-sectional area along the first and third directions of the pillar 113 may be varied depending on process characteristics or errors.

  For example, the pillar 113 may be formed by providing a material such as a silicon material and an insulating material in a hole formed by etching. As the etched depth increases, the area along the first and third directions of the holes formed by the etching can be reduced. That is, the cross-sectional area along the first and third directions of the pillar 113 can be reduced as the distance from the substrate 111 becomes closer.

  FIG. 6 is a circuit diagram showing an equivalent circuit BLKi_1 according to the first embodiment of the memory block BLKi described with reference to FIGS. 3 to 6, NAND strings NS11 to NS31 are provided between the first bit line BL1 and the common source line CSL. NAND strings NS12, NS22, NS32 are provided between the second bit line BL2 and the common source line CSL. NAND strings NS13, NS23, NS33 are provided between the third bit line BL3 and the common source line CSL. The first to third bit lines BL1 to BL3 correspond to the second conductive materials 331 to 333 extended in the third direction, respectively.

  The string selection transistor SST of each NAND string NS is connected to the corresponding bit line BL. The ground selection transistor GST of each NAND string NS is connected to the common source line CSL. A memory cell MC is provided between the string selection transistor SST and the ground selection transistor GST of each NAND string NS.

  Hereinafter, a NAND string NS is defined in units of rows and columns. NAND strings NS commonly connected to one bit line form one column. For example, NAND strings NS11 to NS31 connected to the first bit line BL1 correspond to the first column. The NAND strings NS12 to NS32 connected to the second bit line BL2 correspond to the second column. NAND strings NS13 to NS33 connected to the third bit line BL3 correspond to the third column.

  NAND strings NS connected to one string selection line SSL form one row. For example, the NAND strings NS11 to NS13 connected to the first string selection line SSL1 form a first row. NAND strings NS21 to NS23 connected to the second string selection line SSL2 form a second row. NAND strings NS31 to NS33 connected to the third string selection line SSL3 form a third row.

  A height is defined for each NAND string NS. For example, the height of the ground selection transistor GST is 1 in each NAND string NS. The height of the memory cell MC1 adjacent to the ground selection transistor GST is defined as 2. The height of the string selection transistor SST is defined as 9. The height of the memory cell MC7 adjacent to the string selection transistor SST is defined as 8. As the distance between the memory cell MC and the ground selection transistor GST increases, the height of the memory cell MC increases. That is, the first to seventh memory cells MC1 to MC7 are defined by having second to eighth heights, respectively.

  Each NAND string NS shares a ground selection line GSL. The ground selection line GSL corresponds to the first conductive lines 211 to 213 having the first height. That is, it can be understood that the ground selection transistor GST also has the first height.

  The memory cells MC having the same height in the NAND string NS in the same row share the word line WL. The word lines WL of the NAND strings NS having the same height and corresponding to different rows are connected in common. That is, memory cells MC having the same height share the word line WL.

  First conductive lines 221 to 223 having a second height are commonly connected to form a first word line WL1. First conductive lines 231 to 233 having a third height are commonly connected to form a second word line WL2. First conductive lines 241 to 243 having a fourth height are connected in common to form a third word line WL3. First conductive lines 251 to 253 having a fifth height are commonly connected to form a fourth word line WL4. First conductive lines 261 to 263 having a sixth height are commonly connected to form a fifth word line WL5. First conductive lines 271 to 273 having a seventh height are commonly connected to form a sixth word line WL6. First conductive lines 281 to 283 having an eighth height are commonly connected to form a seventh word line WL7.

  NAND strings NS in the same row share a string selection line SSL. NAND strings NS in different rows are connected to different string selection lines SSL1, SSL2, and SSL3, respectively. The first to third string selection lines SSL1 to SSL3 correspond to the first conductive lines 291 to 293 having a ninth height, respectively.

  Hereinafter, the first string selection transistor SST1 is defined as a string selection transistor SST connected to the first string selection line SSL1. The second string selection transistor SST2 is defined as a string selection transistor SST connected to the second string selection line SSL2. The third string selection transistor SST3 is defined as a string selection transistor SST connected to the third string selection line SSL3.

  The common source line CSL is commonly connected to the NAND string NS. For example, in the active region on the substrate 111, the first to fourth doping regions 311 to 314 are connected to each other to form a common source line CSL.

  As shown in FIG. 6, the word lines WL having the same height are connected in common. Accordingly, when a word line WL having a specific height is selected, all NAND strings NS connected to the selected word line WL are selected.

  NAND strings NS in different rows are connected to different string selection lines SSL. Therefore, by selecting and deselecting the string selection lines SSL1 to SSL3, the NAND string NS of the non-selected row among the NAND strings NS connected to the same word line WL is separated from the corresponding bit line, and the selected row NAND strings NS may be connected to corresponding bit lines.

  For example, one of the string selection lines SSL1 to SSL3 is selected during a program and read operation. That is, the program and read operations are performed in units of rows of the NAND strings NS11 to NS13, NS21 to NS23, NS31 to NS33.

  For example, during a program and read operation, a selection voltage is applied to a selected word line of a selected row, and a non-selection voltage is applied to an unselected word line. For example, the selection voltage can be the program voltage Vpgm or the selection read voltage Vrd. For example, the non-select voltage may be a pass voltage Vpass or a non-select read voltage Vread. That is, the program and read operations are performed in units of rows of the NAND strings NS11 to NS13, NS21 to NS23, NS31 to NS33.

FIG. 7 is a diagram exemplarily showing a rising slope of a drive signal in a general case.
As described with reference to FIGS. 3 to 5, the cross-sectional area of the pillar 113 along the first and third directions decreases as it approaches the substrate 111 due to process characteristics or errors. For example, the cross-sectional area along the first and third directions of the pillar 113 corresponding to the second height is smaller than the cross-sectional area along the first and third directions of the pillar 113 corresponding to the eighth height.

  A decrease in the cross-sectional area along the first and third directions of the pillar 113 means an increase in the cross-sectional area along the second and third directions of the first conductive line. That is, it means that the closer the cross-sectional area of the word line along the second and third directions is to the substrate 111, the more it increases. For example, as shown in FIG. 4, the first conductive lines 221 to 223 having the second height have the cross-sectional areas along the second and third directions of the first conductive lines 221 to 223 having the second height. Greater than the cross-sectional area along the second and third directions. That is, referring to FIG. 6, the cross-sectional area along the second and third directions of the first word line WL1 having the second height is the second and third cross-sectional areas of the seventh word line WL7 having the eighth height. It is larger than the cross-sectional area along the third direction. Accordingly, since the resistance of the word line is inversely proportional to the cross-sectional area, the resistance of the first word line WL1 is smaller than the resistance of the seventh word line WL7.

  As described above, the word line resistance of a memory cell array having a three-dimensional structure is smaller as it is closer to the substrate. Therefore, in a general nonvolatile memory device, a driving signal provided to a word line close to the substrate has a higher slope than a driving signal applied to a word line far from the substrate. Such a difference in the slope of the rising slope may cause a decrease in read margin due to a difference in program speed.

  For example, referring to FIG. 7, during the program operation, the first driving signal DS <1> provided to the first word line WL1 has a rising slope of 'γ' while rising to the pass voltage Vpass. The seventh driving signal DS <7> provided to the seventh word line WL7 has a rising slope of “α” while increasing to the pass voltage Vpass. That is, during the rise to the pass voltage Vpass, the rising slope of the first drive signal DS <1> is larger than the rising slope DS <7> of the seventh drive signal.

  Further, for example, the first drive signal DS <1> and the seventh drive signal DS <7> have rising slopes of “β” and “δ”, respectively, while the pass voltage Vpass rises to the program voltage Vpgm. That is, the rising slope of the first drive signal DS <1> is larger than the rising slope DS <7> of the seventh drive signal while rising to the pass voltage Vpass.

  Accordingly, when the memory cells connected to the first word line WL1 and the seventh word line WL7 are each programmed, the memory cells connected to the first word line WL1 are changed to the memory cells connected to the seventh word line WL7. It is programmed more quickly than it is. Such a difference in the programming speed of the memory cell causes a reduction in the read margin.

  In order to minimize such a problem, the non-volatile memory device 100 (see FIG. 1) according to the embodiment of the present invention gradually increases to the program voltage Vpgm in response to the control of the ramping logic 170 (see FIG. 1). A first voltage signal VS_1 that increases and a second voltage signal VS_2 that increases stepwise up to the pass voltage Vpass are generated. The non-volatile memory device 100 provides the first voltage signal VS_1 and the second voltage signal VS_2 as the driving signal DS to the selected word line and the non-selected word line. Hereinafter, the high voltage generation circuit 120 and the ramping logic 170 according to the embodiment of the present invention will be described in more detail.

  FIG. 8 is a block diagram illustrating the high voltage generation circuit 120 and the ramping logic 170 of FIG. 1 in more detail. Referring to FIG. 8, the high voltage generation circuit 120 includes a first high voltage generator 121 and a second high voltage generator 122. The ramping logic 170 includes a first sub-ramping logic 171 and a second sub-ramping logic 172.

  The first voltage generator 121 generates the first voltage signal VS_1 that increases stepwise up to the program voltage Vpgm in response to the control of the first sub-ramping logic 171. During the program operation, the first voltage signal VS_1 is provided to the selected word line as the driving signal DS.

  The second voltage generator 122 generates a second voltage signal VS_2 that gradually increases to the pass voltage Vpass in response to the control of the second sub-ramping logic 172. During the program operation, the second voltage signal VS_2 is provided to the selected word line as the driving signal DS.

  FIG. 9 is a diagram illustrating the first voltage signal VS_1 generated by the first voltage generator 121 of FIG.

  Referring to FIG. 9, the rising slope of the first voltage signal VS_1 is set lower than that in the general case (that is, the case where the first sub-ramping logic 171 (see FIG. 8) is not provided). For example, as illustrated in FIG. 9, the rising slope of the first voltage signal VS_1 may be set based on the seventh driving signal DS <7> (see FIG. 7) having the lowest rising slope.

  In this case, the rising slope of the first voltage signal VS_1 is the rising slope of the seventh drive signal DS <7> provided to the word line having the largest resistance (ie, the seventh word line WL7 (see FIG. 6)). Are the same. Accordingly, the rising slope of the first voltage signal VS_1 is constant in the word lines having lower resistance than the seventh word line WL7 (that is, the first to sixth word lines WL1 to WL6 (see FIG. 6)). Can be maintained.

  FIG. 10 is a diagram illustrating the second voltage signal VS_2 generated by the second voltage generator 122 of FIG.

  Referring to FIG. 10, the rising slope of the second voltage signal VS_2 is set to be lower than that in a general case (that is, when the second sub-ramping logic 172 (see FIG. 8) is not provided). For example, similarly to the first voltage signal VS_1 of FIG. 9, the rising slope of the second voltage signal VS_2 may be set based on the rising slope of the seventh drive signal DS <7>. Accordingly, the rising slope of the second voltage signal VS_2 can be maintained constant in the first to seventh word lines WL1 to WL7 (see FIG. 6).

  As illustrated in FIGS. 8 to 10, the first and second voltage generators 121 and 122 may have a first rising slope that is low in response to control of the first and second sub-ramping logics 171 and 172, respectively. The second voltage signals VS_1 and VS_2 can be generated. For example, the rising slopes of the first and second voltage signals VS_1 and VS_2 can be set similarly to the rising slope of the seventh drive signal DS <7>. However, this is exemplary, and the rising slopes of the first and second voltage signals VS_1 and VS_2 are set to be lower or higher within a predetermined range than the rising slope of the seventh drive signal DS <7>. obtain.

  Meanwhile, during the program operation, the first voltage signal VS_1 is provided as a drive signal to the selected word line, and the second voltage signal VS_2 is provided as a drive signal to the non-selected word line. 11 and 12 below, the configuration of the row selection circuit 130 (see FIG. 1) that provides the first and second voltage signals VS_1 to the word lines as drive signals will be described in more detail.

  FIG. 11 is a block diagram showing the row selection circuit 130 of FIG. 1 in more detail. Referring to FIG. 11, the row selection circuit 130 includes a word line driver 131 and a row decoder 132. The word line driver 131 includes a decoding block 131_a and first to seventh driving blocks 131_b1 to 131_b7.

  The decoding block 131_a receives the row address RAi. The decoding block 131_a generates a decoded row address DRAi by decoding the received row address RAi. The decoding block 131_a transmits the decoded row address DRAi to the corresponding driving block among the first to seventh driving blocks 131_b1 to 131_b7.

  The first to seventh driving blocks 131_b1 to 131_b7 each receive the decoded row address DRAi from the decoding block 131_a. The first to seventh driving blocks 131_b1 to 131_b7 receive the first voltage signal VS_1 and the second voltage signal VS_2 from the high voltage generation circuit 120 (see FIG. 1), respectively. The first to seventh driving blocks 131_b1 to 131_b7 output one of the first voltage signal VS_1 and the second voltage signal VS_2 as the driving signal DS in response to the decoded row address DRAi. Each driving block is described in more detail in FIG. 12 below.

  The row decoder 133 is connected to the word line driver 131 through signal lines SL1 to SL7. The row decoder 133 is connected to a plurality of memory blocks BLK1 to BLKz, and each memory block is connected to the row decoder 133 through word lines WL1 to WL7. The row decoder 133 receives the row address RAj and selects a memory block in response to the row address RAj. The row decoder 133 receives the driving signals DS <1> to DS <7> through the signal lines SL1 to SL7, and applies the driving signals DS <1> to DS <7> to the word lines WL1 to WL7 of the selected memory block. provide.

  FIG. 12 is a view for explaining the driving block of FIG. 11 in more detail. FIG. 12 exemplarily shows the first driving block 131_b1. Referring to FIG. 12, the first driving block 131_b1 includes a first switch S / W1 and a second switch S / W2.

  The first switch S / W1 receives the first voltage signal VS_1 and the first activation signal EN_1 from the high voltage generation circuit 120 (see FIG. 1) and the control logic 160 (see FIG. 1), respectively. The second switch S / W2 receives the second voltage signal VS_2 and the second activation signal EN_2 from the high voltage generation circuit 120 and the control logic 160, respectively. The first switch S / W1 and the second switch S / W2 may be selected from the first voltage signal VS_1 and the second voltage signal VS_2 in response to the decoded row address DRAi1 provided from the decoding block 131_a. One of them is output as the first drive signal DS <1>.

  13 and 14 are diagrams illustrating a rising slope of the driving signal when the voltage signal generated by the high voltage generating circuit 120 of FIG. 1 is provided to the word line as the driving signal.

  Specifically, in FIG. 13, the first voltage signal VS_1 is provided to the seventh word line WL7 selected as the driving signal, and the second voltage signal VS_2 is the non-selected word line as the driving signal, that is, the first to first lines. A case in which the sixth word lines WL1 to WL6 are provided is illustrated. In FIG. 14, the first voltage signal VS_1 is provided to the first word line WL1 selected as the driving signal, and the second voltage signal VS_2 is deselected as the driving signal (that is, the second to seventh word lines). The case provided in WL2-WL7) is illustrated.

  As shown in FIG. 13, when the seventh word line WL7 is selected during the program operation, the seventh drive signal DS <7> is increased to the pass voltage Vpass and the program voltage Vpgm while the α and Has a rising slope of 'β'. In this case, the driving signals DS <1> to DS <6> having a rising slope of “α” are provided to the unselected first to sixth word lines WL1 to WL6, respectively, while rising to the pass voltage Vpass. The

  As shown in FIG. 14, when the program operation first word line WL1 is selected, the first drive signal DS <1> is similar to the seventh drive signal DS <1> in the pass voltage Vpass. And rising ramps of 'α' and 'β', respectively, while rising to the program voltage Vpgm. In this case, the non-selected second to seventh word lines WL2 to WL7 are respectively provided with driving signals DS <2> to DS <7> having a rising slope of “α” while rising to the pass voltage Vpass. The

  As a result, the nonvolatile memory device 100 (see FIG. 1) according to the embodiment of the present invention can provide driving signals having the same rising slope to the word lines regardless of the resistance difference between the plurality of word lines. Therefore, the nonvolatile memory device 100 can prevent a read margin from being reduced due to a difference in program speed.

  On the other hand, the embodiments described in FIGS. 1 to 14 are exemplary, and the technical idea of the present invention is not limited thereto. The technical idea of the present invention can be applied to various embodiments and application examples. In the following, other embodiments and application examples of the present invention will be described in more detail.

  FIG. 15 is a block diagram illustrating a non-volatile memory device 200 according to another embodiment of the present invention. The nonvolatile memory device 200 of FIG. 15 is similar to the nonvolatile memory device 100 of FIG. 1 except that the ramping control unit 270 is implemented outside the control logic 260. That is, the non-volatile memory device 100 of FIG. 15 assigns part of the control logic 160 (see FIG. 1) to the ramping logic 170 (see FIG. 1), and the non-volatile memory device 200 of FIG. Unit 270 is embodied in a separate module that is distinct from control logic 260.

  In this case, the ramping control unit 270 operates in response to the control of the control logic 260, and the high voltage generation unit 220 includes first and second voltage signals that increase stepwise in response to the control of the ramping control unit 270. VS_1 and VS_2 are generated. Since the operation of the high voltage generation unit 220 is similar to the operation of the high voltage generation circuit 120 of FIG. 1, detailed description thereof is omitted.

  1 to 15, the nonvolatile memory devices 100 and 200 according to an embodiment of the present invention are described by providing a driving signal having the same rising slope to each word line during a program operation. However, this is exemplary, and the nonvolatile memory devices 100 and 200 according to the embodiment of the present invention may be applied during a read operation. This will be described in more detail with reference to FIGS. 16 to 20 below.

  16 to 18 are diagrams for explaining read disturbance due to driving signals having different rising slopes.

  FIG. 16 illustrates the threshold voltage distribution of the memory cells MC. Illustratively, it is assumed that the memory cell MC has a threshold voltage distribution corresponding to four logic states E, P1, P2, and P3. That is, it is assumed that the memory cell MC stores 2 bits. However, the memory cell MC is not limited to storing 2 bits.

  FIG. 17 shows a read operation by drive signals having different rising slopes. For convenience of explanation, it is assumed that the rising slope of the driving signal provided to the first to seventh word lines WL1 to WL7 increases as the distance from the substrate increases. In addition, it is assumed that a read operation for the second word line WL2 is performed.

  FIG. 18 shows the channel voltage of one NAND string among the NAND strings corresponding to the selected string line (Selected SSL) of FIG. Specifically, FIG. 18 shows the channel voltage of the NAND string at the sixth time t6 (see FIG. 17). The first to seventh memory cells MC1 to MC7 correspond to memory cells belonging to the same NAND string among the memory cells of the first to seventh word lines WL1 to WL7 of FIG. For convenience of explanation, it is assumed that the third memory cell MC3 has a threshold voltage corresponding to the logic state P3. It is assumed that the first, second, fourth to seventh memory cells MC1, MC2, MC4 to MC7 have a threshold voltage corresponding to the erased state E.

  16 to 18, first, the bit line BL is precharged with the bit line precharge voltage VBL. Thereafter, the string selection voltage VSSL and the ground selection voltage VGSL are provided to the selected string selection line (Selected SSL) and the ground selection line GSL, respectively. In addition, the first selected read voltage Vrd1 is provided to the selected second word line WL2, and the non-selected read voltage Vread is provided to the unselected word lines WL1, WL3 to WL7.

  The closer to the substrate 111, the larger the rising slope, so that the first to seventh drive signals DS <1> to DS <7> provided to the first to seventh word lines WL1 to WL7 are sequentially selected as the first. The read voltage Vrd1 level is reached. In this case, since the memory cells MC1, MC2, MC4 to MC7 excluding the third memory cell MC3 have the threshold voltage of the erased state E, the memory cells MC1, MC2, MC4 to MC7 are sequentially turned on. For example, the first memory cell MC1 is turned on at the third time t3 that is the fastest compared to other memory cells in the erased state, and the seventh memory cell MC7 is the fifth time that is the latest compared to the memory cells in the other erased state. Turned on at t5.

  On the other hand, since the third memory cell MC3 has a threshold voltage corresponding to the logic state P3, the third memory cell MC3 has a third drive signal DS <3> provided to the third word line WL3. When the selected read voltage Vread is reached, it is turned on. Therefore, the third memory cell MC3 can be turned on at the latest sixth time t6 as compared with the other memory cells MC1, MC2, MC4 to MC7.

  In this case, as shown in FIG. 18, the channel voltage of the NAND string including the first to seventh memory cells MC1 to MC7 can be separated around the third memory cell MC3. That is, at the sixth time t6, the third memory cell MC3 is turned off and the other memory cells MC1, MC2, and MC4 to MC7 are turned on, so that the channel voltage of the NAND string is centered on the third memory cell MC3. Each is divided into a ground voltage Vss and a bit line precharge voltage VBL. Such a difference in channel voltage may cause read disturbance due to hot electron injection, and such read disturbance may cause a decrease in read margin.

  In order to prevent the read disturbance described above, the non-volatile memory devices 100 and 200 according to an embodiment of the present invention generates a voltage signal that gradually increases to a target voltage during a read operation, and uses this as a drive signal to a word line. provide. This is explained in more detail in FIGS. 19 and 20 below.

  FIG. 19 is a block diagram illustrating an embodiment of the high voltage generation circuit 120 and ramping logic 170 of FIG. Referring to FIG. 19, the high voltage generation circuit 120 includes first and second voltage generators 121 and 122, and the ramping logic 170 includes first and second sub-ramping logics 171 and 172.

  As shown in FIG. 19, the first voltage generator 121 generates the first voltage signal VS_1 that increases stepwise up to the selected read voltage Vrd in response to the control of the first sub-ramping logic 171. That is, the first voltage generator 121 generates the first voltage signal VS_1 that increases stepwise up to the program voltage Vpgm during the program operation, and the first voltage signal increases stepwise up to the selected read voltage Vrd during the read operation. VS_1 is generated. The first voltage signal VS_1 generated by the first voltage generator 121 is provided as a driving signal to the selected word line thereafter.

  Similarly, the second voltage generator 122 generates the second voltage signal VS_2 that increases stepwise up to the pass voltage Vpass during the program operation in response to the control of the second sub-ramping logic 172, and is not used during the read operation. A second voltage signal VS_2 that increases stepwise up to the selected read voltage Vread is generated. The second voltage signal VS_2 generated by the second voltage generator 122 is subsequently provided as a driving signal to the selected word line.

  As described above, the first and second voltage generators 121 and 122 may prevent the read disturbance by generating the first and second voltage signals VS_1 and VS_2 that increase stepwise during the read operation, respectively. Can do.

  On the other hand, in FIG. 19, it is assumed that the first and second voltage generators 121 and 122 operate not only during a program operation but also during a read operation. However, this is exemplary, and the high voltage generation circuit 120 according to another embodiment of the present invention includes a voltage generator that operates during a program operation and a voltage generator that operates during a read operation. Can do. This is explained in more detail in FIG. 20 below.

  FIG. 20 is a block diagram illustrating another embodiment of the high voltage generation circuit 120 and the ramping logic 170 of FIG. Referring to FIG. 20, the high voltage generation circuit 120 includes first to fourth voltage generators 121 to 124, and the ramping logic 170 includes first to fourth sub-ramping logics 171 to 174.

  As shown in FIG. 20, the first and second voltage generators 121 and 122 operate when a program operation is performed, and are responsive to the control of the first and second sub-ramping logics 171 and 172, respectively. A first voltage signal VS_1 that gradually increases to the program voltage Vpgm and a second voltage signal VS_2 that gradually increases to the pass voltage Vpass are generated. The third and fourth voltage generators 123 and 124 operate when a read operation is performed, and step by step up to the selected read voltage Vrd in response to the control of the third and fourth sub-ramping logics 173 and 174, respectively. A third voltage signal VS_3 that increases and a fourth voltage signal VS_4 that increases stepwise up to the unselected read voltage Vread are generated. Accordingly, a read margin can be reduced during a program operation and read disturbance during a read operation can be prevented.

  Meanwhile, for convenience of explanation, it is assumed that the voltage generation circuit of FIGS. 19 and 20 is applied to the nonvolatile memory device 100 of FIG. 1, but may be applied to the nonvolatile memory device 200 of FIG. 15. Of course.

  Meanwhile, in FIGS. 1 to 20, it is assumed that the non-volatile memory devices 100 and 200 according to the embodiment of the present invention generate a first voltage signal VS_1 and a second voltage signal VS_2 that gradually increase to a target voltage. . However, this is exemplary, and the technical idea of the present invention is not limited to this. For example, the non-volatile memory device according to the embodiment of the present invention can be generated by gradually increasing only the second voltage signal VS_2 provided to the non-selected word line to the target voltage.

  Meanwhile, the ramping logic 170 can flexibly adjust the magnitude of the ramping step of the first and second voltage signals VS_1 and VS_2 according to the operation of the nonvolatile memory device 100. For example, the ramping logic 170 may control the high voltage generation circuit 120 to have different ramping step sizes according to the target voltage levels of the first and second voltage signals VS_1 and VS_2.

  On the other hand, in FIG. 6, the memory block BLKi described with reference to FIGS. 3 to 5 is described as corresponding to the equivalent circuit BLK_1 according to the first embodiment. However, this is exemplary, and embodiments of the present invention are not limited thereto. Hereinafter, equivalent circuits according to the second to fifth embodiments of the memory block BLKi described with reference to FIGS. 3 to 5 will be described.

  FIG. 21 is a circuit diagram illustrating an equivalent circuit BLKi_2 according to the second embodiment of the memory block BLKi described with reference to FIGS. 3 to 5. Compared to the equivalent circuit described with reference to FIG. 6, a side transistor LTR is additionally provided for each NAND string NS of the memory block BLKi_3.

  In each NAND string NS, the side transistor LTR is connected between the ground selection transistor GST and the common source line CSL. The gate of the side transistor LTR (or the control gate is the gate (or control gate) of the ground selection transistor GST) is connected to the ground selection line GSL.

  As described with reference to FIGS. 3 to 6, the first conductive lines 211, 212, and 213 having the first height correspond to the ground selection line GSL.

  When a specific voltage is applied to the first conductive lines 211, 212, and 213 having the first height, a channel is formed in the region of the surface layer 114 adjacent to the first conductive lines 211, 212, and 213. That is, a channel is formed in the ground selection transistor GST. If a specific voltage is applied to the first conductive lines 211, 212, and 213, a channel is formed in the region of the substrate 111 adjacent to the first conductive lines 211, 212, and 213.

  The first doping region 311 is connected to a channel generated in the substrate 111 by the voltage of the first conductive line 211. The channel generated in the substrate 111 by the voltage of the first conductive line 211 is connected to the channel generated in the surface layer 114 that operates as a body in the second direction by the voltage of the first conductive line 211.

  Similarly, a channel is formed in the substrate 111 by the voltage of the first conductive lines 211, 212, and 213. The first to fourth doping regions 311 to 314 are respectively connected to the surface layer 114 that operates as a body in the second direction through a channel generated in the substrate 111 by the voltage of the first conductive lines 211, 212, and 213.

  As described with reference to FIGS. 3 to 6, the first to fourth doping regions 311 to 314 are commonly connected to form a common source line CSL. The common source line CSL and the channels of the memory cells MC1 to MC7 are electrically connected through a channel perpendicular to the substrate 111 and a channel parallel to the substrate 111 formed by the voltage of the ground selection line GSL.

  That is, it can be understood that a transistor that is driven by the ground selection line GSL and is perpendicular to the substrate and a transistor parallel to the substrate are provided between the common source line CSL and the memory cells MC1 to MC3. A transistor perpendicular to the substrate can be understood as a ground selection transistor GST, and a transistor parallel to the substrate can be understood as a side transistor LTR.

  FIG. 22 is a circuit diagram illustrating an equivalent circuit BLKi_4 according to the third embodiment of the memory block BLKi described with reference to FIGS. Compared to the memory block BLKi_1 of FIG. 6, two ground selection transistors GST1 and GST2 may be provided between the memory cells MC1 to MC6 and the common source line CSL in each NAND string NS. The ground selection transistors GST1 and GST2 are connected to one ground selection line GSL.

  FIG. 23 is a circuit diagram illustrating an equivalent circuit BLKi_5 according to the fourth embodiment of the memory block BLKi described with reference to FIGS. Compared with the memory block BLKi_3 of FIG. 22, in each NAND string NS, two string selection transistors SST1, SST2 may be provided between the memory cells MC1 to MC5 and the bit line BL.

  In a NAND string in the same row, string selection transistors SST having the same height share one string selection line SSL. For example, in the NAND strings NS11 to NS13 in the first row, the first string selection transistor SST1 shares the eleventh string selection line SSL11. The second string selection transistor SST2 shares the 21st string selection line SSL21.

  In the NAND strings NS21 to NS23 in the second row, the first string selection transistor SST1 shares the twelfth string selection line SSL12. The second string selection transistor SST2 shares the 22nd string selection line SSL22.

  In the NAND strings NS31 to NS33 in the third row, the first string selection transistor SST1 shares the thirteenth string selection line SSL13. The second string selection transistor SST2 shares the 23rd string selection line SSL23.

  FIG. 24 is a circuit diagram showing an equivalent circuit BLKi_6 according to the fifth embodiment of the memory block BLKi described with reference to FIGS. Compared with the memory block BLKi_4 of FIG. 23, the string selection lines SSL corresponding to the NAND strings NS in the same row are connected in common.

  Meanwhile, the memory block described with reference to FIGS. 3 to 5 in the memory block of FIG. 2 may be implemented in various modifications. Hereinafter, variations of the memory block according to the embodiment of the present invention will be described.

  FIG. 25 is a perspective view showing one second embodiment BLKj among the memory blocks BLK1 to BLKz of FIG. A cross-sectional view taken along line I-I 'of the memory block BLKj is the same as the cross-sectional view shown in FIG.

  Compared with the memory block BLKi of FIG. 3, in the memory block BLKj, the pillar 113 'is provided in the form of a square pillar. In addition, the insulating material 101 is provided between the pillars 113 ′ arranged at a specific distance along the first direction. Illustratively, the insulating material 101 is stretched along the second direction and contacts the substrate 111.

  The first conductive materials 211 to 291, 212 to 292, and 213 to 293 described with reference to FIG. 3 are divided into first portions 211 a to 291 a, 212 a to 292 a, 213 a to 293 a and second portions 211 b to It is separated into 291b, 212b to 292b, and 213b to 293b.

  In the region above the first and second doping regions 311 and 312, each pillar 113 ′ forms a NAND string NS with the first portions 211 a to 291 a of the first conductive material and the insulating film 116. The second portions 211b to 291b of the material and the insulating film 116 and another NAND string NS are formed.

  In the region above the second and third doping regions 312, 313, each pillar 113 ′ forms a NAND string NS with the first portions 212a to 292a of the first conductive material and the insulating film 116 to form the first conductive layer. The second portion 212b to 292b of the material and the insulating film 116 and another NAND string NS are formed.

  In the region above the third and fourth doping regions 313 and 314, each pillar 113 'forms one NAND string NS with the first portions 213a to 293a of the first conductive material and the insulating film 116, thereby forming the first conductive material. The second portion 213b to 293b of the material and the insulating film 116 and another NAND string NS are formed.

  That is, each pillar 113 ′ is divided into two by separating the first and second portions 211a to 291a and 211b to 291b of the first conductive material provided on both sides of each pillar 113 ′ using the insulating material 101. Two NAND strings NS can be formed.

  The memory block BLKj may be implemented in the equivalent circuit described with reference to FIG. 6 or FIGS. The rising slopes of the program voltage Vpgm and the pass voltage Vpass provided to the word line of the memory block BLKj during the program operation are kept constant. Therefore, a decrease in read margin due to a difference in program speed can be prevented. The rising slopes of the selected read voltage Vrd and the non-selected read voltage Vread provided to the word lines of the memory block BLKj during the read operation can be kept constant. Thus, read disturb can be prevented.

  FIG. 26 is a perspective view showing a modification BLKj ′ of the memory block BLKj of FIG. A cross-sectional view taken along line I-I 'of the memory block BLKj' is the same as the cross-sectional view shown in FIG. Except that one pillar of the memory block BLKj ′ includes the first sub-pillar 113a and the second sub-pillar 113b, the memory block BLKj ′ is the same as the memory block BLKj described with reference to FIG.

  One pillar in the memory block BLKj ′ includes a first sub-pillar 113a and a second sub-pillar 113b. The first sub pillar 113a and the second sub pillar 113b are configured in the same manner as described with reference to FIGS.

  One pillar 113 'forms two NAND strings NS. The first portions 211a to 291a and the second portions 211b to 291b, 212b to 292b, and 213b to 293b of the first conductive material correspond to the ground selection line GSL, the word line WL, and the string selection line SSL. The word lines WL having the same height are connected in common.

  The memory block BLKj ′ can be implemented in the equivalent circuit described with reference to FIG. 6 or FIGS. The rising slopes of the program voltage Vpgm and the pass voltage Vpass provided to the word line of the memory block BLKj during the program operation are kept constant. Therefore, a decrease in read margin due to a difference in program speed can be prevented. The rising slopes of the selected read voltage Vrd and the non-selected read voltage Vread provided to the word line of the memory block BLKj ′ during the read operation can be adjusted. Thus, read disturb can be prevented.

  FIG. 27 is a perspective view showing one third embodiment BLKm among the memory blocks BLK1 to BLKz of FIG. FIG. 28 is a cross-sectional view taken along line III-III ′ of the memory block BLKm of FIG. Except that the n-type doping region 315 forming the common source line CSL is provided in a plate form, the memory block BLKm is similar to the memory block BLKi described with reference to FIGS. Composed. Illustratively, the n-type doping region 315 may be provided as an n-type well.

  The memory block BLKm may be implemented in the equivalent circuit described with reference to FIG. 6 or FIGS. The rising slopes of the program voltage Vpgm and the pass voltage Vpass provided to the word line of the memory block BLKm during the program operation are kept constant. Therefore, a decrease in read margin due to a difference in program speed can be prevented. The rising slopes of the selected read voltage Vrd and the non-selected read voltage Vread provided to the word line of the memory block BLKm during the read operation can be maintained constant. Thus, read disturb can be prevented.

  FIG. 29 is a perspective view showing a modification BLKm ′ of the memory block BLKm of FIG. FIG. 30 is a cross-sectional view taken along line IV-IV ′ of the memory block BLKm ′ of FIG. 29. Except that one pillar of the memory block BLKm ′ includes the first sub-pillar 113a and the second sub-pillar 113b, the memory block BLKm ′ is the same as the memory block BLKm described with reference to FIGS. .

  One pillar in the memory block BLKm ′ includes a first sub-pillar 113a and a second sub-pillar 113b. The first sub pillar 113a and the second sub pillar 113b are configured in the same manner as described with reference to FIGS. Similar to that described with reference to FIGS. 27 and 28, an n-type doping region 315 forming a common source line CSL is provided in a plate form.

  The memory block BLKm ′ may be implemented in the equivalent circuit described with reference to FIG. 6 or FIGS. The rising slopes of the program voltage Vpgm and the pass voltage Vpass provided to the word line of the memory block BLKm ′ during the program operation are adjusted to be constant. Therefore, a decrease in read margin due to a difference in program speed can be prevented. The rising slopes of the selected read voltage Vrd and the non-selected read voltage Vread provided to the word line of the memory block BLKm ′ during the read operation can be adjusted to be constant. Thus, read disturb can be prevented.

  FIG. 31 is a perspective view showing one fourth embodiment BLKn among the memory blocks BLK1 to BLKz of FIG. FIG. 32 is a cross-sectional view taken along line V-V ′ of the memory block BLKn in FIG. 31. Referring to FIGS. 31 and 32, the n-type doping region 315 forming the common source line CSL is provided in a plate shape as described with reference to FIGS.

  Compared with the memory block BLKi described with reference to FIGS. 3 and 4, the first conductive lines 221 'to 281' forming the word lines WL1 to WL7 are provided in a plate shape.

  The surface layer 116 ′ of each pillar 113 ′ includes an insulating film. The surface layer 116 ′ of the pillar 113 ′ is configured to store data similarly to the insulating film 116 described with reference to FIG. 5. For example, the surface layer 116 ′ includes a tunnel ring insulating film, a charge storage film, and a blocking insulating film. The intermediate layer 114 ′ of the pillar 113 ′ includes p-type silicon. The intermediate layer 114 'of the pillar 113' operates as a body in the second direction. The inner layer 115 ′ of the pillar 113 ′ includes an insulating material.

  Exemplarily, when the first conductive line 281 ′ having the eighth height is used as the string selection line SSL, the first conductive line 281 ′ having the eighth height is the first conductive line having the ninth height. It is divided in the same manner as 291 ′.

  The memory block BLKn may be implemented in the equivalent circuit described with reference to FIG. 6 or FIGS. The rising slopes of the program voltage Vpgm and the pass voltage Vpass provided to the word line of the memory block BLKn during the program operation are kept constant. Therefore, a decrease in read margin due to a difference in program speed can be prevented. The rising slopes of the selected read voltage Vrd and the non-selected read voltage Vread provided to the word lines of the memory block BLKn during the read operation can be kept constant. Thus, read disturb can be prevented.

  FIG. 33 is a perspective view showing a modification BLKn ′ of the memory block BLKn of FIG. FIG. 34 is a cross-sectional view taken along line VI-VI ′ of the memory block BLKn ′ of FIG. Except that one pillar of the memory block BLKn ′ includes the first sub-pillar 113a and the second sub-pillar 113b, the memory block BLKn ′ is the same as the memory block BLKn described with reference to FIGS. is there.

  One pillar in the memory block BLKn ′ includes a first sub pillar 113a and a second sub pillar 113b. The first sub pillar 113a and the second sub pillar 113b are configured in the same manner as described with reference to FIGS.

  The memory block BLKn ′ may be implemented in the equivalent circuit described with reference to FIG. 6 or FIGS. The rising slopes of the program voltage Vpgm and the pass voltage Vpass provided to the word line of the memory block BLKn ′ during the program operation are kept constant. Therefore, a decrease in read margin due to a difference in program speed can be prevented. The rising slopes of the selected read voltage Vrd and the non-selected read voltage Vread provided to the word line of the memory block BLKn ′ during the read operation can be maintained constant. Thus, read disturb can be prevented.

  FIG. 35 is a perspective view showing one fifth embodiment BLKo among the memory blocks BLK1 to BLKz of FIG. FIG. 36 is a cross-sectional view of the memory block BLKo of FIG. 35 taken along line VII-VII '.

  Referring to FIGS. 35 and 36, first to fourth upper word lines UW1 to UW4 extending in the first direction are sequentially provided on the substrate 111 along the second direction. The first to fourth upper word lines UW1 to UW4 are provided apart from each other by a specific distance along the second direction. A first upper pillar UP1 is provided that is spaced apart by a specific distance along the first direction and penetrates the first to fourth upper word lines UW1 to UW4 along the second direction.

  First to fourth lower word lines DW1 to DW4 extending along the first direction are formed in the second direction on the substrate 111 spaced apart from the first to fourth upper word lines UW1 to UW4 in the third direction. Provided sequentially along. The first to fourth lower word lines DW1 to DW4 are provided apart from each other by a specific distance along the second direction.

  A first lower pillar DP1 penetrating the first to third lower word lines DW1 to DW4 is provided at a specific distance along the first direction. A second lower pillar DP2 is provided that is spaced apart by a specific distance along the first direction and penetrates the first to fourth lower word lines DW1 to DW4 along the second direction. For example, the first lower pillar DP1 and the second lower pillar DP2 may be disposed in parallel along the second direction.

  The fifth to eighth upper word lines UW5 to UW8 extended along the first direction are sequentially formed along the second direction on the substrate 111 spaced apart from the lower word lines DW1 to DW4 in the third direction. Provided. The fifth to eighth upper word lines UW5 to UW8 are provided separated by a specific distance along the second direction. A second upper pillar UP2 is provided that is spaced apart by a specific distance along the first direction and penetrates the fifth to eighth upper word lines UW5 to UW8 along the second direction.

  A common source line CSL extended in the first direction is provided on the first and second lower pillars DP1 and DP2. Illustratively, the common source line CSL includes a silicon material having n type. For example, when the common source line CSL is made of a conductive material having no polarity, such as metal or polysilicon, an n type is provided between the common source line CSL and the first and second lower pillars DP1 and DP2. Additional sources can be provided. For example, the common source line CSL and the first and second lower pillars DP1 and DP2 may be connected through contact plugs.

  Drains 320 are respectively provided on the upper portions of the first and second upper pillars UP1 and UP2. Illustratively, the drain 320 includes a silicon material having an n type. A plurality of bit lines BL1 to BL3 extending along the third direction are sequentially provided on the drain 320 along the first direction. For example, the bit lines BL1 to BL3 are made of metal. For example, the bit lines BL1 to BL3 and the drain 320 may be connected through a contact plug.

  Each of the first and second upper pillars UP1, UP2 includes a surface layer 116 "and an inner layer 114". Each of the first and second lower pillars DP1, DP2 includes a surface layer 116 "and an inner layer 114". The surface layer 116 ″ is configured to store data in the same manner as the insulating film 116 described with reference to FIG. 5. For example, the first and second upper pillars UP1 and UP2, and the first and second lower portions. The surface layer 116 ″ of the pillars DP1 and DP2 includes a blocking insulating film, a charge storage film, and a tunneling insulating film.

  The tunnel insulating film includes a thermal oxide film. The charge storage film 118 includes a nitride film or a metal oxide film (for example, an aluminum oxide film or a hafnium oxide film). The blocking insulating film 119 can be formed in a single layer or multiple layers. The blocking insulating film 119 may be a high dielectric film (for example, an aluminum oxide film, a hafnium oxide film, etc.) having a higher dielectric constant than the tunnel insulating film and the charge storage film. For example, the tunnel insulating film, the charge storage film, and the blocking insulating film may constitute an ONO (oxide-nitride-oxide).

  The inner layers 114 ″ of the first and second upper pillars UP1 and UP2 and the first and second lower pillars DP1 and DP2 include a silicon material having p-type. The first and second upper pillars UP1, UP2, The inner layer 114 ″ of the first and second lower pillars DP1 and DP2 operates as a body in the second direction.

  In the substrate 111, the first upper pillar UP1 and the first lower pillar DP1 are connected through the first pipeline contact PC1. Exemplarily, the surface layer 116 "of the first upper pillar UP1 and the first lower pillar DP1 are connected through the surface layer of the first pipeline contact PC1. The surface layer of the first pipeline contact PC1 is the first upper pillar. The surface layer 116 ″ of the pillar UP1 and the first lower pillar DP1 is made of the same material.

  For example, the inner layers 114 ″ of the first upper pillar UP1 and the first lower pillar DP1 are connected through the inner layer of the first pipeline contact PC1. The surface layer of the first pipeline contact PC1 is the first layer. The inner pillar 114 ″ of the upper pillar UP1 and the first lower pillar DP1 is made of the same material.

  That is, the first upper pillar UP1 and the first to fourth upper word lines UW1 to UW4 form a first upper string, and the first lower pillar DP1 and the first to fourth lower word lines DW1 to DW4 are the first lower string. Form a string. The first upper string and the first lower string are connected through the first pipeline contact PC1. The drain 320 and the bit lines BL1 to BL3 are connected to one end of the first upper string. A common source line CSL is connected to one end of the first lower string. That is, the first upper string and the first lower string form a plurality of strings connected between the bit lines BL1 to BL3 and the common source line CSL.

  Similarly, the second upper pillar UP2 and the fifth to eighth upper word lines UW5 to UW8 form a second upper string, and the second lower pillar DP2 and the first to fourth lower word lines DW1 to DW4 are second. A lower string is formed. The second upper string and the second lower string are connected through the second pipeline contact PC2. The drain 320 and the bit lines BL1 to BL3 are connected to one end of the second upper string. A common source line CSL is connected to one end of the second lower string. That is, the second upper string and the second lower string form a plurality of strings connected between the bit lines BL1 to BL3 and the common source line CSL.

  The equivalent circuit of the memory block BLKo is the same as that of FIG. 6 except that eight transistors are provided in one string and two strings are connected to each of the first to third bit lines BL1 to BL3. . However, the number of word lines, bit lines, and strings in the memory block BLKo is not limited.

  Illustratively, first and second pipeline contact gates (not shown) may be provided to form a channel in an inner layer operating as a body with the first and second pipeline contacts PC1, PC2, respectively. Illustratively, first and second pipeline contact gates (not shown) are provided on the surfaces of the first and second pipeline contacts PC1, PC2.

  For the sake of simplicity, it has been described that the conductive lines UW1 to UW8 and DW1 to DW4 extended in the first direction are word lines. However, the upper word lines UW1 and UW8 adjacent to the bit lines BL1 to BL3 are used as the string selection line SSL.

  FIG. 37 is a block diagram illustrating a memory system 1000 including the nonvolatile memory devices 100 and 200 of FIG. Referring to FIG. 37, the memory system 1000 includes a nonvolatile memory device 1100 and a controller 1200.

  The nonvolatile memory device 1100 is configured and operates in the same manner as described with reference to FIGS. That is, the non-volatile memory device 1100 maintains a constant rising slope of the driving signal provided to the word line by generating a voltage that gradually increases to the target voltage (eg, Vpgm / Vpass or Vrd / Vread). Accordingly, read margin reduction and read disturb are prevented.

  The controller 1200 is connected to the host and nonvolatile memory device 1100. In response to a request from the host, the controller 1200 is configured to access the nonvolatile memory device 1100. For example, the controller 1200 is configured to control read, write, erase, and background operations of the non-volatile memory device 1100. The controller 1200 is configured to provide an interface between the nonvolatile memory device 1100 and the host. The controller 1200 is configured to drive firmware for controlling the nonvolatile memory device 1100.

  For example, the controller 1200 may further include widely known components such as a random access memory (RAM), a processing unit, a host interface, and a memory interface. The RAM is used as at least one of an operation memory of the processing unit, a cache memory between the nonvolatile memory device 1100 and the host, and a buffer memory between the nonvolatile memory device 1100 and the host. The processing unit controls various operations of the controller 1200.

  The host interface includes a protocol for performing data exchange between the host and the controller 1200. For example, the controller 1200 includes a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-E (PCI-express) protocol, an ATA (advanced technol t e nt e nt e n t e r e t e nt e n t e r a t e n e nt e n t e r e t e nt e n ent e nt e n t e t e r e t). -ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, and IDE (Integrated Drive Electronics) Configured to communicate with an external (host) through at least one among a variety of interfaces protocols such as protocols. The memory interface interfaces with the nonvolatile memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

  Memory system 1000 may be configured to additionally include error correction blocks. The error correction block is configured to detect and correct an error in data read from the nonvolatile memory device 1100 using an error correction code (ECC). Illustratively, the error correction block is provided as a component of the controller 1200. The error correction block may be provided as a component of the nonvolatile memory device 1100.

  The controller 1200 and the nonvolatile memory device 1100 can be integrated in one semiconductor device. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device to form a memory card. For example, the controller 1200 and the non-volatile memory device 1100 are integrated in one semiconductor device, and a PC card (PCMCIA, personal computer memory card international association), a compact flash (registered trademark) card (CF), a smart media card (SM, A memory card such as an SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMC-micro), an SD card (SD, miniSD, microSD, SDHC), a universal flash storage device (UFS) or the like is configured.

  The controller 1200 and the nonvolatile memory device 1100 can be integrated into one semiconductor device to constitute a semiconductor drive (SSD, Solid State Drive). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 10 is used as a semiconductor drive (SSD), the operation speed of the host connected to the memory system 1000 is dramatically improved.

  As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, a wireless tablet. A telephone (wireless phone), a mobile phone (mobile phone), a smart phone (smart phone), an e-book (e-book), a PMP (portable multimedia player), a portable game machine, a navigation device, a black box (black) box), digital camera (digital camera) 3D receiver (3-dimensional television), digital audio recorder, digital audio player, digital picture recorder, digital video player (digital video player) A digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, and one of a variety of electronic devices constituting a groove network, constituting a computer network One of a variety of electronic devices, one of a variety of electronic devices constituting a telematics network One of the various components of the electronic device, such as one of the various components constituting the RFID device or computing system.

  For example, the nonvolatile memory device 1100 or the memory system 1000 may be implemented in various forms of packages. For example, the non-volatile memory device 1100 or the memory system 1000 includes PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), and Plastic-In-DneP , Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQP) C), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), MultiChip Package (MCP), W It can be packaged and implemented in a scheme such as Level Processed Stack Package (WSP).

  FIG. 38 is a block diagram showing an application example of the memory system 1000 of FIG. Referring to FIG. 38, the memory system 2000 includes a nonvolatile memory device 2100 and a controller 2200. The nonvolatile memory device 2100 includes a plurality of nonvolatile memory chips. The plurality of nonvolatile memory chips are divided into a plurality of groups. Each group of the plurality of nonvolatile memory chips is configured to communicate with the controller 2200 through one common channel. In FIG. 38, the plurality of nonvolatile memory chips are illustrated as communicating with the controller 2200 through the first to kth channels CH1 to CHk.

  Each nonvolatile memory chip is configured similarly to the nonvolatile memory device 100 described with reference to FIGS. That is, the nonvolatile memory chip generates a voltage that gradually increases to the target voltage (for example, Vpgm / Vpass or Vrd / Vread), thereby maintaining a constant rising slope of the driving signal provided to the word line. Accordingly, read margin reduction and read disturbance are prevented.

  In FIG. 38, it has been described that a plurality of nonvolatile memory chips are connected to one channel. However, it can be understood that the memory system 2000 may be modified such that one nonvolatile memory chip is connected to one channel.

  FIG. 39 is a block diagram illustrating a computing system 3000 that includes the memory system 2000 described with reference to FIG. Referring to FIG. 39, the computing system 3000 includes a central processing unit 3100, a RAM 3200, a user interface 3300, a power source 3400, and a memory system 2000.

  The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300, and the power source 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

  In FIG. 39, the non-volatile memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200. However, the non-volatile memory device 2100 may be configured to be directly connected to the system bus 3500.

  39, the memory system 2000 described with reference to FIG. 38 is provided. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to FIG.

  Illustratively, the computing system 3000 may be configured to include all of the memory systems 1000, 2000 described with reference to FIGS.

  Although the detailed description of the present invention has been given with reference to specific embodiments, various modifications can be made without departing from the scope and technical idea of the present invention. Therefore, the scope of the present invention should not be defined by being limited to the above-described embodiments, and should be determined not only by the claims described later but also by the equivalents of the claims of the invention.

100, 200 ... Nonvolatile memory devices 110, 210 ... Memory cell array 120, 220 ... High voltage generator circuit 121 ... First voltage generator 122 ... Second voltage generator 123 ... Third voltage generator 124 ... Fourth voltage generator 130, 230 ... Row selection circuit 131 ... Word line driver 133 ... Row decoder 140, 240 ... Read and write circuits 150, 250 Data input / output circuits 160, 260 ... control logic 170, 270 ... ramping logic 171 ... first sub-ramping logic 172 ... second sub-ramping logic 173 ... third sub-ramping logic 174 ... 4th sub-ramping logic BLK1 to BLKz ... Memory block NS ... NAN String Vpgm · · · program voltage Vpass · · · pass voltage Vrd · · · select read voltage Vread · · · unselected read voltage VS_1 · · · first voltage signal VS_2 · · · second voltage signal

Claims (10)

A memory cell array including a plurality of memory cells stacked in a direction perpendicular to the substrate;
A row selection circuit connected to the memory cell array through a word line;
A voltage generating circuit for generating a voltage provided to the word line,
The non-volatile memory device, wherein the voltage generating circuit generates the voltage in a stepwise manner up to a target voltage level.   The nonvolatile memory device according to claim 1, wherein the voltage generation circuit generates a voltage signal that gradually increases to a pass voltage level during a program operation. The voltage generation circuit includes:
A first voltage generator for generating a first voltage signal that gradually increases to a program voltage level;
The nonvolatile memory device according to claim 1, further comprising: a second voltage generator that generates a second voltage signal that gradually increases to a pass voltage level.   The row selection circuit provides the second voltage signal as a driving signal to a non-selected word line among the word lines, and the driving signal provided to the non-selected word line has the same rising slope. The nonvolatile memory device according to claim 3, comprising:   The non-volatile memory device according to claim 1, wherein the voltage generation circuit generates a voltage signal that gradually increases to a non-selected read voltage level during a read operation. The voltage generation circuit includes:
A first voltage generator for generating a first voltage signal that increases stepwise to a selected read voltage level;
The non-volatile memory device according to claim 1, further comprising: a second voltage generator that generates a second voltage signal that gradually increases to a non-selected read voltage level.   The row selection circuit provides the second voltage signal as a driving signal to a non-selected word line among the word lines, and the driving signal provided to the non-selected word line has the same rising slope. The nonvolatile memory device according to claim 6. The voltage generation circuit includes:
A first voltage generator for generating a first voltage signal that gradually increases to a program voltage level;
A second voltage generator for generating a second voltage signal that gradually increases to a pass voltage level;
A third voltage generator for generating a third voltage signal that increases stepwise to a selected read voltage level;
The nonvolatile memory device according to claim 1, further comprising: a fourth voltage generator that generates a fourth voltage signal that increases stepwise up to a non-selected read voltage level.   The nonvolatile memory device of claim 1, further comprising a ramping logic that controls the voltage generation circuit to have different ramping step sizes according to a target voltage level of the voltage.   The nonvolatile memory device according to claim 1, wherein memory cells on a plane parallel to the substrate share the same word line.

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