JP2012165125A - Calibration circuit and analog-digital converter - Google Patents

Abstract

A technique for calibrating a large number of circuits having the same configuration with small area, low power, and high accuracy is provided.
In a calibration circuit, each comparator 2 ₁ to 2 _N has an analog voltage holding circuit 15 ₁ to 15 _N including a capacitor capable of holding an analog control voltage value for a certain period of time, and each comparator 2 ₁ to 2 _N. having each _N, as inputs and digital memory 12 ₁ to 12 _N which stores the current digital control value, the current digital control value stored in the digital memory 12 ₁ to 12 _N, the analog control voltage digital control value and one high-precision DAC 20 that converts a value, set in the order of the current digital control value stored in the digital memory ₁₂ 1 to 12 _N of the comparators ₂ 1 to 2 _N in the DAC 20, the analog And a controller 30 that periodically refreshes the capacitances of the voltage holding circuits 15 ₁ to 15 _N.
[Selection] Figure 4

Description

  The present invention relates to a calibration technique that compensates for characteristic variations of a large number of circuits having the same configuration, and more particularly, a calibration circuit that compensates for characteristic variations such as a large number of comparator circuits, and an ADC (analog-digital) having the calibration circuit. The present invention relates to a technique effective when applied to a converter.

For example, as an ADC having a large number of comparator circuits or the like, a fully parallel ADC or the like can be given as an example. As shown in an example of FIG. 1, for example, the basic configuration of a general all-parallel ADC includes ladder resistors 1 ₁ to 1 _{N + 1} connected between a power supply potential and a ground potential, and an input analog signal is a positive input terminal ( And a plurality of comparators 2 ₁ to 2 _{N to} which the reference voltages of the connection nodes of the ladder resistors 1 ₁ to 1 _{N + 1} are input to the negative input terminals (−), and these comparators 2 ₁ to 2 _N And a bubble removal circuit / encoder 3 that converts the thermometer code into a binary code and outputs the binary code as a digital signal.

  In such a fully parallel ADC, for example, it is formed on a semiconductor substrate and manufactured as an LSI. When the ADC is manufactured as an LSI, the variation in characteristics of a large number of comparators increases as the manufacturing process becomes finer, which may adversely affect AD conversion accuracy. Therefore, it is necessary to perform calibration to compensate for the characteristic variation of the comparator. As a technique for calibrating the comparator, for example, a technique described in Non-Patent Document 1 can be cited.

M.M. Miyahara, Y .; Asada, D.M. Park, and A.A. Matsuzawa, “A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs,” ASSCC Dig. Tech. Papers, pp. 269-272, Nov. 2008.

By the way, in the general all-parallel ADC described above, in the comparator variation compensation method, for example, as shown in FIG. 2, for example, the positive input terminal (+) and the negative input terminal (−) of the comparators 2 ₁ to 2 _N. Calibration of the comparators 2 ₁ to 2 _N using the first switches 4 ₁ to 4 _{N + 1} for switching the calibration mode connected to the output terminal of the calibration controller 5 connected to the output terminals of the comparators 2 ₁ to 2 _N Is done. At the time of calibration, the first switches 4 ₁ to 4 _{N + 1} short-circuit all the comparators 2 ₁ to 2 _N to the common voltage (Vcm) for both positive and negative inputs. In this state, the comparators 2 _{1 to} 2 _N are operated, and the offsets of the comparators 2 ₁ to 2 _N are adjusted so that the outputs of the comparators 2 ₁ to 2 _N output the H level and the L level with equal probability. . This compensates for variations in the comparators 2 ₁ to 2 _N.

As such a variation compensation method for the comparators 2 _{1 to} 2 _N , in the technique of Non-Patent Document 1 described above, a digital calibration method (FIG. 3 (a)) as shown in FIG. An analog calibration method (FIG. 3B) is used.

In the digital calibration method shown in FIG. 3A, the controller 5a is connected to the output (Dout) of the comparator 2 ₁ (the same applies to 2 ₂ to _2N ) and is controlled (UP / DOWN) by the controller 5a. a digital memory 5b that, DAC connected to the digital memory 5b - comprising a (digital analog converter) 5c, it is configured to calibrate the comparator _{2 1} by a voltage (Vcal) from the DAC5c. This digital calibration method has an advantage that the refresh is unnecessary because the digital memory 5b is used. However, since the DAC 5c is used, the DAC 5c is provided with the comparators 2 ₁ to 2 _N. One is required per one, and there is a disadvantage that the area becomes large.

In the analog calibration method shown in FIG. 3B, the controller 5d is connected to the output (Dout) of the comparator 2 ₁ (the same applies to 2 ₂ to 2 _N ) and is controlled (UP / DOWN) by the controller 5d. a charge pump circuit 5e that, an analog voltage holding circuit 5f connected to the charge pump circuit 5e, the comparator 2 ₁ in a configuration for calibrating the voltage stored in the capacitor Chold of the analog voltage holding circuit 5f (Vcal) is there. This analog calibration method has the advantage that fine control is possible because the charge pump circuit 5e is used, but on the other hand, because the capacitor Hold is used for the analog voltage holding circuit 5f, There is a drawback in that the capacity Hold needs to be refreshed and the power cannot be reduced.

  Therefore, the present invention makes use of the advantages of the digital calibration method and the analog calibration method described above in a calibration circuit that compensates for characteristic variations of a large number of identically configured circuits such as comparator circuits. The main purpose is to provide a technique for calibrating a circuit having a small area, low power, and high accuracy.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, in a calibration circuit that compensates for characteristic variations of a number of circuits having the same configuration (for example, a comparator circuit), the characteristics of each number of circuits can be varied by an analog control voltage value input from the outside. A voltage holding circuit including a capacity capable of holding an analog control voltage value for a certain period of time; a storage circuit storing a current digital control value for each circuit; and a current digital control value stored in the storage circuit , The digital control value is converted into an analog control voltage value and output, and the current digital control value stored in the storage circuit of each circuit is sequentially set in the DAC, and the voltage holding circuit And a control circuit for periodically refreshing the capacity of the device.

  Further, the number of DACs is not limited to one. For example, when a plurality of DACs are used, the configuration is as follows. In a calibration circuit that compensates for variations in characteristics of N (N is an integer of 3 or more) identically configured circuits (for example, comparator circuits), the characteristics of each of the N circuits are variable depending on an analog control voltage value input from the outside. A voltage holding circuit including a capacity capable of holding an analog control voltage value for a certain period of time, a storage circuit for storing a current digital control value for each circuit, and a storage circuit The M digital (M is an integer greater than or equal to 2 and M <N) and the M DACs are output by converting the digital control values into analog control voltage values. The current digital control values stored in the memory circuit of the first circuit among the N circuits are sequentially set in the first DAC, and the capacity of the voltage holding circuit is periodically refreshed. The current digital control values stored in the memory circuit of the second circuit different from the first circuit among the N circuits are sequentially set to the second DAC different from the first DAC among the DACs, and the voltage And a control circuit for periodically refreshing the capacity of the holding circuit.

  In addition, an ADC having a calibration circuit has a large number of comparator circuits having the same configuration and a calibration circuit that compensates for characteristic variations of the large number of comparator circuits. A voltage holding circuit including a capacity capable of holding the analog control voltage value for a certain period of time, which is variable for each analog control voltage value input from the outside, and for each comparator circuit, and a current digital for each comparator circuit A memory circuit that stores a control value, and the current digital control value stored in the memory circuit as an input, and the digital control value is converted into an analog control voltage value and output. A plurality of DACs are stored in the storage circuit of each comparator circuit. It is set in the order of the current digital control value, and having a control circuit for periodically refreshing the capacity of the voltage holding circuit.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In other words, in a calibration circuit that compensates for characteristic variations of a large number of identically configured circuits such as comparator circuits, it is possible to provide a technique for performing calibration of a large number of identically configured circuits with a small area, low power, and high accuracy. it can.

It is a figure which shows an example of the basic composition of a general all parallel type ADC. FIG. 2 is a diagram for explaining an example of a method for compensating for variation in a comparator in the general all parallel ADC of FIG. 1. As a comparator variation compensation method of Non-Patent Document 1, (a) illustrates a digital calibration method, and (b) illustrates an example of an outline of an analog calibration method. FIG. 5 is a diagram illustrating an example of a configuration of a calibration circuit of a comparator in the all parallel ADC according to the first embodiment of the present invention. In the fully parallel ADC according to the second embodiment of the present invention, as an example of the configuration of a comparator calibration circuit, (a) shows a configuration of a comparator slice, and (b) shows a configuration of an LPF. In the fully parallel ADC according to the third embodiment of the present invention, (a) shows an example of the configuration of the analog voltage holding circuit part constituting the calibration circuit of the comparator, and (b) shows a comparison of calibration voltage holding times. It is a figure for demonstrating an example of the voltage change speed of a node. FIG. 10 is a diagram illustrating an example of a configuration of a calibration circuit of a comparator in the all parallel ADC according to the fourth embodiment of the present invention.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of embodiments or sections. However, unless otherwise specified, they are not irrelevant and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

<Outline of Embodiment of the Present Invention>
[First Outline of Embodiment]
The calibration circuit according to the embodiment of the present invention is a calibration circuit that compensates for variations in characteristics of a large number of circuits (comparators) having the same configuration, and the characteristics of the numerous circuits are variable depending on an analog control voltage value input from the outside. A voltage holding circuit (analog voltage holding circuit) including a capacity capable of holding an analog control voltage value for a certain period of time, and a storage circuit storing current digital control values for each circuit. (Digital memory), one DAC (high-accuracy DAC) that converts the digital control value into an analog control voltage value and outputs the current digital control value stored in the storage circuit, and the DAC The current digital control value stored in the memory circuit of each circuit is set in order, and the capacity of the voltage holding circuit is periodically refreshed. And a control circuit (controller). It is characterized by an ADC (all parallel ADC) having this calibration circuit. The first outline of the present embodiment corresponds to the first to third embodiments described later.

[Second Outline of Embodiment]
The calibration circuit according to the embodiment of the present invention is a calibration circuit that compensates for characteristic variations of N (N is an integer of 3 or more) identically configured circuits (comparators). A voltage holding circuit (analog voltage holding circuit) including a capacity capable of holding the analog control voltage value for a certain period of time, which can be varied according to an analog control voltage value input from the outside, and each circuit, A memory circuit (digital memory) for storing the current digital control value, and M (M) that converts the digital control value into an analog control voltage value and outputs the current digital control value stored in the storage circuit as an input Is an integer of 2 or more, M <N) DAC (high-precision DAC), and the first DAC of the M DACs is the memory circuit of the first circuit among the N circuits. The stored current digital control values are set in order, the capacity of the voltage holding circuit is periodically refreshed, and the second DAC, which is different from the first DAC among the M DACs, is switched to the first of the N circuits. A control circuit (controller) that sequentially sets the current digital control values stored in the memory circuit of the second circuit different from the one circuit and periodically refreshes the capacity of the voltage holding circuit; It is characterized by an ADC (all parallel ADC) having this calibration circuit. The second outline of the present embodiment corresponds to a fourth embodiment described later.

  Each embodiment will be specifically described below based on the outline of the embodiment of the present invention described above. The embodiment described below is an example using the present invention, and the present invention is not limited to the following embodiment.

[Embodiment 1]
A first embodiment of the present invention will be described with reference to FIG.

<Configuration of calibration circuit>
First, an example of the configuration of the calibration circuit of the comparator in the all parallel ADC according to the first embodiment will be described with reference to FIG. FIG. 4 is a diagram showing an example of the configuration of the calibration circuit of the comparator.

The comparator calibration circuit shown in FIG. 4 includes N comparator slices (1) 10 ₁ to (N) 10 _N corresponding to the number of comparators, and one common to these comparator slices 10 ₁ to 10 _N. It comprises a high-accuracy DAC 20 and a controller 30 that controls the calibration of these comparator slices 10 ₁ to 10 _N.

The comparator slice ₍₁₎ 10 1 ~ (N) 10 _N, for example, a comparator slice (1) 10 _1, a comparator _{2 1,} the positive input terminal of the comparator _{2 1} (+), a negative input terminal -, respectively () The first switches 4 ₁ and 4 ₂ for switching the calibration mode to be connected, the digital counter 11 ₁ whose input terminal is connected to the output terminal of the comparator 2 ₁ , and the input terminal of this digital counter 11 ₁ is the input terminal. a digital memory 12 ₁ connected, one end to the output terminal of the digital memory 12 ₁ is connected to the second switch 13 ₁ for calibration mode switching the other end is connected to the input terminal of the DAC 20, the output of the DAC 20 a third switch 14 ₁ for calibration mode switching one end to the terminal is connected, The third consists of an analog voltage holding circuit 15 _1, including the capacity Chold connected to the control terminal of the comparator 2 ₁ with one end connected to the other end of the switch 14 _1.

This comparator slice (1) 10 ₁ other than the other comparators slice ₍₂₎ 10 2 ~ (N) 10 _N also comparators slice (1) 10 ₁ the same configuration (the comparator ₂ 2 to 2 _N, the first switch 4 ₃ to 4 _{N + 1} , digital counters 11 _{2 to} 11 _N , digital memories 12 _{2 to} 12 _N , second switches 13 _{2 to} 13 _N , third switches 14 _{2 to} 14 _N , analog voltage holding circuits 15 ₂ to 15 _N ) It has become. In the following, mainly described comparator slice (1) 10 ₁ Example.

The first switch ₄ 1, _{4 2,} under the control of the controller 30, the positive input terminal (+) side of the comparator _{2 1} is switched to the input analog signal or the common voltage (Vcm), the comparator _{2 1} negative input terminal (- ) Side is a switch for switching a calibration mode which can be switched to a reference voltage input or a common voltage (Vcm). In a state where the first switch 4 _1, 4 ₂ are switched input analog signal, to the reference voltage input, to the input of the analog signal to the comparator 2 ₁ positive input terminal (+), the reference voltage of the comparator 2 ₁ negative input terminal Input to (-). On the other hand, in the state where the first switch ₄ 1, _{4 2} is switched to the common voltage (Vcm), the comparator _{2 1} positive input terminal (+) and the negative input terminal (-) to both shorted to the common voltage (Vcm).

Digital counter 11 ₁ is a digital counter to increase or decrease the current digital control value stored in the digital memory 12 ₁ based on the comparator 2 ₁ comparison result, the output signal from the comparator 2 ₁ (Dout1) based on the counts H level or L level, so that the H level and the L level becomes equal probability, a counter for outputting the UP signal or DOWN signal to a digital memory 12 _1.

Digital memory 12 ₁ is a storage circuit that stores the current digital control value, based on the UP signal or DOWN signal from the digital counter 11 _1, in the case of UP signal is calibrated value is +1, if the DOWN signal Is a memory in which the calibration value is decremented by ₁ , and the calibration value after being incremented by +1 or -1 is output to the DAC 20 via the second switch 131.

The second switch 13 ₁ is controlled by the controller 30, a switch for calibration mode switching ON / OFF is controlled. In the second switch 13 ₁ is turned ON, the output terminal of the digital memory 12 ₁ connected to the input terminal of the DAC 20, to output the calibration value from the digital memory 12 ₁ to DAC 20. On the other hand, in the second switch 13 ₁ is the OFF state, between the input terminals of the output terminal and DAC20 digital memory 12 ₁ is cut off.

The third switch 14 ₁ is controlled by the controller 30, a switch for calibration mode switching ON / OFF is controlled. The third switch 14 ₁ is turned ON, by connecting the output terminal and the analog voltage holding circuit 15 ₁ of the DAC 20, to accumulate the analog voltage based on the analog signal from the DAC 20 to an analog voltage holding circuit 15 ₁ capacity Chold . On the other hand, the third switch 14 ₁ is in the OFF state, between the output terminal and the analog voltage holding circuit 15 ₁ of DAC20 is blocked.

Analog voltage holding circuit 15 _1, a voltage holding circuit comprising an analog control voltage value for a predetermined period of time capable of holding capacity Chold, the comparator 2 ₁ by the voltage accumulated in the capacitor Chold included in the analog voltage holding circuit 15 ₁ A circuit for calibration.

DAC20 is input with current digital control value stored in the digital memory 12 _1, the digital control value to a DAC that converts the analog control voltage value, the digital calibration values from the digital memory 12 ₁ an analog converter - converts the signal into an analog signal, the voltage of the analog signal, the third high-precision digital to accumulate the analog voltage holding circuit 15 ₁ capacity Chold connected via a switch 14 _1. The DAC 20 has high accuracy due to, for example, a large number of bits.

The controller 30 sets the order of the current digital control value stored in the digital memory 12 ₁ to DAC 20, a capacitor Chold of the analog voltage holding circuit 15 ₁ and a control circuit for periodically refreshing, first to This is a calibration controller that controls the third switches 4 ₁ , 4 ₂ , 13 ₁ , and 14 ₁ with a selection control signal (SEL1). The first switch 4 _1, 4 _2, an analog signal is input to the comparator 2 ₁ positive input terminal (+), the reference voltage comparator 2 ₁ negative input terminal - is controlled to a state that is input to the (). The second switch 13 ₁ and the third switch 14 ₁ is controlled to the respective ON / OFF states.

The calibration circuits of the comparators 2 ₁ to 2 _N as described above are configured as fully parallel ADCs having this calibration circuit. In this fully parallel type ADC, ladder resistors 1 ₁ to 1 _{N + 1} connected between a power supply potential and a ground potential, and an input analog signal are input to a positive input terminal (+), and ladder resistors 1 ₁ to 1 _{N + 1} are respectively connected. The reference voltage of the connection node is processed based on the above-described comparators 2 ₁ to 2 _N inputted to the respective negative input terminals (−) and outputs (Dout ₁ to DoutN) from these comparators 2 ₁ to 2 _N , and bubble Along with the removal, the thermometer code is converted into a binary code, and this binary code is output as a digital signal (not shown) (illustrated in FIG. 1).

In the ladder resistor 1 ₁ to 1 N + _1, for example, ladder resistor 1 _{N + 1} of the ladder resistor 1 ₁ and connected to a ground potential that is connected to the power supply potential, as compared to the ladder resistor 1 ₂ to 1 _N connected between them The resistance value is set to R / 2.

  Such a fully parallel ADC is manufactured as a single LSI (semiconductor device) by being formed on a semiconductor substrate such as a single crystal silicon substrate by a semiconductor integrated circuit manufacturing technique, for example.

<Calibration cycle (at normal ADC operation)>
During the ADC normal operation in the calibration cycle, the comparators 2 ₁ to 2 _N perform calibration using the analog voltage from the high-accuracy DAC 20 and the voltage accumulated in the capacitor Hold of the analog voltage holding circuits 15 ₁ to 15 _N. The output of this high-accuracy DAC 20 is switched in order so that it becomes the calibration voltage of each of the comparators 2 ₁ to 2 _N , and the analog voltages for calibration of the many comparators 2 ₁ to 2 _N are periodically refreshed. To do. During the normal ADC operation in this calibration cycle, the following operation sequence is performed.

(1) to the second switch ₁₃ 1 to 13 _N, all of the third switch ₁₄ 1 to 14 _N OFF of the comparators slice _{(1) 10 1 ~ (N} ) 10 N.

(2) reads the calibration value of the comparator slice (1) 10 ₁ of the comparator 2 ₁ from the digital memory 12 _1, the digital signal of the calibration value is converted into high-precision DAC20 an analog signal, and outputs the analog voltage .

(3) The second switch 13 ₁ and the third switch 14 ₁ of the comparator slice (1) 10 ₁ are turned ON. The timing at which the second switch 13 ₁ and the third switch 14 ₁ are turned on is after the highly accurate DAC 20 value is switched.

It performs the (1) to (3), the comparator slice (1) 10 ₁ of the comparator _{2 1,} repeatedly until the comparator slice (N) 10 _N of the comparator _{2 N.}

  As described above, the ADC normal operation in the calibration cycle is performed.

<Calibration cycle (during calibration operation)>
At the time of the calibration operation in the calibration cycle, the positive input terminal (+) = the negative input terminal (−) = 0.5V to all the comparators 2 ₁ to 2 _N of the respective comparator slices (1) 10 ₁ to (N) 10 _N. Enter. Then, the comparators 2 _{1 to} 2 _N are operated, and the comparison result is calibrated so that the L level and the H level have an equal probability. The following operation sequence is performed during the calibration operation in this calibration cycle.

(1) to the second switch ₁₃ 1 to 13 _N, all of the third switch ₁₄ 1 to 14 _N OFF of the comparators slice _{(1) 10 1 ~ (N} ) 10 N. Also, the digital counters 11 _{1 to} 11 _N are reset.

(2) reads the current calibration value of the comparator slice (1) 10 ₁ of the comparator 2 ₁ from the digital memory 12 _1, the digital signal of the calibration value with high precision DAC20 into an analog signal, the analog voltage Output.

(3) The third switch 14 ₁ of the comparator slice (1) 10 ₁ is turned ON. Timing of the third switch 14 ₁ to ON, and the switched value of the highly accurate DAC 20.

(4) The second switch 13 ₁ of the comparator slice (1) 10 ₁ is turned ON. Furthermore, to reset the digital counter 11 _1.

(5) a calibration value by ± 1 in accordance with the H level / L level of the output of the digital counter 11 ₁ is written back to the digital memory 12 _1.

(6) and the second switch 13 ₁ of the comparator slice (1) 10 ₁ to OFF, followed by the third switch 14 ₁ to OFF.

Performs the (1) to (6) from the comparator slice (1) 10 ₁ of the comparator _{2 1,} repeatedly until the comparator slice (N) 10 _N of the comparator _{2 N.}

  As described above, the calibration operation in the calibration cycle is performed.

<Effect of Embodiment 1>
According to the calibration circuits of the comparators 2 ₁ to 2 _N in the all-parallel ADC of the first embodiment described above, N comparator slices (1) 10 ₁ to 10 corresponding to the number of the comparators 2 ₁ to 2 _N are obtained. (N) and 10 _N, 1 single highly accurate DAC20 common to these comparators slice ₁₀ 1 to 10 _N, that it has a like controller 30 which controls the calibration of these comparators slice ₁₀ 1 to 10 _N use with time division of a high-precision DAC 20, the calibration of a number of comparators 2 ₁ to 2 _N can be accurately performed. In addition, the capacitor Hold for calibration of the comparators 2 ₁ to 2 _N can be periodically refreshed by one high-accuracy DAC 20. In addition, since there is one highly accurate DAC 20, the area can be reduced.

[Embodiment 2]
A second embodiment of the present invention will be described with reference to FIG.

  The second embodiment is different from the first embodiment in that UP / DOWN averaging is performed using an analog LPF and a binary quantizer instead of a digital counter. In the following, this different point will be mainly described.

<Configuration of calibration circuit>
Based on FIG. 5, an example of the configuration of the calibration circuit of the comparator in the fully parallel ADC according to the second embodiment will be described. FIG. 5 is a diagram showing an example of the configuration of the calibration circuit of this comparator.

Shown in FIG. 5 (a) calibration circuit comparators, each comparator slice ₍₁₎ 10 1 ~ (N) 10 _N (illustrated comparator slice (1) 10 ₁ in this case, other comparators slice (2) 10 ₂ in ~ (N) also applies to 10 _N), the input terminal of the comparator _{2 1} of the output terminal to the LPF (low-pass filter) 16 ₁ is connected, the binary input of the quantizer 17 ₁ to the output terminal of the LPF 16 ₁ terminal is connected, the input terminal of the digital memory 12 ₁ has become connected to each output terminal of the binary quantizer 17 _1.

LPF 16 ₁ is an active LPF using inverters, as shown in FIG. 5 (b) in detail, one end of the resistor 16b to the input terminal of the inverter 16a is connected also to the input terminal of the inverter 16a and the output terminal A capacitor 16c and a reset input switch 16d are connected in parallel. The reset input switch 16d is ON / OFF controlled by a selection control signal (SEL1) from the controller 30.

Binary quantizer 17 ₁ is a binary quantizer by the inverter.

For example, a CMOS inverter or the like can be used for the LPF 16 ₁ and the binary quantizer 17 ₁ .

Performs averaging processing of UP / DOWN using this LPF 16 ₁ a binary quantizer 17 _1, by outputting the processing result to the digital memory 12 _1, the calibration value of the digital memory 12 ₁ is +1 or -1 Is done.

<Effect of Embodiment 2>
In the calibration circuit of the comparators 2 ₁ to 2 _N in the all-parallel ADC of the second embodiment described above, the same effect as that of the first embodiment can be obtained, and the LPFs 16 _{1 to} 16 _N and the binary quantum can be obtained. By using a CMOS inverter for each of the generators 17 _{1 to} 17 _N , the area and power can be reduced compared to a configuration using a normal current-driven operational amplifier.

[Embodiment 3]
A third embodiment of the present invention will be described with reference to FIG.

  In the third embodiment, compared to the first and second embodiments, a fourth switch and a capacitor are added between the high-accuracy DAC and the third switch in the previous stage of the analog voltage holding circuit, so that the charge However, in the following, this different point will mainly be described.

<Configuration of calibration circuit>
Based on FIG. 6, in the all-parallel ADC of the third embodiment, an example of the configuration of the analog voltage holding circuit part constituting the calibration circuit of the comparator, comparison of calibration voltage holding time, and node voltage change An example of the speed will be described. FIG. 6A is a diagram showing an example of the configuration of the analog voltage holding circuit portion constituting the calibration circuit of the comparator.

Calibration circuit of the comparator shown in FIG. 6 (a), the comparators slice ₍₁₎ 10 1 ~ (N) 10 _N (illustrated comparator slice (1) 10 ₁ in this case, other comparators slice (2) 10 ₂ in ~ (N) also applies to 10 _N), the fourth switch 18 ₁ of the one end connected to the output terminal of the high-accuracy DAC 20, with one end of the capacitor C2 to the fourth switch 18 ₁ of the other end connected the third switch 14 ₁ of the one end is connected, a control terminal of the comparator 2 ₁ has become connected to each one end of the capacitor Cmain to the third switch 14 ₁ of the other end is connected.

In other words, in front of the capacitor Cmain, by connecting a capacitor C2 of the small capacitance value than the capacitance Cmain (e.g. capacitance value of about 10% to 30% of the capacitance of the capacitor Cmain), a third switch 14 ₁ switch fourth divided into two switches 18 _1. The third switch 14 ₁ and the fourth switch 18 ₁ is turned ON / OFF by the same control signal (SEL1) from the controller 30.

  In this way, even when the two switches are not completely turned off and there is a leak, the voltage change at the node n2 is slowed down by the capacitor C2, so that the speed at which the charge of the capacitor Cmain is released becomes slow, and the calibration voltage The holding time of (Vcal) becomes long. FIG. 6B is a diagram for explaining this.

  FIG. 6B shows the comparison between the calibration voltage (Vcal) according to the third embodiment and the holding time of the calibration voltage (Vcal) according to the first and second embodiments, and the node n2 according to the third embodiment. It is a figure for demonstrating an example of a voltage change speed. In the example of FIG. 6B, the total sum of the capacitance values in the case of two capacitors C2 and Cmain as in the third embodiment and in the case of one capacitor Hold as in the first and second embodiments. Are the same. That is, the capacitance value of the capacitor C2 + the capacitance value of the capacitor Cmain is equal to the capacitance value of the capacitor Hold.

  As can be seen from FIG. 6B, the holding time of the calibration voltage (Vcal) according to the third embodiment can be made longer than the calibration voltage (Vcal) according to the first and second embodiments.

<Effect of Embodiment 3>
In the calibration circuit of the comparators 2 ₁ to 2 _N in the all-parallel ADC of the third embodiment described above, the same effects as those of the first and second embodiments can be obtained, and the fourth switches 18 ₁ to 18 can be obtained. By adding _N and a capacitor C2 to form a capacitor arrangement in which charges are not easily lost, the holding time of the calibration voltage (Vcal) can be extended.

[Embodiment 4]
A fourth embodiment of the present invention will be described with reference to FIG.

  The fourth embodiment is different from the first to third embodiments in that a plurality of DACs (a plurality less than the total number of comparators) are used. The following mainly describes the differences. To do.

<Configuration of calibration circuit>
Based on FIG. 7, an example of the configuration of the calibration circuit of the comparator in the all parallel ADC of the fourth embodiment will be described. FIG. 7 is a diagram showing an example of the configuration of the calibration circuit of the comparator.

The comparator calibration circuit shown in FIG. 7 includes N comparator slices (1) 10 ₁ to (N) 10 _N corresponding to the number of comparators, and these comparator slices (1) 10 ₁ to (N) 10 _N. Among them, one high-precision DAC 20a common to the comparator slices (1) 10 ₁ to (N / 2) 10 _{N / 2} and the comparator slice (N / 2 + 1) 10 _{N / 2 + 1} to (N) 10 _N And a controller 30 for controlling calibration of these comparator slices (1) 10 ₁ to (N) 10 _N , and the like.

That is, in the fourth embodiment, two DACs 20a and 20b are provided, and an analog signal voltage is output from one DAC 20a to the comparator slices (1) 10 ₁ to (N / 2) 10 _{N / 2} . For the comparator slices (N / 2 + 1) 10 _{N / 2 + 1} to (N) 10 _N , the analog signal voltage is output from the other DAC 20 b. Others are the same as those of the first embodiment, and the description thereof is omitted here.

  Further, in the fourth embodiment, as in the second embodiment, a configuration for performing an UP / DOWN averaging process using an analog LPF and a binary quantizer, as in the third embodiment. Needless to say, it is also possible to add a fourth switch and a capacitor between the high-accuracy DAC and the third switch in the previous stage of the analog voltage holding circuit so as to have a capacitance arrangement in which charges are not easily removed. .

<Effect of Embodiment 4>
Even in the calibration circuits of the comparators 2 ₁ to 2 _N in the all-parallel ADC of the fourth embodiment described above, the number of high-accuracy DACs 20a and 20b is increased to two and the area is slightly increased. The effect similar to 1-3 can be acquired.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to fourth embodiments, the calibration circuit of the comparator in the fully parallel ADC has been described as an example. However, the calibration circuit of the comparator in the ADC of another type, the DAC is not limited to the ADC, and the like. The present invention can be widely applied to calibration techniques having a large number of circuits having the same configuration and compensating for variations in characteristics of these circuits.

  The calibration technique of the present invention is effective when applied to a calibration circuit that compensates for characteristic variations such as a large number of comparator circuits, and an ADC having the calibration circuit, and is also widely applicable to a DAC or the like. .

1 ₁ to 1 _{N + 1} ... Ladder resistance, 2 ₁ to 2 _N ... Comparator, 3 ... Bubble removal circuit / encoder, 4 ₁ to 4 _{N + 1} ... First switch, 5 ... Calibration controller, 5a ... Controller, 5b ... Digital memory, 5c ... DAC, 5d ... controller, 5e ... charge pump circuit, 5f ... analog voltage holding circuit,
10 ₁ to 10 _N : Comparator slice, 11 _{1 to} 11 _N ... Digital counter, 12 _{1 to} 12 _N ... Digital memory, 13 _{1 to} 13 _N ... Second switch, 14 _{1 to} 14 _N ... Third switch, 15 ₁ to 15 N _... analog voltage holding _{circuit, 16 1 ~16 N ... LPF,} 16a ... inverter, 16b ... resistance, 16c ... capacitor, 16d ... _switch, 17 1 _{~17 N} ... 2 value _quantizer, 18 1 _{~18 N} ... The fourth switch,
20 ... DAC, 20a, 20b ... DAC,
30: Controller.

Claims (17)

A calibration circuit that compensates for characteristic variations of a number of identically configured circuits,
The characteristics of each of the multiple circuits can be varied by an analog control voltage value input from the outside,
A voltage holding circuit including a capacitor capable of holding the analog control voltage value for a certain period of time for each circuit;
A storage circuit for storing the current digital control value for each circuit;
One DAC that receives the current digital control value stored in the storage circuit as an input, converts the digital control value into the analog control voltage value, and outputs the DAC.
A calibration circuit comprising: a control circuit that sequentially sets current digital control values stored in the storage circuit of each circuit in the DAC and periodically refreshes the capacitance of the voltage holding circuit. circuit. The calibration circuit according to claim 1,
Each of the circuits is a comparator circuit. The calibration circuit according to claim 2,
During the calibration operation of each comparator circuit, the comparison result of each comparator circuit is stored in the storage circuit based on the comparison result of each comparator circuit so that the L level and the H level have equal probability. A calibration circuit, further comprising a digital counter for increasing or decreasing a current digital control value for each of the comparator circuits. The calibration circuit according to claim 2,
During the calibration operation of each comparator circuit, the comparison result of each comparator circuit is stored in the storage circuit based on the comparison result of each comparator circuit so that the L level and the H level have equal probability. A calibration circuit, further comprising an LPF and a binary quantizer for increasing or decreasing a current digital control value for each comparator circuit. The calibration circuit according to claim 2,
Between the DAC and each comparator circuit, a first capacitor and a second capacitor are connected in order from the DAC side to each comparator circuit side via each switch.
The calibration circuit according to claim 1, wherein a capacitance value of the first capacitor is smaller than a capacitance value of the second capacitor. The calibration circuit according to claim 2,
During the calibration operation of each comparator circuit,
The same voltage is input to each comparator circuit,
Operate each comparator circuit under the set value of the current digital control value stored in the storage circuit, and the comparison result of each comparator circuit has an equal probability between the L level and the H level. A calibration circuit characterized in that the set value of the current digital control value stored in the storage circuit is incremented by ± 1 based on the comparison result of each comparator circuit. A calibration circuit that compensates for characteristic variations of N (N is an integer of 3 or more) identically configured circuits,
The characteristics of each of the N circuits can be changed by an analog control voltage value input from the outside,
A voltage holding circuit including a capacitor capable of holding the analog control voltage value for a certain period of time for each circuit;
A storage circuit for storing the current digital control value for each circuit;
M DACs (M is an integer greater than or equal to 2 and M <N) which converts the digital control value into the analog control voltage value and outputs the current digital control value stored in the storage circuit. When,
The current digital control value stored in the memory circuit of the first circuit among the N circuits is sequentially set in the first DAC of the M DACs, and the capacity of the voltage holding circuit is periodically set. Refreshed and stored in the memory circuit of the second circuit different from the first circuit of the N circuits in the second DAC different from the first DAC of the M DACs. And a control circuit that sets the digital control values in order and periodically refreshes the capacitance of the voltage holding circuit. The calibration circuit according to claim 7, wherein
Each of the circuits is a comparator circuit. The calibration circuit according to claim 8, wherein
During the calibration operation of each comparator circuit, the comparison result of each comparator circuit is stored in the storage circuit based on the comparison result of each comparator circuit so that the L level and the H level have equal probability. A calibration circuit, further comprising a digital counter for increasing or decreasing a current digital control value for each of the comparator circuits. The calibration circuit according to claim 8, wherein
During the calibration operation of each comparator circuit, the comparison result of each comparator circuit is stored in the storage circuit based on the comparison result of each comparator circuit so that the L level and the H level have equal probability. A calibration circuit, further comprising an LPF and a binary quantizer for increasing or decreasing a current digital control value for each comparator circuit. The calibration circuit according to claim 8, wherein
Between the DAC and each comparator circuit, a first capacitor and a second capacitor are connected in order from the DAC side to each comparator circuit side via each switch.
The calibration circuit according to claim 1, wherein a capacitance value of the first capacitor is smaller than a capacitance value of the second capacitor. The calibration circuit according to claim 8, wherein
During the calibration operation of each comparator circuit,
The same voltage is input to each comparator circuit,
Operate each comparator circuit under the set value of the current digital control value stored in the storage circuit, and the comparison result of each comparator circuit has an equal probability between the L level and the H level. A calibration circuit characterized in that the set value of the current digital control value stored in the storage circuit is incremented by ± 1 based on the comparison result of each comparator circuit. A number of comparator circuits of the same configuration;
An analog-to-digital converter having a calibration circuit that compensates for variations in characteristics of the multiple comparator circuits,
The calibration circuit includes:
The characteristics of each of the multiple comparator circuits can be varied according to an analog control voltage value input from the outside.
A voltage holding circuit including a capacitor capable of holding the analog control voltage value for a certain period of time for each comparator circuit;
A storage circuit for storing the current digital control value for each comparator circuit;
One or a plurality of DACs less than the total number of the comparator circuits, which receives the current digital control value stored in the storage circuit as an input, converts the digital control value into the analog control voltage value, and outputs the analog control voltage value; ,
An analog circuit comprising: a control circuit configured to sequentially set a current digital control value stored in the storage circuit of each comparator circuit in the DAC and periodically refresh the capacitance of the voltage holding circuit; A digital converter. The analog-to-digital converter of claim 13.
The calibration circuit includes:
During the calibration operation of each comparator circuit, the comparison result of each comparator circuit is stored in the storage circuit based on the comparison result of each comparator circuit so that the L level and the H level have equal probability. An analog-to-digital converter, further comprising a digital counter for increasing or decreasing a current digital control value for each of the comparator circuits. The analog-to-digital converter of claim 13.
The calibration circuit includes:
During the calibration operation of each comparator circuit, the comparison result of each comparator circuit is stored in the storage circuit based on the comparison result of each comparator circuit so that the L level and the H level have equal probability. An analog-to-digital converter, further comprising an LPF and a binary quantizer for increasing or decreasing a current digital control value for each comparator circuit. The analog-to-digital converter of claim 13.
Between the DAC and each comparator circuit, a first capacitor and a second capacitor are connected in order from the DAC side to each comparator circuit side via each switch.
The analog-digital converter characterized in that the capacitance value of the first capacitor is smaller than the capacitance value of the second capacitor. The analog-to-digital converter of claim 13.
During the calibration operation of each comparator circuit,
The same voltage is input to each comparator circuit,
Operate each comparator circuit under the set value of the current digital control value stored in the storage circuit, and the comparison result of each comparator circuit has an equal probability between the L level and the H level. An analog-digital converter characterized in that the set value of the current digital control value stored in the storage circuit is incremented by ± 1 based on the comparison result of each comparator circuit.

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