JP2012164872A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent wiring that should be left from being etched by a resist film thickness reduction, and prevent wire linewidth variations by suppressing a focus deviation during wire patterning by an exposure machine.SOLUTION: In a scribe line, a region where interlayer insulating films 2, 4 and 6 do not exist on both sides of the scribe line and a surface of a semiconductor substrate 1 is exposed is provided, and the interlayer insulting films 2, 4 and 6 are left at a middle position of the scribe line, namely in a region held between grooves T. This suppresses a film thickness reduction of a resist 21 used as a mask during formation of a third wiring layer 7, in the vicinity of a boundary position between the scribe line and a chip. It is therefore capable of preventing the wire that should be left from being etched by the film thickness reduction of the resist 21, and preventing a focus deviation during patterning of the third wiring layer 7 by an exposure machine, thereby preventing the occurrence of linewidth variations of the third wiring layer 7.

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor device is manufactured by forming a semiconductor element on a semiconductor substrate and then cutting the semiconductor element into chip units by cutting along a scribe line.

  Conventionally, after forming a semiconductor device on a semiconductor substrate, a wiring pattern for electrical connection with the semiconductor device is formed, and this is covered with a protective film such as a nitride film and then cut with a scribe line. Thus, the semiconductor device is manufactured by dividing into chips. When cutting into chips, if the protective film is hard and the protective film is present at the cutting position, problems such as chipping (minute chipping) and deterioration of the dicing blade are caused. Further, when the semiconductor chip is resin-molded, film peeling occurs between the respective interlayer insulating films or between the interlayer insulating film and the protective film on the chip end surface that is diced by the stress of the mold resin after molding.

  For this reason, a structure is adopted in which grooves are formed by removing the interlayer insulating film on the scribe line for dicing, and the edge of each interlayer insulating film is covered with the uppermost protective film on the chip end surface. (For example, refer to Patent Document 1).

JP-A-5-41450

  In order to dig a groove without making a dedicated process for forming a groove in the scribe line and without increasing the cost, it is necessary to also etch the interlayer insulating film on the scribe line at the time of via-hole etching connecting the wirings of each layer.

  However, if the interlayer insulating film on the scribe line is previously etched in this way, a large groove exists in the scribe line when patterning the wiring of each layer, and the resist for wiring patterning is a chip. It causes film loss at the end face. FIG. 9 is a cross-sectional view of the semiconductor device during the manufacturing process showing this state.

  As shown in this figure, since the large groove T exists in the scribe line, the resist J1 is inclined at the boundary position between the scribe line and the chip, and the film thickness of the resist J1 is changed to another position in the vicinity of the boundary position. It causes the film to become thinner. For this reason, since the film thickness of the resist J1 is thinner than the far side on the side near the scribe line at the time of patterning the wiring J2, the part where the film thickness is thin is completely etched before the other part, Etching is performed up to the wiring J2 below the wiring J2, and etching is performed up to the wiring J2 that should be left at the outer periphery of the chip. Also, when the resist J1 is patterned by the exposure machine, the scribe line has a large deep groove, so that the focus shifts and the line width of the wiring J2 varies.

  Such a phenomenon is prominent when the chip size is small and the area occupied by the scribe lines in the wafer is large. In addition, since the scribe line TEG for process performance management is arranged for the width of the scribe line, it is impossible to reduce the width, and the above problem cannot be solved by reducing the width.

  In view of the above points, the present invention prevents the wiring to be left behind from being etched due to the reduction of the resist film, suppresses the focus shift at the time of wiring patterning by the exposure machine, and causes variations in the line width of the wiring. An object of the present invention is to provide a method of manufacturing a semiconductor device that can be prevented.

  In order to achieve the above object, according to the first aspect of the present invention, the interlayer insulating film (2, 4, 6) is formed as the step of forming the interlayer insulating film (2, 4, 6) and the wiring layer (3, 5, 7). 6), the interlayer insulating films (2, 4, 6) are removed on both sides of the scribe line to form grooves (T) on the scribe line, and between the grooves (T). After leaving the interlayer insulating film (2, 4, 6) and forming the metal layer (20) constituting the wiring layer (3, 5, 7) on the interlayer insulating film (2, 4, 6) A step of forming a resist (21) as a mask for patterning the metal layer (20) on the metal layer (20), and patterning the resist (21) by exposing with an exposure machine; The metal layer (20) is patterned using the resist (21) as a mask to form the wiring layers (3, 5). It is characterized by performing a step of forming a 7).

  In this way, in the scribe line, there is a region where the surface of the semiconductor substrate (1) is exposed without the interlayer insulating film (2, 4, 6) at both sides of the scribe line, that is, at the boundary position with the portion to be the chip. The interlayer insulating films (2, 4, 6) are left in the region between the trenches (T) in the scribe line. For this reason, it can suppress that the resist (21) used as a mask at the time of forming a wiring layer (3, 5, 7) decreases in the vicinity of the boundary position between the scribe line and the chip.

  Accordingly, it is possible to prevent the wiring to be left behind from being etched due to the film thickness reduction of the resist (21), and to suppress a focus shift at the time of patterning the wiring layers (3, 5, 7) by the exposure machine. It is possible to prevent variations in the line widths of (3, 5, 7).

  According to the second aspect of the present invention, as the step of forming the protective film (8), the interlayer insulating film (on the scribe line) is covered while covering the end surface of the interlayer insulating film (2, 4, 6) on the chip side. 2, 4, 6) is characterized in that a step of forming a protective film (8) is performed so as to be separated from the substrate.

  As described above, the interlayer insulating films (2, 4, 6) are separated from the interlayer insulating films (2, 4, 6) and the protective film (8) formed on the chip on both sides of the scribe line. Therefore, even if chipping occurs in the interlayer insulating films (2, 4, 6) on the scribe line, the interlayer insulating films (2, 4, 6) and the protective film (8) formed on the chip are Chipping can be prevented from occurring. Moreover, the penetration | invasion of a water | moisture content can also be suppressed by covering a chip end surface with a protective film (8).

  According to a third aspect of the present invention, in the step of leaving the interlayer insulating film (2, 4, 6) between the trenches (T), the dicing blade of the scribe line passes through the interlayer insulating film (2, 4, 6). It is characterized in that it is removed on the line to be processed.

  In this way, the dicing blade can be prevented from touching the interlayer insulating films (2, 4, 6). Therefore, it is possible to suppress the deterioration of the dicing blade due to the relatively hard interlayer insulating film (2, 4, 6). It is also possible to prevent generation of particles due to scraping of the interlayer insulating films (2, 4, 6) during dicing.

  According to a fourth aspect of the present invention, in the step of forming the protective film (8), even on the scribe line, the end surface of the interlayer insulating film (2, 4, 6) formed on the scribe line is formed on the scribe line. A protective film (8) is formed so as to cover the surface along the surface, and the protective film (8) formed on the scribe line is separated from the protective film (8) formed on the chip side.

  Thus, the protective film (8) is formed so as to cover the surface along the scribe line among the end faces of the interlayer insulating films (2, 4, 6) formed on the scribe line. For this reason, the corner formed by the interlayer insulating films (2, 4, 6) and the semiconductor substrate (1) can be covered with the protective film (8). For this reason, even if there is an etching residue (20a) of the wiring layer (3, 5, 7), the etching residue (20a) is peeled off in a later step and becomes particles by covering with the protective film (8). This can be prevented. Further, when patterning the protective film (8), the portion of the interlayer insulating film (2, 4, 6) made of the same material as the protective film (8), or the etching selectivity with the protective film (8) The interlayer insulating film (2, 4, 6) having a low thickness can be prevented from being peeled off from the portion by being etched in the lateral direction.

  According to a fifth aspect of the present invention, in the step of leaving the interlayer insulating film (2, 4, 6) between the trenches (T), the interlayer insulating film (2, 4, 6) is perpendicular to the longitudinal direction of the scribe line. It is characterized by dividing into a plurality.

  In this manner, the interlayer insulating films (2, 4, 6) may be divided into a plurality of parts in the direction perpendicular to the longitudinal direction of the scribe line.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

It is sectional drawing which showed the manufacturing process of the semiconductor device concerning 1st Embodiment of this invention. FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 1; FIG. 10 is a layout diagram during the manufacturing process of the semiconductor device. It is sectional drawing which showed the manufacturing process of the semiconductor device concerning 2nd Embodiment of this invention. FIG. 10 is a layout diagram during the manufacturing process of the semiconductor device. It is sectional drawing which showed the manufacturing process of the semiconductor device concerning 3rd Embodiment of this invention. It is a partial expanded sectional view which shows the mode in the manufacturing process of the semiconductor device which compared 1st Embodiment and 3rd Embodiment. It is a layout view in the manufacturing process of the semiconductor device demonstrated by other embodiment. It is sectional drawing in the manufacturing process of the semiconductor device which showed a mode that the resist for wiring patterning produced a film loss in a chip | tip end surface.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. 1 and 2 are cross-sectional views showing the manufacturing process of the semiconductor device according to the present embodiment. FIG. 3 is a layout diagram during the manufacturing process of the semiconductor device according to the present embodiment. FIG. 3 corresponds to a layout view in which the upper surface of the semiconductor device in the step of FIG. 2C is partially enlarged, and the AA ′ cross section in FIG. 3 corresponds to FIG. Hereinafter, the method for manufacturing the semiconductor device according to the present embodiment will be described with reference to these drawings.

[Step shown in FIG. 1 (a)]
First, the semiconductor substrate 1 is prepared. As the semiconductor substrate 1, any semiconductor material such as a silicon substrate or a silicon carbide substrate may be used, but here, a silicon substrate is used. Although not shown, a semiconductor device is formed on the surface layer portion of the semiconductor substrate 1 by ion implantation of impurities, and then an interlayer insulating film 2 made of BPSG or the like is formed.

  Then, after forming a contact hole (not shown) for electrical connection with the semiconductor device to the interlayer insulating film 2, the surface of the interlayer insulating film 2 is made of a wiring material such as an Al layer. One metal layer (1st Al layer) is formed, and further, a first wiring layer 3 is formed by patterning using a resist as a mask. At this time, in the present embodiment, the first wiring layer 3 is not left on the scribe line.

  Thereafter, the interlayer insulating film 4 is formed so as to cover the surface of the first wiring layer 3 including the surface of the interlayer insulating film 2. For the interlayer insulating film 4, for example, a first thin insulating film 4 a composed of TEOS or the like, a second insulating film 4 b for planarization such as SOG formed thereon, and further A third-layer insulating film 4c formed of TEOS or the like formed thereon is used.

  In FIG. 1 (a), a region to be a scribe line and a region to be a chip on both sides thereof are shown, but the following FIGS. 1 (b) and 1 (c) and FIGS. 2 (a) to 2 (c) are shown. The same applies to. Further, as shown in FIG. 3, a plurality of scribe lines are formed in the vertical direction and the horizontal direction of the semiconductor substrate 1, and the scribe lines are laid out so that a rectangular chip is formed between the scribe lines.

[Step shown in FIG. 1B]
After disposing an etching mask (not shown) on the interlayer insulating film 4, the interlayer insulating film 4 and the interlayer insulating film 2 positioned therebelow are patterned by performing etching using the mask. Thereby, a contact hole (not shown) for electrical connection with the first wiring layer 3 is formed with respect to the interlayer insulating film 4. At this time, the trench T is formed at both ends of the scribe line so that the interlayer insulating films 2 and 4 are removed until the surface of the semiconductor substrate 1 is exposed, and the interlayer insulating film 2 is formed at the center of the scribe line. 4 is left.

[Step shown in FIG. 1 (c)]
A second metal layer (2nd Al layer) made of a wiring material such as an Al layer is formed on the surface of the interlayer insulating film 4, and further, the second wiring layer 5 is formed by patterning using a resist as a mask. Form. At this time, in the present embodiment, the second wiring layer 5 is not left on the scribe line.

  Thereafter, an interlayer insulating film 6 is formed so as to cover the surface of the second wiring layer 5 including the surface of the interlayer insulating film 4. For the interlayer insulating film 6, for example, a first thin insulating film 6 a composed of, for example, TEOS, a second insulating film 6 b for planarization such as SOG formed thereon, and A third-layer insulating film 6c made of TEOS or the like formed thereon is used.

[Step shown in FIG. 2 (a)]
After an unillustrated etching mask is disposed on the interlayer insulating film 6, the interlayer insulating film 6 is patterned by performing etching using the mask. Thereby, a contact hole (not shown) for electrical connection with the second wiring layer 5 is formed in the interlayer insulating film 6. At this time, as in the step shown in FIG. 1B, the trench T is formed again at both ends of the scribe line so that the interlayer insulating film 6 is removed until the surface of the semiconductor substrate 1 is exposed. In addition, the interlayer insulating films 2, 4, and 6 are left in the central portion of the scribe line.

  As long as the trench T is formed when the interlayer insulating film 6 is patterned, the position of the sidewall surface of the trench T is not particularly limited, but in this embodiment, the sidewall surface of the trench T is formed at the chip end. Is arranged inside the scribe line with respect to the side wall surface of the trench T formed when the interlayer insulating film 4 is patterned. By doing so, it is possible to cover the end faces of the interlayer insulating films 2 and 4 with the interlayer insulating film 6.

[Step shown in FIG. 2 (b)]
A third metal layer (3rdAl layer) 20 made of a wiring material such as an Al layer is formed on the surface of the interlayer insulating film 6, and a resist 21 serving as a mask is further formed. Then, the resist 21 is patterned using an exposure machine (not shown), and the resist 21 is left in the same layout as the third wiring layer 7 (see FIG. 2C) to be formed thereafter.

  At this time, in this embodiment, since the interlayer insulating films 2, 4, and 6 are also left on the scribe line, even if the groove T exists, the resist 21 as shown by the broken line in the figure. Is formed with almost no film loss. For this reason, the resist 21 after patterning is in a state in which there is not much difference in film thickness even on the side closer to the scribe line than on the far side.

[Step shown in FIG. 2 (c)]
The third wiring layer 7 is formed by patterning the third metal layer 20 using the resist 21 as a mask. Also at this time, in the present embodiment, the third wiring layer 7 is not left on the scribe line.

  Then, a protective film 8 made of a silicon nitride film or the like is disposed so as to cover the surface of the third metal layer 20 including the surface of the interlayer insulating film 6, and this is patterned using a mask (not shown). Thereby, each chip is covered with the protective film 8. At this time, the protective film 8 does not remain on the scribe line, and the end portions of the protective film 8 and the interlayer insulating films 2, 4, 6 remaining on the scribe line are separated. . In addition, the end surfaces of the interlayer insulating film 6 and the like are covered with the protective film 8 at the end of each chip so that the surface of the interlayer insulating film 6 and the like is not exposed from the protective film 8.

  Although the subsequent steps are not shown, the semiconductor substrate 1 is divided into chip units in a scribe line using a dicing blade to form semiconductor chips. For example, the semiconductor chip is mounted on a lead frame or a mounting substrate, and then resin molded. Thus, the semiconductor device is completed.

  In the manufacturing method of the semiconductor device according to the present embodiment described above, the interlayer insulating films 2, 4, 6 do not exist in the scribe line at both sides of the scribe line, that is, at the boundary position with the portion to be the chip. A region where the surface is exposed is provided, and the interlayer insulating films 2, 4, and 6 are left in the central position of the scribe line, that is, the region sandwiched between the trenches T. For this reason, it is possible to suppress a reduction in the thickness of the resist 21 used as a mask when forming the third wiring layer 7 in the vicinity of the boundary position between the scribe line and the chip.

  Therefore, it is possible to prevent the wiring to be left behind from being etched due to the reduction in the thickness of the resist 21, and it is possible to suppress a focus shift at the time of patterning the third wiring layer 7 by the exposure machine, and to reduce the line width of the third wiring layer 7. It is possible to prevent the variation from occurring.

  In this embodiment, since the interlayer insulating films 2, 4, and 6 are left in the scribe line, the relatively hard interlayer insulating films 2, 4, and 6 are also cut by a dicing blade when cutting in units of chips. It will be. For this reason, there is a concern about the problem of chipping. However, since the interlayer insulating films 2, 4, 6 are separated from the interlayer insulating films 2, 4, 6 and the protective film 8 formed on the chip on both sides of the scribe line, Even if the chipping occurs in the interlayer insulating films 2, 4, 6, the chipping does not occur in the interlayer insulating films 2, 4, 6 and the protective film 8 formed on the chip.

  In addition, although the film reduction of the resist 21 used for forming the third wiring layer 7 has been described here, the resist used when forming the first and second wiring layers 3 and 5 located in the lower layers is also described. The same can be said. In other words, here, the upper layer wiring, in which the resist film is significantly reduced in the case of the multilayer wiring structure, has been described as an example, but a problem due to the reduction of the resist film may occur even in the lower layer. Also in this case, as in the present embodiment, by leaving the interlayer insulating films 2 and 4 at the center position of the scribe line, the film thickness reduction of the resist can be suppressed, and the above effect can be obtained.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the pattern of the interlayer insulating films 2, 4, 6 to be left in the scribe line is changed with respect to the first embodiment. Only the parts different from the form will be described.

  FIG. 4 is a cross-sectional view of the semiconductor device according to the present embodiment during the manufacturing process. FIG. 5 is a layout diagram during the manufacturing process of the semiconductor device according to the present embodiment. FIG. 4 corresponds to a cross-sectional view in the step shown in FIG. 2C described in the first embodiment. 5 corresponds to a layout diagram in which the upper surface of the semiconductor device in the process of FIG. 4 is partially enlarged, and a B-B ′ cross section in FIG. 5 corresponds to FIG. 4.

  As shown in FIGS. 4 and 5, in this embodiment, although the manufacturing method is basically the same as that of the first embodiment, the interlayer insulating films 2, 4 are formed on the scribe line on the line through which the dicing blade passes. , 6 are removed to expose the semiconductor substrate 1.

  In this way, it is possible to prevent the dicing blade from touching the interlayer insulating films 2, 4 and 6. Accordingly, it is possible to suppress the deterioration of the dicing blade due to the relatively hard interlayer insulating films 2, 4, 6. Further, it is possible to prevent generation of particles due to shavings of the interlayer insulating films 2, 4, 6 during dicing.

  In the first embodiment, the first to third wiring layers 3, 5, and 7 are not left in the scribe line. This may cause an electrical failure such as a short circuit in the chip due to shavings when the first to third wiring layers 3, 5, 7 are diced or residual wrinkles on the dicing surface. Going to eliminate. However, when the interlayer insulating films 2, 4, 6 are not left at the dicing locations as in this embodiment, the first to third wiring layers 3, 5, 7 are not left at the dicing locations as well. In addition, by making it remain in other places, the height of the interlayer insulating films 2, 4, 6, etc. on the scribe line is made closer to the chip part while preventing the above problem from occurring. Is possible. Thereby, the film loss of the resist 21 can be further suppressed, and the above effect can be further obtained.

(Third embodiment)
A third embodiment of the present invention will be described. This embodiment is different from the first embodiment because the protective film 8 is also partially left in the scribe line with respect to the first embodiment, and the others are the same as the first embodiment. Only the part will be described.

  FIG. 6 is a cross-sectional view of the semiconductor device according to the present embodiment during the manufacturing process. This figure corresponds to a sectional view in the step shown in FIG. 2C described in the first embodiment.

  As shown in FIG. 6, in this embodiment, although the manufacturing method is basically the same as that in the first embodiment, the length of the scribe line in the end faces of the interlayer insulating films 2, 4, 6 is also used in the scribe line. The protective film 8 is left so as to cover the surface along the direction. However, the protective film 8 in the scribe line is not left on the line through which the dicing blade passes and both sides of the scribe line among the interlayer insulating films 2, 4 and 6, and the protective film 8 is cut by the dicing blade. The structure is such that it does not need to be provided and is separated from the chip-side protective film 8 on both sides of the scribe line.

  According to such a structure, since the hard protective film 8 does not need to be cut with a dicing blade, the following effects can be obtained without deteriorating the dicing blade. This will be described with reference to a partially enlarged cross-sectional view in the manufacturing process of the semiconductor device shown in FIG.

  As described in the first embodiment, the third metal layer 20 is patterned in the steps shown in FIGS. At this time, as illustrated in FIG. 7A, an etching residue 20 a of the third metal layer 20 may occur in a corner portion formed by the interlayer insulating films 2, 4, 6 and the semiconductor substrate 1. Such etching residue 20a may be peeled off in a subsequent process to become particles, which may cause an electrical failure such as occurrence of a short-circuited portion in the chip.

  On the other hand, in the present embodiment, the corner portion formed by the interlayer insulating films 2, 4, 6 and the semiconductor substrate 1 can be covered with the protective film 8 not only in the chip portion but also in the scribe line. For this reason, as shown in FIG. 7B, even if the etching residue 20a exists, the etching residue 20a of the wiring layer (Al) is peeled off in the subsequent process and becomes particles by covering with the protective film 8. This can be prevented.

  In the first embodiment, the silicon oxide film such as TEOS or SOG has been described as an example of the constituent material of the interlayer insulating films 2, 4, 6. However, these are the same material as the protective film 8, for example, silicon A nitride film can also be used. In such a case, when the protective film 8 is patterned in the step shown in FIG. 2C, the portion constituted by the silicon nitride film recedes by lateral etching, for example, as shown in FIG. There is a possibility that film peeling occurs from the portion, which becomes particles.

  On the other hand, in this embodiment, the side wall surfaces of the interlayer insulating films 2, 4, 6 can be covered with the protective film 8 not only in the chip portion but also in the scribe line. For this reason, as shown in FIG. 7D, when the protective film 8 is patterned, portions of the interlayer insulating films 2, 4, 6 made of the same material as the protective film 8 are laterally etched. Therefore, it is possible to prevent film peeling from the portion.

(Other embodiments)
In each of the above-described embodiments, the method for manufacturing a semiconductor device having a multilayer wiring structure having a three-layer wiring structure has been described. However, the method for manufacturing a semiconductor device having a wiring structure having various numbers of layers is not necessary. The present invention can be applied as follows.

  In each of the above embodiments, only the structure in which the semiconductor device is formed on the semiconductor substrate 1 has been described. However, other elements such as a structure in which a thin film resistor is provided between the interlayer insulating films constituting the wiring structure are provided. The present invention can also be applied to a method for manufacturing a semiconductor device to be formed.

  In the second embodiment, an example in which the interlayer insulating films 2, 4, and 6 that remain on the scribe line are not left on the line through which the dicing blade passes is shown. . However, this is merely an example of a structure example, while the interlayer insulating films 2, 4, 6 are not left on both sides of the scribe line and the line through which the dicing blade passes, Any other structure may be used as long as the interlayer insulating films 2, 4, and 6 are left in place. For example, FIG. 8 shows an example of such a structural example, and as shown in this figure, a structure in which the interlayer insulating films 2, 4, 6 are divided into a plurality in the direction perpendicular to the longitudinal direction of the scribe line. It may be said.

  Of course, the structure in which the interlayer insulating films 2, 4, 6 are divided into a plurality of parts in the direction perpendicular to the longitudinal direction of the scribe line in this way is the interlayer insulating film 2 on the line through which the dicing blade passes as in the first embodiment. The present invention can also be applied to a structure in which 4 and 6 are removed.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 4, 6 Interlayer insulating film 3, 5, 7 1st-3rd wiring layer 8 Protective film 20 3rd metal layer 20a Etching remainder 21 Resist

Claims (5)

Preparing a semiconductor substrate (1) and forming a semiconductor device on the semiconductor substrate (1);
An interlayer insulating film (2, 4, 6) is formed on the semiconductor substrate (1), and a wiring layer (3, 5, 7) is formed through the interlayer insulating film (2, 4, 6). Process,
Forming a protective film (8) covering the wiring layers (3, 5, 7) and the interlayer insulating films (2, 4, 6);
After forming the protective film (8), the semiconductor substrate (1) is cut by a scribe line using a dicing blade to divide the semiconductor substrate into chip units, thereby producing a semiconductor device. In
Forming the interlayer insulating films (2, 4, 6) and the wiring layers (3, 5, 7),
After forming the interlayer insulating film (2, 4, 6), the interlayer insulating film (2, 4, 6) is removed on both sides of the scribe line to form a trench (T) on the scribe line. However, leaving the interlayer insulating film (2, 4, 6) between the trenches (T),
After the metal layer (20) constituting the wiring layer (3, 5, 7) is formed on the interlayer insulating film (2, 4, 6), the metal layer is formed on the metal layer (20). (20) forming a resist (21) serving as a mask for patterning, and patterning the resist (21) by exposing with an exposure machine;
Forming a wiring layer (3, 5, 7) by patterning the metal layer (20) using the resist (21) as a mask.   The step of forming the protective film (8) includes the step of covering the end face of the interlayer insulating film (2, 4, 6) on the chip side and forming the interlayer insulating film (2, 4, 4) formed on the scribe line. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the protective film is formed so as to be separated from 6).   In the step of leaving the interlayer insulating film (2, 4, 6) between the trenches (T), the interlayer insulating film (2, 4, 6) is placed on the line of the scribe line through which the dicing blade passes. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is removed.   In the step of forming the protective film (8), even on the scribe line, the surface along the scribe line is covered among the end faces of the interlayer insulating film (2, 4, 6) formed on the scribe line. The protective film (8) is formed as described above, and the protective film (8) formed on the scribe line is separated from the protective film (8) formed on the chip side. A method for manufacturing a semiconductor device according to any one of 1 to 3.   In the step of leaving the interlayer insulating film (2, 4, 6) between the trenches (T), the interlayer insulating film (2, 4, 6) is divided into a plurality in a direction perpendicular to the longitudinal direction of the scribe line. The method for manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method.

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